JP2021108361A - Laminated ceramic capacitor - Google Patents

Abstract

To provide a laminated ceramic capacitor configured so that at least an electric field can be suppressed from concentrating in an end part of an internal electrode to improve reliability.SOLUTION: On a surface including a length direction and a width direction, an intersection point of an interface is formed from a second dielectric ceramic layer, a first internal electrode layer or a second internal electrode layer, and a third dielectric ceramic layer. The second dielectric ceramic layer and the third dielectric ceramic layer include regions near the intersection point in the vicinity of the intersection point. An average particle size of dielectric particles included in the region near the intersection point is smaller than any of an average particle size of dielectric particles included in the first dielectric ceramic layer, an average particle size of dielectric particles included in the second dielectric ceramic layer and an average particle size of dielectric particles included in the third dielectric ceramic layer.SELECTED DRAWING: Figure 19

Description

The present invention relates to multilayer ceramic capacitors.

In recent years, multilayer ceramic electronic components such as multilayer ceramic capacitors have been made smaller and have higher capacities. In order to reduce the size and increase the capacity of the multilayer ceramic capacitor, the side margins are thinned with respect to each side surface of the laminate in which the plurality of dielectric ceramic layers and the plurality of internal electrode layers are laminated. It is effective to increase the area of the internal electrode layers facing each other.

Patent Document 1 includes a step of preparing a chip including a plurality of laminated dielectric ceramic layers and a plurality of internal electrode layers, and the plurality of internal electrode layers are exposed on the side surface, and a plurality of dielectrics for coating. A method for manufacturing an electronic component is disclosed, which comprises a step of sticking body sheets to each other to form a dielectric laminated sheet and a step of sticking the dielectric laminated sheet on a side surface of the chip.

Further, in Patent Document 2, when a plurality of ceramic green sheets on which internal electrodes are printed are laminated, pressurized and fired to manufacture a laminated ceramic capacitor, a step is eliminated in a region where the internal electrodes are not printed. It is disclosed that by applying the ceramic slurry, it is possible to prevent a step from being generated between the portion where the internal electrodes overlap and the portion where the internal electrodes do not overlap.

JP-A-2017-147358 Japanese Unexamined Patent Publication No. 2003-209025

However, in Cited Document 1, the composition of the ceramic dielectric sheet to be attached to the side surface of the laminated body is not particularly mentioned. Further, the composition of the ceramic paste for eliminating steps used in Cited Document 2 is not particularly mentioned. Therefore, in References 1 and 2, there is room for improving the reliability of the laminated ceramic capacitor by optimizing the composition of the dielectric laminated sheet and the ceramic paste for eliminating the step.
In addition, since the electric field is concentrated at the end of the internal electrode close to the step-eliminating ceramic paste described in Reference 2, there is a risk of lowering the reliability.

An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing electric field concentration at least on the end of an internal electrode and improving reliability.

The multilayer ceramic capacitor of the present invention is a laminated ceramic capacitor including a laminate including a dielectric ceramic layer and an internal electrode layer, which are laminated in the lamination direction, and an external electrode connected to the internal electrode layer. The laminated body includes a first main surface and a second main surface facing each other in the laminating direction, a first side surface and a second side surface facing each other in a width direction orthogonal to the laminating direction, and the laminating direction and It has a first end face and a second end face that are opposed to each other in a length direction orthogonal to the width direction, and the internal electrode layer is a first internal electrode layer that is drawn out to the first end face and said. A second internal electrode layer is drawn out to the second end face so as to face the first inner electrode layer via a dielectric ceramic layer, and the outer electrode is placed on the first end face. A first external electrode that is arranged and connected to the first internal electrode layer, and a second external that is arranged on the second end face and is connected to the second internal electrode layer. The dielectric ceramic layer including an electrode is composed of a first dielectric ceramic layer and a second dielectric ceramic layer, and the first dielectric ceramic layer is the first internal electrode layer and the said. The second dielectric ceramic layer is arranged between the second internal electrode layer, and the internal electrode layer is arranged between the first dielectric ceramic layers facing each other via the internal electrode layer. A part of the region is arranged so as to overlap with the first dielectric ceramic layer in the stacking direction, and the laminated body includes the first internal electrode layer and the second. An inner layer portion in which the inner electrode layers of the above are alternately laminated via the dielectric ceramic layer, an outer layer portion arranged so as to sandwich the inner layer portion in the lamination direction, and an outer layer portion made of a ceramic material, and the inner layer. A surface including a third dielectric ceramic layer, which is arranged so as to sandwich the portion and the outer layer portion in the width direction and is made of a dielectric ceramic material, and includes the length direction and the width direction. In, the second dielectric ceramic layer, the first internal electrode layer or the second internal electrode layer, and the third dielectric ceramic layer form an intersection of interfaces, and the second The dielectric ceramic layer and the third dielectric ceramic layer include a region near the intersection in the vicinity of the intersection, and the average particle diameter of the dielectric particles contained in the region near the intersection is the first dielectric ceramic. The average particle size of the dielectric particles contained in the layer, the dielectric particles contained in the second dielectric ceramic layer It is smaller than the average particle size of both the average particle size of the children and the average particle size of the dielectric particles contained in the third dielectric ceramic layer.

According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing electric field concentration at least on the end of an internal electrode and improving reliability.

It is a perspective view which shows an example of the multilayer ceramic capacitor of this invention schematically. It is a perspective view which shows typically an example of the laminated body which comprises the laminated ceramic capacitor shown in FIG. FIG. 5 is a cross-sectional view taken along the line AA of the multilayer ceramic capacitor shown in FIG. FIG. 5 is a cross-sectional view taken along the line CC of the multilayer ceramic capacitor shown in FIG. FIG. 5 is a cross-sectional view taken along the line BB of the multilayer ceramic capacitor shown in FIG. It is a top view which shows an example of a ceramic green sheet schematically. It is a top view which shows an example of a ceramic green sheet schematically. It is a top view which shows an example of a ceramic green sheet schematically. It is an exploded perspective view which shows an example of a mother block schematically. It is a perspective view which shows an example of a green chip schematically. It is a part of the LT cross section of the multilayer ceramic capacitor of this invention, and is the figure which shows typically the 1st alloy part and the 2nd alloy part. It is a partially enlarged view of FIG. It is a part of the LT cross section of the multilayer ceramic capacitor of this invention, and is the figure which shows typically the 1st dotted internal electrode, the 2nd dotted internal electrode, and the 4th alloy part. It is a part of the WT cross section of the multilayer ceramic capacitor of this invention, and is the figure which shows typically the 1st alloy part and the 3rd alloy part. It is a partially enlarged view of FIG. 14, and is the figure which shows typically the 5th alloy part. It is sectional drawing which shows typically the mode in which the end portion of the second dielectric ceramic layer is superposed on the end portion of the internal electrode layer in the multilayer ceramic capacitor of the present invention. It is sectional drawing which shows typically the mode in which the end portion of the second dielectric ceramic layer is superposed on the end portion of the internal electrode layer in the multilayer ceramic capacitor of the present invention. It is a figure for demonstrating the TEM analysis method which analyzes the amount of a metal element contained in the internal electrode layer of the multilayer ceramic capacitor of this invention. It is a part of FIG. 5 and is a figure which shows the region near the intersection of this invention. It is a figure for demonstrating the method of measuring the average particle diameter of the dielectric particles contained in the 1st dielectric ceramic layer and the 3rd dielectric ceramic layer. It is a figure for demonstrating the method of measuring the average particle diameter of the dielectric particles contained in the 3rd dielectric ceramic layer. It is a figure for demonstrating the 1st step of the method of measuring the average particle diameter of the dielectric particles contained in the 2nd dielectric ceramic layer and the region near an intersection. It is a figure for demonstrating the 2nd step of the method of measuring the average particle diameter of the dielectric particles contained in the 2nd dielectric ceramic layer and the region near an intersection. It is a figure for demonstrating the method of measuring the average particle diameter of the dielectric particles contained in the region near an intersection. It is a figure which shows typically the step of removing the side surface of the unfired laminate in the manufacturing method of the multilayer ceramic capacitor of this invention. It is a figure which shows the end face of the unfired laminated body which the side surface was removed in the manufacturing method of the laminated ceramic capacitor of this invention. FIG. 5 is a cross-sectional view schematically showing an embodiment in which an end portion of a second dielectric ceramic layer is superimposed on an end portion of an internal electrode layer in the method for manufacturing a multilayer ceramic capacitor of the present invention. It is a part of the WT cross section of the multilayer ceramic capacitor of this invention, and is the figure which shows typically the defect part of the 2nd dielectric ceramic layer. FIG. 28 is a cross-sectional view taken along the line KK of FIG. 28. It is a part of the LT cross section of the multilayer ceramic capacitor of this invention, and is the figure which shows typically the first segregation. It is a partially enlarged view of FIG. It is a part of the WT cross section of the multilayer ceramic capacitor of this invention, and is the figure which shows typically the 2nd segregation. It is a part of the LW cross section of the multilayer ceramic capacitor of this invention, and is the figure which shows the 3rd segregation which segregates into the 1st corner region and the 2nd corner region. FIG. 5 is a cross-sectional view schematically showing an embodiment in which an end portion of a second dielectric ceramic layer is superimposed on a third segregation in the multilayer ceramic capacitor of the present invention. It is a figure which shows the thickness of the 1st dielectric ceramic layer in the central part in the length (L) direction of the multilayer ceramic capacitor of this invention. It is a figure which shows the thickness of the 2nd dielectric ceramic layer of the multilayer ceramic capacitor of this invention.

Hereinafter, the multilayer ceramic capacitor of the present invention will be described.
However, the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. It should be noted that a combination of two or more of the individual desirable configurations described below is also the present invention.

[Multilayer ceramic capacitor]
FIG. 1 is a perspective view schematically showing an example of a multilayer ceramic capacitor of the present invention. FIG. 2 is a perspective view schematically showing an example of a laminated body constituting the multilayer ceramic capacitor shown in FIG. 1. FIG. 3 is a cross-sectional view taken along the line AA of the multilayer ceramic capacitor shown in FIG. FIG. 4 is a sectional view taken along line CC of the multilayer ceramic capacitor shown in FIG.

In the present specification, the stacking direction, width direction, and length direction of the laminated ceramic capacitor and the laminated body are indicated by arrows T, W, and L in the laminated ceramic capacitor 1 shown in FIG. 1 and the laminated body 10 shown in FIG. 2, respectively. The direction to be determined. Here, the stacking (T) direction, the width (W) direction, and the length (L) direction are orthogonal to each other. The stacking (T) direction is a direction in which a plurality of dielectric ceramic layers 20 and a plurality of pairs of the first internal electrode layer 21 and the second internal electrode layer 22 are stacked.

The multilayer ceramic capacitor 1 shown in FIG. 1 includes a laminated body 10 and a first external electrode 51 and a second external electrode 52 provided on both end surfaces of the laminated body 10, respectively.

As shown in FIG. 2, the laminated body 10 has a rectangular parallelepiped shape or a substantially rectangular parallelepiped shape, and is laminated (T) with the first main surface 11 and the second main surface 12 facing each other in the stacking (T) direction. The first side surface 13 and the second side surface 14 facing each other in the width (W) direction orthogonal to the direction and the first side surface 14 facing each other in the length (L) direction orthogonal to the stacking (T) direction and the width (W) direction. It has an end face 15 and a second end face 16.

In the present specification, the cross section of the laminated ceramic capacitor 1 or the laminated body 10 orthogonal to the first end surface 15 and the second end surface 16 and parallel to the laminated (T) direction is shown in the length (L) direction and It is called an LT cross section, which is a cross section in the stacking (T) direction. Further, the cross section of the laminated ceramic capacitor 1 or the laminated body 10 orthogonal to the first side surface 13 and the second side surface 14 and parallel to the laminated (T) direction is shown in the width (W) direction and the laminated (T) direction. It is called a WT cross section, which is a cross section of. Further, a cross section of the laminated ceramic capacitor 1 or the laminated body 10 orthogonal to the first side surface 13, the second side surface 14, the first end surface 15 and the second end surface 16 and orthogonal to the laminated (T) direction is obtained. , It is called an LW cross section which is a cross section in the length (L) direction and the width (W) direction. Therefore, FIG. 3 is an LT cross section of the multilayer ceramic capacitor 1, and FIG. 4 is a WT cross section of the multilayer ceramic capacitor 1.

The laminated body 10 preferably has rounded corners and ridges. The corner portion is a portion where the three surfaces of the laminated body intersect, and the ridge portion is a portion where the two surfaces of the laminated body intersect.

As shown in FIGS. 2, 3 and 4, the laminate 10 is formed along the interface between the plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction and the dielectric ceramic layers 20. It has a laminated structure including a plurality of pairs of the first internal electrode layer 21 and the second internal electrode layer 22. The dielectric ceramic layer 20 extends along the width (W) direction and the length (L) direction, and each of the first internal electrode layer 21 and the second internal electrode layer 22 is a dielectric ceramic layer 20. It extends in a flat plate shape along.

The first internal electrode layer 21 is drawn out to the first end surface 15 of the laminated body 10. On the other hand, the second internal electrode layer 22 is drawn out to the second end surface 16 of the laminated body 10.

The first internal electrode layer 21 and the second internal electrode layer 22 face each other via the dielectric ceramic layer 20 in the stacking (T) direction. Capacitance is generated by a portion where the first internal electrode layer 21 and the second internal electrode layer 22 face each other via the dielectric ceramic layer 20.

Each of the first internal electrode layer 21 and the second internal electrode layer 22 preferably contains a metal such as Ni, Cu, Ag, Pd, Ag—Pd alloy, or Au. Each of the first internal electrode layer 21 and the second internal electrode layer 22 may contain the same dielectric ceramic material as the dielectric ceramic layer 20 in addition to the metal.

The dielectric ceramic layer 20 has a first dielectric ceramic layer 20a and a second dielectric ceramic layer 20b.
The first dielectric ceramic layer 20a is a dielectric ceramic layer arranged between the first internal electrode layer 21 and the second internal electrode layer 22.
The second dielectric ceramic layer 20b is arranged in a region where the internal electrode layer (21, 22) is not arranged between the first dielectric ceramic layers 20a facing each other via the internal electrode layer (21, 22). It is a dielectric ceramic layer to be formed.

The first external electrode 51 is provided on the first end surface 15 of the laminated body 10, and in FIG. 1, the first main surface 11, the second main surface 12, the first side surface 13, and the second side surface 13 are provided. It has a portion that wraps around to each part of the side surface 14. The first external electrode 51 is connected to the first internal electrode layer 21 at the first end surface 15.

The second external electrode 52 is provided on the second end surface 16 of the laminated body 10, and in FIG. 1, the first main surface 11, the second main surface 12, the first side surface 13, and the second side surface 13 are provided. It has a portion that wraps around to each part of the side surface 14. The second external electrode 52 is connected to the second internal electrode layer 22 at the second end surface 16.

It is preferable that the first external electrode 51 and the second external electrode 52 each include a Ni layer containing Ni and a ceramic material. The Ni layer is a base electrode layer. Such a Ni layer can be formed by a so-called cofire method in which the first internal electrode layer 21 and the second internal electrode layer 22 are fired at the same time. The Ni layer is preferably arranged directly on the laminated body 10.

The first external electrode 51 preferably includes a Ni layer, a first plating layer, and a second plating layer in order from the first end surface 15 side of the laminated body 10. Similarly, the second external electrode 52 preferably includes a Ni layer, a first plating layer, and a second plating layer in this order from the second end face 16 side of the laminated body 10. The first plating layer is preferably formed by Ni plating, and the second plating layer is preferably formed by Sn plating. The first external electrode 51 and the second external electrode 52 may each include a conductive resin layer containing conductive particles and a resin between the Ni layer and the first plating layer. Examples of the conductive particles in the conductive resin layer include metal particles such as Cu, Ag, and Ni.

The Ni layer may be formed by a so-called post-fire method in which a conductive paste is applied to the end face of the laminated body after firing and baked. In this case, the Ni layer does not have to contain a ceramic material.

Alternatively, the first external electrode 51 and the second external electrode 52 may each include a base electrode layer containing a metal such as Cu. The base electrode layer may be formed by a cofire method or a postfire method. Further, the base electrode layer may be a plurality of layers.

For example, the first external electrode 51 includes a Cu layer which is a base electrode layer, a conductive resin layer containing conductive particles and a resin, and a first plating in order from the first end surface 15 side of the laminated body 10. It may have a four-layer structure including a layer and a second plating layer. Similarly, the second external electrode 52 includes a Cu layer which is a base electrode layer, a conductive resin layer containing conductive particles and a resin, and a first, in order from the second end surface 16 side of the laminated body 10. It may have a four-layer structure including a plating layer and a second plating layer.

As shown in FIGS. 3 and 4, the dielectric ceramic layer 20 has a first dielectric ceramic layer 20a and a second dielectric ceramic layer 20b.
The first dielectric ceramic layer 20a is arranged between the first internal electrode layer 21 and the second internal electrode layer 22.
The second dielectric ceramic layer 20b is arranged in a region where the internal electrode layer is not arranged, between the first dielectric ceramic layers 20a facing each other via the internal electrode layer.

As shown in FIGS. 2, 3 and 4, the laminated body 10 has an inner layer portion 30 in which the first internal electrode layer 21 and the second internal electrode layer 22 face each other via the dielectric ceramic layer 20. , The outer layer portions 31 and 32 are arranged so as to sandwich the inner layer portion 30 in the stacking (T) direction, and the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32 are arranged so as to be sandwiched in the width (W) direction. It includes a third dielectric ceramic layer 41 and 42. The third dielectric ceramic layers 41 and 42 are also referred to as side margin portions.
In FIGS. 3 and 4, the inner layer portion 30 has a first internal electrode layer 21 closest to the first main surface 11 and a first one closest to the second main surface 12 along the stacking (T) direction. It is a region sandwiched between the internal electrode layers 21 of the above. Although not shown, each of the outer layer portion 31 and the outer layer portion 32 is preferably composed of a plurality of dielectric ceramic layers 20 laminated in the stacking (T) direction, from the first dielectric ceramic layer 20a. It is more preferable to be configured.

The thicknesses of the outer layer portions 31 and 32 are preferably 15 μm or more and 40 μm or less, respectively. Each of the outer layer portions 31 and 32 may have a single-layer structure instead of a multi-layer structure.

As shown in FIG. 4, each of the third dielectric ceramic layer 41 and the third dielectric ceramic layer 42 may be composed of a plurality of dielectric ceramic layers laminated in the width (W) direction. ..
Of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer, the innermost layer in the width direction is referred to as an inner layer, and the outermost layer is referred to as an outer layer. An interface exists between the inner layer and the outer layer.
In FIG. 4, the third dielectric ceramic layer 41 includes an inner layer 41a arranged on the innermost side of the laminated body 10 and an outer layer 41b arranged on the outermost side of the laminated body 10 as the dielectric ceramic layer. It is a two-layer structure including. Similarly, the third dielectric ceramic layer 42 includes, as the dielectric ceramic layer, an inner layer 42a arranged on the innermost side of the laminated body 10 and an outer layer 42b arranged on the outermost side of the laminated body 10. It has a two-layer structure including.
The third dielectric ceramic layer is not limited to the two-layer structure, and may have a structure of three or more layers. When the third dielectric ceramic layer includes three or more dielectric ceramic layers, the innermost dielectric ceramic layer in the width direction is used as the inner layer, and the outermost dielectric ceramic in the width direction. The layer is an outer layer.
Further, the number of layers of the dielectric ceramic layer may be different between the third dielectric ceramic layer on the first side surface side and the third dielectric ceramic layer on the second side surface side of the laminate.

When the third dielectric ceramic layer has a two-layer structure including an inner layer and an outer layer, the two layers are observed by using an optical microscope in a dark field due to the difference in sinterability between the inner layer and the outer layer. It can be confirmed that it is a structure and the interface between layers. The same applies when the third dielectric ceramic layer has a structure of three or more layers.

The first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 are made of, for example, _{a dielectric ceramic material containing BaTIO 3} or the like as a main component. The dielectric ceramic layer 20 constituting the inner layer portion 30 may further contain a sintering aid element.

The dielectric ceramic layer constituting the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may contain ceramic grains. The details of the diameter of the ceramic grain will be described later.

In the multilayer ceramic capacitor of the present invention, the composition of at least one dielectric ceramic layer among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is the other dielectric ceramic. Different from the composition of the layer.
Since the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer all have different properties required for the purpose of arrangement and the manufacturing method, the first dielectric ceramic layer, The dielectric ceramic layer is arranged by making the composition of at least one of the second dielectric ceramic layer and the third dielectric ceramic layer different from the composition of the other dielectric ceramic layers. It is possible to realize the optimum composition according to the place where the ceramic is formed, and it is possible to improve the reliability.

In the multilayer ceramic capacitor of the present invention, the composition of the first dielectric ceramic layer may be different from the composition of the second dielectric ceramic layer and the third dielectric ceramic layer, or the composition of the second dielectric. The composition of the ceramic layer may be different from the composition of the first dielectric ceramic layer and the third dielectric ceramic layer, and the composition of the third dielectric ceramic layer may be different from the composition of the first dielectric ceramic layer and the first dielectric ceramic layer. The composition of the second dielectric ceramic layer may be different, or the composition of the first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer may be different from each other.

In the multilayer ceramic capacitor of the present invention, the composition of the second dielectric ceramic layer and the composition of the third dielectric ceramic layer are preferably different, and the first dielectric ceramic layer, the second dielectric ceramic layer and It is more preferable that the compositions of the third dielectric ceramic layers are all different.

When the third dielectric ceramic layer is composed of a plurality of dielectric ceramic layers, the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer may have the same composition as each other. , May have different compositions.
When the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the first dielectric ceramic layer, the composition of the third dielectric ceramic layer and the first It can be said that the composition of the dielectric ceramic layer is different.
When the composition of any one of the plurality of dielectric ceramic layers constituting the third dielectric ceramic layer is different from that of the second dielectric ceramic layer, the composition of the third dielectric ceramic layer and the composition of the third dielectric ceramic layer It can be said that the composition of the second dielectric ceramic layer is different.

Of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, the dielectric ceramic layers having different compositions preferably have the same main component and different types of additives. ..
Examples of the main component include BaTIO ₃ , CaTIO _3, SrTiO _{3, and the} like.
The additive preferably contains elements such as Si, Mg, Mn, Sn, Cu, rare earths, Ni and Al.
The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may contain two or more of the above elements.

In addition, "same composition" means that the types of elements contained in the dielectric ceramics constituting each dielectric ceramic layer are the same, and the contents (molar ratio) of other elements based on Ti are all the same. It means that it is within ± 0.5%.
The difference in the diameter of the ceramic grains constituting each dielectric ceramic layer and the difference in the porosity are not included in the difference in the composition of the dielectric ceramic layers.

Regarding the composition of each dielectric ceramic layer, wavelength dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis It can be obtained by performing elemental analysis by TEM-EDX). At this time, the composition of each dielectric ceramic layer is measured at five points to obtain an average value.
Regarding the second dielectric ceramic layer, from five places from the second dielectric ceramic layer exposed on the first end face of the laminate and from the second dielectric ceramic layer exposed on the second end face of the laminate. The average value measured at 5 points.
When the third dielectric ceramic layer has a multi-layer structure, the ratio of the thickness of each layer to the third dielectric ceramic layer is added to the composition obtained by measuring the composition of each layer at five points. It is the sum of the times.
If element segregation is observed near the interface with another dielectric ceramic layer or internal electrode layer, the location where element segregation is observed is not subject to WDX measurement.

Mg is preferable as the element added to the first dielectric ceramic layer.
The content of Mg in the first dielectric ceramic layer is preferably 0.05 mol% or more and 3.0 mol% or less with respect to 100 mol of Ti.
It is more preferable that the Mg content in the first dielectric ceramic layer is smaller than the Mg content in the second dielectric ceramic layer and the third dielectric ceramic layer.
When the Mg content in the first dielectric ceramic layer is low, the relative permittivity of the first dielectric ceramic layer increases, so that the capacitance of the monolithic ceramic capacitor can be improved. In some cases, the content of Mg in the first dielectric ceramic layer is preferably as low as possible.

Sn is preferable as the element added to the second dielectric ceramic layer.
The Sn content in the second dielectric ceramic layer is preferably 0.05 mol% or more and 3.0 mol% or less with respect to 100 mol of Ti.
The Sn content in the second dielectric ceramic layer is preferably higher than the Sn content in the first dielectric ceramic layer and the third dielectric ceramic layer.

Si is preferable as the element added to the third dielectric ceramic layer.
The content of Si in the third dielectric ceramic layer is preferably 0.05 mol% or more and 5.0 mol% or less with respect to 100 mol of Ti.
The Si content in the third dielectric ceramic layer is preferably higher than the Si content in the first dielectric ceramic layer and the second dielectric ceramic layer.
When the Si content in the third dielectric ceramic layer is high, the sinterability of the dielectric ceramic layer is enhanced, so that moisture or the like invades from the first side surface and the second side surface of the laminate to enter the internal electrode layer. Can be suppressed from deteriorating.

Mg is preferable as the element added to the third dielectric ceramic layer.
The content of Mg in the third dielectric ceramic layer is preferably 0.05 mol% or more and 5.0 mol% or less with respect to 100 mol of Ti.
The Mg content in the third dielectric ceramic layer is preferably higher than the Mg content in the first dielectric ceramic layer and the second dielectric ceramic layer.
When the Mg content in the third dielectric ceramic layer is high, it is possible to suppress the grain growth of the ceramic grains contained in the third dielectric ceramic layer, and it is possible to prevent short circuits between the internal electrode layers from occurring. can.

Mn is preferable as the element added to the third dielectric ceramic layer.
The Mn content in the third dielectric ceramic layer is preferably 0.01 mol% or more and 3.0 mol% or less with respect to 100 mol of Ti.
The Mn content in the third dielectric ceramic layer is preferably higher than the Mn content in the first dielectric ceramic layer and the second dielectric ceramic layer.
When the Mn content in the third dielectric ceramic layer is high, it is possible to suppress the grain growth of the ceramic grains contained in the third dielectric ceramic layer, and it is possible to prevent short circuits between the internal electrode layers from occurring. can.

In the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, elements other than the main component contained in each dielectric ceramic layer are diffused into the other dielectric ceramic layers. Is preferable.
In addition, some of the elements contained as additives in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer are added to the other adjacent dielectric ceramic layers and the internal electrode layer. It is preferably diffused.

FIG. 5 is a cross-sectional view taken along the line BB of the multilayer ceramic capacitor shown in FIG.
FIG. 5 is an LW cross section of the monolithic ceramic capacitor 1.
As shown in FIG. 5, the second internal electrode layer 22 is exposed on the second end surface 16 of the laminate 10, and the second dielectric ceramic layer 20b is exposed on the first end surface 15 of the laminate 10. Is exposed. Further, a third dielectric ceramic layer 41 and a third dielectric ceramic layer 42 are arranged on the first side surface 13 side and the second side surface 14 side of the laminated body 10, respectively.

As shown in FIG. 5, an interface 2220b exists between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. Further, interfaces 2241 and 2242 exist between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42. Further, there are interfaces 20b41 and 20b42 between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42.

Further, although not shown in FIG. 5, the first dielectric ceramic layer 20a is arranged on both sides of the second internal electrode layer 22 and the second dielectric ceramic layer 20b in the thickness direction. .. Therefore, it can be said that the first dielectric ceramic layer 20a has an interface that directly contacts the second dielectric ceramic layer 20b, the third dielectric ceramic layers 41 and 42, and the internal electrode layers 21 and 22. ..

Further, regarding the first internal electrode layer 21, similarly to the second internal electrode layer 22 shown in FIG. 5, the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric It has an interface with the ceramic layers 41 and 42.

In the first dielectric ceramic layer 20a, an element derived from the second dielectric ceramic layer 20b may be segregated in the vicinity of the interface with the second dielectric ceramic layer 20b. Further, in the first dielectric ceramic layer 20a, even if an element derived from the third dielectric ceramic layer 41 or 42 is segregated in the vicinity of the interface with the third dielectric ceramic layer 41 or 42. good.

Of the second dielectric ceramic layer 20b, an element derived from the first dielectric ceramic layer 20a may be segregated in the vicinity of the interface with the first dielectric ceramic layer 20a. Further, in the second dielectric ceramic layer 20b, elements derived from the third dielectric ceramic layer 41 or 42 are segregated in the vicinity of the interfaces 20b41 and 20b42 with the third dielectric ceramic layer 41 or 42. May be.

Of the third dielectric ceramic layers 41 and 42, an element derived from the first dielectric ceramic layer 20a may be segregated in the vicinity of the interface with the first dielectric ceramic layer 20a. Further, among the third dielectric ceramic layers 41 and 42, elements derived from the second dielectric ceramic layer 20b are segregated in the vicinity of the interfaces 20b41 and 20b42 with the second dielectric ceramic layer 20b. May be good.

Of the first internal electrode layer 21 and the second internal electrode layer 22, elements derived from the first dielectric ceramic layer 20a are segregated in the vicinity of the interface with the first dielectric ceramic layer 20a. May be good. Further, among the first internal electrode layer 21 and the second internal electrode layer 22, elements derived from the second dielectric ceramic layer 20b are segregated in the vicinity of the interface 2220b with the second dielectric ceramic layer 20b. You may be doing it. Further, of the first internal electrode layer 21 and the second internal electrode layer 22, the third dielectric ceramic layers 41 and 42 are located near the interfaces 2241 and 2242 with the third dielectric ceramic layers 41 and 42. The elements derived from the above may be segregated.
Further, the interface 2220b between the second internal electrode layer 22 and the second dielectric ceramic layer 20b and the interface 2241 or 2242 between the second internal electrode layer 22 and the third dielectric ceramic layer 41 or 42 are formed. In the vicinity of the contacting portion (the corner portion of the second internal electrode layer 22 on the first end face 15 side), the element derived from the second dielectric ceramic layer 20b and the third dielectric ceramic layer Both elements derived from 41 or 42 may be segregated.

The porosities of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may be the same, but may be different from each other.
The cut surface obtained by cutting the multilayer ceramic capacitor and exposing each dielectric ceramic layer is observed with a scanning electron microscope (SEM) at a magnification of 20000. A region with a visual field size of 6.3 μm × 4.4 μm was photographed at five locations so that the regions did not overlap each other, and the ratio of the area occupied by the voids to the entire visual field was calculated as the porosity from each SEM image obtained by image analysis. Then, the average value in 5 fields of view is calculated. However, when the third dielectric ceramic layer is composed of a plurality of layers, the porosity of each layer is obtained individually, and then the thickness of the layer is divided by the thickness of the third dielectric ceramic layer and the value of each layer. The sum of the products of the porosities is taken as the porosity of the third dielectric ceramic layer.

The first dielectric ceramic layer, the second dielectric ceramic layer and the third dielectric ceramic layer preferably contain ceramic grains.
When the dielectric ceramic layer contains ceramic grains, interfacial resistance is generated at the interface between the ceramic grains, the insulation resistance between the internal electrode layers is increased, and the occurrence of a short circuit can be prevented.

Rare earths are preferably present at the interface of the ceramic grains.
The presence of rare earths at the interface of ceramic grains can be confirmed by elemental analysis by TEM-EDX. Examples of rare earths include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y and the like.
The presence of rare earths at the interface of the ceramic grain can further increase the interfacial resistance of the dielectric ceramic layer and further improve the reliability of the monolithic ceramic capacitor. In addition, Mg, Mn, Si and the like may be present.

Rare earths are preferably present in an amount of 0.2 mol% or more and 5 mol% or less with respect to 100 mol of Ti.
The Ti 100 mol here is based on the premise that the dielectric ceramic material constituting the dielectric ceramic layer _{contains a compound having a perovskite type structure (structure shown by ABO 3} ; B = Ti) as a main component. It defines the abundance of rare earths.
The abundance of rare earths can be confirmed by TEM-EDX.

In the multilayer ceramic capacitor, the thickness of the first internal electrode layer and the second internal electrode layer is preferably 0.4 μm or less, respectively.
The thickness of the first internal electrode layer and the second internal electrode layer is preferably 0.38 μm or less, respectively.
Further, the thickness of the first internal electrode layer and the second internal electrode layer is preferably 0.25 μm or more, respectively.

The thickness of the first dielectric ceramic layer is preferably 0.55 μm or less.
The thickness of each of the first dielectric ceramic layers is preferably 0.4 μm or more.

The thickness of the second dielectric ceramic layer is preferably the same as the thickness of the internal electrode layer.

The thicknesses of the third dielectric ceramic layers 41 and 42 are preferably 5 μm or more and 40 μm or less, and more preferably 5 μm or more and 20 μm or less, respectively. It is preferable that the thicknesses of the third dielectric ceramic layers 41 and 42 are the same as each other. However, it is preferable that the outer layer 41b is thicker than the inner layer 41a while the inner layer 41a and the outer layer 41b satisfy the above range. Similarly, it is preferable that the outer layer 42b is thicker than the inner layer 42a while the inner layer 42a and the outer layer 42b satisfy the above range.

From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor 1, the inner layer 41a is preferably thinner than the outer layer 41b. Similarly, the inner layer 42a is preferably thinner than the outer layer 42b.

The thicknesses of the inner layers 41a and 42a are preferably 0.1 μm or more and 20 μm or less, respectively. It is preferable that the inner layers 41a and 42a have the same thickness.

The thicknesses of the outer layers 41b and 42b are preferably 5 μm or more and 20 μm or less, respectively. It is preferable that the outer layers 41b and 42b have the same thickness.

The thickness of each ceramic layer in the side margin portion means an average value when the thickness of the third dielectric ceramic layer is measured at a plurality of points along the stacking (T) direction.

[Manufacturing method of multilayer ceramic capacitors]
The method for producing a monolithic ceramic capacitor of the present invention preferably comprises a plurality of unfired first dielectric ceramic layers, a plurality of second dielectric ceramic layers, and a plurality of pairs of first internal electrode layers. It has a laminated structure composed of a second internal electrode layer, and has the first internal electrode layer and the second interior on the first side surface and the second side surface facing each other in the width direction orthogonal to the stacking direction. Unfired by the step of preparing the green chip with the exposed electrode layer and by forming the unfired third dielectric ceramic layer on the first side surface and the second side surface of the green chip. In the step of preparing the green chip, which comprises a step of producing the laminate and a step of firing the unfired laminate, the unfired first surface of the unfired first dielectric ceramic layer is provided. The internal electrode layer or the second internal electrode layer of the above is formed, and an unfired second dielectric ceramic layer is formed in a region where the first internal electrode layer and the second internal electrode layer are not provided. In the step of laminating the ceramic green sheets to prepare the unfired laminate, an unfired inner layer is formed on the first side surface and the second side surface, and the unfired outer layer is formed on the outermost side. By forming, the unfired side margin portion is formed, and at least one of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is formed. The composition of the ceramic layer is different.

Hereinafter, an example of a method for manufacturing the multilayer ceramic capacitor 1 shown in FIG. 1 will be described.

First, a ceramic green sheet to be the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 is prepared. The ceramic green sheet contains a binder, a solvent, and the like in addition to the ceramic raw material including the dielectric ceramic material described above. Further, an additive containing rare earths may be added to the ceramic raw material. By changing the elements contained in the additive, the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer can be changed. It is preferable that the ceramic raw materials as the main components are the same.
The ceramic green sheet is formed on a carrier film, for example, by using a die coater, a gravure coater, a micro gravure coater, or the like.

6, 7 and 8 are plan views schematically showing an example of a ceramic green sheet. 6, 7 and 8, respectively, show a first ceramic green sheet 101 for forming the inner layer portion 30, a second ceramic green sheet 102 for forming the inner layer portion 30, and an outer layer portion 31, respectively. Alternatively, a third ceramic green sheet 103 for forming 32 is shown.

In FIGS. 6, 7, and 8, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are not separated for each multilayer ceramic capacitor 1. 6, 7, and 8 show cutting lines X and Y for cutting each multilayer ceramic capacitor 1. The cutting line X is parallel to the length (L) direction, and the cutting line Y is parallel to the width (W) direction.

As shown in FIG. 6, the first ceramic green sheet 101 corresponds to the first internal electrode layer 21 on the unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer 20a. The unfired first internal electrode layer 121 is formed. Further, an unfired second dielectric ceramic layer 120b corresponding to the second dielectric ceramic layer 20b is formed in a region where the unfired first internal electrode layer 121 is not formed.
The unfired first dielectric ceramic layer 120a and the unfired second dielectric ceramic layer 120b are also unfired dielectric ceramic layers 120 corresponding to the dielectric ceramic layer 20.

As shown in FIG. 7, the second ceramic green sheet 102 corresponds to the second internal electrode layer 22 on the unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer 20a. An unfired second internal electrode layer 122 is formed. Further, an unfired second dielectric ceramic layer 120b corresponding to the second dielectric ceramic layer 20b is formed in a region where the unfired second internal electrode layer 122 is not formed.
The unfired first dielectric ceramic layer 120a and the unfired second dielectric ceramic layer 120b are also unfired dielectric ceramic layers 120 corresponding to the dielectric ceramic layer 20.

The method for producing the first ceramic green sheet 101 shown in FIG. 6 and the second ceramic green sheet shown in FIG. 7 is not particularly limited, but the surface of the unfired first dielectric ceramic layer 120a is formed by firing. Examples thereof include a method of applying a dielectric paste which is a mixture of a dielectric ceramic and a solvent which becomes the dielectric ceramic layer 20b of No. 2 and a conductive paste which becomes an internal electrode layer 21 or 22 by firing to a predetermined region, respectively. ..
The order in which the dielectric paste and the conductive paste are applied is not particularly limited, and the conductive paste may be applied after the dielectric paste is applied first, or the conductive paste may be applied first and then the dielectric paste. May be given.
Further, the dielectric paste and the conductive paste may be applied so that a part of the surface of the paste applied earlier is covered with a part of the paste applied later.

As shown in FIG. 8, the third ceramic green sheet 103 corresponding to the outer layer portion 31 or 32 is composed of an unfired first dielectric ceramic layer 120a corresponding to the first dielectric ceramic layer, and is unfired. The internal electrode layer 121 or 122 of the above and the unfired second dielectric ceramic layer 120b are not formed.

The first internal electrode layer 121 and the second internal electrode layer 122 can be formed by using an arbitrary conductive paste. For the formation of the first internal electrode layer 121 and the second internal electrode layer 122 by the conductive paste, for example, a screen printing method, a gravure printing method, or the like can be used.

The first internal electrode layer 121 and the second internal electrode layer 122 are arranged over two regions adjacent to each other in the length (L) direction separated by the cutting line Y, and extend in a strip shape in the width (W) direction. There is. In the first internal electrode layer 121 and the second internal electrode layer 122, the regions partitioned by the cutting line Y are shifted one row at a time in the length (L) direction. That is, the cutting line Y passing through the center of the first internal electrode layer 121 passes through the region between the second internal electrode layers 122 (that is, the center of the second dielectric ceramic layer 120b), and the second internal electrode layer. A cutting line Y passing through the center of 122 passes through the region between the first internal electrode layers 121 (ie, the center of the second dielectric ceramic layer 120b).

Then, the mother block is produced by laminating the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103.

FIG. 9 is an exploded perspective view schematically showing an example of the mother block.
In FIG. 9, for convenience of explanation, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are shown in an exploded manner. In the actual mother block 104, the first ceramic green sheet 101, the second ceramic green sheet 102, and the third ceramic green sheet 103 are pressure-bonded and integrated by means such as a hydrostatic press.

In the mother block 104 shown in FIG. 9, the first ceramic green sheet 101 and the second ceramic green sheet 102 corresponding to the inner layer portion 30 are alternately laminated in the lamination (T) direction. Further, a third ceramic green sheet 103 corresponding to the outer layer portions 31 and 32 is laminated on the upper and lower surfaces of the alternately laminated first ceramic green sheet 101 and the second ceramic green sheet 102 in the lamination (T) direction. Has been done. In FIG. 9, three third ceramic green sheets 103 are laminated, but the number of third ceramic green sheets 103 can be changed as appropriate.

A plurality of green chips are produced by cutting the obtained mother block 104 along the cutting lines X and Y (see FIGS. 6, 7 and 8). For this cutting, for example, methods such as dicing, push-cutting, and laser cutting are applied.

FIG. 10 is a perspective view schematically showing an example of a green chip.
The green chip 110 shown in FIG. 10 has a plurality of pairs of the first internal electrode layers 121 and the second interior of the plurality of first dielectric ceramic layers 120a and the second dielectric ceramic layers 120b in an unfired state. It has a laminated structure composed of an electrode layer 122 and the electrode layer 122. The first side surface 113 and the second side surface 114 of the green chip 110 are the surfaces revealed by cutting along the cutting line X, and the first end surface 115 and the second end surface 116 are exposed by cutting along the cutting line Y. It is a face. The first internal electrode layer 121 and the second internal electrode layer 122 are exposed on the first side surface 113 and the second side surface 114. Further, only the first internal electrode layer 121 and the second dielectric ceramic layer 120b are exposed on the first end surface 115, and the second internal electrode layer 122 and the second inner electrode layer 122 and the second are exposed on the second end surface 116. Only the dielectric ceramic layer 120b is exposed.
The first dielectric ceramic layer 120a is exposed on the first side surface 113, the second side surface 114, the first end face 115 and the second end face 116, but the second dielectric ceramic layer is arranged. The exposed areas are different in the area to be exposed.
That is, the second dielectric ceramic layer 120b arranged on the first end face 115 side is not exposed on the second end face 116, and the second dielectric placed on the second end face 116 side. The ceramic layer 120b is not exposed on the first end face 115.

An unfired laminate is produced by forming an unfired third dielectric ceramic layer on the first side surface 113 and the second side surface 114 of the obtained green chip 110. The unfired third dielectric ceramic layer is formed, for example, by attaching a ceramic green sheet made of dielectric ceramic to the first side surface and the second side surface of the green chip.

For example, when the third dielectric ceramic layer is composed of two layers, an inner layer and an outer layer, first, in order to prepare a ceramic green sheet for the inner layer _{, a dielectric ceramic material containing BaTIO 3} or the like as a main component is used. In addition to the ceramic raw material contained, a ceramic slurry containing a binder, a solvent, etc. is prepared. Si, which is a sintering aid, may be added to the ceramic slurry for the inner layer. The inner layer has a role of adhering to the green chip 110.
Further, a liquid phase type metal may be added to the ceramic slurry for the inner layer, or more rare earth elements, Mg, and Mn may be added to the ceramic slurry for the inner layer than the ceramic green sheet for forming the inner layer portion. good. By doing so, it is possible to suppress the grain growth of the ceramic grains contained in the dielectric ceramic layer sandwiched between the widthwise end portions of the internal electrode layer.

Next, in order to prepare a ceramic green sheet for the outer layer _{, a ceramic raw material containing a dielectric ceramic material containing BaTiO 3} or the like as a main component, as well as a ceramic slurry containing a binder, a solvent, or the like is prepared. Further, Si, which is a sintering aid, may be added to the ceramic slurry for the outer layer. Further, it is preferable that the amount of Si contained in the ceramic green sheet for the inner layer is larger than the amount of Si contained in the ceramic green sheet for the outer layer. The high content rate is determined by the size of the area of the region where Si is detected by imaging the cross section with WDX.

A ceramic green sheet for the outer layer is formed by applying the ceramic slurry for the outer layer to the surface of the resin film and drying it. The ceramic green sheet for the inner layer is formed by applying the ceramic slurry for the inner layer to the surface of the ceramic green sheet for the outer layer on the resin film and drying the ceramic slurry for the inner layer. From the above, a ceramic green sheet having a two-layer structure can be obtained.

The ceramic green sheet having a two-layer structure can also be obtained, for example, by forming each of the ceramic green sheet for the outer layer and the ceramic green sheet for the inner layer in advance, and then laminating each of them. Further, the ceramic green sheet is not limited to two layers, and may be a plurality of layers having three or more layers.

Then, the ceramic green sheet is peeled off from the resin film.

Subsequently, the ceramic green sheet for the inner layer of the ceramic green sheet and the first side surface 113 of the green chip 110 face each other and are pressed and punched to form an unfired side margin portion 41. Further, also on the second side surface 114 of the green chip 110, the unfired side margin portion 42 is formed by pressing and punching the ceramic green sheet for the inner layer of the ceramic green sheet so as to face each other. At this time, it is preferable to apply an organic solvent as an adhesive to the side surface of the green chip in advance. From the above, an unfired laminate can be obtained.

It is preferable to perform barrel polishing or the like on the unfired laminate obtained by the above method. By polishing the unfired laminate, the corners and ridges of the fired laminate 10 are rounded.

Then, in the unfired laminate, a conductive paste for an external electrode containing Ni and a ceramic material is applied onto each of the end faces 115 of the first end face 115 and the second end face 116 of the green chip 110.

The conductive paste for an external electrode preferably contains the same dielectric ceramic material as the first dielectric ceramic layer, the second dielectric ceramic layer, or the outer layer as the ceramic material. The content of the ceramic material in the conductive paste for the external electrode is preferably 15% by weight or more. The content of the ceramic material in the conductive paste for the external electrode is preferably 25% by weight or less.

Next, the unfired laminate coated with the conductive paste for the external electrode is subjected to a degreasing treatment under predetermined conditions in a nitrogen atmosphere, and then in a nitrogen-hydrogen-steam mixed atmosphere. Bake at temperature. As a result, the unfired laminate and the conductive paste for the external electrode are fired at the same time, and the laminate 10, the Ni layer connected to the first internal electrode layer 21, and the second internal electrode are fired by the so-called cofire method. A Ni layer connected to the layer 22 is formed at the same time. Then, the first plating layer by Ni plating and the second plating layer by Sn plating are laminated in order on the surface of each Ni layer. As a result, the first external electrode 51 and the second external electrode 52 are formed.

The laminated body 10, the first external electrode 51, and the second external electrode 52 may be formed at different timings by the so-called post-fire method. Specifically, first, the unfired laminate is subjected to degreasing treatment under predetermined conditions in a nitrogen atmosphere, and then fired at a predetermined temperature in a nitrogen-hydrogen-steam mixed atmosphere. , The laminated body 10 is formed. Then, a conductive paste containing Cu powder is applied and baked on each of the first end face 15 and the second end face 16 of the laminate 10. As a result, a base electrode layer connected to the first internal electrode layer 21 and a base electrode layer connected to the second internal electrode layer 22 are formed. Then, on the surface of each base electrode layer, a conductive resin layer containing conductive particles (for example, metal particles such as Cu, Ag, Ni, etc.) and a resin, and a first plating layer by Ni plating, The second plating layer by Sn plating is laminated in order. As a result, the first external electrode 51 and the second external electrode 52 are formed.

As described above, the monolithic ceramic capacitor 1 is manufactured.

In the above-described embodiment, the mother block 104 is cut along the cutting lines X and Y to obtain a plurality of green chips, and then unfired third dielectric ceramic layers are formed on both side surfaces of the green chips. , It is also possible to change as follows.

That is, by cutting the mother block only along the cutting line X, a plurality of rod-shaped greens in which the first internal electrode layer and the second internal electrode layer are exposed on the side surface appeared by the cutting along the cutting line X. After obtaining the block body, an unfired third dielectric ceramic layer was formed on both side surfaces of the green block body, and then cut along the cutting line Y to obtain a plurality of unfired laminates, and then unfired. The fired laminate may be fired. After firing, a monolithic ceramic capacitor can be manufactured by performing the same steps as in the above-described embodiment.

The present invention further comprises the following configurations [1] to [7].

[1] Alloy portion between the dielectric ceramic layer, the internal electrode layer, and the external electrode In the multilayer ceramic capacitor 1 of the present invention, as shown in FIG. 11, the second dielectric ceramic layer 20b and the first internal electrode A second alloy portion 320 is formed between the layer 21 and between the second dielectric ceramic layer 20b and the second internal electrode layer 22. Further, in the multilayer ceramic capacitor 1 of the present invention, between the first dielectric ceramic layer 20a and the first internal electrode layer 21, and between the first dielectric ceramic layer 20a and the second internal electrode layer 22. A first alloy portion 310 is formed in each of the spaces.

As shown in FIG. 12, the metal element 321a is segregated at the interface 2220b of the second internal electrode layer 22 with the second dielectric ceramic layer 20b. The second alloy portion 320 is formed by a segregation layer 321 which is a layered segregation by the metal element 321a. Similarly, the metal element 321a segregates the segregation layer 321 at the interface 2220b with the second dielectric ceramic layer 20b in the first internal electrode layer 21, and the segregation layer 321 forms the second alloy. The portion 320 is formed. A second alloy portion 320 is formed on the surfaces of the first internal electrode layer 21 and the second internal electrode layer 22 on the side of the second dielectric ceramic layer 20b, respectively. The second alloy portion 320 is formed between the first internal electrode layer 21 and the second dielectric ceramic layer 20b and between the second internal electrode layer 22 and the second dielectric ceramic layer 20b. Will be.

Further, as shown in FIG. 12, the metal element 311a is segregated at the interface 2220a of the second internal electrode layer 22 with the first dielectric ceramic layer 20a. The first alloy portion 310 is formed by a segregation layer 311 which is a layered segregation by the metal element 311a. Similarly, at the interface 2220a of the first internal electrode layer 21 with the first dielectric ceramic layer 20a, the metal element 311a segregates to form the segregation layer 311, and the segregation layer 311 forms the first alloy. The portion 310 is formed. A first alloy portion 310 is formed on the surfaces of the first internal electrode layer 21 and the second internal electrode layer 22 on the side of the first dielectric ceramic layer 20a, respectively. The first alloy portion 310 is formed between the first internal electrode layer 21 and the first dielectric ceramic layer 20a and between the second internal electrode layer 22 and the first dielectric ceramic layer 20a. Will be.

There are a plurality of types of segregated metal elements 321a forming the second alloy portion 320. The plurality of types of metal elements 321a forming the segregation layer 321 include a metal element containing the largest amount of the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and a second dielectric material. Contains elements derived from the ceramic layer 20b. The same applies to the segregated metal element 311a forming the first alloy portion 310. That is, the metal element 311a contains the most abundant metal element among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and the element derived from the first dielectric ceramic layer 20a. ,including.

As the metal element contained most in the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, for example, one of Ni, Cu, Ag, Pd, Au, and Pt is used. Can be mentioned. On the other hand, examples of the elements derived from the second dielectric ceramic layer 20b and the first dielectric ceramic layer 20a include metal elements as additives. Specifically, any one of the metal groups of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, Y, and Ge. The above metal elements are mentioned, and among them, Sn, Ga, and Ge are particularly preferable. Hereinafter, the metal group may be referred to as a metal group M.

In the segregation of the metal element 321a, the metal element contained in the second dielectric ceramic layer 20b moves to the first internal electrode layer 21 and the second internal electrode layer 22 when the second dielectric ceramic layer 20b is fired. It is caused by doing. Further, in the segregation of the metal element 311a, the metal element contained in the first dielectric ceramic layer 20a is the first internal electrode layer 21 and the second internal electrode layer 22 when the first dielectric ceramic layer 20a is fired. Caused by moving to.

When the first dielectric ceramic layer 20a _{contains BaTiO 3} as a main component, the second alloy portion 320 is a metal element contained in the second dielectric ceramic layer 20b rather than the first alloy portion 310. That is, the molar ratio of any one or more of the above metal groups M to 100 mol of Ti is high.

FIG. 13 shows the surface of the laminated body 10 including the central portion in the width (W) direction, the length (L) direction, and the laminated (T) direction. In the multilayer ceramic capacitor 1 of the present invention, in the plane shown in FIG. 13, the first internal electrode layer 21 has a length at an end portion in the length (L) direction that is not connected to the second external electrode 52. Includes a plurality of first interspersed internal electrodes 210 interspersed in the (L) direction. Further, the second internal electrode layer 22 is a plurality of second components scattered discontinuously in the length (L) direction at the end portion in the length (L) direction that is not connected to the first external electrode 51. Includes interspersed internal electrodes 220. Each of the first scattered internal electrodes 210 and the second scattered internal electrodes 220 is formed inside the second dielectric ceramic layer 20b. The plurality of first scattered internal electrodes 210 may be connected to the first internal electrode layer 21 while extending in the width (W) direction. Further, the plurality of second scattered internal electrodes 220 may also be connected to the second internal electrode layer 22 while extending in the width (W) direction.

A fourth alloy portion 340 is formed around each of the first scattered internal electrodes 210 and the second scattered internal electrodes 220. The fourth alloy portion 340 is formed by a segregation layer 341 which is a layered segregation by the metal element 341a. The metal element 341a is the metal element contained most among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and the metal group M derived from the second dielectric ceramic layer 20b. Includes any one or more of the metal elements.

In the segregation of the metal element 341a, the metal element contained in the second dielectric ceramic layer 20b is the first interspersed internal electrode 210 and the second interspersed internal electrode 220 when the second dielectric ceramic layer 20b is fired. Caused by moving to. Segregation of the metal element 341a occurs around one or more of the first interspersed internal electrodes 210 and the plurality of second interspersed internal electrodes 220. Alternatively, it may occur around the entire first interspersed internal electrode 210 and around the entire second interspersed internal electrode 220.

As shown in FIG. 14, in the multilayer ceramic capacitor 1 of the present invention, between the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21, and the third dielectric ceramic layer 41 and A third alloy portion 330 is formed between the 42 and the second internal electrode layer 22, respectively.

As shown in FIG. 14, the metal element 331a is segregated at the interface 2220c between the first internal electrode layer 21 and the third dielectric ceramic layers 41 and 42. Further, the metal element 331a is also segregated at the interface 2220c between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42. The third alloy portion 330 is formed by a layered segregation by the metal element 331a, that is, a segregation layer 331. A third alloy portion 330 is formed on the surfaces of the third dielectric ceramic layer 41 side and the 42 side of the first internal electrode layer 21 and the second internal electrode layer 22, respectively. The third alloy portion 330 is provided between the first internal electrode layer 21 and the third dielectric ceramic layers 41 and 42, and between the second internal electrode layer 22 and the third dielectric ceramic layers 41 and 42. Will be formed in each of.

The metal element 331a is a metal element contained in the largest amount among the metal elements constituting the first internal electrode layer 21 and the second internal electrode layer 22, and the metal derived from the third dielectric ceramic layers 41 and 42. Includes any one or more metal elements of the group M. Examples of the element derived from the third dielectric ceramic layers 41 and 42 include a metal element as an additive. Specifically, any one or more kinds of metal elements in the metal group M can be mentioned.

In the segregation of the metal element 331a, the metal element contained in the third dielectric ceramic layers 41 and 42 is the first internal electrode layer 21 and the second internal electrode when the third dielectric ceramic layers 41 and 42 are fired. It occurs by moving to layer 22.

In the multilayer ceramic capacitor 1 of the present invention, when the first external electrode 51 and the second external electrode 52 each include a Ni layer as a base electrode layer and are formed by the cofire method, as shown in FIG. , A fifth alloy portion 350 is formed on the Ni layer.

FIG. 15 shows a state in which the fifth alloy portion 350 is formed at the interface 51b of the first external electrode 51 with the second dielectric ceramic layer 20b. The fifth alloy portion 350 is formed by a segregation layer 351 which is a layered segregation by the metal element 351a. Similarly, a fifth alloy portion 350 is formed at the interface 51b of the second external electrode 52 with the second dielectric ceramic layer 20b by segregation of the metal element 351a. The segregation of the metal element 351a means that the metal element contained in the second dielectric ceramic layer 20b moves to the first external electrode 51 and the second external electrode 52 when the second dielectric ceramic layer 20b is fired. Caused by.

In the laminated body 10 of the multilayer ceramic capacitor 1 of the present invention, the end portions of the first internal electrode layer 21, the second internal electrode layer 22, and the second dielectric ceramic layer 20b that are adjacent to each other are , It may be a mode in which they overlap each other. For example, as shown in FIG. 16, the end portion of the second dielectric ceramic layer 20b may be superimposed on the end portion of the second internal electrode layer 22. Further, as shown in FIG. 17, the end portion of the second dielectric ceramic layer 20b may be superimposed on the end portion of the first internal electrode layer 21. In the embodiment in which the ends are overlapped in this way, the first internal electrode layer 21 and the second internal electrode layer 22 may be superimposed on the second dielectric ceramic layer 20b, respectively.

In the multilayer ceramic capacitor 1 of the present invention, between the second dielectric ceramic layer 20b and the first internal electrode layer 21, and between the second dielectric ceramic layer 20b and the second internal electrode layer 22. In each of the spaces, one metal element contained most among the metal elements constituting the internal electrode layer, Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, A second alloy portion 320 containing any one or more metal elements of the metal group M of Ru, Os, Fe, V, and Y is formed.

An electric field is likely to be concentrated at each end of the first internal electrode layer 21 and the second internal electrode layer 22 in contact with the second dielectric ceramic layer 20b, and therefore, the reliability as a multilayer ceramic capacitor is improved. There was a risk of lowering it. However, in the multilayer ceramic capacitor 1 of the present invention, the second alloy portion 320 is formed between the second dielectric ceramic layer 20b and the first internal electrode layer 21 and the second internal electrode layer 22. As a result, the electric field concentration can be suppressed and the reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, when the first dielectric ceramic layer 20a contains Ba and Ti, the space between the first dielectric ceramic layer 20a and the first internal electrode layer 21 and the first Between the dielectric ceramic layer 20a of 1 and the second internal electrode layer 22, each of the metal element contained most among the metal elements constituting the internal electrode layer, and any one of the metal group M described above. A first alloy portion 310 containing one or more kinds of metal elements is formed. The second alloy portion 320 has a higher molar ratio to 100 mol of Ti in the content of the metal group M than the first alloy portion 310.

As a result, the electric field concentration is suppressed by the second alloy portion 320 in the vicinity of the interface between the first internal electrode layer 21 and the second internal electrode layer 22 with the second dielectric ceramic layer 20b, and the reliability is reduced. Can be improved. Further, the first alloy portion 320 formed at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 in contact with the second dielectric ceramic layer 20b where electric field concentration is likely to occur is first. By increasing the molar ratio of the metal group M to 100 mol of Ti as compared with the first alloy portion 310 formed on the dielectric ceramic layer 20a side, the electric field concentration on the second dielectric ceramic layer 20b side can be increased. It can be effectively suppressed and the reliability can be further improved.

By controlling the amount of metal of the metal group M added to each of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b, the first alloy portion 310 and the second alloy portion 320 The thickness and the concentration of the contained metal group M can be controlled. For example, when the concentration of the metal group M added to the second dielectric ceramic layer 20b is higher than that of the first dielectric ceramic layer 20a, as shown in FIG. 12, the metal group M approaches the second dielectric ceramic layer 20b. Therefore, the thickness of the second alloy portion 320 is increased, or the concentration of the metal group M is increased, and in some cases, both of them are changed.

In the laminated ceramic capacitor 1 of the present invention, the first internal electrode layer 21 is formed on the surface of the laminated body 10 including the central portion in the width (W) direction, the length (L) direction, and the laminated (T) direction. The end portion in the length (L) direction that is not connected to the second external electrode 52 includes the first scattered internal electrodes 210 that are discontinuously scattered in the length (L) direction, and includes a second internal electrode. The electrode layer 22 includes second interspersed internal electrodes 220 that are discontinuously interspersed in the length (L) direction at the end portion in the length (L) direction that is not connected to the first external electrode 51. , The metal element containing the largest amount of the metal elements constituting the internal electrode layer around each of the first scattered internal electrodes 210 and the second scattered internal electrodes 220, and any of the above metal group M. A fourth alloy portion 340 containing one or more kinds of metal elements is formed.

When the first interspersed internal electrodes 210 and the second interspersed internal electrodes 220 are connected to the first internal electrode layer 21 and the second internal electrode layer 22 while extending in the width (W) direction, the first scattered internal electrodes 210 and the second scattered internal electrodes 220 are connected to each other, respectively. If the electric field is concentrated on the connected portion, dielectric breakdown may occur and reliability may decrease. However, in the multilayer ceramic capacitor 1 of the present invention, dielectric breakdown due to electric field concentration is caused by the fourth alloy portion 340 formed around each of the first scattered internal electrodes 210 and the second scattered internal electrodes 220. It can be suppressed and reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, between the third dielectric ceramic layers 41 and 42 and the first internal electrode layer 21, and between the third dielectric ceramic layers 41 and 42 and the second internal electrode. A third layer containing the most abundant metal element among the metal elements constituting the internal electrode layer and one or more kinds of metal elements in the above metal group M, respectively, between the layers 22. The alloy portion 330 is formed.

As a result, the electric field concentration of the first internal electrode layer 21 and the second internal electrode layer 22 near the interface with the third dielectric ceramic layers 41 and 42 is suppressed by the third alloy portion 330. Reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, the first external electrode 51 and the second external electrode 52 contain Ni, the second dielectric ceramic layer 20b, the first external electrode 51, and the second external electrode. A fifth alloy portion 350 is formed between the 52 and 52, in which one or more of the metal elements of the metal group M are segregated into Ni.

As a result, the distance between the first internal electrode layer 21 and the second external electrode 52 and between the second internal electrode layer 22 and the first external electrode 51, that is, the second dielectric ceramic Even when the distance of the layer 20b in the length (L) direction is narrow, for example, less than 15 μm, the presence of the fifth alloy portion 350 causes insulation failure due to electric field concentration between the internal electrode layer and the external electrode. Is less likely to occur, thus improving reliability.

[Test Example 1]
Next, in the multilayer ceramic capacitor 1 of the present invention, Test Example 1 for verifying the effects of the first alloy portion 310, the second alloy portion 320, and the third alloy portion 330 will be described.

-TEM analysis In the method for manufacturing a multilayer ceramic capacitor of the present invention described above, the laminate 10 obtained by firing the green chip 110 without cofiring the first external electrode 51 and the second external electrode 52. Then, polishing is performed from the first side surface 13 side and the second side surface 14 side, and a polished body having a central portion in the width (W) direction as shown in FIG. 18 is obtained as a test body.
The type of metal element and the amount of metal (metal concentration) contained in the first alloy portion 310 were analyzed as follows.
As shown in FIG. 18, a virtual line OL1 orthogonal to the length (L) direction is assumed in the central portion in the length (L) direction. Then, along the virtual line OL1, a region in which the first dielectric ceramic layer 20a related to the acquisition of the capacitance of the polished body, the first internal electrode layer 21, and the second internal electrode layer 22 are laminated. Is divided into three equal parts in the stacking direction, and is divided into three regions, an upper region E1, a central region E2, and a lower region E3.
The upper region E1, the central region E2, and the lower region E3 are cut out from the polished body, and each of the upper region E1, the central region E2, and the lower region E3 is thinned by Ar ion milling or the like, and three thin film samples are obtained from each region. obtain.

The three thin film samples of the upper region E1, the central region E2, and the lower region E3 of the test body obtained as described above were subjected to TEM observation and element mapping by EDX attached to the TEM.
As a result, no significant difference was observed between the upper region E1 and the lower region E3 and the central region E2. Therefore, the result obtained from the central region E2 is regarded as the fine structure of the dielectric ceramic layer and the internal electrode layer. As a result, the type of metal element and the amount of metal (metal concentration) contained in the first alloy portion 310 can be known.
Further, the type of metal element and the amount of metal (metal concentration) contained in the second alloy portion 320 are the same as above in the region of one end in the length (L) direction in which the second alloy portion 320 exists. It can be analyzed by obtaining a sample. That is, in the polished body shown in FIG. 18, a virtual line OL2 orthogonal to the length (L) direction is assumed at one end in the length (L) direction, and is divided into three equal parts in the stacking direction along the virtual line OL2. A thin film sample of three regions, an upper region E4, a central region E5, and a lower region E6, is obtained. Then, the three thin film samples of the upper region E4, the central region E5, and the lower region E6 are subjected to TEM observation and element mapping by the EDX attached to the TEM, and the types of metal elements contained in the second alloy portion 320 and the types of metal elements contained in the second alloy portion 320 and The amount of metal (metal concentration) was examined.

For the second alloy portion and the first alloy portion, the Sn concentration was examined by analysis using an EDX mapping image using a TEM observation image. The TEM measurement points were measured at intervals of about 5 nm to 10 nm. At the interface between the internal electrode layer and the dielectric ceramic layer, the region where the observed value obtained at least 3 times that of other measurement points is obtained is defined as the alloy portion, and the average value thereof is defined as the metal concentration of the alloy portion.

Eighteen multilayer ceramic capacitors of Test Examples 1-1 to 1-5 shown in Table 1 were prepared. In Test Example 1-2, in the multilayer ceramic capacitor of the present invention, the first internal electrode layer 21 and the second internal electrode layer 22 are made of Ni, and the first dielectric ceramic layer 20a and the second dielectric material are used. The same amount of Sn as an additive was added to the ceramic layer 20b. In Test Examples 1-3 to 1-5, the amount of Sn added to the second dielectric ceramic layer 20b is gradually increased as compared with Test Example 1-2. Further, Test Example 1-1 was a monolithic ceramic capacitor having the same conditions as in Test Examples 1-2 to 1-5, except that Sn was not added to the second dielectric ceramic layer 20b.

For the multilayer ceramic capacitors of Test Examples 1-1 to 1-5, measure the resistance value (kΩ) in an environment of room temperature of 150 ° and apply a voltage of 6.3V, and check the MTTF (Mean Time Between Failure). , Judgment was made. For MTTF, the time when the resistance value becomes 10 kΩ or less is set, the judgment when the MTTF is 15.3 hours (hr) or less is set as x, and the judgment is made when the resistance value exceeds 15.3 hours (hr) and is up to 30 hours. (Good), over 30 hours was judged as ◎ (excellent). The results are also shown in Table 1. When the coverage of the internal electrode layer is less than 80%, it is difficult to obtain the capacitance, so it is not possible to measure.

According to Table 1, due to the formation of the second alloy portion, the MTTF is good beyond the specified time of 15.3 hours, and the higher the Sn concentration, the better. Understand. On the other hand, in Test Example 1-1 in which the second alloy portion was not formed by Sn, the MTTF could not exceed the specified time. As a result, it was confirmed that the second alloy portion enhances the reliability of the monolithic ceramic capacitor.

Next, in addition to Test Example 1-1, 18 multilayer ceramic capacitors of Test Examples 1-6 to 1-9 shown in Table 2 were prepared. In Test Example 1-6, in Test Example 1-2, Sn as an additive was further added to the third dielectric ceramic layer in the same amount as the first dielectric ceramic layer and the second dielectric ceramic layer. .. In Test Examples 1-7 to 1-9, the amount of Sn added to the third dielectric ceramic layer is gradually increased as compared with Test Example 1-6. In Test Example 1-1, Sn was not added to the third dielectric ceramic layer.

For Test Examples 1-1 and 1-6 to 1-9, MTTF determination was performed in the same manner as in Test Examples 1-1 to 1-5. The results are shown in Table 2.

According to Table 2, the MTTF is good beyond the specified time of 15.3 hours due to the formation of the third alloy portion together with the second alloy portion, and the higher the Sn concentration, the higher the MTTF. It turns out that it is as good as it is. On the other hand, in Test Example 1-1 in which neither the second alloy portion nor the third alloy portion was formed by Sn, the MTTF could not exceed the specified time. As a result, it was confirmed that the second alloy portion and the third alloy portion enhance the reliability of the multilayer ceramic capacitor.

[2] Average particle diameter of dielectric particles contained in the region near the intersection FIG. 19 is a surface of the multilayer ceramic capacitor 1 of the present invention including the length (L) direction and the width (W) direction. The surface including the dielectric ceramic layer 20b and the second internal electrode layer 22 of the above is shown. As shown in FIG. 19, the second dielectric ceramic layer 20b, the second internal electrode layer 22, and the second inner electrode layer 22 are provided on both sides of the multilayer ceramic capacitor 1 on the side of the first end surface 15 in the width (W) direction. It has an interface 400 surrounded by the dielectric ceramic layers 41 and 42 of 3. This intersection 400 is the intersection of the interface 2220b between the second dielectric ceramic layer 20b and the second internal electrode layer 22 and the inner surface 401 of the third dielectric ceramic layers 41 and 42 in the width (W) direction. Is. Similarly, on both sides of the end portion on the second end surface 16 side in the width (W) direction, the second dielectric ceramic layer 20b, the first internal electrode layer 21, and the third dielectric ceramic are also provided. It has an intersection 400 of interfaces surrounded by layers 41 and 42.

The region inside the circle 400r having a radius of 5 μm centered on the intersection 400 is defined as the region near the second intersection 420. The region inside the circle 400r having a radius of 5 μm centered on the intersection 400 is defined as the region near the third intersection 430. The area inside the circle 400r also includes the line of the circle 400r. In the following description, the region 420 near the second intersection on the second dielectric ceramic layer 20b side and the region 430 near the third intersection on the third dielectric ceramic layer 41 and 42 side are collectively referred to as the vicinity of the intersection. It may be referred to as region 440.
The region inside the region 420 near the second intersection includes a part of the second dielectric ceramic layer 20b. The region inside the region 430 near the third intersection includes a part of the third dielectric ceramic layers 41 and 42.

In the multilayer ceramic capacitor 1 of the present invention,
(A) The average particle diameter of the dielectric particles contained in the region near each intersection 440 is that of the dielectric particles contained in the first dielectric ceramic layer 20a and the dielectric particles contained in the second dielectric ceramic layer 20b. It is smaller than the average particle size and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

(B) Further, the ratio of the smallness is preferably as small as 5% or more.

In this case, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is the dielectric contained in the second dielectric ceramic layer 20b in a portion other than the region 420 near the second intersection. The average particle size of the particles, and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is the third dielectric ceramic layer 41 in a portion other than the region near the third intersection 430. And 42 means the average particle size of the dielectric particles contained in.

The multilayer ceramic capacitor 1 of the present invention having the above configuration (A) or (B) further preferably has any of the following configurations (C) to (I).

(C) The difference between the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%. The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b and the third dielectric ceramic layer 41. The average particle size of the dielectric particles contained in and 42 is larger than the average particle size of any of the dielectric particles, and the average particle size of the dielectric particles contained in the region near the intersection 440 is the dielectric contained in the second dielectric ceramic layer 20b. The average particle size of the body particles and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 are smaller than any of the average particle sizes.

(D) The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is within 5%. The average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b. The average particle size of the dielectric particles contained in is smaller than any of the average particle sizes, and the average particle size of the dielectric particles contained in the region near the intersection 440 is the dielectric contained in the third dielectric ceramic layers 41 and 42. It is smaller than the average particle size of body particles.

(E) The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%. The average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the third dielectric ceramic. The average particle size of the dielectric particles contained in the layers 41 and 42 is smaller than any of the average particle sizes, and the average particle size of the dielectric particles contained in the region near the intersection 440 is included in the second dielectric ceramic layer 20b. It is smaller than the average particle size of the dielectric particles.

(F) Difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a and the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, the first dielectric The difference between the average particle size of the dielectric particles contained in the ceramic layer 20a and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, and the second dielectric ceramic layer 20b. The difference between the average particle size of the contained dielectric particles and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is within 5%, and is located in the region near the intersection 440. The average particle size of the contained dielectric particles includes the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b. , The average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 is smaller than any of the average particle sizes.

(G) The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b, and the third dielectric material. The average particle size of the dielectric particles contained in the ceramic layers 41 and 42 is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle size of the dielectric particles contained in the region near the intersection 440. The average particle size is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

(H) The average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42, and the second The average particle size of the dielectric particles contained in the dielectric ceramic layer 20b is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the average particle size of the dielectric particles contained in the region near the intersection 440 The average particle size is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b.

(I) The average particle size of the dielectric particles contained in the region near the intersection 440 is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a, and the third dielectric ceramic layer 41 and The average particle size of the dielectric particles contained in 42 or the average particle size of the dielectric particles contained in the second dielectric ceramic layer 20b is smaller than the average particle size of the dielectric particles contained in the region near the intersection 440.

The average particle diameter of the dielectric particles contained in the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the third dielectric ceramic layers 41 and 42 forms each dielectric ceramic layer. It can be controlled by adjusting the amount of the sintering aid typified by Si, Mn, etc. contained in the dielectric ceramic slurry, and further adjusting the firing temperature.

As described above, in the multilayer ceramic capacitor 1 of the present invention, the average particle diameter of the dielectric particles contained in the region near the intersection 440 is the dielectric contained in the first dielectric ceramic layer 20a around the region 440 near the intersection. It is smaller than the average particle size of the body particles, the dielectric particles contained in the second dielectric ceramic layer 20b, and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42.

The electric field is likely to be concentrated in the region near the intersection 440, and if the electric field is concentrated, the reliability of the multilayer ceramic capacitor may be lowered. However, in the multilayer ceramic capacitor 1 of the present invention, the average particle diameter of the dielectric particles contained in the region near the intersection is the first dielectric ceramic layer 20a, the second dielectric ceramic layer 20b, and the periphery thereof. , Smaller than the average particle size of the dielectric particles contained in each of the third dielectric ceramic layers 41 and 42. Since the average particle size is small as described above, a large number of grain boundaries are present and the electric field concentration is suppressed. As a result, the reliability of the monolithic ceramic capacitor can be improved.

[Test Example 2]
Next, in the multilayer ceramic capacitor 1 of the present invention, the average particle size of the dielectric particles contained in the region near the intersection 440 is the first dielectric ceramic layer 20a around the dielectric ceramic layer 20a and the third dielectric ceramic layer 41. Test Example 2 for verifying that it is superior that it is smaller than the average particle size of the dielectric particles contained in each of 42 and 42 will be described.

The average particle size of the dielectric particles contained in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is measured as follows.

(Average particle size of dielectric particles contained in the first dielectric ceramic layer)
In the method for manufacturing a monolithic ceramic capacitor of the present invention described above, the first external electrode 51 and the second external electrode 52 are not co-fired, and the green chip 110 is fired to obtain a first laminated body 10. Polishing from the end face 15 side or the second end face 16 side of the above, and as shown in FIG. 20, a polished body in which the central portion in the length (L) direction is left is obtained as a test piece.
As shown in FIG. 20, a virtual line OS1 orthogonal to the width (W) direction is assumed in the central portion in the width (W) direction. Then, along the virtual line OS1, a region in which the first dielectric ceramic layer 20a related to the acquisition of the capacitance of the abrasive body, the first internal electrode layer 21, and the second internal electrode layer 22 are laminated. Was divided into three equal parts in the stacking direction, and divided into three regions, an upper region F1, a central region F2, and a lower region F3. The first dielectric ceramic layer 20a is imaged in each of the regions F1, F2 and F3 with a field size of 4.3 μm × 3.2 μm, and for each of the regions F1, F2 and F3, for each of the 20 dielectric particles. , The area was measured by image processing. Then, the diameter equivalent to the circle was calculated from the measured area and averaged to obtain the average particle diameter. The average particle size was measured in each of the upper region F1, the central region F2, and the lower region F3, and no significant difference was found in the measured values. Considered as the average particle size.

(Average particle size of dielectric particles contained in the third dielectric ceramic layer)
In the test body shown in FIG. 20, the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the first side surface 13 side or the second side surface 14 side are laminated (T). Imagine a virtual line connected in a direction. FIG. 20 shows a virtual line OS3 in which the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the second side surface 14 side are connected in the stacking (T) direction. .. As shown in FIG. 21, the third dielectric ceramic layer 42 is imaged from the virtual line OS3 on the third dielectric ceramic layer 42 side with a field of view size of 4.3 μm × 3.2 μm in the range of 5 μm, and each image is taken. For each of the regions F1, F2 and F3, the area of 20 dielectric particles was measured by image processing. Reference numeral 42F in FIG. 21 indicates an imaging region. Then, the diameter equivalent to the circle was calculated from the measured area and averaged to obtain the average particle diameter. The average particle size was measured in each of the upper region F1, the central region F2, and the lower region F3, and no significant difference was found in the measured values. Considered as the average particle size.

(Average particle size of dielectric particles contained in the second dielectric ceramic layer)
The laminate 10 is polished from the first end face 15 side or the second end face 16 side until at least one internal electrode layer appears. For example, as shown in FIG. 22, polishing is performed from the side of the second end surface 16 to the surface J immediately before the appearance of the second internal electrode layer 22. As shown in FIG. 23, a virtual line OS2 orthogonal to the width (W) direction is assumed in the central portion in the width (W) direction. Then, along the virtual line OS2, the second dielectric ceramic layer 20b was divided into three equal parts in the stacking direction, and divided into three regions, an upper region G1, a central region G2, and a lower region G3. A second dielectric ceramic layer was imaged in each of the regions G1, G2, and G3 with a field of view size of 4.3 μm × 3.2 μm, and for each of the regions G1, G2, and G3, for each of the 20 dielectric particles. The area was measured by image processing. Then, the diameter equivalent to the circle was calculated from the measured area and averaged to obtain the average particle diameter. The average particle size was measured in each of the upper region G1, the central region G2, and the lower region G3, and no significant difference was found in the measured values. Considered as the average particle size.

(Average particle size of dielectric particles contained in the region near the intersection)
In the test body shown in FIG. 23, the virtual line OS4 in which the ends of the plurality of first internal electrode layers 21 and the plurality of second internal electrode layers 22 on the second side surface 14 side are connected in the stacking (T) direction. Is assumed. Then, along the virtual line OS4, the regions on both sides of the virtual line OS4 including the intersection vicinity region 440 in the width (W) direction are divided into three equal parts in the stacking direction, and the upper region H1, the central region H2, and the lower region H3 are divided into three equal parts. Divided into areas. As shown in FIG. 24, the second dielectric ceramic layer 20b and the third dielectric ceramic layer 42 have a field size of 4.3 μm × 3.2 μm in the range of 5 μm on both sides of the virtual line OS 4 in the width (W) direction. An image was taken, and the area of 20 dielectric particles was measured by image processing for each of the regions F1, F2 and F3. Reference numeral 42H in FIG. 24 indicates an imaging region. Then, the diameter equivalent to the circle was calculated from the measured area and averaged to obtain the average particle diameter. The average particle size was measured in each of the upper region H1, the central region H2, and the lower region H3, and no significant difference was found in the measured values. Consider it as.

Test Examples 2-1 to 2-24 shown in Table 3 were prepared as multilayer ceramic capacitors corresponding to the above-mentioned (C) to (I). Further, in Test Examples 2-25 to 2-27, the average particle size of the dielectric particles contained in the region near the intersection is the average particle size of the dielectric particles contained in the first dielectric ceramic layer 20a. The average particle size of the dielectric particles contained in the dielectric ceramic layer 20b of the above and the average particle size of the dielectric particles contained in the third dielectric ceramic layers 41 and 42 are larger than the average particle size of any of the above. And said. For these Test Examples 2-1 to 2-27, the average particle size was examined by the above-mentioned measuring method.

In Table 3, the "first" in the item for comparing the average particle size is the average particle size of the dielectric particles contained in the first dielectric ceramic layer, and the "second" is the second dielectric ceramic. The average particle size of the dielectric particles contained in the layer, the "third" is the average particle size of the dielectric particles contained in the third dielectric ceramic layer, and the "intersection point" is the dielectric content in the region near the intersection point. It is the average particle size of body particles.

On the other hand, with respect to the multilayer ceramic capacitor of Test Example 2-25 to 2-27, the resistance value (kΩ) was measured in an environment of room temperature of 150 ° with a voltage of 6.3 V applied, and MTTF (Mean Time Between Failure). Was examined and a judgment was made. For MTTF, the time when the resistance value becomes 10 kΩ or less is set, the judgment when the MTTF is 15.3 hours (hr) or less is set as x, and the judgment is made when the resistance value exceeds 15.3 hours (hr) and is up to 30 hours. (Good), over 30 hours was judged as ◎ (excellent). The results are also shown in Table 3. When the coverage of the internal electrode layer is less than 80%, it is difficult to obtain the capacitance, so it is not possible to measure.

According to Table 3, the average particle diameter of the dielectric particles contained in the region near the intersection is the dielectric contained in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer. It was confirmed that the MTTF increases when the particle size is smaller than the average particle size of the body particles, and the reliability of the multilayer ceramic capacitor increases.

[3] Manufacturing method in which a step of removing the side surface of the laminated body is added In the manufacturing method of the laminated ceramic capacitor 1 of the present invention described above, in obtaining the green chip 110 which is the unburned laminated body 10, the unfired first. The step of printing the unfired first internal electrode layer 121 and the second internal electrode layer 122 on the dielectric ceramic layer 120a of 1, and the first internal electrode layer 121 of the first dielectric ceramic layer 120a. The step of forming the unfired second dielectric ceramic layer 120b in the region other than the region where the second internal electrode layer 122 is printed, and the step of laminating the plurality of first dielectric ceramic layers 120a to the green chip 110. From the first side surface 113 and the second side surface 114 of the individual green chips 110, the first internal electrode layer 121 and the second internal electrode layer 122, The step of exposing the first dielectric ceramic layer 120a and the second dielectric ceramic layer 120b, and the unfired third side surface 113 and the second side surface 114 of the individual green chips 110. It includes a step of laminating and forming dielectric ceramic layers (side margin portions 41 and 42).
Here, the green chip 110 is an example of a laminated body. The first dielectric ceramic layer 120a is an example of the dielectric layer. The first internal electrode layer 121 and the second internal electrode layer 122 are examples of internal electrode patterns. The second dielectric ceramic layer 120b is an example of a dielectric pattern. The first side surface 113 and the second side surface 114 are examples of side surfaces. The side margin portions 41 and 42, which are the unfired third dielectric ceramic layers, are an example of the dielectric gap layer.

In this manufacturing method, by cutting the mother block 104, from the first side surface 113 and the second side surface 114 of the green chip 110, the first internal electrode layer 121 and the second internal electrode layer 122, the first After the step of exposing the dielectric ceramic layer 120a and the second dielectric ceramic layer 120b, the third dielectric ceramic layer is formed on the first side surface 113 and the second side surface 114 of the green chip 110. A removal step of removing a certain thickness from the first side surface 113 and the second side surface 114 can be added before the step of forming the ceramics by bonding them together. As a result, the first dielectric ceramic layer 120a, the second dielectric ceramic layer 120b, the first internal electrode layer 121, and the second internal electrode layer 122 are exposed on the first side surface 113 and the second side surface 114. Sides are removed.

FIG. 25 shows a flattened state in which the first side surface 113 and the second side surface 114 of the green chip 110 are removed to a certain thickness (for example, 1 μm or less). In FIG. 25, the left side shows before the removal step, and the right side shows after the removal step. The first side surface 113 and the second side surface 114 of the green chip 110 are formed in FIG. 25 due to the stress applied to the lower side in the drawing in the cutting direction when a plurality of green chips 110 are obtained by cutting the mother block 104. As shown in, the side surface may flow slightly downward and plastically deform. In addition, the cut surface may not be sufficiently smooth, or foreign matter may be present on the cut surface. Therefore, the thickness is removed so that the deformed portion disappears. The means for removing the first side surface 113 and the second side surface 114 in this way is not limited, but for example, polishing by an appropriate polishing means is preferable.

As shown in FIG. 26, the first side surface 113 and the second side surface 114 after the removal step are formed on a smooth surface and are surfaces from which foreign matter has been removed. A third dielectric ceramic layer (side margin portions 41 and 42) is formed by laminating the first side surface 113 and the second side surface 114 after the removal step.

In the present invention, each of the second dielectric ceramic layer 20b, the first internal electrode layer 21, and the second internal electrode layer 22 may contain a resin. The resin can be contained by adding it to the material at the time of manufacture. That is, in the second dielectric ceramic layer 20b, the dielectric paste contains the resin, and in the first internal electrode layer 21 and the second internal electrode layer 22, the conductive paste contains the resin.

The resin contained in the dielectric paste and the conductive paste is added for the purpose of functioning as a binder, improving the viscosity of the material, and the like. Examples of such resins include polyvinyl acetal resins such as polyvinyl butyral and polyvinyl acetacetal, polyvinyl alcohol resins such as polyvinyl alcohol, cellulose resins such as methyl cellulose, ethyl cellulose, and cellulose acetate phthalate, and (meth) acrylic acid esters. (Meta) acrylic resin, polyamideimide, imide resin such as polyimide, ethylene resin such as polyethylene oxide, nitrile resin such as polyacrylonitrile and polymetallylonitrile, urethane resin such as polyurethane, polyethylene, polypropylene , Vinyl-based resin such as vinyl acetate, rubber-based resin such as styrene butadiene rubber, and the like, but are not limited thereto.

Further, as the content of the resin, it is preferable that the content contained in the second dielectric ceramic layer 20b and the content contained in the first dielectric ceramic layer 20a are different. The resin content of the first dielectric ceramic layer 20a and the second dielectric ceramic layer 20b is preferably, for example, 30 wt% or more and 50 wt% or less. Within this range, it is preferable that the resin contents of the first dielectric ceramic layer and the second dielectric ceramic layer 20b are different from each other.

Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thickness of the first dielectric ceramic layer 120a is preferably 0.4 μm or more and 0.8 μm or less. Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thickness of the first internal electrode layer 121 and the second internal electrode layer 122 is preferably 0.4 μm or more and 0.8 μm or less.

Further, in forming the green chip 110, a part of the second internal electrode layer 122 may be superimposed on a part of the first internal electrode layer 121 and the second internal electrode layer 122. .. Specifically, the ends of the second dielectric ceramic layer 120b, the first internal electrode layer 121, and the second internal electrode layer 122, which are adjacent to each other in the length (L) direction, overlap each other. It may be an embodiment. For example, as shown in FIG. 27, the end portion of the second dielectric ceramic layer 120b may be superimposed on the end portion of the first internal electrode layer 121 in the length (L) direction. Similarly, the end portion of the second dielectric ceramic layer 120b may be superimposed on the end portion of the second internal electrode layer 122. In the embodiment in which the ends in the length (L) direction are overlapped in this way, the end of the first internal electrode layer 121 and the second dielectric ceramic are placed on the end of the second dielectric ceramic layer 120b. The ends of the layer 120b may overlap.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, after removing a certain thickness from the first side surface 113 and the second side surface 114 of the green chip 110, which is an unfired laminate 10, the first side surface 113 and the first side surface 113 and the first side surface 114 are removed. An unfired third dielectric ceramic layer is attached to the side surface 114 of No. 2 to form the third dielectric ceramic layer. As a result, the unfired third dielectric ceramic layer can be formed in a smooth and clean state with respect to the first side surface 113 and the second side surface 114.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, by removing the first side surface 113 and the second side surface 114 by polishing, the first side surface 113 and the second side surface 114 can be easily and accurately made to have a predetermined thickness. It can be removed with the amount of removal.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, the second dielectric ceramic layer 120b contains a resin, and the amount of the resin is the amount of the resin contained in the first internal electrode layer 121 and the second internal electrode layer 122. More is preferable. As a result, the viscosity of the second dielectric ceramic layer 120b is relatively increased, and it is possible to suppress the occurrence of defects such as cracking or chipping of the cut surface of the second dielectric ceramic layer 20b when the mother block 104 is cut. can.

Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thickness of the first dielectric ceramic layer 120a is preferably 0.4 μm or more and 0.8 μm or less. Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the thickness of the first internal electrode layer 121 and the second internal electrode layer 122 is preferably 0.4 μm or more and 0.8 μm or less. By having the unfired dielectric layer and the internal electrode layer having such a thickness, the first dielectric ceramic layer 20a, the first internal electrode layer 21, and the second internal electrode layer 22 after firing can be formed. It can be formed to an appropriate thickness.

Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, a part of the second internal electrode layer 122 may be superimposed on the first internal electrode layer 121 and the second internal electrode layer 122. As a result, after firing, the second dielectric ceramic layer 20b can be arranged with a sufficient thickness without any gaps.

[4] Defects in the Second Dielectric Ceramic Layer In the multilayer ceramic capacitor 1 of the present invention, as shown in FIGS. 28 and 29, at least one second dielectric ceramic layer 20b and one third It has a defective portion 520 in which a part of the second dielectric ceramic layer 20b is missing from the dielectric ceramic layer 42. Similarly, a defective portion in which a part of the second dielectric ceramic layer 20b is missing between at least one second dielectric ceramic layer 20b and the other third dielectric ceramic layer 41. Has 520.

The defective portion 520 is connected to the second external electrode 52 in the first internal electrode layer 21 in the region where the second dielectric ceramic layer 20b is arranged, that is, in the length (L) direction of the laminated body 10. Between the non-existing end and the second external electrode 52, and between the end not connected to the first external electrode 51 in the second internal electrode layer 22 and the first external electrode 51. In at least one of the regions, the position in the stacking (T) direction is between the first dielectric ceramic layers 20a on the surface including the stacking (T) direction and the width (W) direction, and the width (W) direction. At the position of, it is formed between the second dielectric ceramic layer 20b and the third dielectric ceramic layer 41 or 42.

When the green chip 110, which is the unfired laminate 10, is produced, the side surface of the unfired second dielectric ceramic layer 120b is processed and then fired to obtain the side surface of the second dielectric ceramic layer 20b. A laminated body 10 having a defective portion 520 is obtained. The processing method for obtaining the defective portion 520 is arbitrary, and can be formed by, for example, drilling with a suitable tool or the like.

Further, in the above-mentioned "manufacturing method in which a step of removing the side surface of the laminated body is added", when the first side surface 113 or the second side surface 114 of the unfired green chip 110 is removed by means such as polishing. , A part of the side surface of the second dielectric ceramic layer 20b may be missing and a fine hole may be formed. When such a hole is generated, the hole can be used as a defective portion 520. The defective portion 520 does not have to be formed on the side surfaces of all the second internal electrode layers 22, and is formed on both ends in the length (L) direction on the first side surface 13 side and the second side surface 14 side. It is sufficient that one or more are formed in each.

Further, as shown in FIGS. 28 and 29, the segregation 530 of Si may be arranged in the defective portion 520. The Si segregation 530 is the segregation of Si added as an additive to the second dielectric ceramic layer 20b.

The size of the segregation 530 of Si is preferably larger than 1/3 of the thickness of the second dielectric ceramic layer 20b in terms of the diameter equivalent to the circle. Further, it may be 100 nm or more and 600 nm or less.

The defective portion 520 is preferably arranged in the vicinity of the first internal electrode layer 21 or the second internal electrode layer 22. In FIG. 29, the defective portion 520 is arranged close to the end portion of the second internal electrode layer 22 in the length (L) direction. Similarly, it is preferable that the defective portion 520 is arranged close to the end portion of the first internal electrode layer 21 in the length (L) direction.

The size of the segregation 530 of Si is preferably 0.1% or more and 5% or less of the size of the third dielectric ceramic layers 41 and 42 in the width (W) direction.

The multilayer ceramic capacitor 1 of the present invention has a second external electrode in the first internal electrode layer 21 in a region where the second dielectric ceramic layer 20b is arranged, that is, in the length (L) direction of the laminate 10. Between the 52 and the end and the second external electrode 52, and between the end of the second internal electrode layer 22 that is not connected to the first external electrode 51 and the first external electrode 51. In at least one of the regions, the position in the stacking (T) direction is between the first dielectric ceramic layers 20a on the surface including the stacking (T) direction and the width (W) direction, and the width (W) direction. At the position of, a defect portion 520 is provided between the second dielectric ceramic layer 20b and the third dielectric ceramic layers 41 and 42.

Thereby, the stress generated in the second dielectric ceramic layer 20b at the time of firing can be relaxed by the defective portion 520. As a result, it is possible to prevent the second dielectric ceramic layer 20b from being cracked or chipped.

In the multilayer ceramic capacitor 1 of the present invention, the segregation 530 of Si may be arranged in the defective portion 520. When the segregation 530 is present in the defective portion 520, the segregation 530 suppresses the invasion of water. The presence of the segregation 530 in the defective portion 520 improves the moisture resistance of the multilayer ceramic capacitor 1. The segregation 530 may be present in all of the defective portion 520, or may be present in a part of the defective portion 520. The defect portion 520 in which the segregation 530 is present can prevent the second dielectric ceramic layer 20b from being cracked or chipped, and can also improve the moisture resistance of the multilayer ceramic capacitor 1.

In the multilayer ceramic capacitor 1 of the present invention, the segregation 530 of Si is 1/3 or more (or less than) the thickness of the second dielectric ceramic layer 20b.

In the multilayer ceramic capacitor 1 of the present invention, the defective portion 520 is arranged close to the first internal electrode layer 21 and the second internal electrode layer 22. In the region close to the first internal electrode layer 21 and the second internal electrode layer 22, the stress generated during firing is relatively large, but the stress is relaxed by the defect portion 520, so that cracks and chips may occur. It can be effectively suppressed.

In the multilayer ceramic capacitor 1 of the present invention, the dimension of the segregation 530 of Si in the width direction is preferably 0.1% or more and 5% or less of the dimensions of the third dielectric ceramic layers 41 and 42. When the segregation 530 of Si is present in the defective portion 520, the occurrence of cracks and chips can be effectively suppressed, and the moisture resistance of the multilayer ceramic capacitor 1 can be improved.

[5] Segregation formed at the end of the second dielectric ceramic layer on the inner electrode layer side As shown in FIG. 30, in the multilayer ceramic capacitor 1 of the present invention, the second in the first internal electrode layer 21. The first segregation 610 may be present at the end in the length (L) direction that is not connected to the external electrode 52 of the ceramic. Further, the first segregation 610 may be present at the end portion of the second internal electrode layer 22 in the length (L) direction that is not connected to the first external electrode 51.

As shown in FIG. 31, the first segregation 610 is generated by segregating the metal element 610a derived from the second dielectric ceramic layer 20b into layers. Examples of the metal element 610a include at least one of Mg, Mn, and Si. In the segregation 610 by the metal element 610a, the metal element contained in the second dielectric ceramic layer 20b is transferred to the first internal electrode layer 21 and the second internal electrode layer 22 when the second dielectric ceramic layer 20b is fired. It is caused by moving.

On the other hand, as shown in FIG. 32, the second segregation 620 may be present at the end of the first internal electrode layer 21 in the width (W) direction. Further, the second segregation 620 may be present at the end of the second internal electrode layer 22 in the width (W) direction.

The second segregation 620 is formed by segregating the metal elements 620a derived from the third dielectric ceramic layers 41 and 42 in contact with the first internal electrode layer 21 and the second internal electrode layer 22 in a layered manner. Is. The metal element 620a is the same as the first segregation 610, and examples thereof include at least one of Mg, Mn, and Si. In the segregation 620 by the metal element 620a, the metal element contained in the third dielectric ceramic layers 41 and 42 is contained in the first internal electrode layers 21 and the second inside when the third dielectric ceramic layers 41 and 42 are fired. It is generated by moving to the electrode layer 22.

In the multilayer ceramic capacitor 1 of the present invention, the first segregation 610 segregated on the first internal electrode layer 21, the first segregation 610 segregated on the second internal electrode layer 22, and the first internal electrode layer The second segregation 620 segregated in 21 and the second segregation 620 segregated in the second internal electrode layer 22 contain metal elements contained in at least one set of segregations among the other segregations. It is preferable that the metal element is different from that of the metal element.

When the first dielectric ceramic layer 20a _{contains BaTiO 3} as a main component, the content of the metal element contained in the first segregation 610 with respect to the first internal electrode layer 21 and the second internal electrode layer 22 is determined. It is 0.3 mol% or more with respect to 100 mol of Ti. Similarly, the content of the metal element contained in the second segregation 620 with respect to the first internal electrode layer 21 and the second internal electrode layer 22 is 0.3 mol% or more with respect to 100 mol of Ti. be.

In the present invention, the region in which the first segregation 610 exists in the first internal electrode layer 21 preferably has a length of 0.1 μm or more along the length (L) direction. Further, in the second internal electrode layer 22, the region where the first segregation 610 is present preferably has a length of 0.1 μm or more along the length (L) direction. Further, the region of the first internal electrode layer 21 in which the second segregation 620 is present preferably has a length of 0.1 μm or more along the width (W) direction. Further, in the second internal electrode layer 22, the region where the second segregation 620 exists is preferably a length of 0.1 μm or more along the width (W) direction. By having these lengths, the effect of suppressing the electric field concentration by segregation and improving the reliability can be surely obtained.

When the lengths of the first segregation 610 and the second segregation 620 are less than the above lengths, it becomes difficult to suppress the electric field concentration. Further, in the first segregation 610, when 0.5% in the length (L) direction is exceeded, in the second segregation 620, when it exceeds 1.0% in the width (W) direction, the metal segregates. The element (at least one of Mg, Mn, and Si) becomes excessive, and the function of storing the electric charge of the internal electrode layer deteriorates.

The length of the first segregation 610 in the length (L) direction is contained in the second dielectric ceramic layer 20b, moves to the first internal electrode layer 21 and the second internal electrode layer 22, and segregates. It can be controlled by adjusting the content of the metal element 610a. Further, the length of the second segregation 620 in the width (W) direction is included in the third dielectric ceramic layers 41 and 42, and moves to the first internal electrode layer 21 and the second internal electrode layer 22. It can be controlled by adjusting the content of the metal element 620a segregated.

In the multilayer ceramic capacitor 1 of the present invention, the end portion in the length (L) direction not connected to the second external electrode 52 in the first internal electrode layer 21 and the second internal electrode layer 22 in the second internal electrode layer 22. A first segregation 610 by at least one metal element of Mg, Mn, and Si is present at each of the ends in the length (L) direction that are not connected to the external electrode 51 of 1. ..

The electric field is likely to be concentrated at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 in contact with the second dielectric ceramic layer 20b in the length (L) direction, and the electric field concentration occurs. This may reduce the reliability of the monolithic ceramic capacitor. However, in the multilayer ceramic capacitor 1 of the present invention, the electric field concentration is suppressed by the first segregation 610, and the reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, the end portion of the first internal electrode layer 21 in the width (W) direction and the end portion of the second internal electrode layer 22 in the width (W) direction are There is a second segregation 620 with at least one metal element of Mg, Mn and Si.

The electric field is likely to be concentrated at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 in contact with the third dielectric ceramic layers 41 and 42 in the width (W) direction, and the electric field concentration is concentrated. If this happens, the reliability of the monolithic ceramic capacitor may be reduced. However, the multilayer ceramic capacitor 1 of the present invention can improve the reliability because the electric field concentration is suppressed by the second segregation 620.

In the multilayer ceramic capacitor 1 of the present invention, the first segregation 610 segregated on the first internal electrode layer 21, the first segregation 610 segregated on the second internal electrode layer 22, and the first internal electrode layer The second segregation 620 segregated in 21 and the second segregation 620 segregated in the second internal electrode layer 22 contain metal elements contained in at least one set of segregations among the other segregations. It is different from the metal element.

Thereby, the optimum metal element can be arranged according to the place where the first segregation 610 and the second segregation 620 are arranged, and the reliability can be improved.

In the multilayer ceramic capacitor 1 of the present invention, the first dielectric ceramic layer 20a contains Ba and Ti, and the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620. The content of each of the above in the internal electrode layer is 0.3 mol% or more with respect to 100 mol of Ti.

Thereby, the above-mentioned electric field concentration can be effectively suppressed, and the reliability can be further improved.

In the multilayer ceramic capacitor 1 of the present invention, the region where the first segregation 610 exists in the first internal electrode layer 21 is 0.3 μm or more in the length (L) direction, and in the second internal electrode layer 22 The region where the first segregation 610 exists is 0.3 μm or more in the length (L) direction, and the region where the second segregation 620 exists in the first segregation 610 is 0.3 μm in the width (W) direction. The above is preferable, and the region in which the second segregation 620 exists in the second segregation 620 is preferably 0.3 μm or more in the width (W) direction.

As a result, the effect of suppressing the electric field concentration by segregation and improving the reliability can be surely obtained.

[Test Example 3]
Next, in the multilayer ceramic capacitor 1 of the present invention, Test Example 3 for verifying the effects of the first segregation 610 and the second segregation 620 will be described.

As shown in Table 4, a multilayer ceramic capacitor including a second dielectric ceramic layer 20b and a third dielectric ceramic layers 41 and 42 containing any one of the elements Mg, Mn, and Si. Test Examples 3-1 to 3-18 were prepared. Then, for each test example, the concentration of the element of the first segregation generated at the end of the first internal electrode layer 21 and the second internal electrode layer 22 in the length (L) direction, and the length (L). The length in the direction and the length in the width (W) direction were examined. The concentrations of the metal elements in the first segregation and the second segregation were examined using the same method as the concentration of the second alloy portion and the concentration of the third alloy portion in the above-mentioned "Test Example 1". Moreover, the length of each of the first segregation and the second segregation was measured by EDX analysis.

The resistance value (kΩ) of the multilayer ceramic capacitor of Test Examples 3-1 to 3-18 was measured with a voltage of 6.3 V applied after heating to room temperature for 1 hour in an environment with a temperature of 150 °. Then, MTTF (Mean Time Between Failures) was examined. In addition, the presence or absence of a decrease in capacitance was examined with an LCR meter (manufactured by Keysight: E4980).
A case where the decrease in capacitance is 3% or more or the MTTF is 15.3 hr or less is evaluated as x, and the case where the decrease in capacitance is less than 3% and the MTTF exceeds 15.3 hr and is 30 hours or less is judged. (Good), the decrease in capacitance was less than 3%, and the MTTF exceeded 30 hours was judged as ⊚ (excellent). The results are also shown in Table 4.

By containing Mg, Mn, and Si in the second dielectric layer, segregation portions are formed at the end portions in the length direction and the width direction of the internal electrode, thereby eliminating the reliability deterioration factor that tends to occur at the end portions. Can be done. However, if the content is too large, the region of the internal electrode that functions as a metal is narrowed, resulting in a decrease in capacitance.

[6] Segregation formed in the corner region on the inner electrode layer side of the second dielectric ceramic layer When the first segregation 610 and the second segregation 620 described above are present, as shown in FIG. 33, further. It is preferable that a third segregation 630 is present. The third segregation 630 exists in each of the first corner region 710 and the second corner region 720.

The first corner region 710 is a region in the first internal electrode layer 21 where the length (L) direction in which the first segregation 610 exists and the second segregation 620 width (W) direction overlap. .. Further, the second corner region 720 is a region in the second internal electrode layer 22 where the length (L) direction in which the first segregation 610 exists and the second segregation 620 width (W) direction overlap. Is. The third segregation 630 occurs by segregation of the metal element 610a of the first segregation 610 and the metal element 620a of the second segregation 620.

In the present invention, the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620 are different from each other, and the metal element 630a of the third segregation 630 is the first. It is preferable to contain both the metal element 610a contained in the segregation 610 and the metal element 620a contained in the second segregation 620.

Further, in the present invention, the region where the first segregation 610 exists is 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is 0.1 μm in the width (W) direction. The above is preferable.

FIG. 33 shows the surface of the monolithic ceramic capacitor 1 of the present invention including the length (L) direction and the width (W) direction. The third segregation 630 is substantially perpendicular to the plane including the length (L) direction and the width (W) direction so that the region of existence thereof increases toward the end in the length (L) direction. It is preferable that the segregation is performed in a triangular shape. A part or all of the third segregation 630 is included in the region near the intersection 440 in FIG.

Further, in the multilayer ceramic capacitor 1 of the present invention, a part of the second dielectric ceramic layer 20b is in the laminated (T) direction with respect to the first internal electrode layer 21 and the second internal electrode layer 22. In, it is preferable that the third segregation 630 is arranged so as to be superimposed on the existing region. Specifically, as shown in FIG. 34, in the length (L) direction, the end portion of the second dielectric ceramic layer 120b is the second internal electrode layer 22 in the region containing the third segregation 630. An example is a form in which it is superimposed on the end portion. Similarly, the end portion of the second dielectric ceramic layer 20b may be superimposed on the end portion of the first internal electrode layer 21. In the embodiment in which the ends in the length (L) direction are overlapped in this way, the end of the first internal electrode layer 121 or the second dielectric ceramic is placed on the end of the second dielectric ceramic layer 20b. The ends of the layer 120b may overlap.

In the multilayer ceramic capacitor 1 of the present invention, the end portion in the length (L) direction not connected to the second external electrode 52 in the first internal electrode layer 21 and the second internal electrode layer 22 in the second internal electrode layer 22. A first segregation 610 by at least one metal element of Mg, Mn, and Si is present at each of the ends in the length (L) direction that are not connected to the external electrode 51 of 1. , The end of the first internal electrode layer 21 in the width (W) direction and the end of the second internal electrode layer 22 in the width (W) direction of Mg, Mn, and Si, respectively. There is a second segregation 620 due to at least one metal element, the end of the first internal electrode layer 21 in the length (L) direction where the first segregation 610 is present, and the second segregation. A first corner region 710 that overlaps the width (W) direction in which the 620 exists, and an end portion in the second internal electrode layer 22 in the length (L) direction in which the first segregation 610 exists. A third segregation 630 by each metal element of the first segregation 610 and the second segregation 620 in each of the second corner regions 720 overlapping the width (W) direction in which the second segregation 620 exists. Exists.

Electric fields are likely to be concentrated in the first corner region 710 and the second corner region 720, and if electric field concentration occurs, the reliability of the multilayer ceramic capacitor may be lowered. However, the multilayer ceramic capacitor 1 of the present invention can improve the reliability because the electric field concentration in the first corner region 710 and the second corner region 720 is suppressed by the third segregation 630. ..

In the multilayer ceramic capacitor 1 of the present invention, the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620 are different from each other, and the metal element contained in the third segregation 630 is different. Contains both the metal element 610a contained in the first segregation 610 and the metal element 620a contained in the second segregation 620.

As a result, the electric field concentration on the first corner region 710 and the second corner region 720 is suppressed by the third segregation 630, and the reliability can be improved.

In the third segregation 630, Mg is preferable as the metal element arranged on the side close to the third dielectric ceramic layers 41 and 42. On the other hand, in the third segregation 630, Si is preferable as the metal element arranged on the side close to the second dielectric ceramic layer 20b from the viewpoint of improving the moisture resistance. Therefore, it is preferable that both Mg and Si are segregated in the first corner region 710 and the second corner region 720. Further, the short-circuit recovery may be performed by the first segregation 610 at the ends of the first internal electrode layer 21 and the second internal electrode layer 22 in the width (W) direction. Further, it is more preferable that Sn is solid-solved in the first internal electrode layer 21 and the second internal electrode layer 22.

In the multilayer ceramic capacitor 1 of the present invention, the region where the first segregation 610 exists is 0.1 μm or more in the length (L) direction, and the region where the second segregation 620 exists is in the width (W) direction. It is 0.1 μm or more. As a result, the effect of suppressing the electric field concentration by segregation and improving the reliability can be surely obtained.

In the monolithic ceramic capacitor 1 of the present invention, the third segregation 630 is present in a plane including the length (L) direction and the width (W) direction as it is directed toward the end in the length (L) direction. The area becomes large.

As a result, the area of the third segregation 630 at the end portion of the second dielectric ceramic layer 20b in the length (L) direction where electric field concentration is likely to occur increases, and the electric field concentration is suppressed by the third segregation 630. Can be done more effectively and reliability can be further improved.

In the multilayer ceramic capacitor 1 of the present invention, a part of the second dielectric ceramic layer 20b is the first in the laminated (T) direction with respect to the first internal electrode layer 21 and the second internal electrode layer 22. It is arranged so as to overlap the existing region of the segregation 630 of 3.

As a result, the third segregation 630 is formed so that the existing region becomes larger toward the end in the length (L) direction on the surface including the length (L) direction and the width (W) direction. It will be easier to do.

[Test Example 4]
Next, Test Example 4 for verifying the effect of the third segregation 630 in the multilayer ceramic capacitor 1 of the present invention will be described.

As shown in Table 5, a second dielectric ceramic layer containing any one of Mg, Mn, and Si metal elements and a second dielectric ceramic layer containing any one of Mg, Mn, and Si. Test Examples 4-1 to 4-18 of a multilayer ceramic capacitor provided with the dielectric ceramic layer of No. 3 were prepared. Then, the concentration of the metal element contained in the third segregation generated in the first corner region and the second corner region of each multilayer ceramic capacitor, and the length and width (W) in the length (L) direction. ) The length in the direction was examined. The concentration of the metal element in the third segregation was examined using the same method as the concentration of the second alloy portion and the concentration of the third alloy portion in the above-mentioned "Test Example 1". Also, the length of each of the third segregations was measured by EDX analysis.

For the multilayer ceramic capacitors of Test Examples 4-1 to 4-14, measure the resistance value (kΩ) in an environment of room temperature of 150 ° and apply a voltage of 6.3V, and check the MTTF (Mean Time Between Failures). , Judgment was made. For MTTF, the time when the resistance value becomes 10 kΩ or less is set, the judgment when the MTTF is 15.3 hours (hr) or less is set as x, and the judgment is made when the resistance value exceeds 15.3 hours (hr) and is up to 30 hours. (Good), over 30 hours was judged as ◎ (excellent). The results are also shown in Table 5. Further, the presence or absence of a decrease in capacitance was examined with an LCR meter (manufactured by Keysight: E4980), and those showing a decrease in capacitance of 3% or more were evaluated as x. When the coverage of the internal electrode layer is less than 80%, it is difficult to obtain the capacitance, so it is not possible to measure.

By incorporating Si, Mg, and Mn in the second ceramic dielectric layer and the third ceramic dielectric layer, many segregated regions can be formed at the corners. In particular, electric field concentration tends to occur at the corners, and reliability tends to decrease, but reliability can be improved by creating a biased region. However, if the content is too large, the region of the internal electrode that functions as a metal is narrowed, resulting in a decrease in capacitance.

[7] Thickness of Second Dielectric Ceramic Layer FIG. 35 schematically shows a WT cross section in the central portion in the length (L) direction of the laminate 10 in the multilayer ceramic capacitor 1 of the present invention. The thickness of the first dielectric ceramic layer 20a in the cross section is shown by T1, and the thickness of the end portion in the width (W) direction is shown by T2.

Further, FIG. 36 shows a part of the LT cross section of the multilayer ceramic capacitor 1 of the present invention, and T3 is the thickness of the second dielectric ceramic layer 20b. Although FIG. 36 shows the second dielectric ceramic layer 20b in contact with the second internal electrode layer 22, the thickness of the second dielectric ceramic layer 20b in contact with the first internal electrode layer 21 is also shown. Also regarded as T3. The thickness T3 of the second dielectric ceramic layer 20b is, in other words, the end portion of the first internal electrode layer 21 in the length (L) direction that is not connected to the second external electrode 52, and the second outer electrode layer 21. Between the electrodes 52 and between the end of the second internal electrode layer 22 in the length (L) direction that is not connected to the first external electrode 51 and the second external electrode 52, respectively. The thickness of.

In the present invention, the difference in thickness between T1 and T2 is relatively small, and is within 10% of T1. On the other hand, the thickness of T3 is larger than that of T1 and T2, and the difference is preferably 10% or more of T1 and T2.

There is no limitation on the means for making the thickness T3 of the second dielectric ceramic layer 20b thicker than the thicknesses T1 and T2 of the first dielectric ceramic layer 20a as described above, but for example, the green chip 110 before firing is used. At the time of production, the end portion of the unfired second dielectric ceramic layer 120b in the length (L) direction and the lengths of the unfired first internal electrode layer 121 and the second internal electrode layer 122 ( This is possible by placing the ends in the L) direction on top of each other and then firing the green chip 110.

Of T1, T2 and T3, the thickness T1 of the central portion of the first dielectric ceramic layer 20a is preferably 0.7 μm or less. The thickness T3 of the second dielectric ceramic layer 20b is preferably 0.4 μm or more.

In the multilayer ceramic capacitor 1 of the present invention, the laminated (T) is formed on the surface of the first dielectric ceramic layer 20a including the central portion in the length (L) direction, the laminated (T) direction, and the width (W) direction. The thickness at the center of the direction is T1, the thickness of the end of the first dielectric ceramic layer 20a in the width (W) direction is T2, and the thickness is connected to the second external electrode 52 in the first internal electrode layer 21. Not connected between the end in the length (L) direction and the second external electrode 52, and in the length (L) direction not connected to the first external electrode 51 in the second internal electrode layer 22. When the respective thicknesses between the end portion and the first external electrode 51 are T3, the difference in thickness between T1 and T2 is within 10% of T1, and the thicknesses of T3 are T1 and T2. The difference is more than 10% of T1 and T2.

As a result, the element thickness of the second dielectric ceramic layer 20b arranged for eliminating the step is increased between the first dielectric ceramic layer 20a sandwiching the first internal electrode layer 21 and the second internal electrode layer 22. It has a sufficient thickness, and as a result, reliability can be improved.

1 Laminated ceramic capacitor 10 Laminated body 11 First main surface of the laminated body 12 Second main surface of the laminated body 13 First side surface of the laminated body 14 Second side surface of the laminated body 15 First end surface of the laminated body 16 Second end face of the laminate 20 Dielectric ceramic layer 20a First dielectric ceramic layer 20b Second dielectric ceramic layer 21 First internal electrode layer 22 Second internal electrode layer 30 Inner layer parts 31, 32 Outer layer parts 41, 42 Third dielectric ceramic layer 51 First external electrode 52 Second external electrode 400 Intersection point 440 Intersection point vicinity region

Claims (9)

A laminate including a dielectric ceramic layer and an internal electrode layer, which are laminated in the stacking direction,
A monolithic ceramic capacitor comprising an external electrode connected to the internal electrode layer.
The laminated body includes a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in a width direction orthogonal to the stacking direction, and the stacking direction and It has a first end face and a second end face that are opposed to each other in the length direction orthogonal to the width direction.
The internal electrode layer is drawn out to the second end surface so as to face the first internal electrode layer via the dielectric ceramic layer and the first internal electrode layer drawn out to the first end face. Includes a second internal electrode layer,
The external electrode is arranged on the first end surface and is connected to the first internal electrode layer, and is arranged on the second end surface and the second. Includes a second external electrode, which is connected to the internal electrode layer of the
The dielectric ceramic layer comprises a first dielectric ceramic layer and a second dielectric ceramic layer.
The first dielectric ceramic layer is arranged between the first internal electrode layer and the second internal electrode layer.
The second dielectric ceramic layer includes a region between the first dielectric ceramic layers facing each other via the internal electrode layer, in which the internal electrode layer is not arranged, and a part thereof is the first. It is arranged so as to overlap with the dielectric ceramic layer of
The laminated body is arranged so as to sandwich the inner layer portion and the inner layer portion in which the first internal electrode layer and the second internal electrode layer are alternately laminated via the dielectric ceramic layer. A third dielectric ceramic layer that is arranged so as to sandwich the inner layer portion and the outer layer portion in the width direction and is made of a dielectric ceramic material. Have,
The second dielectric ceramic layer, the first internal electrode layer or the second internal electrode layer, and the third dielectric ceramic layer on a surface including the length direction and the width direction. , The intersection of the interfaces is formed,
The second dielectric ceramic layer and the third dielectric ceramic layer include a region near the intersection in the vicinity of the intersection.
The average particle size of the dielectric particles contained in the region near the intersection is the average particle size of the dielectric particles contained in the first dielectric ceramic layer and the average particle size of the dielectric particles contained in the second dielectric ceramic layer. A multilayer ceramic capacitor that is smaller than the average particle size of either the average particle size or the average particle size of the dielectric particles contained in the third dielectric ceramic layer. The average particle size of the dielectric particles contained in the region near the intersection is the average particle size of the dielectric particles contained in the first dielectric ceramic layer, and the average particle size of the dielectric particles contained in the second dielectric ceramic layer. The multilayer ceramic capacitor according to claim 1, which is 5% or more smaller than the average particle size of both the average particle size and the average particle size of the dielectric particles contained in the third dielectric ceramic layer. The difference between the average particle size of the dielectric particles contained in the second dielectric ceramic layer and the average particle size of the dielectric particles contained in the third dielectric ceramic layer is within 5%.
The average particle size of the dielectric particles contained in the first dielectric ceramic layer is included in the average particle size of the dielectric particles contained in the second dielectric ceramic layer and the third dielectric ceramic layer. Larger than any of the average particle sizes of the dielectric particles,
The average particle size of the dielectric particles contained in the region near the intersection is the average particle size of the dielectric particles contained in the second dielectric ceramic layer and the dielectric contained in the third dielectric ceramic layer. The multilayer ceramic capacitor according to claim 1 or 2, which is smaller than the average particle size of any of the particles. The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer and the average particle size of the dielectric particles contained in the second dielectric ceramic layer is within 5%.
The average particle size of the dielectric particles contained in the third dielectric ceramic layer is included in the average particle size of the dielectric particles contained in the first dielectric ceramic layer and the second dielectric ceramic layer. Smaller than any of the average particle sizes of the dielectric particles,
The multilayer ceramic capacitor according to claim 1 or 2, wherein the average particle size of the dielectric particles contained in the region near the intersection is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layer. The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer and the average particle size of the dielectric particles contained in the third dielectric ceramic layer is within 5%.
The average particle size of the dielectric particles contained in the second dielectric ceramic layer is included in the average particle size of the dielectric particles contained in the first dielectric ceramic layer and the third dielectric ceramic layer. Smaller than any of the average particle sizes of the dielectric particles,
The multilayer ceramic capacitor according to claim 1 or 2, wherein the average particle size of the dielectric particles contained in the region near the intersection is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer. The difference between the average particle size of the dielectric particles contained in the first dielectric ceramic layer and the average particle size of the dielectric particles contained in the second dielectric ceramic layer, the first dielectric ceramic layer. The difference between the average particle size of the dielectric particles contained in the third dielectric ceramic layer and the average particle size of the dielectric particles contained in the third dielectric ceramic layer, and the dielectric particles contained in the second dielectric ceramic layer. Both the difference between the average particle size and the average particle size of the dielectric particles contained in the third dielectric ceramic layer is within 5%.
The average particle size of the dielectric particles contained in the region near the intersection is the average particle size of the dielectric particles contained in the first dielectric ceramic layer and the average particle size of the dielectric particles contained in the second dielectric ceramic layer. The multilayer ceramic capacitor according to claim 1 or 2, which is smaller than either the average particle size or the average particle size of the dielectric particles contained in the third dielectric ceramic layer. The average particle size of the dielectric particles contained in the first dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer.
The average particle size of the dielectric particles contained in the third dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer.
The multilayer ceramic capacitor according to claim 1 or 2, wherein the average particle size of the dielectric particles contained in the region near the intersection is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layer. The average particle size of the dielectric particles contained in the first dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the third dielectric ceramic layer.
The average particle size of the dielectric particles contained in the second dielectric ceramic layer is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer.
The multilayer ceramic capacitor according to claim 1 or 2, wherein the average particle size of the dielectric particles contained in the region near the intersection is smaller than the average particle size of the dielectric particles contained in the second dielectric ceramic layer. The average particle size of the dielectric particles contained in the region near the intersection is smaller than the average particle size of the dielectric particles contained in the first dielectric ceramic layer.
The average particle size of the dielectric particles contained in the third dielectric ceramic layer or the average particle size of the dielectric particles contained in the second dielectric ceramic layer is the average particle size of the dielectric particles contained in the region near the intersection. The multilayer ceramic capacitor according to claim 1 or 2, which is smaller than the average particle size.

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