JP6860051B2 - Multilayer ceramic electronic components - Google Patents

Description

The present invention relates to a laminated ceramic electronic component having an extremely thin dielectric layer.

Along with the miniaturization and thinning of electronic devices, there is a demand for miniaturization and thinning of laminated ceramic electronic components housed therein. Therefore, it is required to make the dielectric layer of the laminated ceramic electronic component thin.

For example, as shown in Patent Document 1, it is known that when the dielectric layer in a laminated ceramic electronic component is thinned, cracks occur during the manufacture thereof, and a method for preventing the cracks has been developed.

However, in the past, the thickness of the dielectric layer was limited to about 1 μm, but recent technological innovations have led to the development of a technique for reducing the thickness of the dielectric layer to 0.5 μm or less. Conventionally, when the thickness of the dielectric layer is reduced to 0.5 μm or less, and further to 0.4 μm or less, a technique has been established for preventing cracks from occurring and ensuring capacitance. It wasn't done.

Japanese Unexamined Patent Publication No. 7-74047

The present invention has been made in view of such an actual situation, and an object of the present invention is to suppress the occurrence of cracks even when the thickness of the dielectric layer is reduced, and the laminated ceramic electronic component has a small decrease in capacitance. Is to provide.

As a result of diligent studies on the above object, the present inventors have only satisfied a specific dimensional relationship, and cracks occur even when the thickness of the dielectric layer is reduced to 0.5 μm or less, further 0.4 μm or less. We have found that it is possible to provide a laminated ceramic electronic component having a small decrease in capacitance, and have completed the present invention.

That is, the laminated ceramic electronic component according to the present invention is
A ceramic body formed by alternately laminating a plurality of dielectric layers and a plurality of internal electrode layers,
A laminated ceramic electronic component having at least a pair of external electrodes connected to the internal electrode layer on the surface of the ceramic body.
The thickness of the dielectric layer is 0.4 μm or less, and the thickness is 0.4 μm or less.
The width dimension (W0) along the width direction of the ceramic element is 0.59 mm or less.
The gap dimension (Wgap) from the outer surface of the ceramic body to the end of the internal electrode layer along the width direction of the ceramic body is 0.010 to 0.025 mm.
The ratio of the gap dimension to the width dimension (Wgap / W0 dimension) is 0.025 or more.

According to the present invention, even when the thickness of the dielectric layer is reduced to 0.5 μm or less, and further to 0.4 μm or less, crack generation can be suppressed and the capacitance is reduced to a small extent. Parts can be provided.

Preferably, the ratio (te / td) of the thickness (te) of the internal electrode layer to the thickness (td) of the dielectric layer is 1.05 or less.

Preferably, the average particle size of the first dielectric particles constituting the dielectric layer located between the internal electrode layers along the stacking direction is Di.
When the average particle size of the second dielectric particles located in the exterior region located outside the stacking direction of the interior region in which the internal electrode layer is laminated with the dielectric layer sandwiched along the stacking direction is Dg,
Dg / Di ≧ 1.

Alternatively, preferably, the average particle size of the particles constituting the dielectric layer located between the internal electrode layers along the stacking direction is set to Di.
When the average particle size of the third dielectric particles constituting the extraction region located between the extraction portions of the internal electrode layer connected to the external electrode is Dh.
Dh / Di ≧ 1.

In such a relationship, even if the dielectric layer is thinned, the capacitance is further improved. Generally, it has been reported that the relative permittivity decreases as the dielectric layer becomes thinner. However, the present inventors have found that by controlling the particle size of the dielectric particles in a specific region, it is possible to suppress a decrease in the relative permittivity even if the dielectric layer is made thin.

FIG. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. FIG. 3 is a schematic cross-sectional view showing a process of laminating a green sheet in the process of manufacturing the monolithic ceramic capacitor shown in FIG. FIG. 4 is a plan view showing a part of the pattern of the internal electrode layer along the IV-IV line shown in FIG. FIG. 5A is a schematic cross-sectional view of the laminated body after laminating the green sheet shown in FIG. 3 parallel to the XX axis plane. FIG. 5B is a schematic enlarged cross-sectional view of the laminated body after laminating the green sheet shown in FIG. 3 parallel to the YZ axis plane.

Hereinafter, the present invention will be described based on the embodiments shown in the drawings.

Overall Configuration of Multilayer Ceramic Capacitor First, the overall configuration of the monolithic ceramic capacitor will be described as an embodiment of the monolithic ceramic electronic component according to the present invention.

As shown in FIG. 1, the multilayer ceramic capacitor 2 according to the present embodiment has a capacitor body 4, a first terminal electrode 6, and a second terminal electrode 8. The capacitor element 4 has an inner dielectric layer 10 and an inner electrode layer 12, and the inner electrode layers 12 are alternately laminated between the inner dielectric layers 10. The portion where the inner dielectric layer 10 and the inner electrode layer 12 are alternately laminated is the interior region 13.

The capacitor element 4 has exterior regions 11 on both end faces in the stacking direction Z (Z axis). The exterior region 11 is formed by laminating a plurality of dielectric layers thicker than the inner dielectric layer 10 constituting the interior region 13.

One of the alternately laminated internal electrode layers 12 is a drawer electrically connected to the inside of the first terminal electrode 6 formed on the outside of the first end portion in the Y-axis direction of the capacitor body 4. It has a part 12A. Further, the other internal electrode layer 12 that is alternately laminated is electrically connected to the inside of the second terminal electrode 8 formed on the outside of the second end portion in the Y-axis direction of the capacitor element 4. It has a drawer 12B.

The interior region 13 has a capacity region 14 and drawer regions 15A and 15B. The capacitance region 14 is a region in which the internal electrode layer 12 is laminated with the inner dielectric layer 10 interposed therebetween along the stacking direction. The extraction region 15A is a region located between the extraction portions 12A of the internal electrode layer 12 connected to the external electrode 6. The extraction region 15B is a region located between the extraction portions 12B of the internal electrode layer 12 connected to the external electrode 8.

As shown in FIG. 2, side surface protection regions 16 are formed at both ends of the capacitor element 4 in the X-axis direction. The side protection region 16 is made of the same or different dielectric material as the dielectric material constituting the inner dielectric layer 10 and / or the dielectric layer of the outer region 11. Further, the drawer regions 15A and 15B are made of the same or different dielectric material as the dielectric material constituting the inner dielectric layer 10.

The materials of the dielectric layers forming the inner dielectric layer 10 and the outer region 11 may be the same or different, and are not particularly limited, and are made of a dielectric material having a perovskite structure such as ABO3. In ABO3, A is at least one kind such as Ca, Ba and Sr, and B is at least one kind such as Ti and Zr. The molar ratio of A / B is not particularly limited and is 0.980 to 1.020.

The material of the internal electrode layer 12 is not particularly limited, but for example, metals such as Ni, Cu, Ag, Pd, and Al, or alloys thereof can be used.

The materials of the terminal electrodes 6 and 8 are not particularly limited, but usually at least one kind such as Ni, Pd, Ag, Au, Cu, Pt, Rh, Ru, Ir, or an alloy thereof can be used. Usually, Cu, Cu alloy, Ni or Ni alloy or the like, Ag, Ag-Pd alloy, In-Ga alloy or the like is used.

The shape and size of the multilayer ceramic capacitor 2 may be appropriately determined according to the purpose and application. When the multilayer ceramic capacitor 2 has a rectangular parallelepiped shape, the vertical dimension L0 (see FIG. 1) is usually 0.2 to 5.7 mm, but in the present embodiment, it is preferably 0.3 to 3.2 mm, and further. It is preferably 0.38 to 2.1 mm, particularly preferably 0.38 to 1.60 mm.

In FIG. 1, the vertical dimension L0 of the multilayer ceramic capacitor 2 is drawn as the length in the Y-axis direction of the capacitor element 4, but it is the length in the Y-axis direction of the multilayer ceramic capacitor 2 including the terminal electrodes 6 and 8. It is almost the same. In the drawings, the thicknesses of the terminal electrodes 6 and 8 are drawn thicker than they actually are for the sake of facilitation of illustration, but in reality, they are each about 10 to 50 μm, which is extremely large compared to the vertical dimension L0. thin. Further, in the drawings, the X-axis, the Y-axis, and the Z-axis are perpendicular to each other, the Z-axis coincides with the stacking direction of the inner dielectric layer 10 and the inner electrode layer 12, and the Y-axis is the lead-out region 15A and. It coincides with the direction in which 15B (drawers 12A and 12B) is formed.

As shown in FIG. 2, the height dimension H0 of the multilayer ceramic capacitor 2 varies depending on the number of layers of the inner dielectric layer 10 and the inner electrode layer 12, but is generally 0.2 to 3.2 mm. However, in this embodiment, it is preferably 0.2 to 1.6 mm. The height dimension H0 of the multilayer ceramic capacitor 2 is drawn as the thickness of the capacitor element 4 in the Z-axis direction in FIG. 2, but since the thickness of the terminal electrodes 6 and 8 shown in FIG. 1 is sufficiently thin, It is almost the same as the thickness including these.

The width dimension W0 of the multilayer ceramic capacitor 2 is generally 0.2 to 5.0 mm, but in the present embodiment, it is 0.59 mm or less, preferably 0.10 to 0.59 mm, and more preferably 0. It is .15 to 0.59 mm, particularly preferably 0.185 to 0.47 mm. When the thickness of the dielectric layer is 0.4 μm or less, if the width dimension W0 becomes too large, cracks are likely to occur in the manufactured capacitor body. The possible causes are as follows.

When the thickness of the dielectric layer is reduced, the density of the internal electrode layer is relatively increased in the interior region 13 which is the capacitance forming portion, and the density is relatively high between the dielectric layer and the ceramic layer forming the side surface protection region 16 and the exterior region 11 during firing. It is conceivable that the acting stress will increase. In particular, when the thickness of the dielectric layer is 0.4 μm or less and the width dimension W0 is 0.80 mm or more, the density of the internal electrodes in the interior region 13 which is the capacitance forming portion is large, and the area (volume) occupied in the ceramic capacitor is further increased. ) Is also large, so the influence of stress is large and cracks are likely to occur.

The thickness td (see FIG. 2) of each inner dielectric layer 10 is generally several μm to several tens of μm, but in the present embodiment, it is 0.4 μm or less, preferably 0.4 to 0.1 μm. , More preferably 0.4 to 0.3 μm. The thickness te of the internal electrode layer 12 (see FIG. 2) is preferably about the same as the thickness of the inner dielectric layer 10, but more preferably te / td is determined to be less than 1.25, particularly. Preferably, the te / td is determined to be 0.95 to 1.05. With such a configuration, the crack suppressing effect is improved.

Further, in the present embodiment, the width Wgap of each side surface protection region 16 shown in FIG. 2 in the X-axis direction is the outer surface (X-axis) of the ceramic body 4 along the width direction (X-axis direction) of the ceramic body 4. It matches the clearance dimension from the end face in the direction to the end of the internal electrode layer 12. This width Wgap is 0.010 to 0.025 mm, preferably 0.015 to 0.025 mm. If this width Wgap is too small, cracks are likely to occur, and if this width Wgap is too large, the decrease in capacitance tends to be large.

This width Wgap is determined in relation to the width dimension W0 of the capacitor 2. In the present embodiment, their ratio Wgap / W0 is 0.025 or more, and if this ratio is too small, cracks are likely to occur. It tends to be. It should be noted that the widths Wgaps of the side surface protection regions 16 formed on both sides of the capacitor body 4 in the X-axis direction are the same or different from each other, provided that the above conditions are satisfied. Is also good.

The thickness t0 of the exterior region 11 (see FIG. 1) is not particularly limited, but is preferably in the range of 15 to 200 μm, more preferably 15 to 80 μm. By setting such a thickness t0, cracks are suppressed, the internal electrode layer 12 and the inner dielectric layer 10 are protected, and the size is reduced. The thickness t0 of the exterior region 11 formed on both sides of the capacitor body 4 in the Z-axis direction may be the same or different from each other, provided that the above conditions are satisfied.

In particular, in the present embodiment, when the average particle size of the first dielectric particles constituting the inner dielectric layer 10 is Di and the average particle size of the second dielectric particles located in the exterior region 11 is Dg, The relationship is preferably Dg / Di ≧ 1, more preferably Dg / Di ≧ 1.05, and particularly preferably Dg / Di ≧ 1.15. With this configuration, even if the dielectric layer is thinned, the capacitance is further improved. Generally, it has been reported that the relative permittivity decreases as the dielectric layer becomes thinner. However, the present inventors have found that by controlling the particle size of the dielectric particles in a specific region, it is possible to suppress a decrease in the relative permittivity even if the dielectric layer is made thin.

Further, in the present embodiment, when the average particle size of the first dielectric particles constituting the inner dielectric layer 10 is Di, and the average particle size of the third dielectric particles constituting the extraction regions 15A and 15B is Dh. , Preferably Dh / Di ≧ 1, more preferably Dh / Di ≧ 1.1, and particularly preferably Dh / Di ≧ 1.2. With this configuration, even if the dielectric layer is thinned, the capacitance is further improved. Generally, it has been reported that the relative permittivity decreases as the dielectric layer becomes thinner. However, the present inventors have found that by controlling the particle size of the dielectric particles in a specific region, it is possible to suppress a decrease in the relative permittivity even if the dielectric layer is made thin.

The reason why the decrease in the relative permittivity can be suppressed even if the dielectric layer is made thin is considered as follows.

That is, by making the average particle size of the dielectric particles constituting the exterior region 11 or the extraction regions 15A and 15B larger than the average particle size of the dielectric particles in the capacitance region 14, compressive stress is applied to the dielectric in the capacitance region 14. Is considered to be given. Therefore, it is considered that the relative permittivity is improved. Since the dielectric of the capacitance region 14 of the multilayer ceramic capacitor 2 is a polycrystalline material, the compression direction is not limited, but it is particularly possible to increase the crystal grain size of the dielectrics of the exterior region 11 or the extraction regions 15A and 15B. It is considered to contribute to the improvement of the dielectric constant.

In particular, it was confirmed that the dielectric layer 10 is particularly effective when the thickness of the dielectric layer 10 is 0.5 μm or less. When the dielectric layer is thicker than 0.5 μm, the relative permittivity is high even if the dielectric in the capacitance region of the multilayer ceramic capacitor is not subjected to compressive stress (even if the particle ratio is not controlled), but 0. In the dielectric layer of 5 μm or less, the decrease in the relative permittivity can be suppressed, and conversely, the relative permittivity can be improved.

From this point of view, the same can be said for the dielectric particles in the side protection region 16 which can be composed of the same dielectric particles as the extraction regions 15A and 15B. That is, when the average particle size of the first dielectric particles constituting the inner dielectric layer 10 is Di and the average particle size of the fourth dielectric particles forming the side surface protection region 16 is Dh', Dh is preferable. The relationship is'/ Di ≧ 1, more preferably Dh'/ Di ≧ 1.1, and particularly preferably Dh'/ Di ≧ 1.2.

Method for Manufacturing Multilayer Ceramic Capacitor Next, a method for manufacturing the monolithic ceramic capacitor 2 as an embodiment of the present invention will be described.

First, in order to manufacture the inner green sheet 10a that constitutes the inner dielectric layer 10 shown in FIG. 1 after firing and the outer green sheet 11a that constitutes the outer dielectric layer of the exterior region 11, the inner green Prepare the sheet paste and the outer green sheet paste.

The inner green sheet paste and the outer green sheet paste are usually composed of an organic solvent-based paste or an aqueous paste obtained by kneading a ceramic powder and an organic vehicle.

As the raw material of the ceramic powder, various compounds to be composite oxides and oxides, for example, carbonates, nitrates, hydroxides, organometallic compounds and the like can be appropriately selected and mixed and used. In the present embodiment, the raw material of the ceramic powder is used as a powder having an average particle size of 0.45 μm or less, preferably about 0.1 to 0.3 μm. In order to make the inner green sheet extremely thin, it is desirable to use a powder finer than the thickness of the green sheet.

An organic vehicle is a binder dissolved in an organic solvent. The binder used for the organic vehicle is not particularly limited, and may be appropriately selected from various ordinary binders such as ethyl cellulose and polyvinyl butyral.

Further, the organic solvent to be used is not particularly limited, and various organic solvents such as tarpineol, butyl carbitol, acetone, and toluene may be appropriately selected depending on the method to be used such as a printing method and a sheet method.

The green sheet paste may contain additives selected from various dispersants, plasticizers, dielectrics, subcomponent compounds, glass frits, insulators and the like, if necessary.

Examples of the plasticizer include phthalates such as dioctyl phthalate and benzyl butyl phthalate, adipic acid, phosphoric acid esters, and glycols.

Next, a paste for the internal electrode pattern layer for forming the internal electrode layer 12 shown in FIG. 1 is prepared. The paste for the internal electrode pattern layer is obtained by kneading the above-mentioned conductive material made of various conductive metals and alloys, or the above-mentioned various oxides, organometallic compounds, resinates, etc., which become the above-mentioned conductive material after firing, and the above-mentioned organic vehicle. To prepare. If necessary, the paste for the internal electrode pattern layer may contain ceramic powder as a co-material. The co-material has an effect of suppressing the sintering of the conductive powder in the firing process.

Using the inner green sheet paste and the inner electrode pattern layer paste prepared above, as shown in FIG. 3, the inner green sheet 10a which becomes the inner dielectric layer 10 after firing and the inner electrode layer 12 after firing. The internal electrode pattern layer 12a and the internal electrode pattern layer 12a are alternately laminated to produce an internal laminated body 13a that becomes an interior region 13 after firing. Then, after or before the production of the inner laminate 13a, the outer green sheet paste is used to form the outer green sheet 11a which becomes the outer dielectric layer of the exterior region 11 after firing.

Specifically, first, the inner green sheet 10a is formed on a carrier sheet (for example, PET film) as a support by a doctor blade method or the like. The inner green sheet 10a is formed on the carrier sheet and then dried.

Next, the inner electrode pattern layer 12a is formed on the surface of the inner green sheet 10a formed above by using the paste for the inner electrode pattern layer to obtain the inner green sheet 10a having the inner electrode pattern layer 12a. Then, the inner green sheets 10a having the obtained inner electrode pattern layer 12a are alternately laminated to obtain the inner laminated body 13a. The method for forming the internal electrode pattern layer 12a is not particularly limited, and examples thereof include a printing method and a transfer method. The inner green sheet 10a having the internal electrode pattern layer 12a may be laminated via the adhesive layer.

The outer green sheet 11a is formed on the carrier sheet as a support, similarly to the inner green sheet 10a. The outer green sheet 11a is formed on the carrier sheet and then dried. The thickness of the outer green sheet 11a is sufficiently thicker than that of the inner green sheet 10a.

As shown in FIG. 4, an internal electrode pattern layer 12a is formed on the surface of the inner green sheet 10a, and a gap 30 along the longitudinal direction Y of the internal electrode pattern layer 12a and an internal electrode pattern are formed between them. A gap 32 along the lateral direction X of the layer 12a is formed, and these form a grid-like pattern when viewed from a plane. The step absorbing layer 20 shown in FIG. 3 may be formed in the gaps 30 and 32 of these grid-like patterns. In FIG. 3, only the gap 32 is shown.

By forming the step absorbing layer 20 in these gaps 30 and 32, the step due to the internal electrode pattern layer 12a is eliminated on the surface of the green sheet 10a, which also contributes to the prevention of deformation of the finally obtained capacitor body 4. The step absorbing layer 20 is formed by a printing method or the like in the same manner as the internal electrode pattern layer 12a, for example. The step absorbing layer 20 contains the same ceramic powder and organic vehicle as the green sheet 10a, but unlike the green sheet 11a, it is formed by printing and is therefore adjusted so that it can be easily printed. Examples of the printing method include screen printing and gravure printing, and the printing method is not particularly limited, but screen printing is preferable.

The organic binder component (polymer resin + plasticizer) in the printing paste for forming the step absorbing layer 20 and various additives are the same as those used for the green sheet slurry. However, these do not necessarily have to be exactly the same as those used for the green sheet slurry, and may be different. The thickness of the step absorbing layer 20 is not particularly limited, but is preferably 50 to 100% of the thickness of the internal electrode pattern layer 12a.

Instead of laminating the inner laminated body 13a on the outer green sheet 11a, a predetermined number of the inner green sheet 10a and the inner electrode pattern layer 12a may be alternately laminated directly on the outer green sheet 11a. Further, a laminated body unit in which a plurality of inner green sheets 10a and a plurality of internal electrode pattern layers 12a are alternately laminated may be prepared in advance, and a predetermined number of them may be laminated on the outer green sheet 11a.

As shown in FIGS. 5A and 5B, the obtained green laminate 4a is cut to a predetermined size along, for example, a cutting line C to obtain a green chip. The green chips are solidified by removing the plasticizer by solidification drying. The green chips after solidification and drying are put into a barrel container together with the media and the polishing liquid, and are barrel-polished by a horizontal centrifugal barrel machine or the like. After barrel polishing, the green chips are washed with water and dried. The capacitor element 4 shown in FIG. 1 is obtained by performing a binder removing step, a firing step, and an annealing step performed as necessary on the dried green chip. Note that FIGS. 5A and 5B are only schematic cross-sectional views, and the number of layers and the dimensional relationship are different from the actual ones.

The sintered body (element body 4) thus obtained is subjected to end face polishing by barrel polishing or the like, and terminal electrode paste is baked to form terminal electrodes 6 and 8. Then, if necessary, a pad layer is formed by plating or the like on the terminal electrodes 6 and 8. The terminal electrode paste may be prepared in the same manner as the internal electrode pattern layer paste described above.

The multilayer ceramic capacitor 2 manufactured in this manner is mounted on a printed circuit board or the like by soldering or the like, and is used in various electronic devices and the like.

According to the multilayer ceramic capacitor 2 of the present embodiment, the thickness of the dielectric layer 10 is 0.4 μm or less, the width dimension W0 is 0.59 mm or less, and the gap dimension Wgap is 0.010 to 0.025 mm. , The ratio of the gap dimension to the width dimension Wgap / W0 dimension is 0.025 or more. Therefore, even when the thickness of the dielectric layer is reduced, the occurrence of cracks can be suppressed and the decrease in capacitance is small.

The present invention is not limited to the above-described embodiment, and can be variously modified within the scope of the present invention.

For example, in the above-mentioned usual manufacturing method, a dielectric paste is used as a raw material for forming the dielectric particles constituting the inner dielectric layer 10, the outer region 11, and the extraction regions 15A and 15B shown in FIGS. 1 and 2. The particle sizes of the contained dielectric particles are substantially the same. Therefore, in the resulting multilayer ceramic capacitors 2 shown in FIGS. 1 and 2, when the thickness of the dielectric layer 10 sandwiched between the internal electrode layers 12 is reduced to 0.4 μm or less, the dielectric layers 10 are sandwiched between the internal electrode layers 12. The dielectric particles of the dielectric layer 10 have a larger average particle size than the dielectric particles of the regions 11, 15A and 15B not sandwiched by the internal electrode layers. It is considered that the cause is that the dielectric particles of the dielectric layer 10 sandwiched between the internal electrode layers 12 are more likely to promote grain growth.

That is, in the above-described embodiment, when the average particle size of the first dielectric particles constituting the dielectric layer 10 is Di and the average particle size of the second dielectric particles located in the exterior region 11 is Dg. Dg / Di <1. Further, in the above-described embodiment, when the average particle size of the third dielectric particles constituting the extraction regions 15A and 15B is Dh, Dh / Di <1. Further, when the average particle size of the fourth dielectric particles constituting the side surface protection region 16 is Dh', Dh'/ Di <1.

Therefore, in the production method according to another embodiment of the present invention, the average particle size of the dielectric particles as the dielectric paste raw material for forming the inner dielectric layer 10 shown in FIGS. 1 and 2 is set to the outer region 11. And / or make it larger than the average particle size of the dielectric particles contained in the dielectric paste raw material for forming the respective dielectric particles constituting the extraction regions 15A and 15B. Alternatively, conversely, the dielectrics constituting the exterior region 11 and / or the extraction regions 15A and 15B are compared with the average particle size of the dielectric particles as the dielectric paste raw material for forming the inner dielectric layer 10. The average particle size of the dielectric particles contained in the dielectric paste raw material for forming the particles is reduced.

As a result, in the capacitor element 4 after firing, the relationship of Dg / Di ≧ 1, or Dh / Di ≧ 1, or Dh'/ Di ≧ 1, or all of them can be satisfied. The reason can be considered as follows. The smaller the particle size of the dielectric particles of the dielectric paste raw material, the more active it is with respect to heat, so that grain growth is likely to occur during firing. Therefore, the average particle size of the dielectric particles constituting the outer region 11 and / or the extraction regions 15A and 15B should be smaller than the average particle size of the dielectric particles for forming the inner dielectric layer 10 which is the capacitance portion. Therefore, the dielectric particles forming the outer region 11 and / or the extraction regions 15A and 15B are more likely to grow than the dielectric particles for forming the inner dielectric layer 10 which is the capacitance portion. Then, as a result, the dielectric particles in the exterior region 11 and / or the extraction regions 15A and 15B can be made larger.

In such a relationship, even if the inner dielectric layer 10 is thinned, the capacitance is further improved. Generally, it has been reported that the relative permittivity decreases as the dielectric layer 10 becomes thinner. However, the present inventors have found that by controlling the particle size of the dielectric particles in a specific region, it is possible to suppress a decrease in the relative permittivity even if the dielectric layer 10 is made thinner.

Further, in the present invention, the above-mentioned relationship may be satisfied in the capacitor element 4 after firing by a method other than changing the average particle size of the dielectric particles of the dielectric paste raw material. For example, for forming the dielectric particles constituting the exterior region 11 and / or the extraction regions 15A and 15B as compared with the composition of the dielectric particles as the dielectric paste raw material for forming the inner dielectric layer 10. The composition of the dielectric particles contained in the dielectric paste raw material may be different. For example, the composition of the dielectric particles contained in the dielectric paste raw material for forming the dielectric particles constituting the exterior region 11 and / or the extraction regions 15A and 15B may be set to a composition that facilitates grain growth.

Alternatively, it is possible to control the particle size of the dielectric particles after firing by interposing a dummy electrode that is not connected to the terminal electrodes 6 and 8 between the outer dielectric green sheets in the exterior region 11. ..

The multilayer ceramic electronic component of the present invention is not limited to the multilayer ceramic capacitor, and can be applied to other multilayer ceramic electronic components. Other laminated ceramic electronic components include all electronic components in which a dielectric layer is laminated via internal electrodes, such as a bandpass filter, an inductor, a laminated three-terminal filter, a piezoelectric element, a PTC thermistor, and an NTC thermistor. Varistors and the like are exemplified.

Hereinafter, the present invention will be described based on more detailed examples, but the present invention is not limited to these examples.

Example 1
First, {(Ba1-x-y Cax Sry) O} u (Ti1-z Zrz) v O3 powder (x = 0.05, y = 0, Z = 0) having an average particle size of 100 nm as the raw material powder of the main raw material. .05, u / v = 1.004) was prepared, and then MgCO3, MnCO3, Y2 O3, and SiO2 were prepared as subcomponents. The sub-component was pre-crushed in advance and processed to about 40 nm, which is smaller than the particle size of the barium titanate raw material.

Next, each raw material powder prepared above was weighed against 100 mol of the main raw material, 0.5 mol of MgCO3 powder, 0.3 mol of MnCO3 powder, 0.2 mol of Y2 O3 powder and 2 mol of SiO2 powder. .. Each of these powders was wet-mixed and dried in a ball mill for 20 hours to obtain a dielectric raw material in a volume portion. The BaCO3 and MnCO3 added at this time will be contained in the dielectric porcelain composition as BaO and MnO, respectively, after firing.

Next, the obtained dielectric raw material: 100 parts by weight, polyvinyl butyral resin: 10 parts by weight, dioctyl phthalate (DOP) as a plasticizer: 5 parts by weight, and alcohol as a solvent: 100 parts by weight were charged by a ball mill. The mixture was mixed and made into a paste to obtain a paste for a dielectric layer in the capacitance region 14.

Separately from the above, Ni particles: 44.6 parts by weight, terpineol: 52 parts by weight, ethyl cellulose: 3 parts by weight, and benzotriazole: 0.4 parts by weight are kneaded by three rolls and pasted. To prepare a paste for the internal electrode layer.

Further, as a dielectric raw material for the exterior region 11, a main raw material powder having an average particle diameter of 100 nm, which is the same as the dielectric particles in the capacitance region 14, was prepared. Wet mixing and pasting with the sub-ingredients were carried out in the same manner as the dielectric material of the interior region 13 to obtain a dielectric paste for the exterior region.

Then, a green sheet was formed on the PET film using the dielectric layer paste prepared above. At this time, the thickness of the green sheet was adjusted so that the thickness td of the dielectric layer after firing shown in Table 1 could be obtained. Next, the electrode layer was printed in a predetermined pattern using the paste for the internal electrode layer on this. The thickness of the electrode layer having a predetermined pattern was adjusted so that the thickness te of the internal electrode layer after firing shown in Table 1 could be obtained.

Further, in order to fill the step in the portion where the electrode is not printed, the step absorbing layer 20 is formed by performing pattern printing using the same paste as the dielectric paste in the capacitance region 14, to form the step absorbing layer 20 and to form the internal electrode pattern layer 12a. A green sheet 10a having the step absorbing layer 20 and the step absorbing layer 20 was produced.

Next, a green sheet was formed on the PET film using the dielectric paste for forming the exterior region 11. The thickness of the green sheet for forming the exterior region 11 was set to 10 μm. At this time, a green sheet for forming the exterior region 11 was formed using a green sheet using a dielectric material having a diameter of 100 nm.

A plurality of green sheets for the interior region 13 having an internal electrode layer and a plurality of green sheets for the exterior region 11 are laminated and pressure-bonded to form a green laminate, and the green laminate is cut to a predetermined size. As a result, a green chip was obtained.

Next, the obtained green chips were subjected to binder removal treatment, firing and annealing under the following conditions to obtain a laminated ceramic fired body.

The binder removal treatment conditions were a temperature rising rate of 25 ° C./hour, a holding temperature of 235 ° C., a holding time of 8 hours, and an atmosphere of air.

The firing conditions were a heating rate of 600 to 1000 ° C./hour, a holding temperature of 1100 to 1150 ° C., and a holding time of 1 hour. The temperature lowering rate was 200 ° C./hour. The atmospheric gas was a humidified N2 + H2 mixed gas so that the oxygen partial pressure was ^10-12 MPa.

Annealing conditions are temperature rise rate: 200 ° C./hour, holding temperature 1050 ° C., holding time: 3 hours, temperature lowering rate: 200 ° C./hour, atmospheric gas: humidified N2 gas (oxygen partial pressure: ^10-7 MPa). did.

A wetter was used for humidifying the atmospheric gas during firing and annealing.

Next, after barrel polishing the end face of the obtained laminated ceramic fired body, Cu paste was applied as an external electrode and baked in a reducing atmosphere, and the laminated ceramic capacitor samples of sample numbers 1 to 25 shown in Table 1 ( Hereinafter, it may be simply referred to as "capacitor sample").

The vertical dimension L0, the width dimension W0, and the width Wgap of the obtained capacitor sample were changed for each sample as shown in Table 1.

The capacitance and crack occurrence rate of the obtained capacitor sample were confirmed by the methods shown below.

(Capacitance)
The capacitance was measured with respect to the capacitor sample with a digital LCR meter at a reference temperature of 25 ° C. under the conditions of a frequency of 1.0 kHz and an input signal level (measurement voltage) of 1.0 Vrms. However, the numerical value of the capacitance shown in Table 1 is the capacitance when the capacitance when Wgap is 0.020 is set to 1 for a specific L0 dimension and W0 dimension capacitor body. It represents the ratio. For example, the capacitance of sample numbers 3 to 7 is a ratio based on the capacitance of sample number 5. The capacitance was set to 0.90 or more as good. The results are shown in Table 1.

(Crack occurrence rate)
The method for measuring the crack occurrence rate is the rate at which cracks are detected by visually observing the appearance of the prepared sample (n = 1000) using a microscope or the like. The crack occurrence rate is good from 0 to 1.0, and particularly good from 0 to 0.1. The results are shown in Table 1.

Example 2
As shown in Table 2, a sample of a multilayer ceramic capacitor is obtained in the same manner as in Example 1 except that the thickness td of the dielectric layer 10 after firing and the thickness te of the internal electrode layer 12 after firing are set to 0.3 μm. Was prepared, and their capacitance and crack occurrence rate were measured. The results are shown in Table 2.

Evaluation 1
From the results shown in Tables 1 and 2, the thickness td of the dielectric layer is 0.4 μm or less, the width dimension W0 is 0.59 mm or less, the gap dimension Wgap is 0.010 to 0.025 mm, and the ratio is It was confirmed that (Wgap / W0 dimension) was 0.025 or more, and a multilayer ceramic capacitor having a low crack occurrence rate and a small decrease in capacitance could be obtained.

Example 3
As shown in Table 3, samples of multilayer ceramic capacitors were prepared in the same manner as in Example 1 except that the thickness te of the internal electrode layer 12 after firing was changed, and their capacitances and crack occurrence rates were changed. Was measured. The results are shown in Table 3.

Evaluation 2
From the results shown in Table 3, when te / td is less than 1.25, particularly preferably when te / td is 0.95 to 1.05, the crack generation rate is low and the capacitance is not reduced. It was confirmed that a ceramic capacitor can be obtained.

Example 4
As shown in Table 4, the sample 16 of Example 1 was used, except that the average particle size Dg of the dielectric particles in the exterior region 11 was changed as compared with the average particle size Di of the dielectric particles in the capacitance region 14. In the same manner, samples of multilayer ceramic capacitors (sample numbers 16a to 16b) were prepared, and their capacitance and crack generation rate were measured. The results are shown in Table 4. In order to obtain a relationship of Dg / Di of 1 or more, the average particle size of the dielectric particles of the raw material contained in the dielectric paste for forming the exterior region 11 was set to 60 nm.

Example 5
As shown in Table 5, the sample of Example 1 except that the average particle size Dh of the dielectric particles in the extraction regions 15A and 15B was changed as compared with the average particle size Di of the dielectric particles in the capacitance region 14. Samples of multilayer ceramic capacitors (sample numbers 16c to 16d) were prepared in the same manner as in No. 16, and their capacitances and crack occurrence rates were measured. The results are shown in Table 5. In order to obtain a relationship of Dh / Di of 1 or more, the average particle size of the raw material dielectric particles contained in the step absorbing dielectric paste for forming the extraction regions 12A and 12B and the side surface protection region 16 was set to 60 nm. ..

The average particle size of the dielectric particles after firing was confirmed by the method shown below.

(Average particle size of dielectric)
The capacitor sample was erected vertically so that the stacking direction was on the upper side, and the periphery of the sample was filled with a cured resin using a container made of Teflon (registered trademark) having a diameter of 25 mm and a length of 20 mm. Then, sandpaper and a microfabrication polishing machine were used to polish the sample so that a cross section in the longitudinal direction was obtained, and then milling was performed using argon ions to remove surface damage.

The processed sample was magnified 20,000 times with an electron microscope to observe the dielectric particles in the capacitance region 14, the exterior region 11, and the extraction regions 15A and 15B, and the cross-sectional area of 500 particles was observed using image processing software. The equivalent circle diameter was calculated from.

Evaluation 3
From the results shown in Table 4, the dielectric layer is thinned when the relationship is preferably Dg / Di ≧ 1, more preferably Dg / Di ≧ 1.05, and particularly preferably Dg / Di ≧ 1.15. However, it was confirmed that the capacitance was further improved and the crack occurrence rate was low.

Further, from the results shown in Table 5, the dielectric layer is thinned when the relationship is Dh / Di ≧ 1, more preferably Dh / Di ≧ 1.1, and particularly preferably Dh / Di ≧ 1.2. However, it was confirmed that the capacitance was further improved and the crack occurrence rate was low.

In Example 5, since the average particle size of the raw material dielectric particles contained in the step absorbing dielectric paste was set to 60 nm, the average particle size of the fired dielectric particles contained in the side surface protection region 16 shown in FIG. 2 was set. It has been confirmed that the diameter Dh'is larger than the average particle size Di of the dielectric particles in the capacitance region 14, and Dh'/ Di is substantially the same as Dh / Di.

2 ... Multilayer ceramic capacitor 4 ... Capacitor element 6 ... 1st terminal electrode 8 ... 2nd terminal electrode 10 ... Inner dielectric layer 10a ... Inner green sheet 11 ... Exterior area 11a ... Outer green sheet 12 ... Internal electrode layers 12A, 12B ... Drawer portion 12a ... Internal electrode pattern layer 13 ... Interior area 13a ... Internal laminate 14 ... Capacitor area 15A, 15B ... Drawer area 16 ... Side protection area 20 ... Step absorption layer

Claims (3)

A ceramic body formed by alternately laminating a plurality of dielectric layers and a plurality of internal electrode layers,
A laminated ceramic electronic component having at least a pair of external electrodes connected to the internal electrode layer on the surface of the ceramic body.
The thickness of the dielectric layer is 0.5 μm or less, and the thickness is 0.5 μm or less.
The width dimension (W0) along the width direction of the ceramic element is 0.59 mm or less.
The gap dimension (Wgap) from the outer surface of the ceramic body to the end of the internal electrode layer along the width direction of the ceramic body is 0.010 to 0.025 mm.
Said ratio (WGAP / W0 dimensions) of the gap size and the width dimension Ri der 0.025 or more,
Wherein a thickness of the internal electrode layer (te) the ratio of the thickness of the dielectric layer (td) (te / td) is a multilayer ceramic electronic component, characterized in der Rukoto less than 1.25. The laminated ceramic electronic component according to claim 1, wherein the ratio (te / td) of the thickness (te) of the internal electrode layer to the thickness (td) of the dielectric layer is 0.95 or more. The laminated ceramic electronic component according to claim 1 or 2 , wherein the ratio (te / td) of the thickness (te) of the internal electrode layer to the thickness (td) of the dielectric layer is 0.95 to 1.05. ..

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