JP7292826B2 - 試験測定システム、波形処理方法及びコンピュータ・プログラム - Google Patents
試験測定システム、波形処理方法及びコンピュータ・プログラム Download PDFInfo
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- JP7292826B2 JP7292826B2 JP2018045966A JP2018045966A JP7292826B2 JP 7292826 B2 JP7292826 B2 JP 7292826B2 JP 2018045966 A JP2018045966 A JP 2018045966A JP 2018045966 A JP2018045966 A JP 2018045966A JP 7292826 B2 JP7292826 B2 JP 7292826B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
- H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03834—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping
- H04L25/03853—Shaping by digital methods other than look up tables or up/down converters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03592—Adaptation methods
- H04L2025/03598—Algorithms
- H04L2025/03611—Iterative algorithms
- H04L2025/03636—Algorithms using least mean square [LMS]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Dc Digital Transmission (AREA)
Description
hオリジナル*hイコライザ=hターゲット
に従って生成され、このとき、hオリジナルは信号パルスを表し、hイコライザは線形イコライザを表し、hターゲットはターゲット・パルスを表し、*は畳み込み積分演算子(convolution operator)を表す。
hオリジナル*hイコライザ=hターゲット
に従って生成され、このとき、hオリジナルは信号パルスを表し、hイコライザは線形イコライザを表し、hターゲットはターゲット・パルスを表し、*は畳み込み積分演算子(convolution operator)を表す。
hオリジナル*hイコライザ=hターゲット
に従って生成され、このとき、hオリジナルは信号パルスを表し、hイコライザは線形イコライザを表し、hターゲットはターゲット・パルスを表し、*は畳み込み積分演算子(convolution operator)を表す。
hオリジナル*hイコライザ=hターゲット
710 被試験デバイス(DUT)
720 オシロスコープ
721 プロセッサ
722 ISIイコライザ
725 A/Dコンバータ
727 入力ポート
729 表示装置
761 入力信号
765 波形データ
Claims (5)
- 入力信号を受ける入力ポートと、
上記入力信号を表す波形用の波形メモリと、
該波形メモリに結合されたプロセッサと
を具え、
該プロセッサが、
上記波形から信号パルスを抽出し、
時間領域において、該信号パルスの形状に基づいて整数個のユニット・インターバルの幅を有する窓関数を選択し、
上記信号パルスに上記窓関数を適用して、上記窓関数の窓の外のシンボル間干渉(ISI)を除去するよう構成される
試験測定システム。 - 上記プロセッサは、
上記窓関数を上記信号パルスに適用してターゲット・パルスを取得し、
上記信号パルスと畳み込み積分されたときに上記ターゲット・パルスを生じる線形イコライザを生成し、
該線形イコライザを上記波形に適用することによって、
上記窓関数を上記信号パルスに適用する請求項1の試験測定システム。 - メモリから信号を表す波形を取得する処理と、
プロセッサによって上記波形から信号パルスを抽出する処理と、
上記プロセッサによって時間領域において上記信号パルスの形状に基づいて整数個のユニット・インターバルの幅を有する窓関数を選択する処理と、
上記窓関数の窓の外のシンボル間干渉(ISI)を除去するために、上記プロセッサによって上記窓関数を上記信号パルスに適用する処理と
を具える波形処理方法。 - 上記窓関数を上記信号パルスに適用してターゲット・パルスを取得し、
上記信号パルスと畳み込み積分されたときに上記ターゲット・パルスを生じる線形イコライザを生成し、
該線形イコライザを上記波形に適用することによって、
上記窓関数が上記信号パルスに適用される請求項3の波形処理方法。 - 試験測定システムのプロセッサによって実行されたときに、上記試験測定システムに、請求項3又は4の方法を実行させるコンピュータ・プログラム。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762470757P | 2017-03-13 | 2017-03-13 | |
US62/470,757 | 2017-03-13 | ||
US15/687,364 US10075286B1 (en) | 2017-03-13 | 2017-08-25 | Equalizer for limited intersymbol interference |
US15/687,364 | 2017-08-25 |
Publications (2)
Publication Number | Publication Date |
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JP2018159702A JP2018159702A (ja) | 2018-10-11 |
JP7292826B2 true JP7292826B2 (ja) | 2023-06-19 |
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JP2018045966A Active JP7292826B2 (ja) | 2017-03-13 | 2018-03-13 | 試験測定システム、波形処理方法及びコンピュータ・プログラム |
Country Status (4)
Country | Link |
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US (1) | US10075286B1 (ja) |
EP (1) | EP3376726A1 (ja) |
JP (1) | JP7292826B2 (ja) |
CN (1) | CN108574652B (ja) |
Families Citing this family (1)
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KR102549607B1 (ko) * | 2019-01-28 | 2023-06-29 | 삼성전자주식회사 | 크로스토크 노이즈 및 심볼 간 간섭을 선택적으로 보상할 수 있는 전자 회로 |
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JP2012170081A (ja) | 2011-02-14 | 2012-09-06 | Fujitsu Ltd | 判定帰還型等化器を用いた受信機のためのクロック回復回路 |
JP2016213834A (ja) | 2015-05-01 | 2016-12-15 | テクトロニクス・インコーポレイテッドTektronix,Inc. | クロック・リカバリ装置及び方法並びにクロック・リカバリ方法を実行するためのプログラム |
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2017
- 2017-08-25 US US15/687,364 patent/US10075286B1/en active Active
-
2018
- 2018-03-12 EP EP18161315.9A patent/EP3376726A1/en active Pending
- 2018-03-13 CN CN201810204212.XA patent/CN108574652B/zh active Active
- 2018-03-13 JP JP2018045966A patent/JP7292826B2/ja active Active
Patent Citations (6)
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US6995553B1 (en) | 2005-02-24 | 2006-02-07 | Agilent Technologies, Inc. | User interface for operating upon an eye diagram to find optimum sampling parameters for a receiver |
JP2007325070A (ja) | 2006-06-02 | 2007-12-13 | Netindex Inc | 多重伝送装置および多重伝送方法 |
JP2009271063A (ja) | 2008-04-30 | 2009-11-19 | Tektronix Inc | 等化シミュレータ及び等化シミュレーション方法 |
US20110150060A1 (en) | 2009-12-23 | 2011-06-23 | Sun Microsystems, Inc. | Voltage Margin Monitoring for an ADC-Based Serializer/Deserializer in Mission Mode |
JP2012170081A (ja) | 2011-02-14 | 2012-09-06 | Fujitsu Ltd | 判定帰還型等化器を用いた受信機のためのクロック回復回路 |
JP2016213834A (ja) | 2015-05-01 | 2016-12-15 | テクトロニクス・インコーポレイテッドTektronix,Inc. | クロック・リカバリ装置及び方法並びにクロック・リカバリ方法を実行するためのプログラム |
Also Published As
Publication number | Publication date |
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US20180262325A1 (en) | 2018-09-13 |
CN108574652B (zh) | 2022-06-14 |
CN108574652A (zh) | 2018-09-25 |
JP2018159702A (ja) | 2018-10-11 |
EP3376726A1 (en) | 2018-09-19 |
US10075286B1 (en) | 2018-09-11 |
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