JP7282684B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7282684B2 JP7282684B2 JP2019548787A JP2019548787A JP7282684B2 JP 7282684 B2 JP7282684 B2 JP 7282684B2 JP 2019548787 A JP2019548787 A JP 2019548787A JP 2019548787 A JP2019548787 A JP 2019548787A JP 7282684 B2 JP7282684 B2 JP 7282684B2
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- insulating layer
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- semiconductor
- transistor
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Description
本実施の形態では、本発明の一態様の半導体装置について説明する。以下では、半導体装置の一態様であるトランジスタについて説明する。
図1(A)は、トランジスタ100の上面図であり、図1(B)は、図1(A)に示す一点鎖線A1-A2における切断面の断面図に相当し、図1(C)は、図1(A)に示す一点鎖線B1-B2における切断面の断面図に相当する。なお、図1(A)において、トランジスタ100の構成要素の一部(ゲート絶縁層等)を省略して図示している。また、一点鎖線A1-A2方向をチャネル長方向、一点鎖線B1-B2方向をチャネル幅方向と呼称する場合がある。また、トランジスタの上面図においては、以降の図面においても図1(A)と同様に、構成要素の一部を省略して図示する場合がある。
図2(A)は、トランジスタ100Aの上面図であり、図2(B)は、トランジスタ100Aのチャネル長方向の断面図であり、図2(C)は、トランジスタ100Aのチャネル幅方向の断面図である。
以下では、構成例1及び構成例2の変形例について説明する。
次に、本実施の形態の半導体装置に含まれる構成要素について、詳細に説明する。
基板102の材質などに大きな制限はないが、少なくとも、後の熱処理に耐えうる程度の耐熱性を有している必要がある。例えば、シリコンや炭化シリコンを材料とした単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板、ガラス基板、セラミック基板、石英基板、サファイア基板等を、基板102として用いてもよい。また、これらの基板上に半導体素子が設けられたものを、基板102として用いてもよい。
絶縁層104としては、スパッタリング法、CVD法、蒸着法、パルスレーザー堆積(PLD)法等を適宜用いて形成することができる。また、絶縁層104としては、例えば、酸化物絶縁膜または窒化物絶縁膜を単層または積層して形成することができる。なお、半導体層108との界面特性を向上させるため、絶縁層104において少なくとも半導体層108と接する領域は酸化物絶縁膜で形成することが好ましい。また、絶縁層104には、加熱により酸素を放出する膜を用いることが好ましい。
ゲート電極として機能する導電層112及び導電層106、並びにソース電極またはドレイン電極の一方として機能する導電層120a及び、他方として機能する導電層120bとしては、クロム、銅、アルミニウム、金、銀、亜鉛、モリブデン、タンタル、チタン、タングステン、マンガン、ニッケル、鉄、コバルトから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いてそれぞれ形成することができる。
トランジスタ100等のゲート絶縁膜として機能する絶縁層110は、PECVD法、スパッタリング法等により形成できる。絶縁層110としては、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁層を用いることができる。なお、絶縁層110を、2層の積層構造または3層以上の積層構造としてもよい。
半導体層108がIn-M-Zn酸化物の場合、In-M-Zn酸化物を成膜するために用いるスパッタリングターゲットは、Inの原子数比がMの原子数比以上であることが好ましい。このようなスパッタリングターゲットの金属元素の原子数比として、In:M:Zn=1:1:1、In:M:Zn=1:1:1.2、In:M:Zn=2:1:3、In:M:Zn=3:1:2、In:M:Zn=4:2:4.1、In:M:Zn=5:1:6、In:M:Zn=5:1:7、In:M:Zn=5:1:8、In:M:Zn=6:1:6、In:M:Zn=5:2:5等が挙げられる。
以下では、本発明の一態様のトランジスタの作製方法の例について説明する。ここでは、構成例2で例示したトランジスタ100Aを例に挙げて説明する。
基板102上に導電膜を形成し、これをエッチングにより加工して、ゲート電極として機能する導電層106を形成する(図5(A))。
続いて、基板102、導電層106を覆って絶縁層103と絶縁層104を積層して形成する(図5(B))。絶縁層103及び絶縁層104はそれぞれ、PECVD法、ALD法、スパッタリング法などを用いて形成することができる。
続いて、絶縁層104上に金属酸化物膜108af及び金属酸化物膜108bfを成膜する(図5(D))。
続いて、半導体層108及び絶縁層104上に、ダミー層113を形成する(図6(A))。ダミー層113は、後の導電層112や絶縁層110が設けられる開口部を形成するための層である。
続いて、絶縁層104、半導体層108、及びダミー層113を覆って、絶縁層115を形成する(図6(B))。またこのとき、半導体装置の端部において、絶縁層115と絶縁層103とが接する領域が形成される。
続いて、加熱処理を行うことが好ましい。加熱処理により、半導体層108の領域108nの低抵抗化をより促進させることができる。
続いて、絶縁層115を覆って絶縁層118を形成する(図6(C))。絶縁層118は、後に行われる平坦化処理による薄膜化を考慮して、十分に厚く形成することが好ましい。絶縁層118は、例えばPECVD法により形成することができる。
続いて、ダミー層113の上部が露出するように、絶縁層118、絶縁層115、及びダミー層113に対して平坦化処理を行う(図7(A))。
続いてダミー層113をエッチングにより除去する(図7(B))。これにより、半導体層108のチャネル形成領域上に、絶縁層118の開口部が形成される。またこのとき、絶縁層118の開口部の内壁に接して、絶縁層115が設けられる構造を形成することができる。
続いて、上記開口部を埋めるように絶縁膜110fを成膜し、続けて導電膜112fを成膜する(図7(C))。
続いて、絶縁層118上部が露出するように、導電膜112f、絶縁膜110f、絶縁層115、及び絶縁層118に対して第2の平坦化処理を行う(図8(A))。第2の平坦化処理は、第1の平坦化処理と同様に行うことができる。
続いて、絶縁層118、絶縁層115、絶縁層110及び導電層112上に絶縁層116を形成する(図8(B))。絶縁層116は、絶縁層103と同様の方法により形成できる。
続いて、第2の加熱処理を行うことが好ましい。第2の加熱処理は、上記第1の加熱処理と同様の条件で行うことができる。
続いて、絶縁層116の所望の位置に、リソグラフィによりマスクを形成した後、絶縁層116、絶縁層118、および絶縁層115の一部をエッチングすることで、領域108nに達する開口部141aおよび開口部141bを形成する。
続いて、開口部141a及び開口部141bを覆うように、絶縁層116上に導電膜を成膜し、当該導電膜を所望の形状に加工することで、導電層120a、導電層120bを形成する(図8(C)))。
本実施の形態においては、先の実施の形態で例示したトランジスタを有する表示装置の一例について説明を行う。
図9(A)に、表示装置700の上面図を示す。表示装置700は、シール材712により貼りあわされた第1の基板701と第2の基板705を有する。また第1の基板701、第2の基板705、及びシール材712で封止される領域において、第1の基板701上に画素部702、ソースドライバ回路部704、及びゲートドライバ回路部706が設けられる。また画素部702には、複数の表示素子が設けられる。
本実施の形態では、本発明の一態様の半導体装置を有する表示装置について説明する。
本実施の形態では、図12および図13を用いて、本発明の一態様に係るトランジスタ、および容量素子が適用されている記憶装置の一例として、DOSRAMについて説明する。DOSRAM(登録商標)とは、「Dynamic Oxide Semiconductor RAM」の略称であり、1T(トランジスタ)1C(容量)型のメモリセルを有するRAMを指す。
図12にDOSRAMの構成例を示す。図12に示すように、DOSRAM1400は、コントローラ1405、行回路1410、列回路1415、メモリセルおよびセンスアンプアレイ(以下、「MC-SAアレイ1420」と呼ぶ。)を有する。
MC-SAアレイ1420は、メモリセルアレイ1422をセンスアンプアレイ1423上に積層した積層構造をもつ。グローバルビット線GBLL、GBLRはメモリセルアレイ1422上に積層されている。DOSRAM1400では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。
コントローラ1405は、DOSRAM1400の動作全般を制御する機能を有する。コントローラ1405は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路1410、列回路1415の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。
行回路1410は、MC-SAアレイ1420を駆動する機能を有する。デコーダ1411はアドレス信号をデコードする機能を有する。ワード線ドライバ回路1412は、アクセス対象行のワード線WLを選択する選択信号を生成する。
列回路1415は、データ信号WDA[31:0]の入力を制御する機能、データ信号RDA[31:0]の出力を制御する機能を有する。データ信号WDA[31:0]は書き込みデータ信号であり、データ信号RDA[31:0]は読み出しデータ信号である。
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図14に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。
評価1では、昇温脱離ガス分析法(TDS:Thermal Desorption Spectroscopy)を用いて、窒化アルミニウム膜の水素ブロッキング性を評価した。
評価2では、TDSを用いて、窒化アルミニウム膜の酸素ブロッキング性を評価した。
評価3では、TDSを用いて、窒化アルミニウム膜の酸素吸引性を評価した。
評価4では、酸化物半導体膜上に窒化アルミニウム膜を形成しベークした試料における、酸化物半導体膜のシート抵抗を評価した。
評価5では、酸化物半導体膜上に窒化アルミニウム膜を形成しベークした試料における、酸化物半導体膜中の水素濃度及び窒素濃度を、SSDP-SIMS(Substrate Side Depth Profile Secondary Ion Mass Spectrometry)分析(基板裏面からのSIMS分析)により評価した。
評価6では、酸化物半導体膜上に窒化アルミニウム膜を形成しベークした試料における、酸化物半導体膜中の酸素濃度を、SIMS分析により評価した。
Claims (1)
- 第1の絶縁層、第2の絶縁層、第3の絶縁層、第4の絶縁層、半導体層、及び第1の導電層を有し、
前記半導体層は、前記第1の絶縁層上に接して設けられ、且つ、第1の領域と、第2の領域と、を有し、
前記第2の絶縁層は、前記第1の絶縁層、及び前記第2の領域上に設けられ、且つ、前記第1の領域と重なる第1の開口部を有し、
前記第1の導電層は、前記第1の開口部の内側に位置し、且つ、前記第1の領域と重なる部分を有し、
前記第3の絶縁層は、前記第1の開口部の内側に位置し、且つ、前記第1の導電層の側面及び底面を覆い、且つ、前記半導体層の前記第1の領域の上面に接し、
前記第4の絶縁層は、前記第1の絶縁層の上面、前記半導体層の側面、及び前記第2の領域の上面に接し、且つ、前記第1の開口部の内側において、前記第2の絶縁層と、前記第3の絶縁層との間に位置する部分を有し、
前記半導体層は、金属酸化物を含み、
前記第1の絶縁層及び前記第3の絶縁層は、酸化物を含み、
前記第4の絶縁層は、金属窒化物を含む、
半導体装置。
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PCT/IB2018/057908 WO2019077451A1 (ja) | 2017-10-20 | 2018-10-12 | 半導体装置 |
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JP2015144251A (ja) | 2013-12-26 | 2015-08-06 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
JP2016207759A (ja) | 2015-04-20 | 2016-12-08 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
JP2018073994A (ja) | 2016-10-28 | 2018-05-10 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2018201011A (ja) | 2017-05-26 | 2018-12-20 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
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JP2016207759A (ja) | 2015-04-20 | 2016-12-08 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
JP2018073994A (ja) | 2016-10-28 | 2018-05-10 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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JP2018201011A (ja) | 2017-05-26 | 2018-12-20 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
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