JP7263929B2 - semiconductor equipment - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device including a double-gate switching element.

For example, Patent Literature 1 discloses a semiconductor device including a double-gate switching element having two gate electrodes. In this type of semiconductor device, independent gate voltages can be applied to the two gate electrodes of the switching element.

Patent Document 2 also discloses a semiconductor device having a similar switching element. In this semiconductor device, when turning off the switching element, after applying a turn-off voltage to the second gate, a turn-off voltage is applied to the first gate to turn off the switching element. According to the above configuration, by first lowering the voltage of the second gate to the turn-off voltage equal to or lower than the threshold voltage, some of the carriers accumulated in the drift layer are extracted in advance. Therefore, by first reducing the voltage of the second gate and then reducing the voltage of the first gate to turn off the switching element, the time for extracting carriers is shortened. That is, the turn-off speed of the switching element is improved.

JP 2019-016805 A JP 2013-098415 A

When controlling the switching elements by PWM (Pulse Width Modulation), the following two methods are conceivable in order to realize the above configuration. That is, in the first method, one PWM signal is generated and used to control two gate signals. At this time, a PWM signal obtained by adding a predetermined delay time to the PWM signal is used for the first gate (or the second gate). According to this method, one PWM signal can control two gates at different timings. However, by using the PWM signal with the delay time, there is a possibility that the control of the switching element will also be delayed.

In contrast, in the second method, two PWM signals are generated respectively, one PWM signal is used to control the first gate and the other PWM signal is used to control the second gate. At this time, one PWM signal (hereinafter referred to as the first PWM signal) is generated based on the first carrier signal and the duty value, and the other PWM signal (hereinafter referred to as the second PWM signal) is generated from the first carrier signal. It is generated based on the second carrier signal whose phase is advanced by a predetermined time and the duty value. According to such a configuration, it is possible to suppress a delay in controlling the switching element while enabling the first gate and the second gate to be controlled at different timings. However, if the common duty value is changed before the preceding second PWM signal changes and before the first PWM signal follows and changes, the waveforms of the two PWM signals may differ from each other. . As a result, for example, only the second gate may be turned off (or turned on) for a short period of time, and such unnecessary turning on and off of the second gate may increase the losses of the switching element. This specification provides techniques that can avoid or reduce such problems.

A semiconductor device disclosed in this specification includes a switching element, a controller, and a drive circuit. The switching element is a double gate type switching element having two gates, a first gate and a second gate. The controller generates a first command signal, which is a binary signal, based on the first carrier signal and the common duty value. At the same time, the controller generates a second command signal, which is a binary signal, based on a second carrier signal whose phase is advanced by a predetermined time from the first carrier signal and the common duty value. A drive circuit is connected to the switching element and the controller, and drives the first gate and the second gate based on the first command signal and the second command signal, respectively. The drive circuit has a logic circuit and a gate drive circuit. A logic circuit generates a first signal (MG+V) and a second signal (MG0) based on the first command signal. At the same time, the driving circuit generates a third signal (CG+V), a fourth signal (CG0) and a fifth signal (CG-V) based on the first command signal and the second command signal. The gate control circuit selectively applies a reference voltage or an ON voltage higher than the reference voltage to the first gate based on the first signal (MG+V) and the second signal (MG0). At the same time, the gate control circuit supplies the second gate with a reference voltage, an ON voltage, or a voltage lower than the reference voltage based on the third signal (CG+V), the fourth signal (CG0) and the fifth signal (CG-V). An off-voltage, which is a voltage, is selectively applied. The logic circuit further has a first mask circuit and a second mask circuit. The first mask circuit generates a first latch signal that is latched by a NOT signal of the second command signal and reset by a NOR signal of the first command signal and the second command signal. A second mask circuit generates a second latched signal that is latched by the second command signal and reset by the first command signal. The first signal (MG+V) is the first command signal. The second signal (MG0) is a NOT signal of the first command signal. The third signal (CG+V) is the AND signal of the NOR signal of the first latch signal and the second latch signal and the first command signal. A fourth signal (CG0) is a second latch signal. The fifth signal (CG-V) is the NOR signal of the third signal (CG+V) and the fourth signal (CG0).

According to the above configuration, the first mask circuit and the second mask circuit are respectively the first command signal, the second command signal, and the first latch signal and the second latch signal that are latched by the rise and fall of their OR signal. Generate a signal. More specifically, the first latch signal is a signal that is latched by the NOT signal of the second command signal and reset by the NOR signal of the first command signal and the second command signal. The second latch signal is a signal that is latched by the second command signal and reset by the first command signal. Three signals (third signal, fourth signal, and fifth signal) can be generated by using the first latch signal and the second latch signal, and these three signals are used to generate the second latch signal. By controlling the gate, unnecessary turning on/off of the second gate at unintended timing can be suppressed.

Further, according to the above configuration, the voltage applied to the second gate can be increased stepwise when the switching element is turned on. As a result, the turn-on speed of the switching element can be increased, and loss due to switching can be suppressed.

Details and further improvements of the technique disclosed in this specification are described in the following "Mode for Carrying Out the Invention".

1 is a circuit diagram of a semiconductor device according to a first embodiment; FIG. 1 is a configuration diagram of a logic circuit of a first embodiment; FIG. 4 is a time chart showing two carrier signals, a duty signal, and two command signals generated therefrom; Fig. 2 is a graph of two input signals to a logic circuit, two mask circuit output signals, and a NOR signal of the two output signals; 5 is a graph of the five output signals of the logic circuit and the gate voltage of each gate; It is a circuit diagram of the semiconductor device of the second embodiment. FIG. 11 is a configuration diagram of a logic circuit of a second embodiment; It is a graph of the input signal to the logic circuit and the output signal of the third mask circuit. Fig. 2 is a graph of two output signals for the first gate of the logic circuit; FIG. 4 is a graph of the gate voltage of the first gate; FIG. 7 is a flowchart of changing the set time of the variable timer; 4 is a graph showing conduction loss, switching loss, and total loss with respect to time from turning off the second gate to turning off the first gate 132; It is a circuit diagram of a semiconductor device of a third embodiment. 10 is a flow chart of control of each gate executed by the gate control circuit of the third embodiment; FIG. 11 is a graph of the gate voltage of the first gate and the gate voltage of the second gate for several embodiments controlled by the gate control circuit of the third embodiment; FIG.

In one embodiment of the present technology, the drive circuit may change the timing of turning off the first gate with respect to turning off the second gate, according to the current flowing through the switching element. In this case, the drive circuit may include, for example, a variable timer, and the set time of the variable timer may be changed according to the current flowing through the switching element. Then, the drive circuit may use a variable timer to change the turn-off timing of the first gate with respect to the turn-off of the second gate. With such a configuration, the total loss of the loss due to conduction and the loss due to switching can be reduced.

Additionally or alternatively, the drive circuit may monitor the leakage of each gate, and limit the voltage applied to that gate when leakage is detected for only one gate. On the other hand, the drive circuit may stop driving the switching element when leakage is detected for both gates. According to such a configuration, when a light leak occurs only in one gate, by limiting only the voltage applied to the gate, the operation of the switching element can be continued without being excessively limited. can.

(First Embodiment) A semiconductor device 2 of a first embodiment will be described with reference to FIGS. 1 to 5. FIG. The semiconductor device 2 is mounted on an electric vehicle, for example, and can constitute a part of a power converter such as an inverter or a DC-DC converter that converts power between a power source and a load. However, the semiconductor device 2 of this embodiment is not limited to such uses, and can be used for various uses.

As shown in FIG. 1, the semiconductor device 2 includes an ASIC 4 (Application Specific Integrated Circuit), two insulating elements 6 and 8, a controller 10, a drive circuit 20, and a switching element 30. The switching element 30 is a double gate type switching element having two gates, a first gate 32 and a second gate 34 . As an example, the switching element 30 of this embodiment is a double-gate type IGBT (Insulated Gate Bipolar Transistor). When a voltage greater than the threshold voltage of the gate is applied to at least one of the first gate 32 and the second gate 34 , the switching element 30 is turned on and collector current flows from the collector 36 to the emitter 38 . Switching element 30 further comprises a sense emitter 39 . A minute current proportional to the collector current flows through the sense emitter 39 . By detecting this minute current, the magnitude of the collector current can be measured. Note that the switching element 30 is not limited to an IGBT, and may be a bipolar transistor, for example.

The controller 10 outputs a first command signal PWM1 and a second command signal PWM2 based on control commands input from a higher control unit (not shown). The first command signal PWM1 and the second command signal PWM2 are command signals for the switching element 30, and more specifically, pulse width modulation (PWM) signals. The first command signal PWM1 is a command signal for controlling the first gate 32, and the second command signal PWM2 is a command signal for controlling the second gate . As shown in FIG. 3, the controller 10 generates the first command signal PWM1 based on the first carrier signal and the duty signal. The first command signal PWM1 is a binary signal indicating either high or low. The first command signal PWM1 indicates high when the first carrier signal has a larger value than the duty signal, and indicates low when the first carrier signal has a smaller value than the duty signal.

Similarly, controller 10 generates second command signal PWM2 based on the second carrier signal and the duty signal. The second command signal PWM2 is also a binary signal indicating either high or low. The second command signal PWM2 indicates high when the second carrier signal has a larger value than the duty signal, and indicates low when the second carrier signal has a smaller value than the duty signal. Here, the second carrier signal is a signal whose phase is advanced by a predetermined time from the above-described first carrier signal. This predetermined time is determined by the carrier accumulation time of the switching element 30, for example. On the other hand, as for the duty signal, a common duty signal is used in generating the first command signal PWM1 and the second command signal PWM2. Although not particularly limited, in this embodiment, the first carrier signal and the second carrier signal are triangular waves. The duty signal is a variable signal that is adjusted within the amplitude of the triangular wave based on the above-described control command from the higher order.

The controller 10 is connected to the drive circuit 20 via the ASIC 4 and isolation elements 6,8. The ASIC 4 is an integrated circuit in which circuits with a plurality of functions are combined into one for a specific application, such as an integrated circuit for driving a motor. The insulating elements 6 and 8 can transmit only signals between the controller 10 and the switching element 30 while electrically insulating the controller 10 and the switching element 30 . The insulating elements 6, 8 are photocouplers, for example. Command signals PWM1 and PWM2 output from the controller 10 are input to the drive circuit 20 via the ASIC 4 and the insulating elements 6 and 8 . The drive circuit 20 is connected to the first gate 32 and the second gate 34 of the switching element 30, and based on the input command signals PWM1 and PWM2, the gate voltage Vg1 of each of the first gate 32 and the second gate 34. , Vg2, respectively.

The drive circuit 20 comprises a logic circuit 22 and a gate control circuit 24 . Logic circuit 22 generates five signals MG+V, MG0, CG+V, CG0, and CG-V based on two command signals PWM1 and PWM2 transmitted from controller 10 . The five signals generated in logic circuit 22 are transmitted to gate control circuit 24 . The gate control circuit 24 independently controls the gate voltage Vg1 of the first gate 32 and the gate voltage Vg2 of the second gate 34 based on these transmitted signals. The configuration of the logic circuit 22 will be described in detail later with reference to FIG.

As described above, in the semiconductor device 2 of the present embodiment, the controller 10 generates two command signals PWM1 and PWM2, and the driving circuit 20 controls the two switching elements 30 based on the command signals PWM1 and PWM2. Controls the gates 32,34. However, the drive circuit 20 does not directly use the two command signals PWM1, PWM2 to control the two gates 32, 34, but instead converts the five signals MG+V, MG0, CG+V, CG0, and CG-V by the logic circuit 22. Generate. The two gates 32, 34 of the switching element 30 are controlled based on the five signals MG+V, MG0, CG+V, CG0, and CG-V. This is because using the two command signals PWM1 and PWM2 as they are to control the two gates 32 and 34 causes the following problems.

That is, since the second carrier signal is a signal whose phase is advanced by a predetermined time from the first carrier signal, the second command signal PWM2 is also a signal whose phase is advanced by a predetermined time from the first command signal PWM1. Be expected. However, if the two command signals PWM1 and PWM2 are generated from different carrier signals and a common duty signal, the waveforms of the first command signal PWM1 and the second command signal PWM2 may differ depending on the timing at which the duty signal changes, for example. There may be discrepancies. An example thereof will be described with reference to the time chart illustrated in FIG.

In the time chart shown in FIG. 3, since the first carrier signal and the second carrier signal are larger than the duty signal until time t1, both the first command signal PWM1 and the second command signal PWM2 are high. Next, during the period from time t1 to time ft1, the second carrier signal is smaller than the duty signal. Therefore, the second command signal PWM2 indicates low. On the other hand, the first command signal PWM1 remains high. Next, from time ft1 to time t2, the second carrier signal becomes larger than the duty signal again. Therefore, the second command signal PWM2 indicates high. On the other hand, after time T1 during this period, the first carrier signal becomes smaller than the duty signal. Therefore, the first command signal PWM1 is high from time ft1 to time T1 and low from time T1 to time t2.

Assume that the duty signal is updated at time t2 (D1). Accordingly, the second carrier signal becomes smaller than the duty signal, so PWM2 changes to low. On the other hand, even if the duty signal is updated, the first command signal PWM1 remains low. After that, from time t2 to time t3, the first carrier signal and the second carrier signal are smaller than the duty signal. Therefore, both the first command signal PWM1 and the second command signal PWM2 indicate low.

The second carrier signal is greater than the duty signal from time t3 to time ft2. Therefore, the second command signal PWM2 indicates high. On the other hand, the first command signal PWM1 indicates low. Next, from time ft2 to time D2, the second carrier signal becomes smaller than the duty signal again. Therefore, the second command signal PWM2 indicates low. After time t4 (T2) during this period, the first carrier signal becomes larger than the duty signal. Therefore, the first command signal PWM1 is low from time ft2 to time T2 and high from time T2 to time D2. Assume that the duty signal is updated again at time D2. Accordingly, the second carrier signal becomes larger than the duty signal, so the second command signal PWM2 indicates high. On the other hand, even if the duty signal is updated, the first command signal PWM1 remains high.

As described above, the second command signal PWM2 is temporarily switched to low between time ft1 and time t2. In contrast, such a change does not appear in the first command signal PWM1. Also, during the period from time ft2 to time D2, the second command signal PWM2 is temporarily switched to low, but no such change appears in the first command signal PWM1. If these two command signals PWM1 and PWM2 were used as they were for controlling the switching element 30, only the second gate 34 would be unnecessarily turned off (or turned on). It may increase losses. In order to avoid or reduce such problems, the semiconductor device 2 of this embodiment includes the logic circuit 22 described above, and the five signals MG+V, MG0, CG+V, CG0, and Based on CG-V, two gates 32, 34 of switching element 30 are controlled.

The logic circuit 22 will be described in detail below. As shown in FIG. 2, the logic circuit 22 includes a first mask circuit 22a and a second mask circuit 22b. The first mask circuit 22a outputs a first latch signal La1 for two input signals S and R. FIG. The first latch signal La1 is set when the input signal S rises and reset when the input signal R rises. That is, the first mask circuit 22a is a circuit that outputs high when the input signal S rises when the input signal R indicates low, and holds this output until the next time the input signal R switches from low to high. is. This circuit holds the value of the input signal S at the timing when the input signal R changes from high to low until the next time the input signal R changes from low to high. Note that when both the input signal S and the input signal R indicate high, the first latch signal La1 indicates low. The input signal S is a NOT signal of PWM2. Input signal R is a NOR signal of PWM1 and PWM2. That is, the first mask circuit 22a is a circuit that is latched by the fall of PWM2 and reset when both PWM1 and PWM2 indicate low. The first latch signal La1 will be described in more detail later with reference to the graph of FIG.

The second mask circuit 22b outputs a second latch signal La2 for the two input signals S and R. The second latch signal La2 is set by the rising edge of the input signal S and reset by the input signal R. That is, the second mask circuit 22b is a circuit that outputs high when the input signal S rises when the input signal R indicates low, and holds this until the next time the input signal R switches from low to high. is. Note that when both the input signal S and the input signal R indicate high, the second latch signal La2 indicates low. The input signal S is PWM2. The input signal R is PWM1. That is, the second mask circuit 22b is a circuit that is latched by the rise of PWM2 and reset by the rise of PWM1. The second latch signal La2 will also be described in more detail later with reference to the graph of FIG.

A signal MG+V and a signal MG0 are signals used to control the gate voltage Vg1 of the first gate 32 . More specifically, when the signal MG+V indicates high, the gate control circuit 24 sets the gate voltage Vg1 applied to the first gate 32 to V volts. The voltage V volts is a higher voltage than the threshold voltage of the first gate 32 . Further, when the signal MG0 indicates high, the gate control circuit 24 sets the gate voltage Vg1 applied to the first gate 32 to zero volts. A voltage of zero volts is a voltage lower than the threshold voltage of the first gate 32 . The signal MG+V is the same signal as the first command signal PWM1. Also, the signal MG0 is a NOT signal of the first command signal PWM1. Due to the way the signal MG+V and the signal MG0 are determined, the signal MG+V and the signal MG0 are never high (or low) at the same time. That is, the gate control circuit 24 selectively applies V volts or zero volts to the first gate 32 .

Signal CG+V, signal CG0, and signal CG-V are signals used to control the gate voltage Vg2 of the second gate . More specifically, when the signal CG+V indicates high, the gate control circuit 24 sets the gate voltage Vg2 applied to the second gate 34 to V volts. The voltage V volts is a higher voltage than the threshold voltage of the second gate 34 . When the signal CG0 indicates high, the gate control circuit 24 sets the gate voltage Vg2 applied to the second gate 34 to zero volts. When the signal CG-V indicates high, the gate control circuit 24 sets the gate voltage Vg2 applied to the second gate 34 to -V volts. A voltage of zero volts and a voltage of −V volts are voltages below the threshold voltage of the second gate 34 . The signal CG+V is an AND signal of the first command signal PWM1 and the NOR signal of the first latch signal La1 and the second latch signal La2. The signal CG0 is the same signal as the second latch signal La2. Signal CG-V is the NOR signal of signal CG+V and signal CG0. Because of the way signals CG+V, CG0, and CG-V are defined, no more than two of these three signals are high at the same time. That is, gate control circuit 24 selectively applies V volts, zero volts, or -V volts to second gate 34 .

Subsequently, referring to FIG. 4, regarding the first command signal PWM1, the second command signal PWM2, the first latch signal La1, the second latch signal La2, and the NOR signal of the first latch signal La1 and the second latch signal La2, explain the graph of In addition, below, these signals may be simply described as PWM1, PWM2, La1, and La2. As described above, the phase of the second carrier signal that generates PWM2 leads the phase of the first carrier signal that generates PWM1 by a predetermined time. There is a difference.

Until time t1, both PWM1 and PWM2 are high. The input signal S of the first mask circuit 22a is the NOT signal of PWM2 and therefore indicates low, and the input signal R is the NOR signal of PWM1 and PWM2 and thus indicates low. Therefore, La1 indicates low. Further, the input signal S of the second mask circuit 22b is PWM2, so it indicates high, and the input signal R, which is PWM1, indicates high. Therefore, La2 indicates low.

At time t1, PWM2 falls before PWM1. Then, the input signal S of the first mask circuit 22a switches from low to high, and the input signal R indicates low. Therefore, La1 indicates high. La1 stays high until the next input signal R goes high, ie until both PWM1 and PWM2 go low. Therefore, La1 indicates high during the period from time t1 to time t2.

As for the second mask circuit 22b, the input signal S switches from low to high at time ft1 during the period from time t1 to time t2. However, at time ft1, the input signal R also indicates high, so La2 indicates low at time ft1. Between time t1 and time t2, the timing at which the input signal S switches from low to high is only time ft1. Therefore, since La2 does not switch from low to high during the period from time t1 to time t2, La2 indicates low during this period.

At time t2, PWM1 falls. Also, at time t3, PWM2 rises prior to PWM1. Therefore, during the period from time t2 to time t3, both PWM1 and PWM2 are low. Therefore, since the input signal S of the first mask circuit 22a indicates high and the input signal R indicates high, La1 indicates low. In the second mask circuit 22b, PWM2 is low from time t2 until PWM2 rises at time t3. That is, in the second mask circuit 22b, since the input signal S does not switch from low to high during the period from time t2 to time t3, La2 is held low during the period from time t2 to time t3. there is

At time t3, PWM2 rises before PWM1. In the first mask circuit 22a, the input signal S switches from low to high at time ft2 in the period from time t3 to time t4 when PWM1 falls. However, at time ft2, since both PWM1 and PWM2 indicate low, the input signal R indicates high. During the period from time t3 to time t4, the timing at which the input signal S switches from low to high is only time ft2. Therefore, since La1 does not switch from low to high during the period from time t3 to time t4, La1 indicates low during this period.

Also, as described above, PWM2 rises prior to PWM1 at time t3. Then, the input signal S of the second mask circuit 22b switches from low to high, and the input signal R indicates low. Therefore, La2 indicates high. La2 remains high until the next input signal R becomes high, that is, until PWM1 rises. Therefore, La2 is high during the period from time t3 to time t4.

After time t4, both PWM1 and PWM2 are high. Therefore, the process from time t4 onwards is the same as that up to time t1, so the description is omitted.

Also, the NOR signal of La1 and La2 can be easily calculated from the above La1 and La2.

FIG. 5A is a graph representing five signals output by the logic circuit 22. FIG. As described above, the signal MG+V is the same signal as PWM1, and the signal MG0 is the NOT signal of PWM1, so the graphs of the signal MG+V and the signal MG0 in FIG. 5A can be easily obtained. Since the signal CG+V is an AND signal of PWM1 and the NOR signal of La1 and La2, it indicates high before time t1 and after time t4, and indicates low during the remaining period. Since the signal CG0 is the same signal as La2, it is a signal that indicates high during the period from time t3 to time t4 and indicates low during the remaining period. Since the signal CG-V is the NOR signal of the signal CG+V and the signal CG0, it is a signal that indicates high during the period from time t1 to time t3 and indicates low during the remaining period.

5B is a graph showing the gate voltage Vg1 applied to the first gate 32 and the gate voltage Vg2 applied to the second gate 34 by the gate control circuit 24. FIG. Since the gate voltage Vg1 is determined based on the signal MG+V and the signal MG0 as described above, it can be easily determined from (A) of FIG. Similarly, the gate voltage Vg2 is also easily determined from (A) of FIG.

According to the above configuration, as shown in FIG. 4, PWM2 has unnecessary rising and falling edges, but as shown in FIG. do not. That is, it is possible to suppress unnecessary turning on/off of the second gate 34 at unintended timings.

Also, although PWM2 is a binary signal, by providing the logic circuit 22, the gate control circuit 24 can change the gate voltage Vg2 of the second gate 34 using three values of V volts, zero volts, and -V volts. can be controlled. That is, when the switching element 30 is turned on, the gate voltage Vg2 applied to the second gate 34 can be increased stepwise. As a result, the turn-on speed of the switching element 30 can be increased, and loss due to switching can be suppressed.

(Second Embodiment) A semiconductor device 102 of a second embodiment will be described with reference to FIGS. 6 to 10. FIG. As shown in FIGS. 6 and 7, the semiconductor device 102 further includes a resistor 109, a variable timer 122d, and a current detection circuit 126. FIG. Variable timer 122 d is incorporated in drive circuit 120 and connected to sense emitter 139 via resistor 109 , although not particularly limited. The drive circuit 120 is configured to change the set time of the variable timer 122 d according to the current flowing through the switching element 130 . The drive circuit 120 is configured to change the turn-off timing of the first gate 132 with respect to the turn-off of the second gate 134 using the variable timer 122d. The semiconductor device 102 of the present embodiment is the same as the semiconductor device 2 of the first embodiment, except for these points and the fact that the configuration of the logic circuit 122 is partially different, so the description of overlapping parts will be omitted. .

The reason why the variable timer 122d is provided in the semiconductor device 102 of the second embodiment will be described with reference to FIG. FIG. 10 is a graph showing loss due to conduction (conduction loss) occurring when switching element 130 is turned off, loss due to turn-off (switching loss), and the total loss thereof. Note that the fact that the switching element 130 is off means that both the first gate 132 and the second gate 134 are off. Time on the horizontal axis represents the time from turning off the second gate 134 to turning off the first gate 132 (hereinafter referred to as off delay time). In FIG. 10, a graph connecting diamond points indicates conduction loss, a graph connecting square points indicates switching loss, and a graph connecting triangle points indicates total loss. The point indicated by the arrow in the figure represents the point where the total loss is minimum. The magnitude of the current flowing through the switching element 130 is different between (A) and (B) of FIG. 10 . That is, FIG. 10A shows a case where the current flowing through the switching element 130 is small, and FIG. 10B shows a case where the current flowing through the switching element 130 is large.

Comparing FIG. 10A and FIG. 10B, the switching loss decreases as the off-delay time is set longer, regardless of the magnitude of the current. In addition, as can be understood by comparing the two graphs (A) and (B), regardless of the magnitude of the current, the relationship (behavior of change) of the switching loss with respect to the off-delay time is similar. The rate will gradually decline. On the other hand, the conduction loss increases as the off-delay time is set longer, and the rate of increase increases as the current flowing through the switching element 130 increases. Therefore, the OFF delay time that minimizes the total loss generated in switching element 130 depends on the magnitude of the current flowing through switching element 130 . More specifically, the larger the current flowing through the switching element 130, the shorter the off-delay time at which the total loss is minimized.

The variable timer 122d is connected to the current detection circuit 126, which will be described later in detail. The variable timer 122 d can change the turn-off timing of the first gate 132 with respect to the turn-off of the second gate 134 (that is, the off delay time) according to the current detected by the current detection circuit 126 . Therefore, the total loss generated in switching element 130 can be reduced.

Returning to the description of FIG. 6 again. Resistor 109 is connected between sense emitter 139 and current detection circuit 126 . Current detection circuit 126 measures the current flowing through sense emitter 139 by detecting the voltage drop across resistor 109 caused by the current flowing through sense emitter 139 . Since the collector current flowing from the collector 136 to the emitter 138 of the switching element 130 is proportional to the current flowing through the sense emitter 139, the collector current can be measured by measuring the current flowing through the sense emitter 139. FIG.

Next, the logic circuit 122 will be explained. As shown in FIG. 7, the logic circuit 122 further includes a third mask circuit 122c and a variable timer 122d. Except for this point, the logic circuit 122 of the present embodiment is the same as the logic circuit 22 of the first embodiment, so the description of overlapping portions will be omitted.

The third mask circuit 122c outputs a third latch signal La3 for the two input signals S and R. The third latch signal La3 is set when the input signal S rises and reset when the input signal R rises. That is, the third mask circuit 122c outputs high when the input signal S rises when the input signal R indicates low, and holds this output until the next time the input signal R switches from low to high. is. Note that when both the input signal S and the input signal R indicate high, the third latch signal La3 indicates low. The input signal S is a NOT signal of the first command signal PWM1. The input signal R is a signal obtained by delaying the NOT signal of the first command signal PWM1 by a predetermined time. That is, the first mask circuit 22a is a circuit that is latched by the falling edge of the first command signal PWM1 and reset after a predetermined period of time. The third latch signal La3 will be described later in more detail with reference to the graph of FIG.

As shown in FIG. 7, before the NOT signal of the first command signal PWM1 is input to the reset-side input terminal of the third mask circuit 122c, it is input to the variable timer 122d. The variable timer 122d delays the NOT signal of the input first command signal PWM1 by a predetermined time. The variable timer 122d can change the predetermined delay time. In this embodiment, the variable timer 122d can select any one of the first time, the second time, and the third time for the predetermined delay time. The variable timer 122 d is connected to the current detection circuit 126 . The variable timer 122d sets the set time to any one of the first time, the second time, and the third time based on the current detected by the current detection circuit 126. FIG. Note that in a modified example, the variable timer 122d stores a map regarding the current detected by the current detection circuit 126 and the set time, and may change the set time based on the current detected by the current detection circuit 126.

The signal MG+V is an OR signal of the first command signal PWM1 and the third latch signal La3. Signal MG0 is a NOT signal of signal MG+V. As can be seen from how MG+V and MG0 are determined, the signal MG+V and the signal MG0 are never high (or low) at the same time. That is, the gate control circuit 124 selectively applies +V volts or zero volts to the first gate 132 .

Next, with reference to FIG. 8A, graphs of the first command signal PWM1 and the third latch signal La3 will be described. In the following description, the third latch signal La3 may be simply referred to as La3. PWM1 is high until time T1. Accordingly, the input signal S of the third mask circuit 122c is the NOT signal of PWM1, and therefore indicates low. Also, the input signal R becomes either high or low depending on the delay time of the variable timer 122d. In either case, La3 indicates low.

At time T1, PWM1 falls. Then, the input signal S of the third mask circuit 122c switches from low to high. Also, the input signal R indicates low because the NOT signal of PWM1 is delayed by the variable timer 122d for a predetermined time. Therefore, at time T1, La3 indicates high. La3 remains high until the input signal R of the third mask circuit 122c switches from low to high.

After that, at time T3 after a predetermined time has passed (that is, the predetermined time of the variable timer 122d is T3-T1, and the time T3 changes depending on the set time of the variable timer 122d), the input signal R of the third mask circuit 122c is Switch from low to high. Since the input signal S of the third mask circuit 122c indicates high, La3 switches to low.

Since PWM1 is a pulse wave, the trailing edge occurs only once within one period of PWM1. That is, after time T3, there is no timing at which PWM1 falls within one cycle of PWM1. That is, after time T3, there is no timing at which the input signal S of the third mask circuit 122c switches from low to high within one cycle of PWM1. Therefore, La3 indicates low within one cycle of PWM1 after time T3. Therefore, it is the period from time T1 to time T3 that La3 is high within one cycle of PWM1.

FIG. 8B is a graph representing signal MG+V and signal MG0 output from logic circuit 122. FIG. Since signal MG+V is the OR signal of PWM1 and La3, and signal MG0 is the NOT signal of signal MG+V, these graphs can be easily obtained from (A) of FIG.

(C) of FIG. 8 is a graph representing the gate voltage Vg1 applied to the first gate 132 by the gate control circuit 124 . Since the gate voltage Vg1 is determined based on the signal MG+V and the signal MG0 as described above, it can be easily determined from (B) of FIG.

FIG. 9 is a flowchart for changing the set time of the variable timer 122d. First, the variable timer 122d acquires the sense current detected by the current detection circuit 126 (step S2). After that, it is determined whether or not the sense current acquired in step S2 is greater than the first threshold current (step S4).

When it is determined that the sense current acquired in step S2 is greater than the first threshold current, the variable timer 122d sets the set time to the first time (step S4: YES, S6). If it is determined that the sense current acquired in step S2 is smaller than the first threshold current, it is determined whether or not the sense current is greater than the second threshold current (step S4: NO, S8). note that. The second threshold current is less than the first threshold current.

When it is determined that the sense current acquired in step S2 is greater than the second threshold current, the variable timer 122d sets the set time to the second time (step S8: YES, S10). When it is determined that the sense current acquired in step S2 is smaller than the first threshold current, the variable timer 122d sets the set time to the third time (step S8: NO, S12).

According to the above, the set time of the variable timer 122d, that is, the turn-off timing of the first gate 132 with respect to the turn-off of the second gate 134 can be changed based on the sense current. Thereby, the total loss of the loss due to conduction and the loss due to switching can be reduced.

The technique of the second embodiment is the first method described above, that is, the method of generating one PWM signal and using it to control two gate signals. gate), a method of using a PWM signal obtained by giving a predetermined delay time to the PWM signal is also suitable.

(Third Embodiment) A semiconductor device 202 of a third embodiment will be described with reference to FIGS. 11 to 13. FIG. As shown in FIG. 11, the semiconductor device 202 further includes a first gate resistor 207, a second gate resistor 209, and a current detection circuit 226. FIG. Except for this point, the semiconductor device 2 is the same as the semiconductor device 2 of the first embodiment, so the description of overlapping parts will be omitted.

The first gate resistor 207 is connected between the drive circuit 220 and the first gate 232 . The first gate resistor 207 is also connected to the current detection circuit 226 . The first gate resistor 207 serves to monitor the current flowing through the first gate 232 . The current detection circuit 226 measures the current flowing through the first gate 232 by detecting the voltage drop across the first gate resistor 207 caused by the current flowing through the first gate 232 .

A second gate resistor 209 is connected between the drive circuit 220 and a second gate 234 . The second gate resistor 209 is also connected to the current detection circuit 226 . The second gate resistor 209 serves to monitor the current flowing through the second gate 234 . The current detection circuit 226 measures the current flowing through the second gate 234 by detecting the voltage drop across the second gate resistor 209 caused by the current flowing through the second gate 234 .

The first gate resistor 207 can monitor whether leakage occurs in the first gate 232 . Further, it is possible to monitor whether or not leakage occurs in the second gate 234 by the second gate resistor 209 . Also, the current detection circuit 226 is connected to the gate control circuit 224 . Information about the current flowing through the first gate 232 and information about the current flowing through the second gate 234 detected by the current detection circuit 226 are transmitted to the gate control circuit 224 . That is, information on whether or not leakage occurs in the first gate 232 and the second gate 234 is transmitted to the gate control circuit 224 .

Continued use of the leaky gate may cause failure of the switching element 230 . Therefore, the gate control circuit 224 limits the voltage applied to either the first gate 232 or the second gate 234 when leakage is detected in only one of the gates. Further, the gate control circuit 224 stops driving the switching element 230 when leakage is detected for both gates. Furthermore, when a short circuit is detected in only one of the gates, use of that gate is prohibited.

Control of each gate executed by the gate control circuit 224 will be described with reference to FIG. First, the gate control circuit 224 determines whether or not leakage occurs in the first gate 232 (step S20). The gate control circuit 224 determines whether leakage occurs in the first gate 232 based on the information about the current flowing through the first gate 232 transmitted from the current detection circuit 226 . When it is determined that leakage occurs in the first gate 232, the gate control circuit 224 turns off the first gate 232 (step S20: YES, S22). That is, the gate control circuit 224 sets the gate voltage Vg1 applied to the first gate 232 to zero volts regardless of the two signals MG+V and MG0.

After that, the gate control circuit 224 determines whether or not a short circuit occurs in the first gate 232 (step S24). Similar to the leakage determination, the gate control circuit 224 determines whether or not a short circuit occurs in the first gate 232 based on the information on the current flowing through the first gate 232 transmitted from the current detection circuit 226 . When it is determined that the first gate 232 is short-circuited, the gate control circuit 224 sets the first gate 232 to the OFF mode (step S24: YES, S26). That is, use of the first gate 232 is prohibited.

Further, when it is determined that the first gate 232 is not short-circuited, the gate control circuit 224 sets the first gate 232 to the low voltage mode (step S24: NO, S28). That is, the gate control circuit 224 sets the gate voltage Vg1 applied to the first gate 232 to VL volts when the signal MG+V indicates high. The voltage VL volts is a lower voltage than the voltage V volts applied to the first gate 232 when the signal MG+V indicates high when the first gate 232 is not in the low voltage mode.

After that, the gate control circuit 224 determines whether or not leakage occurs in the second gate 234 (step S30). The gate control circuit 224 determines whether leakage occurs in the second gate 234 based on the information on the current flowing through the second gate 234 transmitted from the current detection circuit 226 .

When it is determined that leakage occurs in the second gate 234, the gate control circuit 224 stops the operation of the switching element 230 (step S30: YES, S32). In this case, both the first gate 232 and the second gate 234 are leaking and/or shorting. In such a situation, the operation of switching element 230 is stopped (step S32).

If it is determined that no leak has occurred in the second gate 234, the process returns to START and restarts from step S20 (step S30: NO, to START). In this case, only the first gate 232 is leaking or shorting. In such a situation, the gate control circuit 224 reduces the voltage applied to the first gate 232 or prohibits the use of the first gate 232, and controls the second gate 234 without restriction. Switching element 230 is operated.

When it is determined in step S20 that no leakage occurs in the first gate 232, the gate control circuit 224 determines whether leakage occurs in the second gate 234 (step S20: NO, S34). . The gate control circuit 224 determines whether leakage occurs in the second gate 234 based on the information on the current flowing through the second gate 234 transmitted from the current detection circuit 226 .

If the second gate 234 determines that no leak has occurred, the process returns to START and restarts from step S20 (step S34: NO, to START). In this case, neither the first gate 232 nor the second gate 234 are leaking or shorting. That is, both gates are normal, and the gate control circuit 224 performs control as described in the first embodiment.

Also, when it is determined that leakage occurs in the second gate 234, the gate control circuit 224 turns off the second gate 234 (step S34: YES, S36). That is, the gate control circuit 224 sets the gate voltage Vg2 applied to the second gate 234 to zero volts regardless of the three CG+V, CG0, and CG-V.

After that, the gate control circuit 224 determines whether or not a short circuit occurs in the second gate 234 (step S38). Similar to the leakage determination, the gate control circuit 224 determines whether a short circuit has occurred in the second gate 234 based on information on the current flowing through the second gate 234 transmitted from the current detection circuit 226 . If it is determined that the second gate 234 is short-circuited, the gate control circuit 224 sets the second gate 234 to the OFF mode (step S38: YES, S42). That is, use of the second gate 234 is prohibited. After that, the process returns to the start and restarts from the process of step S20.

If it is determined that the second gate 234 is not short-circuited, the gate control circuit 224 sets the second gate 234 to the low voltage mode (step S38: NO, S40). That is, the gate control circuit 224 sets the gate voltage Vg2 applied to the second gate 234 to VL volts when the signal CG+V indicates high. The voltage VL volts is a lower voltage than the voltage V volts applied to the second gate 234 when the signal CG+V indicates high when not in the low voltage mode. Further, the gate control circuit 224 sets the gate voltage Vg2 applied to the second gate 234 to -VL volts when the signal CG-V indicates high. After that, the process returns to the start and restarts from the process of step S20.

In these cases, only the second gate 234 is leaking or shorting. In such a situation, the gate control circuit 224 reduces the absolute value of the voltage applied to the second gate 234 or prohibits the use of the second gate 234 and restricts the control of the first gate 232. The switching element 230 is driven without providing it.

Some specific examples of the above control performed by the gate control circuit 224 will now be described with reference to FIG.

FIG. 13A is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when both the first gate 232 and the second gate 234 are leak-free. First, at time MT1, the gate control circuit 224 determines whether or not leakage occurs in the first gate 232 . In FIG. 13A, it is determined that no leak occurs in the first gate 232 (NO in step S20 of FIG. 12). After that, at time MT2, the gate control circuit 224 determines whether or not leakage occurs in the second gate 234 . In FIG. 13A, it is determined that no leak occurs in the second gate 234 (NO in step S34 of FIG. 12). Therefore, since no leakage occurs in both the first gate 232 and the second gate 234, the gate control circuit 224 performs control as described in the first embodiment.

FIG. 13B is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when only the first gate 232 is leaking. First, at time MT1, the gate control circuit 224 determines whether or not leakage occurs in the first gate 232 . In FIG. 13B, it is determined that leakage occurs in the first gate 232 (YES in step S20 of FIG. 12). After that, at time MT2, the gate control circuit 224 determines whether or not the first gate 232 is short-circuited. In FIG. 13B, it is determined that a short circuit has not occurred in the first gate 232 (NO in step S24 of FIG. 12). Therefore, since a leak that does not short-circuit occurs only in the first gate 232, the gate control circuit 224 sets the first gate 232 to the low voltage mode (step S28 in FIG. 12). Also, at time MT2, the gate control circuit 224 determines whether or not leakage occurs in the second gate 234 . In (B) of FIG. 13, it is determined that no leak occurs in the second gate 234 (NO in step S30 of FIG. 12). Therefore, since leakage occurs only in the first gate 232, the gate control circuit 224 sets Vg1 to VL volts, which is lower than the voltage V volts, when MG+V indicates high.

FIG. 13C is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when both the first gate 232 and the second gate 234 are leaky. First, at time MT1, the gate control circuit 224 determines whether or not leakage occurs in the first gate 232 . In (C) of FIG. 13, it is determined that leakage occurs in the first gate 232 (YES in step S20 of FIG. 12). After that, at time MT2, the gate control circuit 224 determines whether or not the first gate 232 is short-circuited. In (C) of FIG. 13, it is determined that a short circuit has not occurred in the first gate 232 (NO in step S24 of FIG. 12). Therefore, since a leak that does not short-circuit occurs only in the first gate 232, the gate control circuit 224 sets the first gate 232 to the low voltage mode (step S28 in FIG. 12). Also, at time MT2, the gate control circuit 224 determines whether or not leakage occurs in the second gate 234 . In (C) of FIG. 13, it is determined that leakage occurs in the second gate 234 (YES in step S30 of FIG. 12). Therefore, since leakage occurs in both the first gate 232 and the second gate 234 , the gate control circuit 224 stops the operation of the switching element 230 . That is, the gate control circuit 224 sets both Vg1 and Vg2 to zero volts.

FIG. 13D is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when the first gate 232 is shorted. First, at time MT1, the gate control circuit 224 determines whether or not leakage occurs in the first gate 232 . In (D) of FIG. 13, it is determined that leakage occurs in the first gate 232 (YES in step S20 of FIG. 12). After that, at time MT2, the gate control circuit 224 determines whether or not the first gate 232 is short-circuited. In (D) of FIG. 13, it is determined that a short circuit has occurred in the first gate 232 (YES in step S24 of FIG. 12). Therefore, the gate control circuit 224 sets the first gate 232 to the off mode (step S26 in FIG. 12). Also, at time MT2, the gate control circuit 224 determines whether or not leakage occurs in the second gate 234 . In (D) of FIG. 13, it is determined that leakage does not occur in the second gate 234 (NO in step S30 of FIG. 12). Therefore, since only the first gate 232 is short-circuited, the gate control circuit 224 prohibits the use of the first gate 232 . That is, the gate control circuit 224 sets Vg1 to zero volts and only the second gate 234 is used to operate the switching element 230 .

According to the above, when a light leak occurs only in one gate, by limiting only the voltage applied to the gate, the operation of the switching element 230 can be continued without being excessively limited. Also, when only one gate is short-circuited, by prohibiting the use of only that gate, the switching element 230 can be operated using the other normal gate. Note that the operation of the switching element 230 can be stopped when both gates are leaking and/or short-circuited.

Points to note regarding this technology are described below. Zero volts described herein corresponds to an example of a reference voltage. V volt described in this specification corresponds to an example of the on-voltage. -V volt described in this specification corresponds to an example of the off-voltage.

Signal MG+V corresponds to an example of the first signal. Signal MG0 corresponds to an example of the second signal. Signal CG+V corresponds to an example of the third signal. Signal CG0 corresponds to an example of the fourth signal. Signal CG-V corresponds to an example of the fifth signal. Note that the description of "MG+V" in parentheses as "first signal (MG+V)" is intended to facilitate understanding, and does not limit the present technology. The description of the second to fifth signals is the same.

Although specific examples of the technology disclosed in this specification have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings can simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

2: Semiconductor device 10: Controller 20: Drive circuit 22: Logic circuits 22a, 22b: Mask circuit 24: Gate control circuit 30: Switching element 32: First gate 34: Second gate

Claims (1)

a double gate type switching element having two gates, a first gate and a second gate;
A first command signal, which is a binary signal, is generated based on the first carrier signal and the common duty value, and based on the second carrier signal whose phase is advanced by a predetermined time from the first carrier signal and the common duty value. a controller that generates a second command signal that is a binary signal;
a driving circuit connected to the switching element and the controller and driving the first gate and the second gate based on the first command signal and the second command signal, respectively;
and
The drive circuit has a logic circuit and a gate control circuit,
The logic circuit generates a first signal (MG+V) and a second signal (MG0) based on the first command signal, and a third signal based on the first command signal and the second command signal. (CG+V), generating a fourth signal (CG0) and a fifth signal (CG-V),
The gate control circuit selectively applies a reference voltage or an ON voltage higher than the reference voltage to the first gate based on the first signal (MG+V) and the second signal (MG0). In addition, based on the third signal (CG+V), the fourth signal (CG0), and the fifth signal (CG-V), the second gate is set to the reference voltage, the on-voltage, or higher than the reference voltage selectively applying a low off-voltage,
The logic circuit is
a first mask circuit that generates a first latch signal that is latched by a NOT signal of the second command signal and reset by a NOR signal of the first command signal and the second command signal;
a second mask circuit that generates a second latch signal that is latched by the second command signal and reset by the first command signal;
The first signal (MG+V) is the first command signal,
the second signal (MG0) is a NOT signal of the first command signal;
the third signal (CG+V) is an AND signal of a NOR signal of the first latch signal and the second latch signal and the first command signal;
the fourth signal (CG0) is the second latch signal;
the fifth signal (CG-V) is a NOR signal of the third signal (CG+V) and the fourth signal (CG0);
semiconductor equipment.

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