JP2020202674A - Semiconductor device - Google Patents

Abstract

To control a double-gate type switching element as appropriate.SOLUTION: A controller generates a first command signal on the basis of a first carrier signal and a common duty value, and generates a second command signal on the basis of the common duty value and a second carrier signal whose phase has been advanced from that of the first carrier signal by a predetermined time. A driving circuit includes a logic circuit and a gate control circuit. The logic circuit generates a first signal (MG+V) and a second signal (MG0) on the basis of the first command signal, and generates a third signal (CG+V), a fourth signal (CG0) and a fifth signal (CG-V) on the basis of the first and second command signals. The gate control circuit selectively applies reference voltage or on voltage to a first gate on the basis of the first signal (MG+V) and the second signal (MG0), and selectively applies the reference voltage, the on voltage, or off voltage to the second gate on the basis of the third signal (CG+V), the fourth signal (CG0) and the fifth signal (CG-V).SELECTED DRAWING: Figure 2

Description

The technique disclosed herein relates to a semiconductor device including a double gate type switching element.

For example, Patent Document 1 discloses a semiconductor device including a double-gate type switching element having two gate electrodes. In this type of semiconductor device, independent gate voltages can be applied to the two gate electrodes of the switching element.

Patent Document 2 also discloses a semiconductor device including a similar switching element. In this semiconductor device, when the switching element is turned off, a turn-off voltage is applied to the second gate, and then a turn-off voltage is applied to the first gate to turn off the switching element. According to the above configuration, by first lowering the voltage of the second gate to a turn-off voltage equal to or lower than the threshold voltage, a part of the carriers accumulated in the drift layer is extracted in advance. Therefore, by first lowering the voltage of the second gate and then lowering the voltage of the first gate to turn off the switching element, the time for pulling out the carrier is shortened. That is, the turn-off speed of the switching element is improved.

JP-A-2019-016805 Japanese Unexamined Patent Publication No. 2013-098415

When the switching element is controlled by the PWM (Pulse Width Modulation) method, the following two methods can be considered in order to realize the above configuration. That is, in the first method, one PWM signal is generated and used to control two gate signals. At this time, for the first gate (or the second gate), a PWM signal in which a predetermined delay time is given to the PWM signal is used. According to this method, two gates can be controlled at different timings with one PWM signal. However, by using the PWM signal with the delay time, there is a possibility that a delay may occur in the control of the switching element.

On the other hand, in the second method, two PWM signals are generated respectively, one PWM signal is used to control the first gate, and the other PWM signal is used to control the second gate. At this time, one PWM signal (hereinafter referred to as the first PWM signal) is generated based on the first carrier signal and the duty value, and the other PWM signal (hereinafter referred to as the second PWM signal) is derived from the first carrier signal. It is generated based on the second carrier signal whose phase is advanced by a predetermined time and the duty value. According to such a configuration, it is possible to control the first gate and the second gate at different timings, and at the same time, it is possible to suppress the delay in the control of the switching element. However, if the common duty value is changed after the preceding second PWM signal changes and before the first PWM signal follows and changes, the waveforms may differ from each other between the two PWM signals. .. As a result, for example, only the second gate may be turned off (or turned on) for a short time, and such unnecessary on / off of the second gate may increase the loss of the switching element. The present specification provides techniques that can avoid or reduce such problems.

The semiconductor device disclosed in the present specification includes a switching element, a controller, and a drive circuit. The switching element is a double gate type switching element including two gates, a first gate and a second gate. The controller generates a first command signal, which is a binary signal, based on the first carrier signal and the common duty value. At the same time, the controller generates a second command signal, which is a binary signal, based on the second carrier signal whose phase is advanced by a predetermined time from the first carrier signal and the common duty value. The drive circuit is connected to a switching element and a controller, and drives the first gate and the second gate based on the first command signal and the second command signal, respectively. The drive circuit includes a logic circuit and a gate drive circuit. The logic circuit generates a first signal (MG + V) and a second signal (MG0) based on the first command signal. At the same time, the drive circuit generates a third signal (CG + V), a fourth signal (CG0), and a fifth signal (CG-V) based on the first command signal and the second command signal. The gate control circuit selectively applies a reference voltage or an on-voltage higher than the reference voltage to the first gate based on the first signal (MG + V) and the second signal (MG0). At the same time, the gate control circuit is lower than the reference voltage, on-voltage, or reference voltage at the second gate based on the third signal (CG + V), the fourth signal (CG0), and the fifth signal (CG-V). The off voltage, which is a voltage, is selectively applied. The logic circuit further includes a first mask circuit and a second mask circuit. The first mask circuit generates a first latch signal that is latched by the NOT signal of the second command signal and reset by the NOR signal of the first command signal and the second command signal. The second mask circuit generates a second latch signal that is latched by the second command signal and reset by the first command signal. The first signal (MG + V) is the first command signal. The second signal (MG0) is a NOT signal of the first command signal. The third signal (CG + V) is an AND signal of the NOR signal of the first latch signal and the second latch signal and the first command signal. The fourth signal (CG0) is the second latch signal. The fifth signal (CG-V) is a NOR signal of the third signal (CG + V) and the fourth signal (CG0).

According to the above configuration, the first mask circuit and the second mask circuit are latched by the rising and falling of the first command signal, the second command signal, and their OR signals, respectively, and the first latch signal and the second latch. Generate a signal. More specifically, the first latch signal is a signal that is latched by the NOT signal of the second command signal and reset by the NOR signal of the first command signal and the second command signal. The second latch signal is a signal that is latched by the second command signal and reset by the first command signal. By using the first latch signal and the second latch signal described above, three signals (third signal, fourth signal, and fifth signal) can be generated, and the second signal is used by using these three signals. By controlling the gate, it is possible to suppress unnecessary on / off of the second gate at an unintended timing.

Further, according to the above configuration, the voltage applied to the second gate can be increased stepwise at the time of turning on the switching element. As a result, the turn-on speed of the switching element can be increased and the loss due to switching can be suppressed.

Details of the techniques disclosed herein and further improvements will be described in the "Modes for Carrying Out the Invention" below.

It is a circuit diagram of the semiconductor device of 1st Example. It is a block diagram of the logic circuit of 1st Example. It is a time chart which shows two carrier signals, duty signals, and two command signals generated from them. It is a graph of two input signals to a logic circuit, an output signal of two mask circuits, and a NOR signal of two output signals. It is a graph of the five output signals of the logic circuit and the gate voltage of each gate. It is a circuit diagram of the semiconductor device of 2nd Example. It is a block diagram of the logic circuit of 2nd Example. It is a graph of the input signal to the logic circuit and the output signal of the third mask circuit. It is a graph of two output signals about the first gate of a logic circuit. It is a graph of the gate voltage of the first gate. It is a flowchart of the setting time change of a variable timer. It is a graph which shows the conduction loss, switching loss, and the total loss with respect to the time change from the turn-off of the 2nd gate to the turn-off of the 1st gate 132. It is a circuit diagram of the semiconductor device of 3rd Example. 6 is a flowchart of control of each gate executed by the gate control circuit of the third embodiment. 3 is a graph of the gate voltage of the first gate and the gate voltage of the second gate for some specific examples controlled by the gate control circuit of the third embodiment.

In one embodiment of the present technology, the drive circuit may change the turn-off timing of the first gate with respect to the turn-off of the second gate according to the current flowing through the switching element. In this case, the drive circuit may include, for example, a variable timer, and the set time of the variable timer may be changed according to the current flowing through the switching element. Then, the drive circuit may change the turn-off timing of the first gate with respect to the turn-off of the second gate by using a variable timer. With such a configuration, the total loss due to conduction and switching loss can be reduced.

In addition to or instead of the above, the drive circuit monitors each gate for leaks and may limit the voltage applied to that gate when a leak is detected for only one gate. On the other hand, the drive circuit may stop driving the switching element when a leak is detected for both gates. According to such a configuration, when a slight leak occurs in only one gate, the operation of the switching element can be continued without being excessively restricted by limiting only the voltage applied to the gate. it can.

(First Example) The semiconductor device 2 of the first embodiment will be described with reference to FIGS. 1 to 5. The semiconductor device 2 is mounted on an electric vehicle, for example, and can form a part of a power conversion device such as an inverter or a DC-DC converter that converts electric power between a power source and a load. However, the semiconductor device 2 of this embodiment is not limited to such applications, and can be used for various purposes.

As shown in FIG. 1, the semiconductor device 2 includes an ASIC4 (Application Specific Integrated Circuit), two insulating elements 6 and 8, a controller 10, a drive circuit 20, and a switching element 30. The switching element 30 is a double gate type switching element having two gates, a first gate 32 and a second gate 34. Although it is an example, the switching element 30 of this embodiment is a double gate type IGBT (Insulated Gate Bipolar Transistor). When a voltage larger than the threshold voltage of the gate is applied to at least one of the first gate 32 and the second gate 34, the switching element 30 turns on and a collector current flows from the collector 36 to the emitter 38. The switching element 30 further includes a sense emitter 39. A minute current proportional to the collector current flows through the sense emitter 39. By detecting this minute current, the magnitude of the collector current can be measured. The switching element 30 is not limited to the IGBT, and may be, for example, a bipolar transistor.

The controller 10 outputs the first command signal PWM1 and the second command signal PWM2 based on the control command input from the upper control unit (not shown). The first command signal PWM1 and the second command signal PWM2 are command signals for the switching element 30, and more specifically, pulse width modulation (PWM) signals. The first command signal PWM1 is a command signal for controlling the first gate 32, and the second command signal PWM2 is a command signal for controlling the second gate 34. As shown in FIG. 3, the controller 10 generates the first command signal PWM1 based on the first carrier signal and the duty signal. The first command signal PWM1 is a binary signal indicating either high or low. The first command signal PWM1 shows high when the first carrier signal has a value larger than the duty signal, and shows low when the first carrier signal has a value smaller than the duty signal.

Similarly, the controller 10 generates the second command signal PWM2 based on the second carrier signal and the duty signal. The second command signal PWM2 is also a binary signal indicating either high or low. The second command signal PWM2 shows high when the second carrier signal has a value larger than the duty signal, and shows low when the second carrier signal has a value smaller than the duty signal. Here, the second carrier signal is a signal whose phase is advanced by a predetermined time from the above-mentioned first carrier signal. This predetermined time is determined, for example, by the carrier accumulation time of the switching element 30. On the other hand, as for the duty signal, a common duty signal is used in the generation of the first command signal PWM1 and the second command signal PWM2. Although not particularly limited, in this embodiment, the first carrier signal and the second carrier signal are triangular waves. The duty signal is a variable signal adjusted within the amplitude of the triangular wave based on the above-mentioned control command from the upper level.

The controller 10 is connected to the drive circuit 20 via the ASIC 4 and the insulating elements 6 and 8. The ASIC 4 is an integrated circuit in which circuits having a plurality of functions are integrated into one for a specific application, and is, for example, an integrated circuit for driving a motor. The insulating elements 6 and 8 can transmit only a signal between the controller 10 and the switching element 30 while electrically insulating the controller 10 and the switching element 30. The insulating elements 6 and 8 are, for example, photocouplers. The command signals PWM1 and PWM2 output from the controller 10 are input to the drive circuit 20 via the ASIC4 and the insulating elements 6 and 8. The drive circuit 20 is connected to the first gate 32 and the second gate 34 of the switching element 30, and each gate voltage Vg1 of the first gate 32 and the second gate 34 is based on the input command signals PWM1 and PWM2. , Vg2 are controlled respectively.

The drive circuit 20 includes a logic circuit 22 and a gate control circuit 24. The logic circuit 22 generates five signals MG + V, MG0, CG + V, CG0, and CG-V based on the two command signals PWM1 and PWM2 transmitted from the controller 10. The five signals generated in the logic circuit 22 are transmitted to the gate control circuit 24. The gate control circuit 24 controls the gate voltage Vg1 of the first gate 32 and the gate voltage Vg2 of the second gate 34 independently of each other based on these transmitted signals. The configuration of the logic circuit 22 will be described in detail later with reference to FIG.

As described above, in the semiconductor device 2 of the present embodiment, the controller 10 generates two command signals PWM1 and PWM2, and the drive circuit 20 has two switching elements 30 based on the command signals PWM1 and PWM2. Controls gates 32 and 34. However, the drive circuit 20 does not use the two command signals PWM1 and PWM2 as they are for controlling the two gates 32 and 34, but uses the logic circuit 22 to generate five signals MG + V, MG0, CG + V, CG0, and CG-V. Generate. Then, the two gates 32 and 34 of the switching element 30 are controlled based on the five signals MG + V, MG0, CG + V, CG0, and CG-V. This is because if the two command signals PWM1 and PWM2 are used as they are for controlling the two gates 32 and 34, the following problems will occur.

That is, since the second carrier signal is a signal whose phase is advanced by a predetermined time from the first carrier signal, the second command signal PWM2 is also a signal whose phase is advanced by a predetermined time from the first command signal PWM1. Be expected. However, when two command signals PWM1 and PWM2 are generated from different carrier signals and a common duty signal, for example, depending on the timing at which the duty signal changes, the waveforms of the first command signal PWM1 and the second command signal PWM2 become mutual. It may be different. An example thereof will be described with reference to the time chart illustrated in FIG.

In the time chart shown in FIG. 3, since the first carrier signal and the second carrier signal are larger than the duty signal until time t1, both the first command signal PWM1 and the second command signal PWM2 show high. Next, during the period from time t1 to time ft1, the second carrier signal becomes smaller than the duty signal. Therefore, the second command signal PWM2 indicates low. On the other hand, the high is maintained for the first command signal PWM1. Next, from time ft1 to time t2, the second carrier signal becomes larger than the duty signal again. Therefore, the second command signal PWM2 indicates high. On the other hand, after the time T1 during this period, the first carrier signal becomes smaller than the duty signal. Therefore, the first command signal PWM1 indicates high from time ft1 to time T1 and low from time T1 to time t2.

It is assumed that the duty signal is updated at time t2 (D1). Along with this, the second carrier signal becomes smaller than the duty signal, so that PWM2 changes to low. On the other hand, even if the duty signal is updated, the first command signal PWM1 is kept low. After that, from time t2 to time t3, the first carrier signal and the second carrier signal become smaller than the duty signal. Therefore, both the first command signal PWM1 and the second command signal PWM2 show low.

From time t3 to time ft2, the second carrier signal is larger than the duty signal. Therefore, the second command signal PWM2 indicates high. On the other hand, the first command signal PWM1 indicates low. Next, from time ft2 to time D2, the second carrier signal becomes smaller than the duty signal again. Therefore, the second command signal PWM2 indicates low. After the time t4 (T2) during this period, the first carrier signal becomes larger than the duty signal. Therefore, the first command signal PWM1 shows low from time ft2 to time T2 and high from time T2 to time D2. It is assumed that the duty signal is updated again at time D2. Along with this, the second carrier signal becomes larger than the duty signal, so that the second command signal PWM2 indicates high. On the other hand, even if the duty signal is updated, the first command signal PWM1 is maintained high.

As described above, the second command signal PWM2 is temporarily switched to low between the time ft1 and the time t2. On the other hand, such a change does not appear in the first command signal PWM1. Further, even between the time ft2 and the time D2, the second command signal PWM2 is temporarily switched to low, but such a change does not appear in the first command signal PWM1. If these two command signals PWM1 and PWM2 are used as they are for controlling the switching element 30, only the second gate 34 is unnecessarily turned off (or turned on), and the switching element 30 May increase loss. In order to avoid or reduce such a problem, the above-mentioned logic circuit 22 is prepared in the semiconductor device 2 of the present embodiment, and the five signals MG + V, MG0, CG + V, CG0, and the five signals generated by the logic circuit 22 are prepared. The two gates 32 and 34 of the switching element 30 are controlled based on the CG-V.

Hereinafter, the logic circuit 22 will be described in detail. As shown in FIG. 2, the logic circuit 22 includes a first mask circuit 22a and a second mask circuit 22b. The first mask circuit 22a outputs the first latch signal La1 to the two input signals S and R. The first latch signal La1 is set by the rising edge of the input signal S and reset by the input signal R. That is, the first mask circuit 22a is a circuit that outputs high when the input signal S rises when the input signal R indicates low, and holds this for a period until the input signal R is then switched from low to high. Is. This is a circuit that holds the value of the input signal S at the timing when the input signal R changes from high to low until the next time the input signal R changes from low to high. When both the input signal S and the input signal R indicate high, the first latch signal La1 indicates low. The input signal S is a NOT signal of PWM2. The input signal R is a NOR signal of PWM1 and PWM2. That is, the first mask circuit 22a is a circuit that is latched by the falling edge of PWM2 and reset when both PWM1 and PWM2 show low. The first latch signal La1 will be described in more detail later with reference to the graph of FIG.

The second mask circuit 22b outputs the second latch signal La2 to the two input signals S and R. The second latch signal La2 is set by the rising edge of the input signal S and reset by the input signal R. That is, the second mask circuit 22b is a circuit that outputs high when the input signal S rises when the input signal R indicates low, and holds this for a period until the input signal R is then switched from low to high. Is. When both the input signal S and the input signal R indicate high, the second latch signal La2 indicates low. The input signal S is PWM2. The input signal R is PWM1. That is, the second mask circuit 22b is a circuit that is latched by the rising edge of PWM2 and reset by the rising edge of PWM1. The second latch signal La2 will also be described in more detail later with reference to the graph of FIG.

The signal MG + V and the signal MG0 are signals used for controlling the gate voltage Vg1 of the first gate 32. More specifically, when the signal MG + V indicates high, the gate control circuit 24 sets the gate voltage Vg1 applied to the first gate 32 to V volt. The voltage V volt is higher than the threshold voltage of the first gate 32. Further, when the signal MG0 indicates high, the gate control circuit 24 sets the gate voltage Vg1 applied to the first gate 32 to zero volt. The voltage zero volt is lower than the threshold voltage of the first gate 32. The signal MG + V is the same signal as the first command signal PWM1. Further, the signal MG0 is a NOT signal of the first command signal PWM1. From the method of determining the signal MG + V and the signal MG0, the signal MG + V and the signal MG0 do not show high (or low) at the same time. That is, the gate control circuit 24 selectively applies V volt or zero volt to the first gate 32.

The signal CG + V, the signal CG0, and the signal CG-V are signals used for controlling the gate voltage Vg2 of the second gate 34. More specifically, when the signal CG + V indicates high, the gate control circuit 24 sets the gate voltage Vg2 applied to the second gate 34 to V volt. The voltage V volt is higher than the threshold voltage of the second gate 34. When the signal CG0 indicates high, the gate control circuit 24 sets the gate voltage Vg2 applied to the second gate 34 to zero volt. When the signal CG-V indicates high, the gate control circuit 24 sets the gate voltage Vg2 applied to the second gate 34 to −V volt. The voltage zero volt and the voltage −V volt are lower than the threshold voltage of the second gate 34. The signal CG + V is an AND signal of the first command signal PWM1 and the NOR signal of the first latch signal La1 and the second latch signal La2. The signal CG0 is the same signal as the second latch signal La2. The signal CG-V is a NOR signal of the signal CG + V and the signal CG0. From the method of determining the signal CG + V, the signal CG0, and the signal CG-V, two or more of these three signals do not show high at the same time. That is, the gate control circuit 24 selectively applies V volt, zero volt, or −V volt to the second gate 34.

Subsequently, with reference to FIG. 4, regarding the first command signal PWM1, the second command signal PWM2, the first latch signal La1, the second latch signal La2, and the NOR signal of the first latch signal La1 and the second latch signal La2. The graph of is explained. In the following, these signals may be simply referred to as PWM1, PWM2, La1, and La2. As described above, since the phase of the second carrier signal that generates PWM2 is advanced by a predetermined time from the first carrier signal that generates PWM1, the waveform is changed between PWM1 and PWM2 as the duty signal changes. There is a difference.

Until time t1, both PWM1 and PWM2 show high. The input signal S of the first mask circuit 22a indicates low because it is a NOR signal of PWM2, and the input signal R indicates low because it is a NOR signal of PWM1 and PWM2. Therefore, La1 indicates low. Further, the input signal S of the second mask circuit 22b indicates high because it is PWM2, and the input signal R indicates high because it is PWM1. Therefore, La2 indicates low.

At time t1, PWM2 falls prior to PWM1. Then, the input signal S of the first mask circuit 22a is switched from low to high, and the input signal R indicates low. Therefore, La1 indicates high. La1 indicates high for the period until the input signal R next shows high, that is, the period until both PWM1 and PWM2 show low. Therefore, La1 indicates high during the period from time t1 to time t2.

Further, regarding the second mask circuit 22b, the input signal S is switched from low to high at the time ft1 in the period from the time t1 to the time t2. However, since the input signal R also shows high at time ft1, La2 shows low at time ft1. Between the time t1 and the time t2, the timing at which the input signal S switches from low to high is only the time ft1. Therefore, since La2 does not switch from low to high during the period from time t1 to time t2, La2 indicates low during this period.

At time t2, PWM1 goes down. Further, at time t3, PWM2 starts up prior to PWM1. Therefore, during the period from time t2 to time t3, both PWM1 and PWM2 show low. Therefore, the input signal S of the first mask circuit 22a indicates high, and the input signal R indicates high, so La1 indicates low. Further, in the second mask circuit 22b, PWM2 shows low after time t2 until PWM2 starts up at time t3. That is, in the second mask circuit 22b, the input signal S does not switch from low to high during the period from time t2 to time t3, so that La2 is kept low during the period from time t2 to time t3. There is.

At time t3, PWM2 starts up prior to PWM1. In the first mask circuit 22a, the input signal S switches from low to high at time ft2 during the period from time t3 to time t4 when PWM1 falls. However, at time ft2, both PWM1 and PWM2 show low, so the input signal R shows high. In the period from time t3 to time t4, the timing at which the input signal S switches from low to high is only time ft2. Therefore, since La1 does not switch from low to high during the period from time t3 to time t4, La1 indicates low during this period.

Further, as described above, at time t3, PWM2 starts up prior to PWM1. Then, the input signal S of the second mask circuit 22b is switched from low to high, and the input signal R indicates low. Therefore, La2 indicates high. La2 indicates high for the period until the input signal R next shows high, that is, the period until PWM1 rises. Therefore, La2 indicates high during the period from time t3 to time t4.

After time t4, both PWM1 and PWM2 show high. Therefore, since the time t4 and thereafter are the same as those up to the time t1, the description thereof will be omitted.

Further, the NOR signals of La1 and La2 can be easily calculated from the above La1 and La2.

FIG. 5A is a graph showing five signals output by the logic circuit 22. As described above, since the signal MG + V is the same signal as PWM1 and the signal MG0 is the NOT signal of PWM1, the graphs of the signal MG + V and the signal MG0 in FIG. 5A can be easily obtained. Since the signal CG + V is an AND signal of PWM1 and the NOR signals of La1 and La2, it is a signal indicating high before time t1 and after time t4, and indicating low for the remaining period. Since the signal CG0 is the same signal as La2, it is a signal indicating high during the period from time t3 to time t4 and indicating low during the remaining period. Since the signal CG-V is a NOR signal of the signal CG + V and the signal CG0, it is a signal indicating high during the period from time t1 to time t3 and indicating low during the remaining period.

FIG. 5B is a graph showing the gate voltage Vg1 applied to the first gate 32 and the gate voltage Vg2 applied to the second gate 34 by the gate control circuit 24. As described above, since the gate voltage Vg1 is determined based on the signal MG + V and the signal MG0, it is easily determined from (A) of FIG. Similarly, the gate voltage Vg2 is also easily determined from (A) of FIG.

According to the above configuration, PWM2 has unnecessary rises and falls as shown in FIG. 4, but as shown in FIG. 5B, it exists in the gate voltage Vg2 applied to the second gate 34. do not do. That is, unnecessary on / off of the second gate 34 at an unintended timing can be suppressed.

Further, although PWM2 is a binary signal, by providing the logic circuit 22, the gate control circuit 24 uses the gate voltage Vg2 of the second gate 34 as three values of V volt, zero volt, and −V volt. Can be controlled. That is, when the switching element 30 is turned on, the gate voltage Vg2 applied to the second gate 34 can be increased stepwise. As a result, the turn-on speed of the switching element 30 can be increased to suppress the loss due to switching.

(Second Example) The semiconductor device 102 of the second embodiment will be described with reference to FIGS. 6 to 10. As shown in FIGS. 6 and 7, the semiconductor device 102 further includes a resistor 109, a variable timer 122d, and a current detection circuit 126. Although not particularly limited, the variable timer 122d is built in the drive circuit 120 and is connected to the sense emitter 139 via a resistor 109. The drive circuit 120 is configured to change the set time of the variable timer 122d according to the current flowing through the switching element 130. Then, the drive circuit 120 is configured to change the turn-off timing of the first gate 132 with respect to the turn-off of the second gate 134 by using the variable timer 122d. Since the semiconductor device 102 of the present embodiment is the same as the semiconductor device 2 of the first embodiment except that these points and the configuration of the logic circuit 122 are partially different, the description of the overlapping portion is omitted. ..

The reason why the variable timer 122d is provided in the semiconductor device 102 of the second embodiment will be described with reference to FIG. FIG. 10 is a graph showing a loss due to conduction (conduction loss), a loss due to turn-off (switching loss), and a total loss thereof that occur when the switching element 130 is turned off. The fact that the switching element 130 is off means that both the first gate 132 and the second gate 134 are off. The time on the horizontal axis represents the time from when the second gate 134 is turned off until when the first gate 132 is turned off (hereinafter, referred to as an off delay time). The graph connecting the diamond-shaped points in FIG. 10 represents the conduction loss, the graph connecting the square points represents the switching loss, and the graph connecting the triangular points represents the total loss. The points indicated by the arrows in the figure represent the points where the total loss is minimized. The magnitude of the current flowing through the switching element 130 differs between (A) in FIG. 10 and (B) in FIG. That is, FIG. 10A shows a case where the current flowing through the switching element 130 is small, and FIG. 10B shows a case where the current flowing through the switching element 130 is large.

Comparing (A) of FIG. 10 and (B) of FIG. 10, the switching loss decreases as the off delay time is set larger, regardless of the magnitude of the current. In addition, as can be understood by comparing the two graphs (A) and (B), the relationship of switching loss (change behavior) with respect to the off delay time is similar regardless of the magnitude of the current, and its decrease The rate gradually declines. On the other hand, the conduction loss increases as the off delay time is set larger, and the rate of increase increases as the current flowing through the switching element 130 increases. Therefore, the off-delay time at which the total loss generated in the switching element 130 is minimized depends on the magnitude of the current flowing through the switching element 130. More specifically, the larger the current flowing through the switching element 130, the shorter the off delay time at which the total loss is minimized.

As will be described in detail later, the variable timer 122d is connected to the current detection circuit 126. The variable timer 122d can change the turn-off timing (that is, the off delay time) of the first gate 132 with respect to the turn-off of the second gate 134 according to the current detected by the current detection circuit 126. Therefore, the total loss generated in the switching element 130 can be reduced.

Returning to the description of FIG. 6 again. The resistor 109 is connected between the sense emitter 139 and the current detection circuit 126. The current detection circuit 126 measures the current flowing through the sense emitter 139 by detecting the voltage drop in the resistor 109 caused by the current flowing through the sense emitter 139. Since the collector current flowing from the collector 136 of the switching element 130 to the emitter 138 is proportional to the current flowing through the sense emitter 139, the collector current can be measured by measuring the current flowing through the sense emitter 139.

Next, the logic circuit 122 will be described. As shown in FIG. 7, the logic circuit 122 further includes a third mask circuit 122c and a variable timer 122d. Except for this point, the logic circuit 122 of the present embodiment is the same as the logic circuit 22 of the first embodiment, and thus the description of the overlapping portion will be omitted.

The third mask circuit 122c outputs the third latch signal La3 to the two input signals S and R. The third latch signal La3 is set by the rising edge of the input signal S and reset by the input signal R. That is, the third mask circuit 122c outputs high when the input signal S rises when the input signal R indicates low, and holds the high for a period until the input signal R is switched from low to high. Is. When both the input signal S and the input signal R indicate high, the third latch signal La3 indicates low. The input signal S is a NOT signal of the first command signal PWM1. The input signal R is a signal obtained by delaying the NOT signal of the first command signal PWM1 for a predetermined time. That is, the first mask circuit 22a is a circuit that is latched by the falling edge of the first command signal PWM1 and reset after a lapse of a predetermined time. The third latch signal La3 will be described in more detail later with reference to the graph of FIG.

As shown in FIG. 7, the NOT signal of the first command signal PWM1 is input to the variable timer 122d before being input to the input terminal on the reset side of the third mask circuit 122c. The variable timer 122d delays the NOT signal of the input first command signal PWM1 for a predetermined time. The variable timer 122d can change a predetermined time to be delayed. In the present embodiment, the variable timer 122d can select any one of the first time, the second time, and the third time as the predetermined time to be delayed. The variable timer 122d is connected to the current detection circuit 126. The variable timer 122d sets the set time to any one of the first time, the second time, and the third time based on the current detected by the current detection circuit 126. In the modified example, the variable timer 122d stores a map regarding the current detected by the current detection circuit 126 and the set time, and the set time may be changed based on the current detected by the current detection circuit 126.

The signal MG + V is an OR signal of the first command signal PWM1 and the third latch signal La3. Further, the signal MG0 is a NOT signal of the signal MG + V. As can be seen from the method of determining MG + V and MG0, the signal MG + V and the signal MG0 do not show high (or low) at the same time. That is, the gate control circuit 124 selectively applies + V volt or zero volt to the first gate 132.

Subsequently, a graph of the first command signal PWM1 and the third latch signal La3 will be described with reference to FIG. 8A. In the following, the third latch signal La3 may be simply referred to as La3. Until time T1, PWM1 indicates high. Therefore, since the input signal S of the third mask circuit 122c is a NOT signal of PWM1, it shows low. Further, the input signal R becomes either high or low depending on the delay time of the variable timer 122d, and in either case, La3 indicates low.

At time T1, PWM1 goes down. Then, the input signal S of the third mask circuit 122c is switched from low to high. Further, the input signal R indicates low because the NOT signal of PWM1 is delayed for a predetermined time by the variable timer 122d. Therefore, at time T1, La3 indicates high. La3 holds high until the input signal R of the third mask circuit 122c is then switched from low to high.

After that, at the time T3 when the predetermined time elapses (that is, the predetermined time of the variable timer 122d is T3-T1 and the time T3 changes depending on the set time of the variable timer 122d), the input signal R of the third mask circuit 122c becomes Switch from low to high. Since the input signal S of the third mask circuit 122c indicates high, La3 is switched to low.

Since PWM1 is a pulse wave, a fall occurs only once within one cycle of PWM1. That is, after the time T3, there is no timing at which PWM1 falls within one cycle of PWM1. That is, after the time T3, there is no timing at which the input signal S of the third mask circuit 122c switches from low to high within one cycle of PWM1. Therefore, within one cycle of PWM1 after the time T3, La3 indicates low. Therefore, it is the period from the time T1 to the time T3 that La3 shows high in one cycle of PWM1.

FIG. 8B is a graph showing the signal MG + V and the signal MG0 output by the logic circuit 122. Since the signal MG + V is an OR signal of PWM1 and La3 and the signal MG0 is a NOT signal of the signal MG + V, these graphs can be easily obtained from (A) of FIG.

FIG. 8C is a graph showing the gate voltage Vg1 applied to the first gate 132 by the gate control circuit 124. As described above, since the gate voltage Vg1 is determined based on the signal MG + V and the signal MG0, it is easily determined from (B) of FIG.

FIG. 9 is a flowchart relating to changing the set time of the variable timer 122d. First, the variable timer 122d acquires the sense current detected by the current detection circuit 126 (step S2). After that, it is determined whether or not the sense current acquired in step S2 is larger than the first threshold current (step S4).

When it is determined that the sense current acquired in step S2 is larger than the first threshold current, the variable timer 122d sets the set time to the first time (steps S4: YES, S6). When it is determined that the sense current acquired in step S2 is smaller than the first threshold current, it is determined whether or not the sense current is larger than the second threshold current (steps S4: NO, S8). In addition. The second threshold current is smaller than the first threshold current.

When it is determined that the sense current acquired in step S2 is larger than the second threshold current, the variable timer 122d sets the set time to the second time (steps S8: YES, S10). When it is determined that the sense current acquired in step S2 is smaller than the first threshold current, the variable timer 122d sets the set time to the third time (steps S8: NO, S12).

According to the above, the set time of the variable timer 122d, that is, the turn-off timing of the first gate 132 with respect to the turn-off of the second gate 134 can be changed based on the sense current. Thereby, the total loss of the loss due to conduction and the loss due to switching can be reduced.

The technique of the second embodiment is the first method described above, that is, a method of generating one PWM signal and controlling two gate signals using the PWM signal, and the first gate (or the second gate) (or the second). For the gate), a method in which a PWM signal obtained by giving a predetermined delay time to the PWM signal is also suitable.

(Third Example) The semiconductor device 202 of the third embodiment will be described with reference to FIGS. 11 to 13. As shown in FIG. 11, the semiconductor device 202 further includes a first gate resistor 207, a second gate resistor 209, and a current detection circuit 226. Since this point is the same as that of the semiconductor device 2 of the first embodiment, the description of the overlapping portion will be omitted.

The first gate resistor 207 is connected between the drive circuit 220 and the first gate 232. The first gate resistor 207 is also connected to the current detection circuit 226. The first gate resistor 207 serves to monitor the current flowing through the first gate 232. The current detection circuit 226 measures the current flowing through the first gate 232 by detecting the voltage drop in the first gate resistor 207 caused by the current flowing through the first gate 232.

The second gate resistor 209 is connected between the drive circuit 220 and the second gate 234. The second gate resistor 209 is also connected to the current detection circuit 226. The second gate resistor 209 plays a role of monitoring the current flowing through the second gate 234. The current detection circuit 226 measures the current flowing through the second gate 234 by detecting the voltage drop in the second gate resistor 209 caused by the current flowing through the second gate 234.

The first gate resistor 207 makes it possible to monitor whether or not a leak has occurred at the first gate 232. Further, the second gate resistor 209 makes it possible to monitor whether or not a leak has occurred in the second gate 234. Further, the current detection circuit 226 is connected to the gate control circuit 224. The information of the current flowing through the first gate 232 and the information of the current flowing through the second gate 234 detected by the current detection circuit 226 are transmitted to the gate control circuit 224. That is, information on whether or not a leak has occurred at the first gate 232 and the second gate 234 is transmitted to the gate control circuit 224.

If the use of the leaking gate is continued, the switching element 230 may malfunction. Therefore, the gate control circuit 224 limits the voltage applied to the gate when a leak is detected in only one of the gates of the first gate 232 and the second gate 234. Further, the gate control circuit 224 stops driving the switching element 230 when a leak is detected for both gates. Furthermore, when a short circuit is detected in only one of the gates, the use of that gate is prohibited.

The control of each gate executed by the gate control circuit 224 will be described with reference to FIG. First, the gate control circuit 224 determines whether or not a leak has occurred at the first gate 232 (step S20). The gate control circuit 224 determines whether or not a leak has occurred at the first gate 232 based on the information of the current flowing through the first gate 232 transmitted from the current detection circuit 226. If it is determined that a leak has occurred at the first gate 232, the gate control circuit 224 turns off the first gate 232 (steps S20: YES, S22). That is, the gate control circuit 224 sets the gate voltage Vg1 applied to the first gate 232 to zero volt regardless of the two signals MG + V and MG0.

After that, the gate control circuit 224 determines whether or not a short circuit has occurred at the first gate 232 (step S24). Similar to the leak determination, the gate control circuit 224 determines whether or not a short circuit has occurred in the first gate 232 based on the information of the current flowing through the first gate 232 transmitted from the current detection circuit 226. When it is determined that a short circuit has occurred in the first gate 232, the gate control circuit 224 sets the first gate 232 to the off mode (steps S24: YES, S26). That is, the use of the first gate 232 is prohibited.

When it is determined that no short circuit has occurred at the first gate 232, the gate control circuit 224 sets the first gate 232 to the low voltage mode (steps S24: NO, S28). That is, the gate control circuit 224 sets the gate voltage Vg1 applied to the first gate 232 to VL volts when the signal MG + V indicates high. The voltage VL volt is lower than the voltage V volt applied to the first gate 232 when the signal MG + V shows high when the first gate 232 is not in low voltage mode.

After that, the gate control circuit 224 determines whether or not a leak has occurred at the second gate 234 (step S30). The gate control circuit 224 determines whether or not a leak has occurred at the second gate 234 based on the information of the current flowing through the second gate 234 transmitted from the current detection circuit 226.

When it is determined that a leak has occurred at the second gate 234, the gate control circuit 224 stops the operation of the switching element 230 (steps S30: YES, S32). In this case, leaks and / or short circuits occur at both the first gate 232 and the second gate 234. In such a situation, the operation of the switching element 230 is stopped (step S32).

If it is determined that no leak has occurred at the second gate 234, the process returns to the start and resumes from the process of step S20 (step S30: NO, to the start). In this case, a leak or short circuit occurs only in the first gate 232. In such a situation, the gate control circuit 224 reduces the voltage applied to the first gate 232 or prohibits the use of the first gate 232, and does not limit the control of the second gate 234. The switching element 230 is operated.

If it is determined in step S20 that no leak has occurred at the first gate 232, the gate control circuit 224 determines whether or not a leak has occurred at the second gate 234 (steps S20: NO, S34). .. The gate control circuit 224 determines whether or not a leak has occurred at the second gate 234 based on the information of the current flowing through the second gate 234 transmitted from the current detection circuit 226.

If it is determined that no leak has occurred at the second gate 234, the process returns to the start and resumes from the process of step S20 (step S34: NO, to the start). In this case, no leak or short circuit has occurred in both the first gate 232 and the second gate 234. That is, both gates are normal, and the gate control circuit 224 executes the control as described in the first embodiment.

If it is determined that a leak has occurred at the second gate 234, the gate control circuit 224 turns off the second gate 234 (steps S34: YES, S36). That is, the gate control circuit 224 sets the gate voltage Vg2 applied to the second gate 234 to zero volt regardless of the three CG + V, CG0, and CG-V.

After that, the gate control circuit 224 determines whether or not a short circuit has occurred at the second gate 234 (step S38). Similar to the leak determination, the gate control circuit 224 determines whether or not a short circuit has occurred in the second gate 234 based on the information of the current flowing through the second gate 234 transmitted from the current detection circuit 226. When it is determined that a short circuit has occurred at the second gate 234, the gate control circuit 224 sets the second gate 234 to the off mode (steps S38: YES, S42). That is, the use of the second gate 234 is prohibited. After that, the process returns to the start and resumes from the process of step S20.

If it is determined that no short circuit has occurred at the second gate 234, the gate control circuit 224 sets the second gate 234 to the low voltage mode (steps S38: NO, S40). That is, the gate control circuit 224 sets the gate voltage Vg2 applied to the second gate 234 to VL volts when the signal CG + V indicates high. The voltage VL volt is lower than the voltage V volt applied to the second gate 234 when the signal CG + V shows high when not in the low voltage mode. Further, the gate control circuit 224 sets the gate voltage Vg2 applied to the second gate 234 to −VL volt when the signal CG-V indicates high. After that, the process returns to the start and resumes from the process of step S20.

In these cases, only the second gate 234 has a leak or a short circuit. In such a situation, the gate control circuit 224 lowers the absolute value of the voltage applied to the second gate 234 or prohibits the use of the second gate 234 and limits the control of the first gate 232. The switching element 230 is driven without being provided.

With reference to FIG. 13, some specific examples of the above control performed by the gate control circuit 224 will be described.

FIG. 13A is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when there is no leak in both the first gate 232 and the second gate 234. First, at time MT1, the gate control circuit 224 determines whether or not a leak has occurred at the first gate 232. In (A) of FIG. 13, it is determined that no leak has occurred at the first gate 232 (NO in step S20 of FIG. 12). After that, at time MT2, the gate control circuit 224 determines whether or not a leak has occurred at the second gate 234. In (A) of FIG. 13, it is determined that no leak has occurred at the second gate 234 (NO in step S34 of FIG. 12). Therefore, since no leak has occurred in both the first gate 232 and the second gate 234, the gate control circuit 224 executes the control as described in the first embodiment.

FIG. 13B is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when a leak occurs only in the first gate 232. First, at time MT1, the gate control circuit 224 determines whether or not a leak has occurred at the first gate 232. In (B) of FIG. 13, it is determined that a leak has occurred at the first gate 232 (YES in step S20 of FIG. 12). Then, at time MT2, the gate control circuit 224 determines whether or not a short circuit has occurred at the first gate 232. In FIG. 13B, it is determined that no short circuit has occurred at the first gate 232 (NO in step S24 of FIG. 12). Therefore, since a leak that does not lead to a short circuit occurs only in the first gate 232, the gate control circuit 224 sets the first gate 232 to the low voltage mode (step S28 in FIG. 12). Further, at the time MT2, the gate control circuit 224 determines whether or not a leak has occurred at the second gate 234. In (B) of FIG. 13, it is determined that no leak has occurred at the second gate 234 (NO in step S30 of FIG. 12). Therefore, since the leak occurs only in the first gate 232, the gate control circuit 224 sets Vg1 to VL volt, which is a voltage lower than the voltage V volt, when MG + V shows high.

FIG. 13C is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when both gates of the first gate 232 and the second gate 234 have a leak. First, at time MT1, the gate control circuit 224 determines whether or not a leak has occurred at the first gate 232. In (C) of FIG. 13, it is determined that a leak has occurred at the first gate 232 (YES in step S20 of FIG. 12). Then, at time MT2, the gate control circuit 224 determines whether or not a short circuit has occurred at the first gate 232. In FIG. 13 (C), it is determined that no short circuit has occurred at the first gate 232 (NO in step S24 of FIG. 12). Therefore, since a leak that does not lead to a short circuit occurs only in the first gate 232, the gate control circuit 224 sets the first gate 232 to the low voltage mode (step S28 in FIG. 12). Further, at the time MT2, the gate control circuit 224 determines whether or not a leak has occurred at the second gate 234. In (C) of FIG. 13, it is determined that a leak has occurred at the second gate 234 (YES in step S30 of FIG. 12). Therefore, since a leak has occurred in both the first gate 232 and the second gate 234, the gate control circuit 224 stops the operation of the switching element 230. That is, the gate control circuit 224 sets both Vg1 and Vg2 to zero volt.

FIG. 13D is a graph of Vg1 and Vg2 controlled by the gate control circuit 224 when a short circuit occurs in the first gate 232. First, at time MT1, the gate control circuit 224 determines whether or not a leak has occurred at the first gate 232. In (D) of FIG. 13, it is determined that a leak has occurred at the first gate 232 (YES in step S20 of FIG. 12). Then, at time MT2, the gate control circuit 224 determines whether or not a short circuit has occurred at the first gate 232. In (D) of FIG. 13, it is determined that a short circuit has occurred at the first gate 232 (YES in step S24 of FIG. 12). Therefore, the gate control circuit 224 sets the first gate 232 to the off mode (step S26 in FIG. 12). Further, at the time MT2, the gate control circuit 224 determines whether or not a leak has occurred at the second gate 234. In (D) of FIG. 13, it is determined that no leak has occurred at the second gate 234 (NO in step S30 of FIG. 12). Therefore, since a short circuit occurs only in the first gate 232, the gate control circuit 224 prohibits the use of the first gate 232. That is, the gate control circuit 224 sets Vg1 to zero volt and uses only the second gate 234 to operate the switching element 230.

According to the above, when a slight leak occurs in only one gate, the operation of the switching element 230 can be continued without being excessively restricted by limiting only the voltage applied to the gate. Further, when a short circuit occurs in only one of the gates, the switching element 230 can be operated by using the other normal gate by prohibiting the use of only the gate. If a leak and / or a short circuit occurs in both gates, the operation of the switching element 230 can be stopped.

The points to keep in mind regarding this technology are described. The zero volt described herein corresponds to an example of a reference voltage. The V volt described herein corresponds to an example of an on-voltage. The −V volt described herein corresponds to an example of off-voltage.

The signal MG + V corresponds to an example of the first signal. The signal MG0 corresponds to an example of the second signal. The signal CG + V corresponds to an example of the third signal. The signal CG0 corresponds to an example of the fourth signal. The signal CG-V corresponds to an example of the fifth signal. It should be noted that the description of "MG + V" in parentheses as "first signal (MG + V)" is for ease of understanding and does not limit the present technology. The same applies to the description of the second signal to the fifth signal.

Although specific examples of the techniques disclosed in the present specification have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

2: Semiconductor device 10: Controller 20: Drive circuit 22: Logic circuit 22a, 22b: Mask circuit 24: Gate control circuit 30: Switching element 32: First gate 34: Second gate

Claims (1)

A double-gate type switching element having two gates, a first gate and a second gate,
Based on the first carrier signal and the common duty value, a binary signal, the first command signal, is generated, and the phase is advanced from the first carrier signal by a predetermined time based on the second carrier signal and the common duty value. And a controller that generates a second command signal, which is a binary signal,
A drive circuit that is connected to the switching element and the controller and drives the first gate and the second gate, respectively, based on the first command signal and the second command signal.
Is equipped with
The drive circuit includes a logic circuit and a gate control circuit.
The logic circuit generates a first signal (MG + V) and a second signal (MG0) based on the first command signal, and a third signal based on the first command signal and the second command signal. (CG + V), 4th signal (CG0) and 5th signal (CG-V) are generated.
The gate control circuit selectively applies a reference voltage or an on-voltage higher than the reference voltage to the first gate based on the first signal (MG + V) and the second signal (MG0). At the same time, based on the third signal (CG + V), the fourth signal (CG0), and the fifth signal (CG-V), the reference voltage, the on voltage, or the reference voltage is higher than the reference voltage at the second gate. Selectively apply a low off voltage,
The logic circuit
A first mask circuit that generates a first latch signal that is latched by the NOT signal of the second command signal and reset by the NOR signal of the first command signal and the second command signal.
It also has a second mask circuit that generates a second latch signal that is latched by the second command signal and reset by the first command signal.
The first signal (MG + V) is the first command signal, and is
The second signal (MG0) is a NOT signal of the first command signal, and is
The third signal (CG + V) is an AND signal of the NOR signal of the first latch signal, the second latch signal, and the first command signal.
The fourth signal (CG0) includes the second latch signal.
The fifth signal (CG-V) is a NOR signal of the third signal (CG + V) and the fourth signal (CG0).
Semiconductor device.

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