JP6699426B2 - Load drive - Google Patents

Description

  The present invention relates to a load driving device that controls energization of a load.

  In a load driving device that drives a load such as a solenoid, pulse width modulation control (hereinafter, PWM control) is performed to energize the load so that a detected value of current flowing in the load (hereinafter, referred to as load current) matches a target value. (Refer to Patent Document 1). In this case, the load current is controlled by performing PWM control of driving a switching element such as one MOS transistor interposed in series in the power supply path from the power supply to the load.

JP, 10-39902, A

  Generally, in a switching element such as a MOS transistor, the turn-on delay time and the turn-off delay time do not completely coincide with each other, but they are different from each other. If there is a difference between the turn-on delay time and the turn-off delay time, in the above-described conventional load current control method, the duty of the drive signal for driving the switching element and the duty of the load current do not match.

  That is, in this case, an error occurs between the desired duty and the actual duty. If such an error exists, it becomes impossible to output a duty smaller than the error, and there is a possibility that the accuracy of control of the load current may be reduced particularly when the load is driven at a relatively high frequency.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a load drive device capable of accurately controlling a current flowing through a load.

The load driving device according to claim 1, wherein the load driving device (1) PWM-controls energization to the load (4), and the upstream switching element is provided on an upstream side of a power supply path from the power supply to the load. (T1), a downstream switching element (T2) provided on the downstream side of the power supply path, a current detection unit (6) that detects a current flowing through the load, and a control unit (5). The control unit controls the driving of the upstream switching element and the downstream switching element so that the detection value of the current detection unit matches the desired target value. Further, the control unit drives the upstream side switching element and the downstream side switching element at a drive cycle twice as long as the cycle of the PWM control, and gives a command for ON-driving the upstream side switching element and the downstream side switching element . The output timings are different from each other by ½ of the drive cycle .

  In the above configuration, the load is energized while both the upstream switching element and the downstream switching element are turned on. Then, the latter half of the drive cycle of the upstream side switching element and the first half of the drive cycle of the downstream side switching element overlap, and the latter half of the drive cycle of the downstream side switching element and the first half of the drive cycle of the upstream side switching element are It overlaps. Therefore, in each of the overlapping periods, the load energization period, that is, the duty of the load current is controlled by the relationship between the timing at which one of the upstream switching element and the downstream switching element is turned on and the timing at which the other is turned off. To be done.

  Then, in this case, the turn-on delay and the turn-off delay of the switching element may be taken into consideration, and the timing of turning on and off each switching element may be determined so that the duty of the load current has a desired value. This makes it possible to control the load current with a minute duty that is smaller than the error based on the difference between the turn-on delay and the turn-off delay of the switching element. Therefore, according to the above configuration, even when the load is driven at a relatively high frequency, the current flowing through the load can be accurately controlled without degrading the accuracy of the current control.

The figure which shows typically the structure of the load drive device which concerns on 1st Embodiment. The figure which shows the structure of the internal block of CPU typically. The figure which shows the flow of the energization control to the load typically Timing chart schematically showing each drive signal, load voltage, and load current when the duty of the load current is relatively high Timing chart that schematically shows each drive signal, upstream voltage, downstream voltage, load voltage, and load current in the case where the duty of the load current is a minute value Part 1 Timing chart that schematically shows each drive signal, upstream voltage, downstream voltage, load voltage, and load current in the case where the duty of the load current is a minute value 2 Timing chart schematically showing each drive signal, load voltage, and load current according to a comparative example The figure which shows typically the structure of the internal block of CPU which concerns on 2nd Embodiment.

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In addition, in each embodiment, the substantially same configurations are denoted by the same reference numerals, and description thereof will be omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the load driving device 1 is provided, for example, in an electronic control unit (ECU) mounted on a vehicle, and is supplied from a power source such as a battery (not shown) through a pair of power supply lines 2 and 3. Is supplied to the load 4. The load driving device 1 PWM-controls energization of the load 4, that is, a current flowing through the load 4 (hereinafter referred to as a load current). The load 4 is, for example, a coil (solenoid) of an electromagnetic valve for controlling the flow rate of fuel. The load driving device 1 includes transistors T1 and T2, a shunt resistor R1, a diode D1, a controller 5, a current detector 6, and the like.

  The transistors T1 and T2 are, for example, N-channel type MOS transistors. The drain of the transistor T1 is connected to the power supply line 2 to which the battery voltage VB is applied, and the source thereof is connected to the upstream terminal of the load 4. The source of the transistor T2 is connected to the power supply line 3 to which the reference potential (ground) is applied, and the drain thereof is connected to the downstream side terminal of the load 4 via the shunt resistor R1. The transistor T1 corresponds to an upstream switching element provided on the upstream side of the power supply path from the power supply to the load 4. The transistor T2 corresponds to a downstream switching element provided on the downstream side of the power supply path from the power supply to the load 4.

  The diode D1 is connected between the source of the transistor T1 and the drain of the transistor T2 with the drain side of the transistor T2 as an anode. The diode D1 is a flywheel diode (reflux diode), and when the power supply to the load 4 is cut off, the load current is circulated to suppress the surge due to the back electromotive force.

  An upstream drive command signal SGH (hereinafter, abbreviated as drive signal SGH) output from the upstream driver 7 of the control unit 5 is applied to the gate of the transistor T1. Further, the gate of the transistor T2 is supplied with a downstream drive command signal SGL (hereinafter, abbreviated as drive signal SGL) output from the downstream driver 8 of the control unit 5. The terminal voltage of the shunt resistor R1 is given to the current detector 6. The current detector 6 detects the load current based on the terminal voltage of the shunt resistor R1 and outputs a detection signal representing the detected value to the A/D converter 9 of the controller 5.

  The A/D converter 9 converts the detection signal given from the current detection unit 6 into a digital value and outputs it to the CPU 10. The CPU 10 acquires the detected value of the load current based on the digital value given from the A/D converter 9. The CPU 10 controls the driving of the transistors T1 and T2 via the upstream driver 7 and the downstream driver 8 so that the detected value of the load current matches the desired target value.

  The CPU 10 realizes various functions relating to drive control of the transistors T1 and T2 by executing programs stored in a memory (not shown). FIG. 2 is a block diagram showing each function realized by the CPU 10. The target value of the load current and the detected value of the load current are input to the duty calculation unit 11. The duty calculator 11 calculates a load duty, which is a duty for energizing the load 4, based on the target value and the detected value. Note that the duty referred to in this specification is the ratio of the ON period in one cycle, that is, the ON duty.

  A load frequency (for example, 10 kHz) that is a frequency corresponding to a control cycle of the load current (cycle of PWM control) is input to the frequency calculation unit 12. The frequency calculator 12 calculates the drive frequency, which is the frequency of the drive signals SGH and SGL, based on the load frequency. In this case, the drive frequency is, for example, 5 kHz, which is 1/2 of the load frequency. Therefore, the period of the drive signals SGH and SGL is 200 μsec, which is twice the control period (100 μsec) of the load current.

  The PWM generators 13 and 14 are input with the load duty calculated by the duty calculation unit 11, the drive frequency calculated by the frequency calculation unit 12, the on-delay time and the off-delay time of the transistors T1 and T2. The on-delay time and the off-delay time may be stored in advance in a memory or the like, or may be externally acquired via communication or the like.

  In this case, the on-delay time of the transistors T1 and T2 is, for example, 0.75 μsec, and the off-delay time is, for example, 5.4 μsec, which are different from each other, and the off-delay time is longer than the on-delay time. ing. In the case of the transistors T1 and T2 which are MOS transistors, the charging/discharging time to the parasitic capacitance between the gate and the source and between the gate and the drain is one of the factors causing such a delay time. In general, in the case of a MOS transistor, the delay due to discharging (off delay) tends to be longer than the delay due to charging (on delay).

  The PWM generator 13 generates a PWM signal having the drive frequency calculated by the frequency calculator 12 and a duty corresponding to the load duty. In this case, the PWM generator 13 determines the duty of the PWM signal to be generated based on the load duty, the on-delay time and the off-delay time of the transistor T1.

Specifically, the duty Dd of the PWM signal is set to a value that satisfies the following expression (1). However, the load duty is D1, the control cycle of the load current is T1, the cycle of the drive signals SGH and SGL is Td, the off delay time is td(off), and the on delay time is td(on).
Dl×Tl=(Dd−0.5)×Td+td(off)−td(on) (1)
The PWM signal output from the PWM generator 13 is given to the gate of the transistor T1 as the drive signal SGH via the upstream driver 7.

  The PWM generator 14 generates a PWM signal having the drive frequency calculated by the frequency calculator 12 and a duty corresponding to the load duty. In this case, the PWM generator 14 determines the duty of the generated PWM signal based on the load duty, the on-delay time and the off-delay time of the transistor T2. Like the duty of the PWM signal generated by the PWM generator 13, the duty of the PWM signal generated by the PWM generator 14 is set to a value that satisfies the above expression (1). The PWM signal output from the PWM generator 14 is given to the delay circuit 15.

  The drive frequency calculated by the frequency calculator 12 is applied to the delay circuit 15. The delay circuit 15 delays the input PWM signal by a period of ½ of the cycle of the drive signals SGH and SGL and outputs the delayed PWM signal. The PWM signal output via the delay circuit 15 is given to the gate of the transistor T2 as the drive signal SGL via the downstream driver 8.

  In the above configuration, the PWM generators 13 and 14, the delay circuit 15, the upstream driver 7 and the downstream driver 8 generate a drive signal SGH that is a drive signal for driving the transistor T1 and has a duty corresponding to the load duty. At the same time, a drive signal generation unit 16 that generates a drive signal SGL that is a drive signal for driving the transistor T2 and has a duty corresponding to the load duty is configured. Further, the PWM generators 13 and 14 correspond to a signal generation unit that generates a drive signal (PWM signal) having a duty corresponding to the load duty.

  With such a configuration, the control unit 5 drives the transistors T1 and T2 at a cycle (for example, 200 μsec) that is twice as long as the load current control cycle (PWM control period, for example, 100 μsec), and The driving phases of T1 and T2 are different from each other by ½ cycle. Then, in the control unit 5, the CPU 10 executes the processing as shown in FIG. 3 to control the duty of the drive signals SGH and SGL (PWM control) so that the detected value of the load current matches the desired target value. Is done.

  That is, as shown in FIG. 3, first, in step S1, it is determined whether the target value of the load current and the detected value match. If the target value and the detected value match, that is, if "YES" in step S1, the process ends without changing the duty. On the other hand, when the target value and the detected value do not match, that is, "NO" in step S1, the process proceeds to step S2.

  In step S2, it is determined whether the detected value is larger than the target value. If the detected value is larger than the target value, that is, if "YES" in step S2, the process proceeds to step S3. In step S3, the duty of the drive signals SGH and SGL is changed so as to be smaller than the duty at that time. On the other hand, if the detected value is smaller than the target value, that is, if "NO" in step S2, the process proceeds to step S4. In step S4, the duty of the drive signals SGH and SGL is changed so as to be larger than the duty at that time. After the execution of steps S3 and S4, the process ends.

Next, the operation of the above configuration will be described.
In the above configuration, the load 4 is energized while both the transistors T1 and T2 are turned on. That is, the load voltage is applied to the load 4 and the load current flows while the transistors T1 and T2 are both turned on. Further, since the drive cycles of the drive signals SGH and SGL are shifted from each other by 1/2 cycle, the latter half of the drive cycle of the transistor T1 and the first half of the drive cycle of the transistor T2 overlap and the first half of the drive cycle of the transistor T2. And the latter half of the driving cycle of the transistor T1 overlap. Therefore, in each of the overlapping periods, the energization period to the load 4, that is, the duty of the load current is controlled by the relationship between the timing when one of the transistors T1 and T2 is turned on and the timing when the other is turned off.

  For example, when the duty of the load current is a relatively high value (for example, 10%), the drive signals SGH and SGL output from the load drive device 1, the load voltage applied to both ends of the load 4, and the load current flowing to the load 4. Has a waveform as shown in FIG. In this case, the period of the drive signals SGH and SGL is 200 μsec, which is twice the period of the load voltage and the load current (100 μsec). The drive phases of the drive signals SGH and SGL differ from each other by ½ of the cycle, that is, 100 μsec. The duty of each drive signal SGH, SGL is set to about 53%.

  In this case, the timing at which the drive signals SGH and SGL turn to the H level, that is, the timing at which the transistors T1 and T2 are turned on, is fixed regardless of the duty. On the other hand, the timing at which the drive signals SGH and SGL turn to the L level, that is, the timing at which the transistors T1 and T2 are turned off changes according to the duty. In FIG. 4, the timing when the drive signal SGL changes to the H level is ta, the timing when the drive signal SGH changes to the L level is tb, the timing when the drive signal SGH changes to the H level is tc, and the drive signal SGL changes to the L level. The timing of turning to the level is td.

  Therefore, in the period in which the latter half of the driving cycle of the transistor T1 and the first half of the driving cycle of the transistor T2 overlap, the load duty is determined based on the timing ta when the transistor T2 is turned on and the timing tb when the transistor T1 is turned off. .. Then, in this period, from the time point after the on-delay time (0.75 μsec) has passed after the drive signal SGL turned to the H level, the off-delay time (5.4 μsec) after the drive signal SGH turned to the L level. The load voltage is applied and the load current flows until the time point after the elapse.

  In the period in which the latter half of the driving cycle of the transistor T2 and the first half of the driving cycle of the transistor T1 overlap, the load duty is determined based on the timing tc at which the transistor T1 turns on and the timing td at which the transistor T2 turns off. .. Then, in this period, the load voltage is applied from the time point after the on-delay time has elapsed after the drive signal SGH turned to the H level to the time point after the off-delay time has passed since the drive signal SGL turned to the L level. Load current will flow.

  When the duty of the load current is a small value (for example, 2.5%), the drive signals SGH and SGL output from the load driving device 1, the upstream voltage that is the voltage of the upstream terminal of the load 4, and the load 4 The downstream voltage, the load voltage, and the load current, which are the voltages at the downstream terminals of the, have the waveforms shown in FIGS. 5 and 6. In this case, the duty of each drive signal SGH, SGL is set to about 49%. That is, in this case, there is no period in which both the drive signals SGH and SGL are at the H level.

  FIG. 5 shows a period in which the latter half of the driving cycle of the transistor T1 and the first half of the driving cycle of the transistor T2 overlap. While the transistor T1 is on, the battery voltage VB is applied to the upstream terminal of the load 4. When the drive signal SGH turns to L level, the transistor T1 turns off after the lapse of the off delay time. Therefore, the upstream side voltage becomes a value substantially equal to the battery voltage VB during the period from when the drive signal SGH turns to the L level to when the off delay time of 5.4 μs elapses.

  Further, the reference potential (0 V) is applied to the downstream side terminal of the load 4 while the transistor T2 is on. When the drive signal SGL turns to H level, the transistor T2 turns on after the lapse of the on-delay time. Therefore, after 0.75 μsec which is the on-delay time elapses from the time when the drive signal SGL changes to the H level, the downstream voltage becomes a value substantially equal to 0V.

  Therefore, in this case, although there is no period in which both the drive signals SGH and SGL are at the H level, there is a period in which both the transistors T1 and T2 are on. The load 4 is energized during a period in which both the transistors T1 and T2 are turned on, that is, a period in which the battery voltage VB is applied to the upstream terminal of the load 4 and 0 V is applied to the downstream terminal.

  Thus, before the command (H level drive signal SGL) for turning on the downstream transistor T2 is output, the command (L level drive signal for turning off the upstream transistor T1 is turned off). By outputting (SGH), it becomes possible to realize a minute load duty without being affected by the on-delay time and the off-delay time of the transistors T1 and T2.

  FIG. 6 shows a period in which the latter half of the driving cycle of the transistor T2 and the first half of the driving cycle of the transistor T1 overlap. In this case, the operation is similar to that in the period shown in FIG. 5, except that the relationship between the transistors T1 and T2 is reversed. Then, as shown in FIG. 6, before the command (H level drive signal SGH) for turning on the upstream transistor T1 is output, the command (for turning off the downstream transistor T2 is turned off). By outputting the L-level drive signal SGL), it becomes possible to realize a minute load duty without being affected by the on-delay time and the off-delay time of the transistors T1 and T2.

According to this embodiment described above, the following effects can be obtained.
In the prior art in which the load current is controlled by PWM-controlling the drive of one MOS transistor that is interposed in series in the power supply path from the power source to the load, an error caused by the difference between the on-delay time and the off-delay time of the MOS transistor is used. Occurs. Therefore, also in the load driving device 1 of the present embodiment, when the control method (hereinafter, referred to as a comparative example) in which the driving of the transistor T2 is PWM-controlled while the transistor T1 is always on, for example, the above error is caused. Occurs.

In such a comparative example, as shown in FIG. 7, even if the duty of the drive signal SGL is set to 10% so that the duty of the load current (load duty) is 10%, the actual duty of the load current is As shown in the following equation (2), the value becomes higher than 10% (14.65%). However, the drive cycle of the drive signal SGL is 100 μsec, the on-delay time of the transistor T2 is 0.75 μsec, and the off-delay time of the transistor T2 is 5.4 μsec.
(10+5.4-0.75)/100=14.65[%] (2)
As described above, in the case of the comparative example, a minute duty of 4.65% or less cannot be realized as the duty of the load current.

  On the other hand, in the load driving device 1 of the present embodiment, the transistor T1 on the upstream side and the transistor T2 on the downstream side are driven at a cycle twice as long as the cycle of the PWM control, and the drive phases of the transistors T1 and T2 are set to 1 with each other. /2 different periods. Then, in the period in which the driving periods of the transistors T1 and T2 overlap, the energization period to the load 4, that is, the load current, depends on the relationship between the timing when one of the transistors T1 and T2 is turned on and the timing when the other is turned off. The duty is controlled. Further, in this case, the duty of the transistors T1 and T2 is determined so that the duty of the load current has a desired value while considering the on-delay time and the off-delay time of the transistors T1 and T2.

  Therefore, it is possible to control the load current with a minute duty that is smaller than the error based on the difference between the on-delay time and the off-delay time of the transistors T1 and T2. Therefore, according to the present embodiment, it is possible to obtain an excellent effect that the current flowing through the load can be accurately controlled without lowering the accuracy of current control even when the load 4 is driven at a relatively high frequency. .

(Second embodiment)
The second embodiment will be described below with reference to FIG.
In the first embodiment, the drive cycle of the drive signal SGL for driving the transistor T2 on the downstream side is delayed by 1/2 cycle with reference to the drive signal SGH for driving the transistor T1 on the upstream side. The drive cycle of the drive signal SGH may be delayed by 1/2 with reference to the drive signal SGL.

  In this case, the configuration of the CPU 10 may be changed as shown in FIG. That is, the drive signal generation unit 21 shown in FIG. 8 is different from the drive signal generation unit 16 in that a delay circuit 22 is provided instead of the delay circuit 15. The delay circuit 22 has the same function as the delay circuit 15.

  In this case, the PWM signal output from the PWM generator 14 is given to the gate of the transistor T2 as the drive signal SGL via the downstream driver 8. Then, the PWM signal output from the PWM generator 13 is given to the delay circuit 22. The PWM signal output via the delay circuit 22 is given to the gate of the transistor T1 as the drive signal SGH via the upstream driver 7.

  With the configuration of the present embodiment as well, the upstream-side transistor T1 and the downstream-side transistor T2 are driven at a cycle that is twice the cycle of the PWM control, and the drive phases of the transistors T1 and T2 are ½ cycle of each other. Since it can be shifted only by that, the same effect as that of the first embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and can be arbitrarily modified, combined, or expanded without departing from the gist thereof.
One of the PWM generators 13 and 14 may be omitted. In that case, if the PWM signal itself generated by one PWM generator is one of the drive signals SGH and SGL, and the PWM signal delayed through the delay circuit 15 is the other of the drive signals SGH and SGL. Good.
The upstream switching element and the downstream switching element are not limited to MOS transistors, and various switching elements such as bipolar transistors and IGBTs can be used.

  In each of the above-described embodiments, the control unit 5 calculates the load duty based on the detected value of the load current based on the target value, and outputs the drive signals SGH and SGL having the duty corresponding to the load duty. The control unit 5 may be configured to control the driving of the transistors T1 and T2 so that the detected value of the load current matches the target value. For example, the control unit 5 may have a configuration capable of executing the process shown in FIG. 3, that is, the process of increasing or decreasing the duty of the drive signals SGH and SGL so that the detected value of the load current matches the target value. However, also in this case, the control unit 5 drives the transistors T1 and T2 at a cycle twice as long as the cycle of the PWM control, and makes the drive phases of the transistors T1 and T2 different from each other by ½ cycle. By doing so, the same effect as that of each of the above-described embodiments, that is, the load current can be controlled with a minute duty even when the load 4 is driven at a relatively high frequency, and thus the accuracy of current control is improved. The effect is obtained.

  The load driving device of the present invention is not limited to the load 4 which is a solenoid of a solenoid valve, but various loads such as a hydraulic control valve and a linear solenoid as an actuator of an automatic transmission. You can

  DESCRIPTION OF SYMBOLS 1... Load drive device, 4... Load, 5... Control part, 6... Current detection part, 11... Duty calculation part, 13, 14... PWM generator, 15, 22... Delay circuit, 16, 21... Drive signal generation part , T1, T2... Transistors.

Claims (6)

A load drive device (1) for PWM control of energization to a load (4), comprising:
An upstream switching element (T1) provided on the upstream side of a power supply path from the power source to the load,
A downstream switching element (T2) provided on the downstream side of the power feeding path,
A current detector (6) for detecting a current flowing through the load,
A control unit (5) that controls driving of the upstream switching element and the downstream switching element so that the detection value of the current detection unit matches a desired target value;
Equipped with
The control unit drives the upstream switching element and the downstream switching element at a drive cycle that is twice the PWM control cycle, and also turns on the upstream switching element and the downstream switching element . Load drive device in which the timings for outputting the commands are different from each other by ½ of the drive cycle . The control unit is
A duty calculation unit (11) for obtaining a load duty that is a duty of energizing the load based on the detected value and the target value;
The drive signal is a drive signal for driving the upstream switching element, and is a drive signal for driving the downstream switching element while generating an upstream drive command signal having a duty according to the load duty, and the upstream command drive A drive signal generation unit (16, 21) for generating a downstream drive command signal having the same duty as the signal;
The load driving device according to claim 1, further comprising: The drive signal generation unit,
A signal generation unit (13, 14) for generating a drive signal having a duty corresponding to the load duty;
A delay circuit (15, 22) for delaying the drive signal generated by the signal generation unit by a half period of the cycle;
Equipped with
The drive signal generated by the signal generation unit is one of the upstream drive command signal and the downstream drive command signal, and the drive signal output through the delay circuit is the upstream drive command signal. The load driving device according to claim 2, wherein the load driving device is the other of the downstream drive command signal.   The drive signal generation unit determines the duty of the upstream drive command signal and the downstream drive command signal based on the load duty, the ON delay time of the switching element, and the OFF delay time of the switching element. 2. The load driving device according to 2 or 3.   The load driving device according to claim 1, wherein the upstream switching element and the downstream switching element are MOS transistors.   The load driving device according to claim 1, wherein the load is a solenoid.

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