JP2018019131A - Load drive device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load drive device capable of controlling the current flowing to a load accurately.SOLUTION: A load drive device 1 performing PWM control of electrification to a load 4 includes a transistor T1 provided on the upstream side of a power supply path from a power source to the load 4, a transistor T2 provided on the downstream side of the power supply path, a current detector 6 for detecting the current flowing to the load 4 and a control section 5. The control section 5 controls driving of the transistors T1, T2 so that the detection value of the current detector 6 matches a desired target value. Furthermore, the control section 5 drives the transistors T1, T2 with a period twice that of the PWM control, and differentiates drive phases of the transistors T1, T2 by 1/2 period from each other.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a load driving device that controls energization to a load.

  In a load driving device that drives a load such as a solenoid, pulse width modulation control (hereinafter referred to as PWM control) is applied to the load so that a detected value of a current flowing through the load (hereinafter referred to as load current) matches a target value. (Refer to Patent Document 1, for example). In this case, control of the load current is realized by PWM control of driving of a switching element such as one MOS transistor that is interposed in series in a power supply path from the power source to the load.

Japanese Patent Laid-Open No. 10-39902

  In general, in a switching element such as a MOS transistor, the turn-on delay time and the turn-off delay time do not completely coincide with each other and are different from each other. If there is a difference between the turn-on and turn-off delay times, the conventional load current control method described above does not match the duty of the drive signal for driving the switching element with the duty of the load current.

  That is, in this case, an error occurs between the desired duty and the actual duty. When such an error exists, it is impossible to output a duty smaller than the error, and there is a possibility that the accuracy of control of the load current is lowered particularly when the load is driven at a relatively high frequency.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a load driving device capable of accurately controlling a current flowing through a load.

  The load driving device according to claim 1 is a load driving device (1) that performs PWM control of energization to a load (4), and is an upstream switching element provided on an upstream side of a power feeding path from a power source to a load. (T1), a downstream switching element (T2) provided on the downstream side of the power feeding path, a current detection unit (6) that detects a current flowing through the load, and a control unit (5). The control unit controls driving of the upstream side switching element and the downstream side switching element so that the detection value of the current detection unit coincides with a desired target value. In addition, the control unit drives the upstream switching element and the downstream switching element at a cycle twice that of the PWM control, and makes the drive phases of the upstream switching element and the downstream switching element different from each other by ½ cycle. It is like that.

  In the above configuration, energization to the load is performed during a period in which both the upstream side switching element and the downstream side switching element are turned on. The second half of the drive cycle of the upstream switching element and the first half of the drive cycle of the downstream switching element overlap, and the second half of the drive cycle of the downstream switching element and the first half of the drive cycle of the upstream switching element are Duplicate. Therefore, in each of the overlapping periods, the energization period to the load, that is, the duty of the load current is controlled by the relationship between the timing when one of the upstream switching element and the downstream switching element is turned on and the timing when the other is turned off. Is done.

  In this case, the timing for turning on and off each switching element may be determined so that the duty of the load current becomes a desired value while considering the turn-on delay and the turn-off delay of the switching element. In this way, it becomes possible to control the load current with a small duty smaller than the error based on the difference between the turn-on delay and the turn-off delay of the switching element. Therefore, according to the above configuration, even when the load is driven at a relatively high frequency, the current flowing through the load can be accurately controlled without causing a decrease in accuracy of current control.

The figure which shows typically the structure of the load drive device which concerns on 1st Embodiment. The figure which shows the structure of the internal block of CPU typically Diagram showing the flow of energization control to the load Timing chart schematically showing each drive signal, load voltage and load current when the duty of the load current is relatively high Timing chart 1 schematically showing each drive signal, upstream voltage, downstream voltage, load voltage and load current when the duty of the load current is a minute value Timing chart 2 schematically showing each drive signal, upstream voltage, downstream voltage, load voltage and load current when the duty of the load current is a minute value Timing chart schematically showing each drive signal, load voltage and load current according to the comparative example The figure which shows typically the structure of the internal block of CPU which concerns on 2nd Embodiment.

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, a load driving device 1 is provided, for example, in an electronic control unit (ECU) mounted on a vehicle, and is supplied with power from a power source such as a battery (not shown) through a pair of power lines 2 and 3. Is supplied to the load 4. The load driving device 1 performs PWM control of energization to the load 4, that is, a current flowing through the load 4 (hereinafter referred to as load current). The load 4 is, for example, a coil (solenoid) of a solenoid valve for controlling the flow rate of fuel. The load driving device 1 includes transistors T1 and T2, a shunt resistor R1, a diode D1, a control unit 5, a current detection unit 6, and the like.

  The transistors T1 and T2 are, for example, N channel type MOS transistors. The drain of the transistor T1 is connected to the power supply line 2 to which the battery voltage VB is applied, and the source thereof is connected to the upstream terminal of the load 4. The source of the transistor T2 is connected to the power supply line 3 to which the reference potential (ground) is applied, and the drain thereof is connected to the downstream terminal of the load 4 via the shunt resistor R1. The transistor T1 corresponds to an upstream switching element provided on the upstream side of the power supply path from the power source to the load 4. The transistor T2 corresponds to a downstream switching element provided on the downstream side of the power supply path from the power supply to the load 4.

  The diode D1 is connected between the source of the transistor T1 and the drain of the transistor T2 with the drain side of the transistor T2 as an anode. The diode D1 is a flywheel diode (refluxing diode), and suppresses a surge caused by the counter electromotive force by circulating the load current when the load 4 is de-energized.

  An upstream drive command signal SGH (hereinafter abbreviated as drive signal SGH) output from the upstream driver 7 of the control unit 5 is given to the gate of the transistor T1. Further, a downstream drive command signal SGL (hereinafter abbreviated as drive signal SGL) output from the downstream driver 8 of the control unit 5 is given to the gate of the transistor T2. The terminal voltage of the shunt resistor R1 is given to the current detector 6. The current detection unit 6 detects a load current based on the terminal voltage of the shunt resistor R1, and outputs a detection signal representing the detected value to the A / D converter 9 of the control unit 5.

  The A / D converter 9 converts the detection signal given from the current detection unit 6 into a digital value and outputs it to the CPU 10. The CPU 10 acquires a load current detection value based on the digital value given from the A / D converter 9. The CPU 10 controls driving of the transistors T1 and T2 via the upstream driver 7 and the downstream driver 8 so that the detected value of the load current matches a desired target value.

  The CPU 10 implements various functions related to drive control of the transistors T1 and T2 by executing a program stored in a memory (not shown). FIG. 2 represents each function realized by the CPU 10 as a block configuration diagram. The duty calculation unit 11 is input with a load current target value and a load current detection value. The duty calculator 11 calculates a load duty that is a duty of energizing the load 4 based on the target value and the detected value. In addition, the duty said in this specification is the ratio for which the ON period occupies in one cycle, that is, the ON duty.

  A load frequency (for example, 10 kHz) that is a frequency corresponding to a load current control cycle (PWM control cycle) is input to the frequency calculation unit 12. The frequency calculation unit 12 calculates a drive frequency that is a frequency of the drive signals SGH and SGL based on the load frequency. In this case, the drive frequency is, for example, 5 kHz, which is ½ of the load frequency. Therefore, the period of the drive signals SGH and SGL is 200 μs, which is twice the control period (100 μs) of the load current.

  The PWM generators 13 and 14 are input with the load duty calculated by the duty calculator 11, the drive frequency calculated by the frequency calculator 12, the on-delay time and the off-delay time of the transistors T1 and T2. The on-delay time and off-delay time may be stored in advance in a memory or may be acquired from the outside via communication or the like.

  In this case, the on-delay time of the transistors T1 and T2 is, for example, 0.75 μsec, and the off-delay time is, for example, 5.4 μsec. The values are different from each other, and the off-delay time is longer than the on-delay time. ing. In the case of the transistors T1 and T2 which are MOS transistors, the charge / discharge time for the parasitic capacitance between the gate and the source and between the gate and the drain is one of the factors causing such a delay time. In general, in the case of a MOS transistor, a delay due to discharging (off delay) tends to be longer than a delay due to charging (on delay).

  The PWM generator 13 generates a PWM signal having a drive frequency calculated by the frequency calculation unit 12 and a duty corresponding to the load duty. In this case, the PWM generator 13 determines the duty of the PWM signal to be generated based on the load duty, the on-delay time and the off-delay time of the transistor T1.

Specifically, the duty Dd of the PWM signal is set to a value that satisfies the following expression (1). However, the load duty is Dl, the load current control period is Tl, the period of the drive signals SGH and SGL is Td, the off-delay time is td (off), and the on-delay time is td (on).
Dl × Tl = (Dd−0.5) × Td + td (off) −td (on) (1)
The PWM signal output from the PWM generator 13 is given to the gate of the transistor T1 as the drive signal SGH via the upstream driver 7.

  The PWM generator 14 generates a PWM signal having the drive frequency calculated by the frequency calculation unit 12 and having a duty corresponding to the load duty. In this case, the PWM generator 14 determines the duty of the PWM signal to be generated based on the load duty, the on delay time and the off delay time of the transistor T2. The duty of the PWM signal generated by the PWM generator 14 is set to a value that satisfies the above equation (1), similarly to the duty of the PWM signal generated by the PWM generator 13. The PWM signal output from the PWM generator 14 is given to the delay circuit 15.

  The delay circuit 15 is given the drive frequency calculated by the frequency calculation unit 12. Delay circuit 15 delays the input PWM signal by a period that is ½ of the cycle of drive signals SGH and SGL, and outputs the delayed signal. The PWM signal output via the delay circuit 15 is given to the gate of the transistor T2 as the drive signal SGL via the downstream driver 8.

  In the above configuration, the PWM generators 13 and 14, the delay circuit 15, the upstream driver 7 and the downstream driver 8 generate a drive signal SGH which is a drive signal for driving the transistor T1 and has a duty corresponding to the load duty. In addition, a drive signal generation unit 16 that generates a drive signal SGL that is a drive signal for driving the transistor T2 and that has a duty corresponding to the load duty is configured. The PWM generators 13 and 14 correspond to a signal generation unit that generates a drive signal (PWM signal) having a duty corresponding to the load duty.

  With such a configuration, the control unit 5 drives the transistors T1 and T2 with a cycle (for example, 200 μsec) that is twice the control cycle of the load current (the PWM control cycle, for example, 100 μsec). The drive phases of T1 and T2 are different from each other by a half period. Then, in the control unit 5, the CPU 10 executes the processing as shown in FIG. 3 to control the duty of the drive signals SGH and SGL so that the detected value of the load current matches the desired target value (PWM control). Is done.

  That is, as shown in FIG. 3, first, in step S1, it is determined whether or not the target value of the load current matches the detected value. If the target value matches the detected value, that is, if “YES” in the step S1, the processing is ended without changing the duty. On the other hand, if the target value does not match the detected value, that is, if “NO” in the step S1, the process proceeds to a step S2.

  In step S2, it is determined whether or not the detected value is larger than the target value. If the detected value is larger than the target value, that is, if “YES” in the step S2, the process proceeds to a step S3. In step S3, the duty of drive signals SGH and SGL is changed to be smaller than the duty at that time. On the other hand, if the detected value is smaller than the target value, that is, if “NO” in the step S2, the process proceeds to a step S4. In step S4, the duty of drive signals SGH and SGL is changed so as to be larger than the duty at that time. After execution of steps S3 and S4, the process ends.

Next, the operation of the above configuration will be described.
In the above configuration, the load 4 is energized during the period in which both the transistors T1 and T2 are turned on. That is, a load voltage is applied to the load 4 and a load current flows during a period in which both the transistors T1 and T2 are turned on. Further, since the drive cycles of the drive signals SGH and SGL are shifted from each other by a half cycle, the second half of the drive cycle of the transistor T1 overlaps the first half of the drive cycle of the transistor T2, and the first half of the drive cycle of the transistor T2. And the second half of the driving cycle of the transistor T1 overlap. Therefore, in each of the above overlapping periods, the energization period to the load 4, that is, the duty of the load current, is controlled by the relationship between the timing when one of the transistors T1 and T2 is turned on and the timing when the other is turned off.

  For example, when the duty of the load current is a relatively high value (for example, 10%), the drive signals SGH and SGL output from the load driving device 1, the load voltage applied to both ends of the load 4, and the load current flowing through the load 4 Has a waveform as shown in FIG. In this case, the cycle of the drive signals SGH and SGL is 200 μsec, which is twice the cycle of the load voltage and load current (100 μsec). Further, the drive phases of the drive signals SGH and SGL are different from each other by ½ of the cycle, that is, 100 μsec. And the duty of each drive signal SGH and SGL is set to about 53%.

  In this case, the timing at which the drive signals SGH and SGL change to the H level, that is, the timing at which the transistors T1 and T2 are turned on is fixed regardless of the duty. On the other hand, the timing at which the drive signals SGH and SGL change to the L level, that is, the timing at which the transistors T1 and T2 are turned off changes according to the duty. In FIG. 4, the timing at which the drive signal SGL changes to H level is ta, the timing at which the drive signal SGH changes to L level is tb, the timing at which the drive signal SGH changes to H level is tc, and the drive signal SGL is L The timing for turning to the level is td.

  Accordingly, in a period in which the second half of the driving cycle of the transistor T1 and the first half of the driving cycle of the transistor T2 overlap, the load duty is determined by the timing tb at which the transistor T1 is turned off with reference to the timing ta at which the transistor T2 is turned on. . In this period, the on-delay time (0.75 μsec) after the drive signal SGL changes to the H level and the off-delay time (5.4 μsec) after the drive signal SGH changes to the L level. A load voltage is applied and a load current flows until a time after the lapse.

  In the period in which the second half of the driving cycle of the transistor T2 and the first half of the driving cycle of the transistor T1 overlap, the load duty is determined by the timing td at which the transistor T2 is turned off with reference to the timing tc at which the transistor T1 is turned on. . In this period, the load voltage is applied from the time when the drive signal SGH changes to the H level to the time after the on-delay time elapses until the time after the drive signal SGL changes to the L level and the elapse of the off-delay time. Load current will flow.

  Further, when the duty of the load current is a small value (for example, 2.5%), the drive signals SGH and SGL output from the load driving device 1, the upstream voltage that is the voltage of the upstream terminal of the load 4, and the load 4 The downstream voltage, the load voltage, and the load current, which are the voltages of the downstream terminals, have waveforms as shown in FIGS. In this case, the duty of each drive signal SGH, SGL is set to about 49%. That is, in this case, there is no period in which both the drive signals SGH and SGL are at the H level.

  FIG. 5 shows a period in which the second half of the driving cycle of the transistor T1 overlaps with the first half of the driving cycle of the transistor T2. While the transistor T1 is on, the battery voltage VB is applied to the upstream terminal of the load 4. When the drive signal SGH changes to the L level, the transistor T1 turns off after the lapse of the off delay time. Therefore, the upstream voltage is substantially equal to the battery voltage VB during the period from when the drive signal SGH changes to the L level until 5.4 μs, which is the off delay time, has elapsed.

  Further, the reference potential (0 V) is applied to the downstream terminal of the load 4 while the transistor T2 is on. When the drive signal SGL turns to H level, the transistor T2 turns on after the on-delay time has elapsed. Therefore, after the time when the on-delay time of 0.75 μs has elapsed since the drive signal SGL changed to the H level, the downstream voltage has a value substantially equal to 0V.

  Therefore, in this case, there is no period in which both the drive signals SGH and SGL are at the H level, but there is a period in which both the transistors T1 and T2 are on. The load 4 is energized during the period when both the transistors T1 and T2 are turned on, that is, during the period when the battery voltage VB is applied to the upstream terminal of the load 4 and 0 V is applied to the downstream terminal.

  In this manner, the command (L level drive signal) for driving the upstream transistor T1 off before the command (H level drive signal SGL) for driving the downstream transistor T2 on is output. SGH) is output, so that a minute load duty can be realized without being affected by the on-delay time and off-delay time of the transistors T1 and T2.

  FIG. 6 shows a period in which the second half of the driving cycle of the transistor T2 overlaps with the first half of the driving cycle of the transistor T1. In this case, the operation is the same as the period of FIG. 5 except that the relationship between the transistors T1 and T2 is reversed. Then, as shown in FIG. 6, before the command (H level drive signal SGH) for turning on the upstream transistor T1 is output, the command for turning off the downstream transistor T2 ( By outputting the L level drive signal SGL), it is possible to realize a minute load duty without being affected by the on-delay time and the off-delay time of the transistors T1, T2.

According to this embodiment described above, the following effects can be obtained.
In the prior art in which the load current is controlled by PWM control of the drive of one MOS transistor that is serially interposed in the power supply path from the power source to the load, an error caused by the difference between the on delay time and the off delay time of the MOS transistor Occurs. Therefore, in the load driving device 1 of the present embodiment as well, if a control method (hereinafter referred to as a comparative example) is employed in which the driving of the transistor T2 is PWM-controlled while the transistor T1 is always turned on, the above error is caused. Arise.

In such a comparative example, as shown in FIG. 7, even if the duty of the drive signal SGL is set to 10% so that the duty of the load current (load duty) is 10%, the actual duty of the load current is As shown in the following formula (2), the value is higher than 10% (14.65%). However, the drive cycle of the drive signal SGL is 100 μs, the on-delay time of the transistor T2 is 0.75 μs, and the off-delay time of the transistor T2 is 5.4 μs.
(10 + 5.4-0.75) /100=14.65 [%] (2)
Thus, in the case of the comparative example, it is impossible to realize a minute duty of 4.65% or less as the duty of the load current.

  On the other hand, in the load driving device 1 of the present embodiment, the upstream side transistor T1 and the downstream side transistor T2 are driven at a cycle twice that of the PWM control cycle, and the drive phases of the transistors T1 and T2 are set to 1 each other. / 2 different periods. In the period in which the driving periods of the transistors T1 and T2 overlap, the energization period of the load 4, that is, the load current of the transistors T1 and T2, depending on the relationship between the timing when one of the transistors T1 and T2 is turned on and the timing when the other is turned off. Duty is controlled. In this case, the duty of the transistors T1 and T2 is determined so that the duty of the load current becomes a desired value in consideration of the on-delay time and the off-delay time of the transistors T1 and T2.

  Therefore, it is possible to control the load current with a small duty smaller than an error based on the difference between the on delay time and the off delay time of the transistors T1 and T2. Therefore, according to this embodiment, even when the load 4 is driven at a relatively high frequency, it is possible to obtain an excellent effect that the current flowing through the load can be accurately controlled without degrading the accuracy of the current control. .

(Second Embodiment)
The second embodiment will be described below with reference to FIG.
In the first embodiment, the drive cycle of the drive signal SGL for driving the downstream transistor T2 is delayed by 1/2 cycle with reference to the drive signal SGH for driving the upstream transistor T1. The drive signal SGH may be delayed by 1/2 with respect to the drive signal SGL.

  In this case, the configuration of the CPU 10 may be changed as shown in FIG. That is, the drive signal generator 21 shown in FIG. 8 differs from the drive signal generator 16 in that a delay circuit 22 is provided instead of the delay circuit 15. The delay circuit 22 has the same function as the delay circuit 15.

  In this case, the PWM signal output from the PWM generator 14 is given to the gate of the transistor T2 as the drive signal SGL via the downstream driver 8. The PWM signal output from the PWM generator 13 is given to the delay circuit 22. The PWM signal output via the delay circuit 22 is supplied to the gate of the transistor T1 as the drive signal SGH via the upstream driver 7.

  Even in the configuration of the present embodiment, the upstream transistor T1 and the downstream transistor T2 are driven at a cycle twice that of the PWM control cycle, and the drive phases of the transistors T1 and T2 are ½ cycle each other. Therefore, the same effect as that of the first embodiment can be obtained.

(Other embodiments)
In addition, this invention is not limited to each embodiment described above and described in drawing, In the range which does not deviate from the summary, it can change, combine or expand arbitrarily.
One of the PWM generators 13 and 14 may be omitted. In that case, if the PWM signal itself generated by one PWM generator is one of the drive signals SGH and SGL, the PWM signal delayed through the delay circuit 15 is the other of the drive signals SGH and SGL. Good.
The upstream switching element and the downstream switching element are not limited to MOS transistors, and various switching elements such as bipolar transistors and IGBTs can be employed.

  In each of the above embodiments, the control unit 5 calculates the load duty based on the detection value of the load current based on the target value, and outputs the drive signals SGH and SGL having a duty corresponding to the load duty. The control unit 5 may be configured to control the driving of the transistors T1 and T2 so that the detected value of the load current matches the target value. For example, the control unit 5 may be configured to execute the process shown in FIG. 3, that is, the process of increasing or decreasing the duty of the drive signals SGH and SGL so that the detected value of the load current matches the target value. However, in this case as well, the control unit 5 drives the transistors T1 and T2 with a cycle twice that of the PWM control, and causes the drive phases of the transistors T1 and T2 to differ from each other by ½ cycle. In this way, the same effect as in each of the above embodiments, that is, even when the load 4 is driven at a relatively high frequency, the load current can be controlled with a minute duty, so that the accuracy of the current control is improved. An effect is obtained.

  The load driving device of the present invention uses not only the load 4 that is a solenoid of a solenoid valve but also various loads such as a linear solenoid as an actuator of a hydraulic control valve, an automatic transmission or the like as a driving target (control target). Can do.

  DESCRIPTION OF SYMBOLS 1 ... Load drive device, 4 ... Load, 5 ... Control part, 6 ... Current detection part, 11 ... Duty calculation part, 13, 14 ... PWM generator, 15, 22 ... Delay circuit, 16, 21 ... Drive signal generation part , T1, T2 ... transistors.

Claims (6)

A load driving device (1) for PWM-controlling energization to a load (4),
An upstream switching element (T1) provided on the upstream side of a power supply path from a power source to the load;
A downstream switching element (T2) provided on the downstream side of the power feeding path;
A current detector (6) for detecting a current flowing through the load;
A control unit (5) for controlling driving of the upstream side switching element and the downstream side switching element so that a detection value of the current detection unit matches a desired target value;
With
The control unit drives the upstream side switching element and the downstream side switching element at a cycle twice that of the PWM control period, and sets the drive phases of the upstream side switching element and the downstream side switching element to 1 / Load drive device that makes two periods different. The controller is
A duty calculator (11) for obtaining a load duty which is a duty of energizing the load based on the detection value and the target value;
A drive signal for driving the upstream switching element and generating an upstream drive command signal having a duty corresponding to the load duty, and a drive signal for driving the downstream switching element and the upstream command drive A drive signal generator (16, 21) for generating a downstream drive command signal having the same duty as the signal;
The load driving device according to claim 1, comprising: The drive signal generator is
A signal generator (13, 14) for generating a drive signal having a duty corresponding to the load duty;
A delay circuit (15, 22) for delaying the drive signal generated by the signal generation unit by a period of ½ of the cycle;
With
The drive signal generated by the signal generator is one of the upstream drive command signal and the downstream drive command signal, and the drive signal output through the delay circuit is the upstream drive command signal. The load drive device according to claim 2, wherein the load drive device is the other of the downstream drive command signals.   The drive signal generation unit determines a duty of the upstream drive command signal and the downstream drive command signal based on the load duty, an on delay time of the switching element, and an off delay time of the switching element. 4. The load driving device according to 2 or 3.   The load driving device according to any one of claims 1 to 4, wherein the upstream side switching element and the downstream side switching element are MOS transistors.   The load driving device according to any one of claims 1 to 5, wherein the load is a solenoid.

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