JP2011065746A - Semiconductor integrated circuit for driving motor and semiconductor integrated circuit for motor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for driving and controlling a coil motor with high precision. <P>SOLUTION: The motor drive semiconductor integrated circuit (200) moves a magnetic head (106) which is used to read information from a storage track on a magnetic storage disk rotated and driven, by performing a feedback control while detecting a drive current of a voice coil motor (108) which moves the magnetic head on the disk, the drive current flowing through a coil of the voice coil motor. A control circuit which performs the feedback control of the voice coil motor includes: a current detector which detects the drive current flowing through the coil of the voice coil motor; and a control signal generator (235) which includes a digital circuit which generates a drive control signal for a driver circuit which causes the drive current to flow through the coil of the voice coil motor, based on the current detected by the current detector and a given current command value. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a control technique for a magnetic disk storage device, and more particularly to a control technique for a voice coil motor that moves a magnetic head for reading / writing information with respect to a storage track on a magnetic storage disk that is rotationally driven.

  A magnetic disk storage device includes a magnetic head for reading / writing information on a storage track on a rotationally driven magnetic storage disk, a voice coil motor for moving the magnetic head on the disk, and the magnetic head And a voice coil motor drive control device for positioning the magnetic head by controlling the drive current of the voice coil motor while monitoring the lead state.

  The information storage density of magnetic disk storage devices is increasing year by year, and accordingly, the magnetic head positioning control is also required to have very high accuracy. Therefore, feedback control is adopted in which the magnetic head is positioned by feedback control of the drive current of the voice coil motor based on the detected value of the drive current. For driving the voice coil motor that moves the magnetic head, a linear drive system that continuously changes the amount of drive current of the voice coil motor was initially employed.

  However, in order to increase the speed of the magnetic disk storage device, it is necessary to shorten the time required to move the magnetic head to the desired storage track, the so-called seek time. To this end, it is necessary to increase the drive current of the voice coil motor. There is. However, when the drive current of the voice coil motor is increased, the power loss particularly in the motor coil is increased, and the heat generation amount is increased accordingly. In the linear drive method, the increase in power supply current accompanying the reduction in seek time is remarkably large. On the other hand, there is pulse width modulation control (hereinafter referred to as PWM control) as a method for reducing the power supply required for moving the magnetic head. However, although PWM control consumes less power than the linear drive method, there is a problem that high-precision control is difficult.

  Therefore, the voice coil motor is driven by PWM control during the so-called seek to move the magnetic head to a predetermined storage track, and the voice coil motor is driven by the linear drive method during track follow to make the magnetic head follow the desired track for reading and writing. A technique for driving was developed (Patent Document 1).

JP 2002-184137 A

  However, when switching from seek operation to track follow operation, switching from PWM drive to linear drive must be performed smoothly and quickly, but it is difficult to control with high accuracy. Since the control circuit for PWM drive and the control circuit for linear drive must be optimally designed separately, there is a problem that the design burden is large and the circuit scale increases. Therefore, the present inventors examined performing both seek operation and track follow operation by PWM control.

  However, at present, a DA converter circuit of around 14 bits is used for PWM control of a voice coil motor, but a DA converter circuit of 16 bits or more is necessary to perform track follow by PWM control. There is a problem that it is relatively difficult to manufacture a DA conversion circuit of 16 bits or more by a mainstream CMOS process in manufacturing technology. Conventionally, for current detection for feedback control of a voice coil motor, a method in which a voltage generated at both ends of a resistor connected in series with a coil is detected by a linear amplifier is generally employed. It has become clear that there are various problems such as power loss and detection error due to jitter of the sampling clock.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit for driving control of a voice coil motor that can perform seek operation and track follow operation by PWM control and has a desired control accuracy and can be manufactured by a CMOS process. There is to do.

  Another object of the present invention is to provide a voice coil motor capable of performing current detection for feedback control of a voice coil motor with high accuracy without being affected by jitter of a sampling clock and without depending on a PWM cycle. Another object of the present invention is to provide a semiconductor integrated circuit for driving control.

  Still another object of the present invention is to provide a drive control semiconductor for a voice coil motor that can suppress the quantization noise and make the entire control system into a digital circuit, thereby improving the SN ratio compared to an analog circuit. It is to provide an integrated circuit.

  Still another object of the present invention is to provide a voice coil motor capable of performing seek operation and track follow operation by PWM control, reducing noise generated by PWM drive, and enabling highly accurate current control. Another object of the present invention is to provide a semiconductor integrated circuit for driving control.

  Still another object of the present invention is to automatically adjust a deviation in propagation delay time and transition time generated in a driver circuit due to manufacturing variations, to prevent a decrease in control accuracy of PWM drive, and to change the output signal of the driver circuit by the head. It is an object to provide a semiconductor integrated circuit for controlling driving of a voice coil motor capable of preventing occurrence of errors in position information and stored information due to noise combined with a read signal.

  Still another object of the present invention is to provide a semiconductor integrated circuit for controlling driving of a voice coil motor capable of reducing power loss generated in a sense resistor.

  Still another object of the present invention is to provide a semiconductor integrated circuit for driving control of a voice coil motor capable of reducing a coil error current caused by fluctuations in power supply voltage and performing highly accurate driving control.

  Still another object of the present invention is to provide a magnetic disk storage device with low power consumption and few read errors.

  The above and other objects and features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the first invention of the present application relates to a driving current of a voice coil motor that moves a magnetic head for reading information on a storage track on a magnetic storage disk that is rotationally driven on the disk. In a voice coil motor drive circuit that moves the magnetic head by performing feedback control while detecting a drive current flowing in the motor coil, the magnetic head based on command values from the controller such as seek operation and track follow operation of the magnetic head The drive current control of the voice coil motor necessary for the positioning control for moving the motor is performed by PWM drive.

  According to the above-described means, since the seek operation and the track follow operation are performed only by the PWM drive, the transition from the seek operation to the track follow operation and vice versa can be executed smoothly and quickly, resulting in a time loss. In addition, since it is not necessary to separately design a control circuit for PWM driving and a control circuit for linear driving, the design burden is reduced and the circuit scale is also reduced. Furthermore, since the PWM driving is less likely to cause characteristic deterioration due to hot carriers of the output MOS transistor than the linear driving, it is easy to adopt an inexpensive CMOS process, thereby reducing the cost.

  Here, preferably, the load operation control for moving the magnetic head from the retracted position onto the disk is also performed by PWM drive. Furthermore, it is preferable that the settling operation control when shifting from the seek operation to the track follow operation is also performed by PWM drive. Further, unloading operation control for moving the magnetic head from the disk to the retracted position can also be performed by PWM driving.

  In the second invention of the present application, the entire control circuit for feedback control of the voice coil motor is constituted by a digital circuit. Conventionally, since the control circuit of the voice coil motor has been constituted by an analog circuit, it is weak to external noise, easily causes an error due to offset, and is easily affected by manufacturing variations, so it is difficult to improve the control accuracy. However, these problems can be solved by configuring the entire control circuit with a digital circuit.

  Here, preferably, a ΣΔ (sigma delta) modulator is used as a modulation circuit for generating a signal for controlling the output driver from the difference signal between the current command value and the current detection value. When the control circuit is configured with a digital circuit, quantization noise becomes a problem, but the ΣΔ modulation circuit has the characteristic of diffusing the quantization noise into the high frequency region, so it is used in the low frequency region necessary for voice coil motor positioning control. Noise can be reduced and the S / N ratio can be improved. On the other hand, the increased noise in the high frequency region can be relatively easily suppressed by a filter (digital filter or the like).

  Another invention of the present application is to solve a new problem derived by configuring the entire control circuit of a voice coil motor with a digital circuit, and includes the following.

  First, noise in the high frequency region generated on the ΣΔ modulator side is usually removed by providing a filter, but a D / A conversion circuit (PWM pulse) that converts a control signal to an analog signal without providing a filter. In addition to noise generated in the generation circuit, etc., it is attenuated by averaging using a time constant (integration action) of the motor coil. Specifically, the output signal of the ΣΔ modulator is directly input to the D / A conversion circuit to generate a PWM pulse or a PAM pulse for controlling the output driver. This eliminates the need for the subsequent filter of the ΣΔ modulator and simplifies the entire control circuit.

  Here, preferably, a multi-bit quantizer is used instead of the 1-bit quantizer as the quantizer of the ΣΔ modulator. In order to increase the speed of the control circuit, it is better to use a 1-bit quantizer as the quantizer of the ΣΔ modulator. However, if a 1-bit quantizer is used, the linearity deteriorates due to the switching delay of the output drive circuit and the SN ratio is increased. Although deterioration or switching loss in the output drive circuit increases, by using a multi-bit quantizer, high-frequency noise diffusion can be concentrated in a frequency band lower than the PWM frequency, thereby improving the SN ratio, Switching loss in the output drive circuit can be reduced.

  Second, a phase compensator composed of an integral digital filter is provided in front of the ΣΔ modulator. Since the control circuit for the voice coil motor is a negative feedback loop, it is necessary to provide a phase compensator in order to stabilize the system and prevent oscillation. By providing a phase compensator before the ΣΔ modulator, the control circuit The whole can be simplified. That is, a predictor for oversampling to reduce quantization noise is required in the preceding stage of the ΣΔ modulator that operates at a frequency higher than the update frequency of the current command value. The circuit for performing phase compensation of the above is constituted by an integral type digital filter and provided in the previous stage of the ΣΔ modulator, so that it can also be used as a predictor, thereby eliminating the need for a separate predictor and simplifying the control circuit. it can. Further, since the time delay caused by the predictor can be reduced, the frequency band of the entire VCM driver circuit of the present invention can be improved.

  Here, desirably, the phase compensator is disposed in front of the ΣΔ modulator using a PI controller having an integration characteristic only in the low frequency region. Thereby, it is possible to give a differential characteristic to the transfer characteristic of the input conversion noise with respect to the output drive current of the quantization noise generated in the ΣΔ modulator and the subsequent D / A converter, which is the differential characteristic of the ΣΔ modulator. Therefore, the S / N ratio in the low frequency region is further improved. In addition, the S / N ratio in the low frequency region of the voice coil motor drive circuit can be determined with substantially the accuracy of the current detection stage, and the accuracy can be improved by using a ΣΔ modulation type A / D conversion circuit for the current detection stage. it can. Further, preferably, a register for setting the filter coefficient of the phase compensator is provided. As a result, the phase compensator can be set so as to obtain optimum characteristics according to the specifications of the applied magnetic disk storage device by changing the firmware.

  Thirdly, as the current detection stage, means for quantizing (AD conversion) after averaging the current flowing through the coil (including a current that reproduces the current) by an integration operation using a high-speed sample is used. Specifically, the current detection means is composed of a current detection amplifier and an A / D conversion circuit that converts an analog signal detected by the amplifier into a digital signal, and an oversampling A / D is used as the A / D conversion circuit. A conversion circuit is used. As a result, detection errors due to sampling pulse jitter are eliminated, and the average current can be detected when the duty ratio of the PWM pulse is small. In addition, since the sampling period for quantization can be set regardless of the PWM driving period, it is easy to improve the bandwidth of the entire voice coil motor driving circuit.

  Here, preferably, a ΣΔ modulation type A / D conversion circuit is used as an A / D conversion circuit for converting a detection signal into a digital signal. Thereby, since the quantization noise is diffused in the high frequency region, the noise in the low frequency region necessary for the positioning control of the voice coil motor can be reduced, and the SN ratio can be improved. Normally, a predictor for oversampling is required in the preceding stage of the ΣΔ AD modulation type A / D converter circuit. In the present invention, this is substituted by the integral characteristic of the coil of the voice coil motor, and the predictor is omitted. To do. That is, the detection signal output from the current detection amplifier is directly input to the A / D conversion circuit. This eliminates the need for a predictor and simplifies the entire control circuit.

  Desirably, a decimation filter having a low-pass and frequency thinning function is provided at the subsequent stage of the ΣΔ modulation type A / D conversion circuit. As a result, it is possible to suppress noise in the high-frequency region that increases due to the use of the ΣΔ modulation type A / D conversion circuit as the current detection means. Furthermore, desirably, a phase lead compensator is provided at the subsequent stage of the decimation filter. As a result, it is possible to prevent instability (gain peaking) of the entire voice coil motor drive circuit caused by the delay of this filter.

  Still another invention of the present application is that the entire control circuit of the voice coil motor is constituted by a digital circuit, and a ΣΔ modulator as a modulation circuit that generates a signal for controlling an output driver from a difference signal between a current command value and a current detection value And a counter electromotive force estimation circuit for estimating the counter electromotive voltage generated in the coil based on the output of the current detection means and the highly accurate drive voltage command signal that is the input of the ΣΔ modulator. Even if the back electromotive force voltage generated in the coil is not detected directly, if the power supply voltage of the voice coil motor drive circuit, the magnitude of the current flowing in the coil, and the drive voltage of the coil are known, the coil impedance model can be determined. However, since these parameters originally exist in the control circuit having the above configuration, they can be easily obtained by calculation. Therefore, it is not necessary to provide an amplifier or the like for detecting a complicated counter electromotive voltage, and the circuit scale can be reduced and the cost can be reduced.

  Still another invention of the present application relates to a driving current of a voice coil motor that moves a magnetic head for reading information on a storage track on a magnetic storage disk that is rotationally driven on the disk. In a voice coil motor drive circuit that moves the magnetic head by performing feedback control while detecting the drive current flowing in the coil, the magnetic head is moved based on command values from the controller such as seek operation and track follow operation of the magnetic head The current control is performed by PWM driving, and one of the driver circuit that drives one terminal of the coil and the driver circuit that drives the other terminal of the coil is PWM driven every 1/2 period of the PWM pulse, and the other The control signal of the driver circuit is fixed for the half cycle. In which was to so that.

  According to the above-described means, fluctuation unevenness of the drive current generated within one cycle of the PWM pulse can be reduced, so that noise generated by PWM drive can be reduced. Further, since a different current command value can be given every ½ cycle, it is possible to control the current more quickly than the conventional PWM drive method that gives a current command value every cycle.

  Still another invention of the present application is to detect a delay time of a signal for controlling a driver circuit by detecting a rise or fall timing of an output voltage of a driver circuit that drives a coil terminal of a voice coil motor drive circuit. A measurement circuit, a variable delay circuit that delays a signal that controls the driver circuit for an arbitrary time, and a negative feedback control loop that feeds back the time measured by the delay time measurement circuit to the variable delay circuit to change the delay time of the signal Is provided.

  As a result, it is possible to automatically adjust the deviation of the propagation delay time that occurs in the driver circuit due to manufacturing variations, temperature changes, and power supply voltage fluctuations, thereby preventing a decrease in linearity in PWM drive control. Here, the delay time measuring circuit may be provided as a common circuit for both the driver circuit that drives one terminal of the coil and the driver circuit that drives the other terminal of the coil, but is provided separately. As a result, more accurate PWM drive control is guaranteed.

  Still another invention of the present application is to detect a transition time of a driver circuit output signal by detecting a time required for a rise or fall of an output voltage of a driver circuit that drives a coil terminal of a voice coil motor drive circuit. Circuit, a slope adjustment circuit that arbitrarily sets the rate of change of the signal that controls the driver circuit, and a negative feedback control loop that feeds back the time measured by the transition time measurement circuit to the slope adjustment circuit to change the signal transition time Are provided.

  As a result, it is possible to automatically adjust the shift of the transition time that occurs in the driver circuit due to manufacturing variations, temperature changes, and power supply voltage fluctuations, and the transition time can be controlled with high precision. Thus, it is possible to prevent an error from occurring in position information and stored information due to noise combined with a signal read out by the head due to an abrupt change in the output signal of the driver circuit. Here, the transition time may be adjusted according to the value set in the register from an external controller by providing a register for setting the transition time, but is supplied from the controller to the voice coil motor drive circuit. The transition time can be adjusted in proportion to the command value based on the current command value.

  According to still another aspect of the present invention, the entire control circuit for performing feedback control of the voice coil motor is constituted by a digital circuit, and an offset that cancels an offset generated in the entire control system in the middle of a path for feeding back the detected coil current. A calibration circuit is provided. By configuring the entire control circuit with a digital circuit, it is possible to consolidate the offset calibration circuits required at various locations in the conventional analog control system into one location, thereby suppressing an increase in circuit scale. Can do. Here, when the circuit for converting the detected coil current into a digital signal includes a ΣΔ modulation type A / D conversion circuit and a decimation filter provided at the subsequent stage, an offset calibration circuit is provided at the subsequent stage of the decimation filter. Is desirable.

  Still another invention of the present application provides a coil current having a sense transistor having a predetermined size ratio that is provided in parallel with an output transistor of a driver circuit that supplies a drive current to a coil of a voice coil motor and that supplies a current proportional to the current of the output transistor. A current detection circuit having a reproduction circuit and a differential amplifier that amplifies a voltage drop generated by flowing the current reproduced by the coil current reproduction circuit through a sense resistor is provided. In the conventional voice coil motor drive circuit (Patent Document 1), since the voltage drop generated in the sense resistor connected in series with the motor coil is amplified by the error amplifier, the coil current is detected. Although power loss has occurred in the resistor, according to the present invention, a sense resistor connected in series with the motor coil is not required, and a separately reduced sense resistor is detected by flowing a current that is proportionally reduced in coil current. Power loss can be reduced.

  In the voice coil motor drive circuit described in Patent Document 1, the voltage divided by the resistor is input to the error amplifier that amplifies the voltage drop generated in the sense resistor. In the case of on-chip, if the resistance value has a bias dependency of the island potential, current detection error will occur, or if the ratio of the resistors used for resistance division cannot be matched due to manufacturing variation or local temperature rise, error amplifier However, according to the present invention, a resistance for dividing the input voltage to the error amplifier is not necessary, so that the detection error is reduced. Will be able to.

  Here, preferably, a current addition circuit that constantly flows an offset current so that a forward current flows in the sense transistor even when a reverse current flows in the output transistor during power regeneration of PWM drive, An offset current cancel circuit for preventing the offset current from being added to the detection current is provided. Furthermore, desirably, a determination circuit for determining the state when the state of the output transistor to be detected by current is not in the ON resistance region and a correct current cannot be reproduced by the current reproduction circuit, and a holding means capable of holding the detection current; In the meantime, the immediately preceding detection current is held. This avoids erroneous current detection and enables more accurate current detection.

  Still another invention of the present application is provided with a power supply voltage detection circuit for detecting a power supply voltage of a voice coil motor drive circuit, and a duty ratio of a drive control signal (PWM drive pulse) or a drive voltage according to a deviation amount compared to a reference voltage. The output voltage value is changed. Thereby, the error current of the coil caused by the fluctuation of the power supply voltage can be reduced. Here, when the signal for changing the duty ratio or output voltage value of the PWM drive pulse is formed by the ΣΔ modulator, multiplication that functions as a variable gain amplifier at the input of the ΣΔ modulator. It is preferable to provide a multiplier and to operate the multiplier so that the gain of the amplifier is inversely proportional to the change in the power supply voltage.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to obtain a coil motor drive control semiconductor integrated circuit capable of highly accurate drive control.

1 is a block diagram showing an outline of a magnetic disk storage device to which the present invention is applied. It is a block diagram which shows the structural example of the voice coil motor drive circuit which comprises the magnetic disc memory | storage device to which this invention is applied. It is explanatory drawing which represented the voice coil motor drive circuit and voice coil motor shown in FIG. 2 with the transfer function. It is a block diagram which shows the specific example of the decimation filter which comprises the voice coil motor drive circuit of an Example. It is a characteristic view which shows the frequency characteristic of a decimation filter. It is a characteristic view which shows the frequency-gain characteristic of the motor drive circuit of an Example. It is a block diagram which shows the equivalent circuit of the digital filter which comprises the phase advance compensation part PGC and the phase compensation circuit 223. It is a timing chart which shows the operation example in the motor drive circuit of an Example. FIG. 6 is a characteristic diagram showing an error current ΔIadc generated in the current detection stage of the voice coil motor drive circuit of the embodiment, an error current ΔIout generated in the output stage, and an error current ΔIvcm of the entire circuit. It is a block diagram which shows the specific example of the output driver which comprises the voice coil motor drive circuit of an Example, and an output control circuit. It is a timing chart which shows the operation example of the output driver of the voice coil motor drive circuit of an Example. FIG. 3 is an enlarged explanatory view showing a configuration example of a cable connecting a head side and a control device side in a magnetic disk storage device to which the present invention is applied. It is a wave form diagram which shows the influence of the signal transmitted with a cable. It is a timing chart which shows the operation example of the current detection circuit in the voice coil motor drive circuit of the form which the present inventor considered and examined previously, and the current detection circuit with which the voice coil motor drive circuit of an Example is equipped. It is a block diagram which shows the specific example of the electric current detection circuit in the voice coil motor drive circuit of an Example. It is a timing chart which shows the operation example of the current detection circuit of an Example. It is a timing chart which shows the operation example in another state of the current detection circuit of an Example. It is a wave form diagram which shows the output voltage waveform when the direction of the electric current of the coil in the current detection circuit of an Example and the polarity of a drive voltage correspond, and when it does not correspond. It is a circuit diagram which shows the specific example of the error amplifier with a hold function provided in a current detection circuit. It is a logic block diagram which shows the specific example of a dead time determination circuit. It is a block diagram which shows the other structural example of the voice coil motor drive circuit which comprises the magnetic disc memory | storage device to which this invention is applied. The relationship between the input command value and the drive pulse in the motor drive circuit of the embodiment of FIG. 21 in the PAM modulation control is compared with the relationship between the input command value and the drive pulse in the motor drive circuit of the embodiment of the PWM modulation control in FIG. It is a timing chart shown.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an outline of a magnetic disk storage device to which the technique of the present invention is applied.

  The magnetic disk storage device shown in FIG. 1 includes a magnetic storage disk 100, a spindle motor 102 that rotationally drives the magnetic storage disk 100, and a magnetic head that reads / writes information from / to a storage track on the magnetic storage disk 100. 104, including a write magnetic head and a read magnetic head), an arm 106 having the magnetic head 104 at the tip, a voice coil motor 108 that rotates the arm 106 to move the magnetic head 104 in the radial direction on the disk 100, A motor drive circuit 200 for driving the voice coil motor 108, a signal processing circuit (signal processing IC) 110 for reading position information from a read signal of the magnetic head 104, and the motor based on the position information read by the signal processing circuit 110. The drive circuit 200 has a drive current command value Ic A control unit 300 for sending md is included.

  Here, the control unit 300 includes a microcomputer (CPU) 310 that controls the operation of the entire magnetic disk storage device, a position command (target track position information) from the microcomputer 310, and a head position from the signal processing circuit 110. The controller 320 generates a drive current command value Icmd composed of, for example, a 16-bit binary code based on the information. The drive current command value Icmd generated by the controller 320 is sent to the motor drive circuit 200 in the form of 2's complement or offset binary so that the direction of current flow can be specified. Although the motor drive circuit 200 is not particularly limited, in this embodiment, it is formed as a semiconductor integrated circuit on one semiconductor chip such as single crystal silicon.

  FIG. 2 shows the configuration of a motor drive circuit 200 that controls the drive of the voice coil motor 108.

  As shown in FIG. 2, the motor drive circuit 200 is a current proportional to the current flowing in the serial port 201 for serially transmitting / receiving data to / from the controller 320 and the coil LVCM of the voice coil motor VCM. A differential amplifier (hereinafter referred to as a current detection amplifier) 202 for detecting a voltage generated at both ends of a sense resistor Rsns through which a current flows, and an output for applying a desired voltage by applying a drive voltage to both terminals of the coil LVCM A current detection control circuit 203 for controlling the current proportional to the current output from the drivers 211 and 212 to flow through the sense resistor Rsns, the drive current command value Icmd received from the controller 320 via the serial port 201, and the current The driver 21 is based on the output voltage Vsns proportional to the drive current Ivcm detected by the detection amplifier 202. , 212 for generating a drive control signal, an offset calibration circuit 204 for calibrating an offset generated in the control circuit 220, and voltage dividing resistors R1, R2 for detecting the voltage value of the power supply voltage VDD And an AD conversion circuit 205, a back electromotive voltage estimation circuit 206 that calculates a back electromotive voltage Vb-emf (estimated value) of the coil based on a signal in the digital control circuit 220, and supplies it to the controller 320 as speed information. It is configured. The circuit blocks and elements shown in FIG. 2 are formed into a semiconductor integrated circuit except for the voice coil motor VCM and the sense resistor Rsns.

The counter electromotive voltage estimation circuit 206 sets the output of a multiplier VGA in the modulation circuit 224, which will be described later, as CNT, the coil current as Ivcm, the coil parasitic resistance as RL, and the reference value of the power supply voltage VDD of the control circuit as VDD0. Vb-emf = Vout−Ivcm · RL
Vout = (2 / CNT) ・ VDD0
Thus, the counter electromotive voltage Vb-emf can be easily calculated. Therefore, the counter electromotive voltage estimation circuit 206 can be constituted by a register for holding the RL value or the VDD0 value, a multiplier, and an adder / subtracter, and a complicated counter electromotive voltage detection circuit as in the conventional analog control system is not required. .

  The counter electromotive voltage Vb-emf calculated by the counter electromotive voltage estimation circuit 206 can be sent to the controller 320 via the serial port 201. The controller 320 can recognize the moving speed of the head from the received back electromotive voltage. For example, the controller 320 can be used to control the speed of the voice coil motor when the head is loaded to move the magnetic head from the retracted position called a ramp onto the disk. it can. If the moving speed of the magnetic head is too high, the magnetic head may come into contact with the disk surface and damage it, but this speed control can avoid this.

  The digital control circuit 220 includes an A / D conversion circuit 221 that converts the output signal of the differential amplifier 202 into a digital signal, a decimation filter 222 provided in the subsequent stage, and a detected current value output from the decimation filter 222. A phase compensation circuit 223 that performs an operation for phase compensation on the difference from the drive current command value Icmd sent from the controller 320, and the phase compensated current value of a predetermined number of bits (7 bits in the embodiment). Modulation circuit 224 for converting to control code signal FCNT, and PWM pulse generation as D / A conversion means for generating drive control signals for the VCM drivers 211 and 212 based on the output signal of the modulation circuit 224 and its sign inversion signal It consists of circuits 225, 226 and the like.

  In this embodiment, the decimation filter 222 and the phase compensation circuit 223 have low-pass filter characteristics, and both are constituted by digital filters. The PWM pulse generation circuits 225 and 226 can be constituted by a counter and a comparator. The modulation circuit 224 gives the count values FCNT and -FCNT corresponding to the pulse width of the output drive signal to the PWM pulse generation circuits 225 and 226 from the current command value and the current measurement value, and the PWM pulse generation circuits 225 and 226 The drive control signals (PWM drive pulses) PL1 and PL2 are generated and output so that the drivers 211 and 212 output the drive voltages VCMP and VCMN having a duty ratio corresponding to the count value. To do. In this embodiment, a 7-bit quantizer is used as the quantizer QTZ in the output section of the modulation circuit 224, so that noise is optimized by PWM driving while appropriately maintaining the switching loss of the output stage. .

  The digital control circuit 220 is provided with registers 227 and 228 for holding coefficients necessary for calculation in the decimation filter (222) and the phase compensator (223), respectively. Is configured so that a value sent from the controller 320 at the time of initialization (initialization) or the like is set and held. The offset calibration circuit 204, when a signal for setting the output amplifiers 211 and 212 in the high impedance state is given from the controller 320 at initialization, a value generated by the offset of the entire current detection circuit is used as an offset cancellation value ACQ of the current detection system. The register 229 is configured to be set.

  In this embodiment, a secondary ΣΔ modulation type A / D conversion circuit (hereinafter referred to as a ΣΔ type A / D conversion circuit), which is a kind of oversampling type A / D converter, is used as the A / D conversion circuit 221. In addition, a second-order ΣΔ modulation circuit is used as the modulation circuit 224. The ΣΔ A / D conversion circuit 221 is provided with a 2-bit A / D converter ADC1 for generating a digital output signal and a 2-bit D / A converter DAC1 for generating an analog feedback signal at an output unit, and has a frequency of 25 MHz. It is operated in synchronization with the sampling clock φs having the frequency The ΣΔ modulation circuit 224 has a multiplier functioning as a variable gain amplifier VGA at the input section and a 7-bit quantizer QTZ at the output section, corresponding to a PWM control period (390 kHz), ½ of that It is configured to operate in synchronization with a clock φ1 having a frequency such as 780 kHz.

  The gain Kr of the variable gain amplifier VGA at the input of the ΣΔ modulation circuit 224 is the ratio VDD0 / VDDS · (1+) between the detected power supply voltage VDDS output from the A / D conversion circuit 205 and the reference value VDD0 of the power supply voltage VDD R1 / R2). Since the voltages VCMP and VCMN output from the drivers 211 and 212 by PWM driving are proportional to the power supply voltage VDD, fluctuations in the power supply voltage VDD become distortions in the output voltage and deteriorate the PSRR (Power Supply Rejection Ratio). Therefore, in this embodiment, an A / D conversion circuit 204 for detecting the power supply voltage VDD is provided, and a multiplier functioning as a variable gain amplifier VGA is provided at the input of the ΣΔ modulation circuit 224, and the gain Kr of the amplifier is set. High PSRR is achieved by controlling the power supply voltage VDD to be inversely proportional to the change in the power supply voltage VDD.

  As described above, in the motor drive circuit of the present embodiment, the ΣΔ A / D conversion circuit and the ΣΔ modulation circuit are used because the noise is diffused in the high frequency region which is a feature of the ΣΔ circuit. This is because a characteristic called noise shaping (noise shaping) that can reduce the noise in the region is used. That is, the control circuit of the voice coil motor drive circuit has a control band of several tens of kHz or less and is relatively low. Therefore, by using the ΣΔ circuit, noise in the low frequency region is reduced and control accuracy is increased. Then, the noise in the high frequency region, which increases as the noise in the low frequency region decreases, is suppressed by providing a decimation filter 222 that functions as a low-pass filter after the ΣΔ A / D conversion circuit 211.

  By the way, conventionally, various types of A / D conversion circuits such as a successive approximation type and an oversample type have been developed. In general, when an analog input signal is converted into a digital signal by an A / D conversion circuit, an S / N (Signal to Noise Ratio) characteristic near the signal frequency can be improved by increasing the sampling frequency. The oversampled A / D converter circuit is a system in which the S / N characteristic is improved by increasing the oversample ratio.

  The oversampled A / D conversion circuit can be roughly classified into a Δ modulation method, a ΣΔ modulation method, and a mixed method thereof. Of these, the ΣΔ modulation method integrates the difference between the output signal and the input signal with an integrator, and performs feedback control so that the output of the integrator is minimized. In this ΣΔ modulation method, the S / N characteristic can be further improved by increasing the order of integration, that is, the number of integrators. That is, every time the integration order is increased by one, a noise shaping characteristic proportional to the frequency can be expected. However, when the order of integration is increased, there are problems that the stability of the system is lowered and the power consumption is increased. In this embodiment, the ΣΔ A / D conversion circuit 221 and the ΣΔ modulation circuit 224 are secondary circuits.

  The present inventors have incorporated conversion accuracy and conversion speed as an A / D conversion circuit that is incorporated in a voice coil motor driving IC and converts an output signal of a sense amplifier 202 that detects a coil current into a digital signal and feeds it back. From this point of view, it was considered that an oversampling A / D converter circuit, particularly, a ΣΔ modulation type A / D converter circuit was suitable. When the ΣΔ modulation method is used, the quantization bit is more effective due to the effect of noise shaping characteristics than when a successive approximation method well known as a normal 16-bit A / D conversion circuit or an oversampling method that does not use a noise shaper is applied. The circuit can be simplified by reducing the number, and there is an advantage that high accuracy can be realized stably without calibration of the cell with respect to manufacturing variations of current cells and the like.

  Another reason for using the ΣΔ modulation method, which is a kind of oversampling A / D conversion circuit, as a circuit for digitally converting a signal that detects the current Ivcm flowing through the coil in this current detection is shorter than the PWM drive cycle. This is because the current detection error can be made smaller by sampling the detection signal at a period than when a normal 16-bit A / D conversion circuit is used.

  That is, when a normal 16-bit A / D converter circuit is used, for example, as shown in FIGS. 14A to 14C, the coil current Ivcm at the center of the PWM pulse is sampled to be a representative value. However, since the sampling clock φs used for this is usually generated by a VCO (Voltage Controlled Oscillator) or the like, it often has jitter as shown by a broken line, and as shown in FIG. As described above, the error ΔI may occur in the detection current Isns. Also, in the above-described invention of the analog control system of Patent Document 1, a system is adopted in which the coil current Ivcm at the center point of the PWM pulse is sampled to obtain a representative value and the difference from the current command value (see Patent Document 1). For this reason, a similar detection current error ΔI may occur.

  In contrast, in the voice coil motor drive circuit of this embodiment, an oversampling A / D conversion circuit is used as a circuit for digitally converting the detection signal of the coil current Ivcm, and the detection signal is shorter than the PWM drive cycle. As shown in FIG. 14E, the current detection error due to the clock jitter can be ignored in principle because the sampling is performed and smoothing is performed by the integration function of the ΣΔ A / D conversion circuit.

  Since the configurations and operations of the ΣΔ A / D converter circuit and the ΣΔ modulator circuit are known, detailed description thereof will be omitted. The output A / D converter ADC1 and the feedback D / A converter DAC1 of the ΣΔ A / D conversion circuit 221 are set to 2 bits in order to reduce noise in the low frequency region and suppress an increase in circuit scale.

  Normally, a predictor (interpolation process) for performing oversampling is required upstream of the ΣΔ modulator, but in this embodiment, a phase compensation circuit 223 that performs phase compensation of the entire motor drive circuit is integrated in the integrator. This is substituted as a predictor of the ΣΔ modulation circuit 224. Moreover, since the integral characteristic of the coil at the time of PWM drive works as a predictor on the A / D conversion circuit 221 side for current detection, the predictor is omitted by substituting the coil as a predictor.

  The phase compensation circuit 223 is a circuit provided for compensating the first order lag characteristic of the coil impedance of the voice coil motor, keeping the entire system at the first order lag, and improving the S / N ratio of the output stage. As can be seen from the transfer function shown in the block of the phase compensation circuit 223 in FIG. 2, in this embodiment, the phase compensation circuit 223 is constituted by an integrator. “s” is a variable used to represent a Laplace transformed function.

  In this embodiment, the phase compensation circuit 223 that performs phase compensation of the feedback loop of the entire voice coil motor drive circuit is a PI controller having an integral characteristic in the low frequency region and a proportional characteristic in the high frequency region, and a ΣΔ type By disposing it before the modulation circuit 224, the transfer characteristic of the input conversion noise with respect to the output drive current of the quantization noise generated by the modulator (quantizer) has a differential characteristic.

  Thereby, the differential characteristic is added to the differential characteristic of the ΣΔ modulation circuit 224, so that the SN ratio in the low frequency region is further improved, and the SN ratio in the low frequency region of the voice coil motor driving circuit 200 of this embodiment is It is determined with the accuracy of the current detection stage (A / D conversion circuit 221). However, in this embodiment, since the ΣΔ A / D conversion circuit 221 having a noise shaping effect is used as the current detection stage, the SN ratio of the entire circuit can be reduced.

  FIG. 9 shows an error current ΔIadc generated in the current detection stage of the voice coil motor drive circuit 200 of the present embodiment, an error current ΔIout generated in the output stage (phase compensation circuit, modulation circuit, and PWM generation circuit), a circuit The total error current ΔIvcm is shown. From the figure, the error current ΔIadc generated in the current detection stage is larger than the error current ΔIout generated in the output stage, but the error current ΔIvcm of the entire circuit is slightly larger than the error current ΔIadc generated in the current detection stage. I understand that. In FIG. 9, ΔIvcmo is an error current of an ideal 16-bit D / A converter having a band of 40 kHz. Further, all error current values shown in FIG. 9 are normalized by ΔIvcmo (at f <fvcm).

  Note that the theoretical S / N ratio of the current detection stage of the present embodiment can be approximated by the following equation (1).

Where n: ΣΔ modulation order N: ΣΔ modulation quantization bit number
ovsa: Oversampling ratio (= fadc / 2fvcm)
fadc: Sampling rate [Hz] of ADC for current detection
fvcm: VCM driver bandwidth [Hz] of this embodiment
It is assumed that the input signal (current command value Icmd) is band-limited to fvcm (that is, the Nyquist frequency is assumed to be fvcm).

  FIG. 3 shows the voice coil motor VCM and the motor drive circuit 200 of the embodiment of FIG. In FIG. 3, “Ksens” is the gain of the differential amplifier 202, “Kadc” is the gain of the A / D conversion circuit 221, “QNadc” is the quantization noise in the A / D conversion circuit 221, and “QNout” is the PWM modulation. Quantization noise, “VDD0” is a reference for the power supply voltage, FCNT is a count value to be counted by the PWM pulse generation circuit 225, 226, and this count value is given from the ΣΔ modulation circuit 224 to the PWM pulse generation circuit 225, 226 It is done.

  FIG. 4 shows a specific example of the decimation filter 222 in the motor drive circuit 200 of the embodiment of FIG.

  The decimation filter of this embodiment has N (for example, N = 16) delay stages DLY and an adder ADD, and has FIR (finite impulse response) filters FIR1 and FIR2 having a filter coefficient of “1” and their outputs. FIR having a low-pass filter unit LPF in which averaging circuits AVR1 and AVR2 for averaging are cascade-connected, M delay stages DLY and an adder ADD (for example, M = 32), and a filter coefficient of “1” A decimation processing unit ELM in which a filter FIR3 and an averaging circuit AVR3 that averages the outputs thereof, and a decimation circuit (M: 1) that extracts and outputs every M pieces of data of the averaging circuit AVR3, are cascaded; It consists of a phase lead compensation unit PGC.

  The phase lead compensation unit PGC is composed of a digital filter that performs an operation represented by a transfer function of (1 + S1 / ωd) / (1 + S1 / m · ωd), and is set so that the numerator becomes larger. Phase advance can be increased. Here, ωd is represented by ωd = 3 × 2 · π · fvcm, where fvcm is the frequency band of the voice coil motor. The reason why the phase lead compensation unit PGC is provided is to suppress an increase in gain near 50 kHz in the frequency-gain characteristic of the motor drive circuit 200. The reason will be described below.

  FIG. 5 shows the frequency characteristics of the decimation filter, and FIG. 6 shows the frequency-gain characteristics of the motor drive circuit 200 of the embodiment. When a decimation filter without a phase lead compensation unit PGC is used, a delay occurs because the digital filter has a low-pass filter characteristic, and the frequency characteristics of gain and group delay time are shown by dotted lines A1 and A2 in FIG. As a result, gain peaking occurs in the frequency characteristic of the motor drive circuit 200 in the vicinity of 50 kHz as indicated by a dotted line A0 in FIG.

  On the other hand, when the decimation filter provided with the phase lead compensation unit PGC is used, the characteristics shown by solid lines B1 and B2 in FIG. 5 are obtained, and thus the frequency characteristics of the motor drive circuit 200 are as shown by the solid line B0 in FIG. In addition, there is no gain peaking.

  Here, the phase lead compensation unit PGC and the phase compensation circuit 223 can be constituted by a digital filter composed of an equivalent circuit as shown in FIG. 7, and its transfer characteristic is Ki ′ = (1 + bz−1). / (1-az-1). The PI-type controller is represented by an expression Ki / s + Kp including a term of Ki and a term of Kp.

Ki / s + Kp = Ki / s (1 + Kp · s / Ki)
= Ki / s (1 + s · Kp / Ki)
It can be deformed. It can be seen that this equation has the same form as the equation Ki / s (1 + s · L / RL) written inside the block of the phase compensation circuit 223 of FIG. The phase compensation circuit 223 of the motor drive circuit of the embodiment of FIG. 2 has parameters in FIG. 7 so that Ki / s (1 + s · Kp / Ki) and Ki / s (1 + s · L / RL) are the same. “K”, “a”, and “b” are designed.

  Next, the PWM pulse generation circuits 225 and 226 in the motor drive circuit of this embodiment will be described. The PWM pulse generation circuits 225 and 226 are circuits each composed of a counter and a comparator, and correspond to a triangular wave generation circuit in an analog drive control circuit. The count values FCNT and -FCNT of the PWM pulse generation circuits 225 and 226 are given as a 7-bit binary code designating the pulse width from the ΣΔ modulation circuit 224, and output when the count value is reached by the count operation with the 50 MHz clock φ0. Is configured to change.

  In addition, in this embodiment, the 7-bit count value is given from the ΣΔ modulation circuit 224 to the PWM pulse generation circuits 225 and 226 at a cycle of 780 kHz, while the PWM pulse generation circuits 225 and 226 have the count values FCNT and −FCNT. The counter is configured so that a fixed value of high or low output is continuously output. The operation of the PWM pulse generation circuits 225 and 226 will be described with reference to FIG.

  In FIG. 8, PWMCNT is a count value of a virtual counter that counts up from “0” at a clock φ0 of 50 MHz simultaneously with an input command of count values FCNT and −FCNT, and PL1 is supplied from the PWM pulse generation circuit 225 to the output driver 211. Drive control signal (PWM drive pulse), PL2 is a drive control signal (PWM drive pulse) supplied from the PWM pulse generation circuit 226 to the output driver 212, and PL1 and PL2 are output from the drivers 211 and 212, and Both ends of the coil are PWM driven. The drive voltages VCMP and VCMN across the motor switch between the GND level and the power supply voltage VDD in synchronization with PL1 and PL2, respectively. VCMP-VCMN is a voltage applied between both terminals of the motor coil.

  As can be seen from FIG. 8, in the present embodiment, the PWM drive pulses PL1 and PL2 are held at a high level or a low level alternately every half cycle, that is, half of the cycle is fixed. As shown in the lower half of FIG. 8, the operation of the counter in PWM drive is such that the pulses PL1 and PL2 are at a high level only during a period corresponding to the input command value during one cycle. However, as in this embodiment, one of the pulses is fixed in the half cycle, and only the other pulse is controlled by the input command value, so that the value of the coil terminal voltage VCMP-VCMN is changed to the PWM drive pulse. It can be updated every half cycle of PL1 and PL2. This has the advantage of increasing the apparent resolution of PWM modulation and increasing the current control accuracy. Whether PL1 or PL2 is fixed is determined by checking the polarity of the FCNT and whether the PWMCNT is in the first half count or the second half count.

  In this embodiment, the output levels of the pulses PL1 and PL2 are made up of sections that match and sections that do not match, and the timing at which the counter value is updated is arranged in the order of the mismatch section and the matching section. As a result, the ripple current of the drive current due to PWM becomes smaller and the highly accurate control becomes possible at the time of track follow where the absolute value of the FCNT value becomes smaller. Further, in this embodiment, when FCNT = 0, the polarity of PL1 and PL2 is switched at the timing of Duty = 50%, so that no zero cross distortion is generated due to the delay time and transition time of the output drive stage.

  More specific function definitions of PL1 and PL2 of the Xbit modulator in the present embodiment described above are as follows.

(i) When FCNT (PL1 indication value) = -FCNT (PL2 indication value) = 0 input
If 0 <= PWMCNT <[2 ^ (X-1)]-1 then PL1 = H, PL2 = H
If [2 ^ (X-1)] <PWMCNT <= [2 ^ X] -1 then PL1 = L, PL2 = L
(ii) FCNT = + N, -FCNT = -N (0 <N = <2 ^ (X-1) -1)
If 0 <= PWMCNT <N-1 then PL1 = H, PL2 = L
If N <= PWMCNT <[2 ^ (X-1)]-1 then PL1 = H, PL2 = H
If [2 ^ (X-1)] <PWMCNT <[2 ^ (X-1)] + N-1 then PL1 = H, PL2 = L
If [2 ^ (X-1)] + N <PWMCNT <= [2 ^ X] -1 then PL1 = L, PL2 = L
(iii) FCNT = -N, -FCNT = + N (0 <N = <2 ^ (X-1) -1)
If 0 <= PWMCNT <N-1 then PL1 = L, PL2 = H
If N <= PWMCNT <[2 ^ (X-1)]-1 then PL1 = H, PL2 = H
If [2 ^ (X-1)] <PWMCNT <[2 ^ (X-1)] + N-1 then PL1 = L, PL2 = H
If [2 ^ (X-1)] + N <PWMCN <= [2 ^ X] -1 then PL1 = L, PL2 = L

  Next, specific examples and operations of the output drivers 211 and 212 having the current detection circuit in the motor drive circuit of this embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 shows the configuration of the P-side driver 211 among the output drivers 211 and 212. Since the output driver 212 has the same configuration as 211, the illustration and description thereof are omitted.

  The output driver 211 of this embodiment includes a waveform adjustment unit 231 that adjusts based on the switching timing of the drive pulse PL1 supplied from the PWM pulse generation circuit 225 and the control signal supplied from the output control circuit 203, and an output drive unit 232. The output control circuit 203 also includes a measuring unit 233 that detects the delay time and transition time of the output voltage VCMP from the power supply voltage VDD and the output voltage VCMP of the output driver 211, and the controller 320 via the serial port (SIO) 201. A register unit 234 that holds the received control information; a control signal generation unit 235 that generates a control signal for the waveform adjustment unit 231 based on the control information held in the register unit 234 and the detection signal from the measurement unit 233; Consists of.

  As shown in FIG. 10, the output driver 232 of the output driver is connected in series between the power supply voltage terminal VDD and the ground point, and applies a drive voltage VCMP to one terminal of the coil to flow current. Output MOS transistors M11 and M21, differential amplifiers AMP1 and AMP2 that drive the gate terminals of M11 and M21, a signal from the waveform adjusting unit 231 and a voltage obtained by dividing the output voltage VCMP by resistors R9 and R10 are input. And a voltage input-current output type differential amplifier circuit (hereinafter referred to as a gm amplifier) AMP0 for generating input signals of the coil drive differential amplifiers AMP1 and AMP2.

  Further, the differential amplifiers AMP1 and AMP2 apply their output voltages, that is, voltages obtained by dividing the output MOS transistors M11 and M21 and the gate voltages of M11 and M21 by resistors R4 and R5 or R7 and R8, respectively, to the inverting input terminal. Has been. Regarding the drive circuit of the output driver having such a configuration, a similar circuit technique is disclosed in Japanese Patent Application Laid-Open No. 2003-52194 and is not the gist of the present invention.

  The measurement unit 233 includes a voltage comparator CMP1 that receives the output voltage VCMP of the output drive unit 232 and a reference potential slightly lower than the power supply voltage VDD, and a reference potential slightly higher than the output voltage VCMP of the output drive unit 232 and the ground potential GND. The delay time Td (see FIG. 11) of the output voltage VCMP is detected from the voltage comparator CMP2 having the inputs of the output, the output DLY1 of the voltage comparator CMP1, the output DLY2 of the voltage comparator CMP2, and the PWM drive pulse PL1 (PL2). And a counter CNT2 for detecting the transition time Ts of the output voltage VCMP from the output DLY1 of the voltage comparator CMP1 and the output DLY2 of the voltage comparator CMP2.

  The control signal generation unit 235 includes subtracters or digital comparators SUB1 and SUB2 that take the difference between the control information held in the register unit 234 and the detection signal from the measurement unit 233, and control codes CC1 and CC2 corresponding to the difference. Are generated from the compensators CPS1 and CPS2 and the like. The compensators CPS1 and CPS2 are constituted by digital filters.

  The waveform adjustment unit 231 is provided in series with a delay counter DLC that delays the PWM drive pulse PL1 according to the control code CC1 from the compensator CPS1, a pair of constant current sources I1 and I2 connected in series, and these. The switches SW1 and SW2 and the capacitive element C3 connected between the coupling node N1 of the current sources I1 and I2 and the ground point are included. The current sources I1 and I2 are configured such that the current value is changed according to the control code CC2 from the compensator CPS2 of the control signal generator 235. The switches SW1 and SW2 are controlled so that either one is turned on. When the switch SW1 is turned on, the capacitor C3 is charged by the current source I1, the output voltage PL1 ′ is increased, and the switch SW2 is turned on. Then, the capacitive element C3 is discharged by the current source I2, and the output voltage PL1 ′ decreases. The speed of change is controlled by the current values of the current sources I1 and I2, thereby adjusting the output change speed (slope), that is, the transition time.

  Thus, in the output driver 211 (212) of the present embodiment, the waveform is based on the switching timing of the drive pulse PL1 (PL2) supplied from the PWM pulse generation circuit 225 (226) and the measurement result by the measurement unit 233. It is controlled by the adjusting unit 231 and feedback is applied so that the measured value matches the set value from the controller. Therefore, as shown in FIG. 11, the delay time Td and the transition time Ts gradually converge to the set value. In this embodiment, the change rate (slope) of the output is controlled by switching the current values of the current sources I1 and I2, but the slew rate adjustment circuit composed of SW1, SW2, I1 and I2 is omitted. The transition time Ts may be adjusted by directly controlling the slew rate of the gm amplifier AMP0.

  Applying the output driver 211 (212) of this embodiment has the following advantages.

  As shown in FIG. 1, in the magnetic disk storage device, a read / write IC mounted between the voice coil motor 108 and the motor driving IC (200) and on the arm 106 that supports the head 104. And a signal processing IC (110) are connected by a signal line. This connection is generally made by a flexible printed wiring cable called FPC (see FIG. 12), and is connected to each component by being branched in the middle. Therefore, in this cable, the wiring connecting the voice coil motor 108 and the motor driving IC (200) and the wiring connecting the read / write IC and the signal processing IC (110) are adjacent to each other. Will be provided.

  The head positioning signal read by the magnetic head 104 is amplified by a preamplifier in the read / write IC on the arm 106 and supplied to the signal processing circuit 110 via the signal line 411 of the flexible cable 400. Further, the drive voltages (VCMP and VCMN) are supplied from the motor drive circuit 200 having the output driver of this embodiment to the voice coil motor 108 through the signal lines 431 and 432 of the same cable. Therefore, for example, as shown in FIG. 12, the floating noises Cs1 and Cs2 existing between the signal lines 411 and 431 and 432 of the flexible cable (FPC) 400 cause the switching noise of the voice coil motor drive voltages VCMP and VCMN. There is a possibility that the positioning control accuracy is deteriorated by coupling to the position signal.

  Since high-speed operation is required during head seek of the magnetic disk, the drive current Ivcm of the voice coil motor is large (up to about 2 A), but the read accuracy of the position signal is relatively less severe than the track follow. On the other hand, when the head track follows, the drive current Ivcm of the voice coil motor itself is small (about several tens of mA), but the positioning signal readout accuracy is severe to maintain the on-track state. Further, since the positioning signal and the read data signal are alternately output in time series on the same wiring during the track follow, the superposition of this coupling noise causes the error rate of the read signal to deteriorate. Furthermore, if the coil drive voltages VCMP and VCMN change simultaneously in the same direction, noise coupled to the position signal may be further increased.

  Therefore, in this embodiment, as shown in FIG. 13, when the head seek has a large current command value Icmd, priority is given to the reduction of switching loss, so the change speed (slope) of the coil drive voltages VCMP and VCMN of the voice coil motor is steep. In order to prioritize coupling noise suppression during track follow with a small current command value Icmd, the change speeds (slopes) of the drive voltages VCMP and VCMN of the voice coil motor are made gentle. By switching the slope, it is possible to realize a practical VCM driver capable of reducing the generation of coupling noise in the cable while suppressing an increase in power consumption of the apparatus. Note that switching of the slope of the drive voltage during head seek and track follow may be determined according to the magnitude of the absolute value of the drive current instruction value Icmd of the voice coil motor, or a mode switching signal of the positioning control system You may make it carry out using.

  Next, an embodiment of a current detection circuit that detects a current flowing in the coil of the voice coil motor will be described. The voice coil motor drive circuit of the embodiment of FIG. 1 can be monitored by detecting a voltage drop caused by a sense resistor connected in series with the motor coil in the same manner as the conventional drive circuit. In the present embodiment, the current flowing through the output MOS transistors (M11, M21, etc. in FIG. 10) of the drivers 211 and 212 is reproduced by a current mirror method, and the reproduced current is provided for sensing independent of the motor coil. A coil current detection circuit is provided in the drivers 211 and 212 so as to monitor the voltage drop caused by the resistance flowing through the resistor.

  FIG. 15 shows a specific circuit example of the coil current detection circuit.

  FIG. 15 shows an H-bridge type motor circuit that is driven by supplying current to the coil Lvcm from the output MOSs M11, M21, M31, and M41. The symbol Lvcm is attached to the coil of the voice coil motor, and RL is the coil. The parasitic resistance component is shown, not the sense resistor Rsns. FIG. 15 does not show the sense resistor Rsns. The gm amplifier AMP0 and the error amplifiers AMP1 and AMP2 shown in FIG. 10 are also not shown in FIG. In FIG. 15, the current detection circuit corresponding to the upper (P side) driver 211 is shown on the right side of the coil Lvcm, and the lower (N side) driver 212 is shown on the left side of the coil Lvcm. Is a current detection circuit corresponding to.

  The MOS transistors M11 and M21 whose drain terminals are connected to one terminal (right side in the figure) of the coil Lvcm are the output MOS transistors of the upper (P side) driver 211, and the gates of these output MOS transistors M11 and M21 are , Driven by the output voltages VCMPU and VCMPL of the differential amplifiers AMP1 and AMP2 in FIG. M31 and M41 are output MOS transistors of the lower (N-side) driver 212. The gates of these output MOS transistors M31 and M41 are driver error amplifiers (AMP1) configured similarly to the driver of FIG. , Corresponding to AMP2) and output voltage VCMNU, VCMNL.

  The coil current detection circuit of this embodiment is provided in parallel with each of the output MOS transistors M11, M21, M31, M41 and has the same voltage as the voltages VCMPU, VCMPL, VCMNU, VCMNL applied to their gate terminals. MOS transistors M12, M22, M32, and M42 that are applied to the terminals and monitor the drain current are provided. M11 and M12, M21 and M22, M31 and M32, and M41 and M42 each have a size (gate width) of m: 1. Thus, a drain current having a magnitude of 1 / m of the drain current flowing through M11, M21, M31, and M41 flows through M12, M22, M32, and M42.

  As can be seen from FIG. 15, each of the output MOS transistors M11, M21, M31, and M41 is provided with a monitor circuit having the same configuration including the monitor MOS transistors M12, M22, M32, and M42. Therefore, the monitor circuit corresponding to the output MOS transistor M11 will be described below, and the description of the monitor circuits corresponding to M21, M31, and M41 will be omitted.

  The MOS transistor M13 and M14 are connected in series to the monitoring MOS transistor M12, and the same voltage as the voltages VCMPU, VCMPL, VCMNU, and VCMNL applied to the gate terminal of M11 is applied to the gate terminal. , A MOS transistor M15 having the same size as M11 and flowing the same current is provided. In addition, MOS transistors M16 and M17 are connected in series with the MOS transistor M15. Among these, M17 has a diode connection in which the drain and the gate are coupled, and the gate terminals of M17 and M14 are connected to each other to connect the current mirror. The circuit is configured. MOS transistors M17 and M14 have the same size.

  The output voltages of the error amplifiers AMP11 and AMP12 are applied to the gate terminals of the MOS transistors M13 and M16, respectively. Here, in the error amplifier AMP11, the source voltage of the monitoring MOS transistor M12 is applied to the non-inverting input terminal, and a voltage lower than the source voltage of the driving MOS transistor M11 by a predetermined voltage Voff is applied to the inverting input terminal. ing. As a result, the MOS transistor M12 is controlled so that its source voltage becomes Voff lower than the source voltage of the driving MOS transistor M11 by the action of the negative feedback loop including the error amplifiers AMP11 and MOSM13. As long as the operation state of the driving MOS M11 and the operation state of the monitoring MOS M12 are completely matched by the above operation and the MOS transistor operates in the ON resistance region, an accurate current mirror is formed.

  On the other hand, in the error amplifier AMP12, the source voltage of the MOS transistor M15 is applied to the non-inverting input terminal, and a voltage lower than the power supply voltage VDD by a predetermined voltage (offset voltage) Voff is applied to the inverting input terminal. Thus, the MOS transistor M16 is controlled so that its source voltage is lower than the power supply voltage VDD by Voff by the action of the negative feedback loop composed of the error amplifier AMP12 and the MOSM16. Then, the drain current of the MOS transistor M16 is supplied to the MOS transistor M17 and transferred to the MOS transistor M14 by the current mirror. As a result, the difference between the drain current flowing in the MOS transistor M13 and the drain current flowing in M14 is output as the detection current Isns, and this is passed to the sense resistor Rsns (see FIG. 2).

  As described above, the error amplifier AMP11 and the MOS transistor M13 are provided so that the source voltage of M12 is lower than the source voltage of M11 by Voff because the output is performed during the power regeneration period when the motor coil Lvcm is PWM-driven. This is because the drain voltage in the reverse direction flows because the source voltage of the MOS transistor M11 becomes higher than the power supply voltage VDD, but the reverse drain current cannot flow in the monitoring MOS transistor M12 due to the circuit configuration. The offset voltage Voff is set to a voltage that prevents a reverse current from flowing through M12 even when a reverse drain current flows through the output MOS transistor M11 during the power regeneration period when PWM driving is performed. . As a result, a predetermined current Ioff flows through the monitoring MOS transistor M12 even when the drain current of the output MOS transistor M11 becomes zero.

  However, if the current of the monitoring MOS transistor M12 is allowed to flow to the sense resistor Rsns as it is, an excess current (offset current Ioff) generated by the offset voltage Voff is added, so that a correct detection current cannot be flowed. Therefore, only the offset current Ioff generated by the offset voltage Voff is generated by M15, M16 and the error amplifier AMP12, transferred to the MOS transistor M14 by the current mirror, and the offset current Ioff flowing in M14 is subtracted from the drain current flowing in the MOS transistor M13. The offset is canceled by outputting the minute as the detection current.

  Further, in the coil current detection circuit of this embodiment, the error amplifiers AMP11, AMP12 to AMP41, AMP42 are activated at a predetermined timing by the enable signals EN, / EN, so that the detection currents are simultaneously generated from a plurality of detection circuits. It is configured to prevent detection of an erroneous coil current by preventing output. Hereinafter, such an operation will be described with reference to FIGS.

  FIG. 16 shows the output MOS transistors M11, M21, and the outputs VCMP and VCMN of the drivers 211 and 212 in the motor driving circuit of the embodiment so that current flows through the coils in the direction of the arrow in FIG. Changes in coil current Ivcm, drain current Id of M11, M21, M31, and M41, enable signals EN and / EN, and detection current Isns when M31 and M41 are on / off controlled are shown. In this control state in which the coil current Ivcm flows in the direction of the arrow in FIG. 15, the output MOS transistors M11 and M41 are turned on during the period of VCMP-VCMN> 0, and the coil is indicated by the arrow (1) in FIG. An effective drive current flows in any direction, but when M41 is switched from on to off and M31 is switched from off to on while M11 is on, a current as indicated by an arrow (2) flows.

  After that, M41 is switched from OFF to ON while M11 is ON, M31 is switched from ON to OFF, and an effective drive current as shown by the arrow (1) is again supplied to the coil, and then M11 is switched from ON to OFF. Switches from off to on and a current as shown by arrow (3) flows. Then, while M41 is on, M11 is switched from off to on, and M21 is switched from on to off, so that an effective drive current as shown by the arrow (1) flows through the coil again. However, when M41 is switched from OFF to ON and M31 is switched from ON to OFF and the current is switched from (2) to (1), a recovery current flows through M31 and M41 for a moment, and M11 is switched from OFF to ON. When the current switches from on to off and the current switches from (3) to (1), a recovery current flows through M11 and M21 for a moment. Therefore, if such a recovery current is flowing, an error will occur if the current of that phase is detected.

  Therefore, in this embodiment, the amplifiers AMP11 and AMP12 are activated during the period TS1 by the enable signals EN and / EN, and the amplifiers AMP41 and AMP42 are activated during the period TS2, so that the voltage of the output drive transistor transitions. Current detection during the period is avoided, and current detection is performed only from the output drive transistor always in the ON resistance state, so that a correct current can be detected. Moreover, by setting the periods TS1 and TS2 to the same time, the detection values on the VCMP side and the detection values on the VCMN side are averaged, and variations in offset and gain occurring between both detection circuits on the VCMP side and the VCMN side are reduced. Yes.

  FIG. 17 shows an output MOS transistor M11, so that the outputs VCMP, VCMN of the drivers 211, 212 in the motor drive circuit of the embodiment flow through the coils in a direction opposite to the arrow in FIG. 15, that is, from left to right. Changes in coil current Ivcm, drain currents of M11, M21, M31, and M41, enable signals EN and / EN, and detection current Isns when M21, M31, and M41 are on / off controlled are shown. In the control state in which the coil current Ivcm flows in the direction opposite to the arrow in FIG. 15, the output MOS transistors M31 and M21 are turned on during the period of VCMP-VCMN <0, and the coil has an effective value as indicated by the arrow (4). A drive current flows, but when M21 switches from OFF to ON and M11 switches from ON to OFF, a recovery current flows through M11 and M21 for a moment, and when M31 switches from OFF to ON and M41 switches from ON to OFF for a moment. A recovery current flows through M31 and M41. Accordingly, when such a recovery current is flowing, detecting a current of that phase causes an error.

  Therefore, in this embodiment, the amplifiers AMP21 and AMP22 are activated during the period TS3 by the enable signals EN and / EN, and the amplifiers AMP31 and AMP32 are activated during the period TS4, so that the voltage of the output drive transistor transitions. Current detection during the period is avoided, and current detection is performed only from the output drive transistor always in the ON resistance state, so that a correct current can be detected. In addition, by setting the periods TS3 and TS4 to be the same time, the detection value on the VCMP side and the detection value on the VCMN side are averaged, and variations in offset and gain occurring between both detection circuits on the VCMP side and the VCMN side are reduced. Yes.

  Further, in the current detection circuit of this embodiment, when the output MOS transistors M11, M21, M31, and M41 are switched on / off, the upper MOS transistor M11 and the lower M21 or M31 are shifted by a slight deviation of the control signals VCMPU to VCMNL. When M41 and M41 are turned on at the same time, a very large through current may flow. Therefore, the timing of the control signals VCMPU to VCMNL is adjusted so that M11 and M21 or M31 and M41 are not turned on at the same time. Yes.

  However, if this is done, for example, when the output MOS transistors M11 and M41 are turned on and a current such as (1) in FIG. Since it is off, a current flows through the base diode of M41, and inconsistent portions appear in the coil terminal voltages VCMP and VCMN as shown by circles in FIGS. 18 (c) and 18 (d). Even if such a current flows and a mismatched portion appears in VCMP and VCMN, if the direction of the coil current and the polarity of the drive voltage match, the output MOS is basically fully turned on. Therefore, the current can be correctly detected by the circuit of FIG. However, if the transition period is slow and the outputs of VCMP and VCMN have not finished transitioning at the start of the period Ts1 and Ts2, a slight detection error occurs.

  However, since the load to be driven according to the present invention is based on an inductive coil, the phase of the drive current Ivcm of the load coil is delayed compared to the differential drive voltage of VCMP-VCMN. For this reason, immediately after switching the polarity of the drive current, the polarity of the drive voltage and the drive current is inverted for a certain period. When the load is a coil of a voice coil motor, there is a period in which the polarity of the drive voltage and the drive current is reversed due to the influence of the reverse voltage B-EMF of the motor. During this polarity inversion period (when the polarity of voltage and current does not match), the output stage potential changes during the period of Tdt shown in FIG. Therefore, it coincides with the switching of the enable signal EN as the phase selection signal. For this reason, it was found that during the dead time Tdt, the output MOS transistor in the current detection phase was not turned on and current detection was not possible.

  Therefore, in this embodiment, the error amplifiers AMP11, AMP21, AMP31, and AMP41 in the coil current detection circuit of FIG. 15 can hold the output level according to the control signal HOLDP or HOLDN as shown in FIG. As described above, it is configured by an error amplifier with an error, and this amplifier is operated by a control signal HOLDP or HOLDN from a logic circuit as shown in FIG. 20 so as to hold the previous detected current value for a predetermined period. It was made possible to avoid various problems. The logic circuit (dead time determination circuit) in FIG. 20 can be provided in the output control circuit 203 in FIG.

  The error amplifier of FIG. 19 has a control signal HOLDP or a control signal at the gate terminal between a differential amplification stage composed of a constant current source CI1 and MOS transistors Mop1 to Mop4 and an output stage composed of a constant current source CI2 and MOS transistor Mop5. Switch MOS transistors Mop6 and Mop7 to which HOLDN is input are connected in series. When the control signal HOLDP or HOLDN is at a high level, Mop6 and Mop7 are turned on and operate as a normal differential amplifier. When HOLDP or HOLDN is at a low level, Mop6 and Mop7 are turned off and the immediately preceding voltages are held in the capacitors Cc2 and Cc1, so that the output voltage OUT can hold the immediately preceding level state.

  In the dead time determination circuit of FIG. 20, the comparator Comp1 for comparing the control signal VCMPU of the output MOS transistor M11 and the threshold voltage VthHP at which M11 can be sufficiently turned on, and the control signals VCMPL and M21 of the output MOS transistor M21 can be sufficiently turned on. A comparator Comp2 for comparing the threshold voltage VthLP, a comparator Comp3 for comparing the control voltage VCMNL of the output MOS transistor M41 and a threshold voltage VthLN at which M41 can be sufficiently turned on, and control signals VCMNU and M31 of the output MOS transistor M31 Comparator Comp4 for comparing the threshold voltage VthHP that can be turned on sufficiently, the NAND gate G1 that receives the outputs of the comparators Comp1 and Comp2 and the enable signal EN, and the outputs of the comparators Comp3 and Comp4 and the inversion of the enable signal EN Input signal / EN NAND gate G2.

  When the gate voltages VCMPU and VCMPL of the output MOS transistors M11, M21, M31 and M41 in FIG. 16 are lower than the threshold voltages VthHP and VthLP, respectively, and when VCMNU and VCMNL are lower than VthHN and VthLN, the corresponding output MOS It is determined that the transistor is in the off state, and the output of the corresponding comparator becomes high level. When all of the comparators Comp1 and Comp2 and the enable signal EN become high level, the output HOLDP of the NAND gate G1 becomes low level, and the amplifiers AMP11 and AMP21 in FIG. 16 are in the hold state.

  Further, when the comparators Comp3 and Comp4 become high level and the enable signal EN becomes low level (/ EN is "H"), the output HOLDN of the NAND gate G2 becomes low level, and the amplifiers AMP31 and AMP41 in FIG. 16 are held. The reference values VthHP, VthLP, VthLN, and VthHN are respectively supplied from a reference voltage generation circuit RVG including reference current sources Iref1, Iref2, Iref3 and resistors Rref1, Rref2, Rref3 provided in the output control circuit 203. Reference voltages VthHP, VthLP (= VthLN), and VthHN corresponding to gate-source voltages at which the output transistors can be fully turned on are determined in advance based on the threshold voltage, mutual conductance, and drive current design values of each output transistor.

  In place of the error amplifiers AMP11, AMP21, AMP31, and AMP41 in the coil current detection circuit of FIG. 15 having the configuration as shown in FIG. 19, the detected current value is set at a predetermined timing after the current detection amplifier 202 of FIG. And a determination circuit for detecting the occurrence of the dead time Tdt is provided in the output control circuit 203, and a control signal is supplied to the hold circuit so as to operate to hold the detected current value immediately before the dead time. It may be configured.

  FIG. 21 shows another configuration example of the motor drive circuit 200 for driving and controlling the voice coil motor 108, and FIG. 22 shows a timing chart thereof.

  In this embodiment, PAM (pulse amplitude modulation) pulse generation circuits 225 and 226 are used instead of the PWM pulse generation circuits 225 and 226 in the motor drive circuit of the embodiment of FIG. The PAM pulse generation circuits 225 and 226 can be configured by ordinary DA converters. As can be seen from FIG. 22 showing the timing of the PAM modulation control in comparison with the timing of the PWM modulation control in FIG. 2, in the PAM modulation control, the pulse width is designated every 1/2 period in the PWM modulation control. The amplitude value is represented by the command value. The amplitudes of the drive pulses PL1 and PL2 (constant pulse width) are changed in accordance with the amplitude command value, thereby changing the voltage VCMP-VCMN applied between both terminals of the coil.

  Thus, for example, in PWM modulation control, the command value +16, -16 represents a pulse duty of 25% (amplitude is 100%), but in PAM modulation control, the command value +16, -16 represents a pulse amplitude of 25% ( (Duty 100%) is expressed. By applying the PAM modulation control of this embodiment, there is an advantage that the noise of the frequency component twice the PAM (PWM) frequency appearing in the coil drive current Ivcm can be reduced.

  According to the motor drive circuit of the above embodiment, the seek operation, the track follow operation, and the settling operation can be performed by PWM control, and the voice coil motor that has a desired control accuracy and can be manufactured by a CMOS process. A drive control semiconductor integrated circuit can be obtained.

  In addition, it is possible to detect the current for feedback control of the voice coil motor with high accuracy without affecting the sampling clock jitter and without depending on the PWM period. A circuit can be obtained.

  Furthermore, it is possible to obtain a semiconductor integrated circuit for driving control of a voice coil motor that can suppress the quantization noise and make the entire control system into a digital circuit, thereby improving the SN ratio compared to an analog circuit. .

  Furthermore, according to the embodiment as described above, a magnetic disk storage device with low power consumption and few read errors can be realized.

  Furthermore, it is possible to perform seek operation, track follow operation, and settling operation by PWM control, reduce noise generated by PWM drive, and drive control semiconductor for voice coil motor capable of highly accurate current control. An integrated circuit can be obtained.

  In addition, it automatically adjusts the delay of propagation delay time and transition time generated in the driver circuit due to manufacturing variations, temperature changes, and power supply voltage fluctuations to prevent a decrease in PWM drive control accuracy, and a change in the output signal of the driver circuit Therefore, it is possible to obtain a semiconductor integrated circuit for driving control of a voice coil motor capable of preventing occurrence of errors in position information and stored information due to noise combined with the signal read out by.

  Further, it is possible to obtain a voice coil motor drive control semiconductor integrated circuit capable of reducing power loss generated in the sense resistor.

  In addition, it is possible to obtain a semiconductor integrated circuit for driving control of a voice coil motor capable of reducing coil error current caused by fluctuations in power supply voltage and performing highly accurate driving control.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Not too long. For example, in the above embodiment, it has been described that the PWM drive by the voice coil motor drive circuit is performed at the time of seek of the magnetic head, at the time of track follow, and at the time of ramp loading. The coil may be PWM driven by a voice coil motor driving circuit, or the head unloading may be performed with relatively rough control. Therefore, a simple linear driving circuit may be separately provided for unloading.

  In the above description, the case where the invention made by the present inventor is applied to a magnetic disk storage device using a hard disk as a storage medium, which is a field of use as a background, has been described. However, the present invention is not limited thereto. In addition, the present invention can be used for all actuator devices that require high-precision torque control, such as optical disc pickup positioning control, printer head positioning control, and industrial AC servo motor torque control.

DESCRIPTION OF SYMBOLS 100 Magnetic storage disk 102 Spindle motor 104 Magnetic head 106 Arm 108 Voice coil motor 110 Signal processing circuit (signal processing IC)
DESCRIPTION OF SYMBOLS 200 Motor drive circuit 201 Serial port 202 Current sense amplifier 203 Output control circuit 204 Offset calibration circuit 205 A / D converter 211, 212 Driver 220 Digital control circuit 221 ΣΔ A / D conversion circuit 222 Decimation filter 223 Phase compensator 224 ΣΔ modulation circuit 225, 226 PWM pulse generation circuit 310 controller 320 microcomputer

Claims (26)

Detects the drive current of the voice coil motor that moves a magnetic head that reads information on the storage track on the magnetic storage disk that is driven to rotate on the disk, and the drive current that flows through the coil of the voice coil motor. A semiconductor integrated circuit for driving a motor that moves the magnetic head by feedback control while
A control circuit for feedback control of the voice coil motor is based on a current detection unit that detects a drive current flowing in the coil of the voice coil motor, a current detected by the current detection unit, and a given current command value. And a control signal generator configured by a digital circuit for generating a drive control signal for a driver circuit for supplying a drive current to the coil of the voice coil motor.   The motor drive according to claim 1, wherein the control signal generation unit includes a ΣΔ modulator as a modulation circuit that generates a signal for controlling the driver circuit from a difference signal between the current command value and a current detection value. Semiconductor integrated circuit.   3. The control signal generation unit according to claim 2, further comprising a D / A conversion circuit that converts the signal modulated by the ΣΔ modulator into an analog signal, and an output signal of the ΣΔ modulator is directly input to the D / A conversion circuit. And a motor-driving semiconductor integrated circuit configured to generate a driving pulse for controlling the driver circuit.   4. The motor-driving semiconductor integrated circuit according to claim 2, wherein a multibit quantizer is used as a quantizer of the ΣΔ modulator.   5. The semiconductor integrated circuit for driving a motor according to claim 2, further comprising a phase compensator comprising a digital filter having an integral characteristic in a stage preceding the ΣΔ modulator.   6. The semiconductor integrated circuit for driving a motor according to claim 5, wherein a PI controller is used as the phase compensator.   6. The semiconductor integrated circuit for driving a motor according to claim 5, further comprising a register for setting a filter coefficient of the phase compensator.   3. The current detection unit according to claim 2, further comprising: a current detection amplifier and an A / D conversion circuit that converts an analog signal detected by the amplifier into a digital signal, and the A / D conversion circuit is an oversampling A / D conversion circuit. A semiconductor integrated circuit for driving a motor, wherein a D conversion circuit is used.   9. The motor driving semiconductor integrated circuit according to claim 8, wherein a ΣΔ modulation type A / D conversion circuit is used as the A / D conversion circuit.   10. The motor-driving semiconductor integrated circuit according to claim 9, further comprising a decimation filter having a low-pass and frequency thinning function at a subsequent stage of the ΣΔ modulation type A / D conversion circuit.   11. The motor-driving semiconductor integrated circuit according to claim 10, wherein the decimation filter includes a phase lead compensator. Detects the drive current of the voice coil motor that moves a magnetic head that reads information on the storage track on the magnetic storage disk that is driven to rotate on the disk, and the drive current that flows through the coil of the voice coil motor. A semiconductor integrated circuit for driving a motor that moves the magnetic head by feedback control while
The control circuit for feedback control of the voice coil motor is composed of a digital circuit, and an output driver based on the output signal of the phase compensator generated from the difference signal between the given current command value and current detection value A ΣΔ modulator is used as a modulation circuit for generating a signal for controlling the voltage, and a counter electromotive voltage for estimating a counter electromotive voltage generated in the coil based on an output of the current detection means and a drive voltage command signal that is an input of the ΣΔ modulator. A motor integrated semiconductor integrated circuit comprising an estimation circuit. 13. The voice coil motor according to claim 12, wherein the control circuit is configured to detect a drive current flowing in a coil of the voice coil motor, and to detect the drive current flowing in the coil of the voice coil motor, based on the current detected by the current detector and the current command value. A control signal generation unit that generates a drive control signal for a driver circuit that supplies a drive current to the coil of
The control signal generation unit includes a ΣΔ modulator that generates a signal for controlling the driver circuit from a difference signal between the current command value and a current detection value, and a digital signal having an integration characteristic provided in a preceding stage of the ΣΔ modulator. A phase compensator comprising a filter, and a D / A conversion circuit for converting the signal modulated by the ΣΔ modulator into an analog signal,
The current detection unit includes a ΣΔ modulation type A / D conversion circuit that converts an analog signal detected by a current detection amplifier into a digital signal, and a low-pass signal provided in a subsequent stage of the ΣΔ modulation type A / D conversion circuit And a decimation filter having a frequency decimation function. A semiconductor integrated circuit for driving a motor.   14. The motor-driving semiconductor integrated circuit according to claim 12, further comprising a driver circuit that causes a driving current to flow through a coil of the voice coil motor in accordance with a signal generated by the control circuit.   14. The semiconductor integrated circuit for driving a motor according to claim 13, wherein the decimation filter includes a phase lead compensator. In a semiconductor integrated circuit for a motor for driving and controlling an output stage for supplying current to the coil, which is used in a motor driven by supplying current to the coil in an H-bridge type,
The control circuit for feedback control of the motor is
A current detector for detecting a drive current flowing in the motor coil; and an output for passing the drive current to the motor coil from a difference signal between a current detection value detected by the current detector and a given current command value. And a control signal generator having a ΣΔ modulator as a modulation circuit for generating a signal for controlling a driver circuit for driving and controlling the stage.   17. The control signal generation unit according to claim 16, further comprising a PWM modulator or a PAM modulator corresponding to a D / A conversion circuit that converts the signal modulated by the ΣΔ modulator into an analog signal, and outputs the ΣΔ modulator. A semiconductor integrated circuit for a motor, wherein a signal is directly input to a D / A conversion circuit to generate a drive pulse for controlling the driver circuit.   18. The motor semiconductor integrated circuit according to claim 16, wherein a multibit quantizer is used as a quantizer of the ΣΔ modulator.   19. The semiconductor integrated circuit for a motor according to claim 16, further comprising a phase compensator including a digital filter having an integral characteristic in a stage preceding the ΣΔ modulator.   20. The motor semiconductor integrated circuit according to claim 19, wherein a PI controller is used as the phase compensator.   20. The motor semiconductor integrated circuit according to claim 19, further comprising a register for setting a filter coefficient of the phase compensator.   17. The current detection unit according to claim 16, further comprising: a current detection amplifier and an A / D conversion circuit that converts an analog signal detected by the amplifier into a digital signal, and the A / D conversion circuit is an oversampling A / D converter. A semiconductor integrated circuit for a motor, wherein a D conversion circuit is used.   23. The motor semiconductor integrated circuit according to claim 22, wherein a ΣΔ modulation type A / D conversion circuit is used as the A / D conversion circuit.   24. The motor semiconductor integrated circuit according to claim 23, further comprising a decimation filter having a low-pass and frequency decimation function downstream of the ΣΔ modulation type A / D conversion circuit.   25. The motor semiconductor integrated circuit according to claim 24, wherein the decimation filter includes a phase lead compensator.   17. The back electromotive force estimation circuit according to claim 16, wherein the control signal generation unit estimates a back electromotive voltage generated in the coil based on an output of the current detection unit and a drive voltage command signal that is an input of the ΣΔ modulator. A semiconductor integrated circuit for a motor, comprising:

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