JP2008078816A - Drive method of voltage driving type semiconductor device, and gate driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce switching loss and a surge voltage. <P>SOLUTION: The method is the drive method of a voltage driving type semiconductor device (IGBT 1). A surge period (turn-on time tON/turn-off time tOFF) from the timing of a turn-on or turn-off command of the voltage driving type semiconductor device till the timing of generation of the surge voltage is stored. The effective gate resistance value of the voltage driving type semiconductor device is changed in the case of turn-on or turn-off in the next time, based on the surge period in the case of turn-on or turn-off which is stored this time,. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for driving a voltage-driven semiconductor element, and more particularly to a technique for reducing switching loss and surge voltage.

  Conventionally, in a technical field related to driving of a voltage-driven semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), a time change rate dIce / dt of a current flowing through the semiconductor element is detected, and the semiconductor element is detected based on the detection result. There is known a technique for realizing the optimum driving of the motor.

  For example, in Patent Document 1, the turn-on loss is reduced, and the reduction in the time change rate dIce / dt of the collector current of the IGBT at the time of turn-on is detected, thereby generating in proportion to the time change rate dIce / dt. A technique for reducing the recovery surge voltage is disclosed. In this technique, the turn-on loss is reduced by switching to a resistor having a low resistance value after a delay time t1 set by a delay circuit.

  Moreover, in patent document 2, the time change rate (for example, dVge / dt) of the electric quantity which changes according to the element state in switching operation is detected, and by changing an effective gate resistance value based on this detection result, A technique for realizing optimum driving of a semiconductor element having any characteristics without requiring adjustment is disclosed.

  Here, with respect to Patent Document 1, the characteristics of the semiconductor element and the temperature characteristics vary, and the gate voltage waveform changes depending on the collector current value. It can be said that it is very difficult to control the accuracy. For the same reason, it can be said that it is very difficult to perform gate control with a fixed delay time even during turn-off.

  Further, with respect to Patent Document 1 and Patent Document 2, there is a problem that high speed performance is required for all of the detection circuit, the control circuit, and the drive circuit. If this high-speed performance cannot be ensured, switching loss and surge voltage will increase, resulting in the problem of destroying the semiconductor element.

Here, FIG. 4 shows a simulation waveform obtained by turning off the IGBT under a certain condition.
When detecting any of the detection signals Vge, dVge / dt, Ice, and dIce / dt, it is necessary to capture the timing of the dotted line B in FIG. The turn-off surge voltage reaches its peak at the timing of the dotted line C. Therefore, it is necessary to complete the feedback control of the detection circuit → the control circuit → the drive circuit in a shorter time than the time tFB in FIG. The time tFB is, for example, about 50 ns, which is substantially equal to the response time of a general high-speed detection circuit. In addition to this time tFB, a response time of about 10 ns of the high-speed control circuit and a response time of about 50 ns of the high-speed drive circuit are necessary for actual control, so in reality feedback in a time shorter than the time tFB is required. Complete control is very difficult.
Further, if Vce is used as a detection signal, there is a margin in the time tFB, but each element constituting the Vce detection circuit needs to have a breakdown voltage equivalent to that of an IGBT. In addition, since Vce having a high impedance has voltage switching noise of other phases, there is a problem that erroneous detection due to noise may occur.
Furthermore, since the switching frequency of the IGBT will continue to increase in the future, the time tFB may be further shortened.
Japanese Patent No. 3614519 JP 2004-266368 A

  SUMMARY OF THE INVENTION An object of the present invention is to propose a new technique capable of reducing switching loss and surge voltage in the driving of a voltage-driven semiconductor element in view of the above-mentioned problems of the prior art.

  The problems to be solved by the present invention are as described above. Next, means for solving the problems will be described.

That is, in claim 1,
Storing a surge period from a turn-on or turn-off command timing of the voltage-driven semiconductor element to a surge voltage generation timing;
At the time of next turn-on or turn-off, a voltage-driven semiconductor element driving method for changing an effective gate resistance value of the voltage-driven semiconductor element based on the surge period stored at the time of turn-on or turn-off stored this time Is.

Further, in claim 2,
The effective gate resistance value is
At the turn-on of the voltage-driven semiconductor element,
In the surge period, it is set large,
After the lapse of the surge period, it is set to be small.

Further, in claim 3,
The effective gate resistance value is
At the time of turn-off of the voltage driven semiconductor element,
In the surge period, it is set small,
After the surge period elapses, it is set large.

Further, in claim 4,
The detection of the surge voltage generation timing is performed by detecting the timing at which the differential value of the collector current of the voltage-driven semiconductor element is minimized or the timing at which the differential value of the gate-emitter voltage is minimized. To be done.

Further, in claim 5,
The effective gate resistance value is changed by connecting a plurality of gate resistors in parallel,
This is done by switching whether or not any of the gate resistors is energized.

In claim 6,
Means for detecting generation of a surge voltage at each switching of the voltage-driven semiconductor element performed in response to a control signal;
Means for storing a surge period from a turn-on or turn-off command timing of the voltage-driven semiconductor element to the surge voltage generation timing;
At the time of next turn-on or turn-off, the timing for changing the effective gate resistance value of the voltage-driven semiconductor element is determined based on the surge period at the time of turn-on or turn-off stored this time by means for storing the surge period Means to
Means for changing the effective gate resistance value based on the timing of changing the effective gate resistance value;
A gate drive circuit for a voltage-driven semiconductor element is provided.

In claim 7,
The effective gate resistance value is
At the turn-on of the voltage-driven semiconductor element,
In the surge period, it is set large,
After the lapse of the surge period, it is set to be small.

Further, in claim 8,
The effective gate resistance value is
At the time of turn-off of the voltage driven semiconductor element,
In the surge period, it is set small,
After the surge period elapses, it is set large.

In claim 9,
The means for detecting the generation of the surge voltage is to detect the timing at which the differential value of the collector current of the voltage-driven semiconductor element is minimized, or the timing at which the differential value of the voltage between the gate and the emitter is minimized, The timing of occurrence of surge voltage is detected.

In claim 10,
The means for changing the effective gate resistance value is configured to change the effective gate resistance value by connecting a plurality of gate resistors in parallel and switching whether or not any of the gate resistors is energized.

  According to the configuration of the present invention, the following effects can be obtained.

  According to the first aspect of the present invention, it is possible to avoid problems of control failure caused by variations in characteristics of semiconductor elements, variations in temperature characteristics, and changes in the gate voltage waveform depending on the collector current value. Compared with the case where the gate control is performed at this time, the control accuracy can be improved.

  According to a second aspect of the present invention, at the time of turn-on, the recovery surge voltage can be lowered during the surge period, and the switching loss can be reduced after the surge period has elapsed.

  According to a third aspect of the present invention, at the time of turn-off, switching loss can be reduced during the surge period, and the turn-off surge voltage can be reduced after the surge period has elapsed.

  According to the fourth aspect of the present invention, the occurrence of surge voltage can be detected with a simple configuration.

  According to the fifth aspect, the effective gate resistance value can be changed with a simple and inexpensive configuration.

  According to the sixth aspect of the present invention, it is possible to avoid problems of control failure caused by variations in characteristics of semiconductor elements, variations in temperature characteristics, and changes in the gate voltage waveform depending on the collector current value. Compared with the case where the gate control is performed at this time, the control accuracy can be improved.

  According to the seventh aspect, at the time of turn-on, the recovery surge voltage can be lowered during the surge period, and the switching loss can be reduced after the surge period has elapsed.

  According to the eighth aspect of the present invention, at the time of turn-off, switching loss can be reduced during the surge period, and the turn-off surge voltage can be reduced after the surge period has elapsed.

  According to the ninth aspect of the present invention, the occurrence of surge voltage can be detected with a simple configuration.

  According to the tenth aspect, the effective gate resistance value can be changed with a simple and inexpensive configuration.

The embodiment of the invention is as shown in FIGS.
A voltage-driven semiconductor element (IGBT1) driving method,
Storing a surge period (turn-on time tON / turn-off time tOFF) from a turn-on or turn-off command timing of the voltage-driven semiconductor element to a surge voltage generation timing;
At the next turn-on or turn-off, the effective gate resistance value of the voltage-driven semiconductor element is changed based on the surge period stored at the turn-on or turn-off stored this time.

Also,
The effective gate resistance value is
At the turn-on of the voltage-driven semiconductor element,
In the surge period, it is set large,
After the lapse of the surge period, it is set to be small.

Also,
The effective gate resistance value is
At the time of turn-off of the voltage driven semiconductor element,
In the surge period, it is set small,
A large value is set after the surge period.

  The detection of the surge voltage generation timing detects the timing at which the differential value of the collector current of the voltage-driven semiconductor element is minimized or the timing at which the differential value of the gate-emitter voltage is minimized. Is to be done.

Also,
The effective gate resistance value is changed by connecting a plurality of gate resistors in parallel,
This is done by switching whether or not any of the gate resistors is energized.

Moreover, as shown in FIG. 1 and FIG.
Means (surge voltage detection circuit 3) for detecting a surge voltage generation at each switching of the voltage-driven semiconductor element (IGBT1) performed according to a control signal;
Means for storing a surge period (time storage circuit 4) from the timing of turn-on or turn-off command of the voltage-driven semiconductor element to the timing of generation of the surge voltage;
Means for determining the timing for changing the effective gate resistance value of the voltage-driven semiconductor element based on the surge period at the time of turn-on or turn-off stored this time by the time memory circuit 4 at the next turn-on or turn-off. Control circuit 5);
Means for changing the effective gate resistance value based on the timing of changing the effective gate resistance value;
The gate drive circuit 10 of the voltage drive type semiconductor element (IGBT1) is provided.

Also,
The effective gate resistance value is
At the turn-on of the voltage-driven semiconductor element,
In the surge period, it is set large,
After the lapse of the surge period, it is set to be small.

Also,
The effective gate resistance value is
At the time of turn-off of the voltage driven semiconductor element,
In the surge period, it is set small,
A large value is set after the surge period.

  Further, the means for detecting the generation of the surge voltage detects the timing at which the differential value of the collector current of the voltage-driven semiconductor element is minimized or the timing at which the differential value of the gate-emitter voltage is minimized. Thus, the timing of occurrence of surge voltage is detected.

Also,
The means for changing the effective gate resistance value is configured such that a plurality of gate resistances R1 to R4 are connected in parallel and the effective gate resistance value is changed by switching whether or not any of the gate resistances are energized. .

  The above configuration is applicable in industries such as automobile manufacturers, semiconductor manufacturers, and inverter manufacturers, and the detailed configuration will be described below.

  First, an inverter that drives a three-phase motor can be considered as one of the apparatuses to which the present invention is applied. This inverter comprises six sets of IGBTs, diodes, and driving circuits as voltage-driven semiconductor elements. Hereinafter, as shown in FIG. 1, two sets of IGBTs 1 and 2 and diodes D1 and D2, and A description will be given with a configuration of one set of drive circuits (gate drive circuit 10 of IGBT 1).

FIG. 1 is a circuit diagram of a gate drive circuit 10 according to the first embodiment. In FIG. 1, reference numeral 1 denotes an IGBT as a voltage-driven semiconductor element.
A diode D1 is connected in parallel to the IGBT1.
The IGBT 1 is a sense IGBT having a sense emitter terminal.
The IGBT 1 is driven by the control circuit 5.
The sense emitter terminal of the IGBT 1 is grounded via a resistor R5.
Further, an IGBT 2 is disposed opposite to the IGBT 1, and the IGBT 2 is driven by a gate drive circuit (not shown) configured similarly to the gate drive circuit 10.

In FIG. 1, reference numeral 3 denotes a surge voltage detection circuit. This surge voltage detection circuit 3 detects the recovery surge voltage (FIG. 3) generated by the opposing diode D2 when the IGBT 1 is turned on, and the turn-off surge voltage (FIG. 4) generated at the IGBT 1 when the IGBT 1 is turned off. It is a circuit for detecting.
The recovery surge voltage and the turn-off surge voltage are detected by measuring the current input from the sense emitter terminal of the IGBT 1 and detecting the change over time, that is, the differential value dIce / dt.
Further, when the surge voltage detection circuit 3 detects the recovery surge voltage and the turn-off surge voltage, it outputs the detection timing to the time storage circuit 4 described later.

In FIG. 1, reference numeral 4 denotes a time memory circuit.
When the time memory circuit 4 is turned on, the turn-on time tON from the IGBT turn-on signal to the generation of the recovery surge voltage (until the recovery surge voltage detection signal is input from the surge voltage detection circuit 3) (FIG. 3). Reference) is memorized.
Further, when the time memory circuit 4 is turned off, the turn-off time tOFF (from the turn-off signal of the IGBT 1 to the turn-off / surge voltage generation (until the turn-off / surge voltage detection signal is input from the surge voltage detection circuit 3)) 4).
The turn-on time tON or the turn-off time tOFF is a surge period from the turn-on or turn-off command timing of the voltage-driven semiconductor element to the surge voltage generation timing.

The time storage circuit 4 stores the surge period (turn-on time tON, turn-off time tOFF) each time the IGBT 1 performs switching, and outputs the result to the control circuit 5.
More specifically, as shown in FIG. 4, the time storage circuit 4 is connected to the control circuit 5 during a period from the timing T1 when the IGBT control signal Is is switched from OFF to ON until the detection signal K is input. In response to this, the signal S5 is output. In this case, the period during which the time storage circuit 4 outputs the signal S5 is the turn-on time tON.
The time memory circuit 4 outputs the signal S5 to the control circuit 5 from the timing T2 when the IGBT control signal Is is switched from on to off until the detection signal K is input. In this case, the period during which the time storage circuit 4 outputs the signal S5 is the turn-off time tOFF.

  Immediately after the power supply of the gate drive circuit 10 of the IGBT 1 is turned on, the stored values of the turn-on time tON and the turn-off time tOFF are zero or fixed initial values, but the current of the load (motor) at this time is Since it is zero or near zero, the surge voltage is at a level that does not cause a problem.

In FIG. 1, reference numeral 5 denotes a control circuit. The control circuit 5 uses the IGBT control signal (turn-on signal / turn-off signal) and the effective gate resistance of the IGBT 1 based on the turn-on time tON or the turn-off time tOFF output from the time memory circuit 4 at the previous switching. The value is changed. By changing the effective gate resistance value, the switching loss and the surge voltage are reduced when the IGBT 1 is turned on and turned off.
The control circuit 5 outputs signals 1 to 4 for turning on / off the IGBT 1 to the switch elements M1 to M4.

  Further, the control circuit 5 determines whether the signal S5 output from the time storage circuit 4 corresponds when the IGBT control signal Is is switched from OFF to ON, or when the signal is switched from ON to OFF. Identification, that is, turn-on time tON and turn-off time tOFF can be identified. This identification method is not particularly limited, and can be realized, for example, by adding information for identifying turn-on / off to the signal S5.

In FIG. 1, M1 to M4 are switch elements to which an on / off signal output from the control circuit 5 is input, and the switch elements M1 to M4 operate according to the on / off signal. , IGBT1 is turned on / off.
More specifically, the switch elements M1 and M3 are respectively operated by the signals S1 and S3 when the IGBT 1 is turned on, and in particular, the effective gate resistance when the IGBT 1 is turned on by switching the switch element M3 on and off. The value can be switched.
The switch elements M2 and M4 are operated by the signals S2 and S4, respectively, when the IGBT 1 is turned off. In particular, the effective gate resistance value when the IGBT 1 is turned off is switched by switching the switch element M4 on and off. It is like that.
The switch elements M1 to M4 are composed of MOS transistors, and are turned on / off by a signal from the control circuit 5 to switch whether the resistors R1 to R4 are energized. In the case of this example, the switch elements M1 and M3 are composed of P-ch MOS transistors, and the switch elements M2 and M4 are composed of N-ch MOS transistors.

  In FIG. 1, R1 to R4 are gate resistors. These resistors R1 to R4 are switched on or off depending on the state of the switch elements M1 to M4, whereby the effective gate resistance value in the IGBT 1 is changed.

More specifically, when the IGBT 1 is turned on, the effective gate resistance value is determined by the resistors R1 and R3. The resistors R1 and R3 are connected in parallel to each other.
The resistor R3 is appropriately switched by the switch element M3, and the effective gate resistance value at turn-on is changed accordingly. That is, when the low speed R3 is energized, the effective gate resistance value is increased, and when the low speed R3 is not energized, the effective gate resistance value is decreased.

  Further, at the time of turn-on, by reducing the effective gate resistance value, high-speed switching can be performed and switching loss can be reduced. Also, by increasing the effective gate resistance value, the time change rate dIce / dt of the collector current Ice of the IGBT can be reduced, so that the recovery surge voltage proportional to the dIce / dt can be reduced. The recovery surge voltage Vr is expressed as Vr = L × (dIce / dt) where dIce / dt and the parasitic inductance component is L.

On the other hand, when the IGBT 1 is turned off, the effective gate resistance value is determined by the resistors R2 and R4. The resistors R2 and R4 are connected in parallel to each other.
As for the resistor R4, the switch element M4 appropriately switches between energization and the effective gate resistance value at the time of turn-off is changed accordingly. When the low speed R4 is energized, the effective gate resistance value is increased, and when the low speed R4 is not energized, the effective gate resistance value is decreased.

  Similarly to the turn-on state, by reducing the effective gate resistance value at the turn-off time, high-speed switching can be performed and switching loss can be reduced. Also, by increasing the effective gate resistance value, the time change rate dIce / dt of the collector current Ice of the IGBT can be reduced, so that the recovery surge voltage proportional to the dIce / dt can be reduced. The recovery surge voltage Vr is expressed as Vr = L × (dIce / dt) where dIce / dt and the parasitic inductance component is L.

Next, the recovery surge voltage waveform at turn-on will be described.
In FIG. 3, the time from when the IGBT 1 turn-on signal is input to the control circuit 5 until the recovery surge voltage is generated is the turn-on time tON (surge period), and the recovery surge voltage is generated at the timing of the dotted line A. I am going to do it.
The generation of the recovery surge voltage can be detected by detecting the timing at which the differential value dIce / dt of the collector current is minimized by the surge voltage detection circuit 3 connected to the sense emitter terminal.
In addition, the generation of the recovery surge voltage is detected by connecting the terminal of the surge voltage detection circuit 3 to the gate wiring and timing at which the differential value dVge / dt of the gate-emitter voltage Vge of the IGBT 1 is minimized. Or by detecting the voltage Vak between the anode and the cathode of the diode D2 facing the IGBT 1.

Next, the waveform of the turn-off surge voltage at the time of turn-off will be described.
In FIG. 4, the time from when the IGBT 1 turn-off signal is input to the control circuit 5 until the turn-off surge voltage is generated is the turn-off time tOFF (surge period), and the turn-off surge voltage is generated at the timing of the dotted line C. I am going to do it.
The generation of the turn-off surge voltage can be detected by detecting the timing at which the differential value dIce / dt of the collector current is minimized by the surge voltage detection circuit 3 connected to the sense emitter terminal.
In addition to detecting the generation of the turn-off surge voltage, the terminal of the surge voltage detection circuit 3 is connected to the gate wiring, and the differential value dVge / dt of the gate-emitter voltage Vge of the IGBT 1 is minimized. Or by detecting the voltage Vak between the anode and the cathode of the diode D2 facing the IGBT 1.

Next, control of the control circuit 5 will be described using the circuit diagram shown in FIG. 1 and the timing chart shown in FIG.
In FIG. 2, the voltage / current value that changes based on the IGBT on / off control signal Is, the detection signal K of the surge voltage detection circuit 3, the signal S5 of the time storage circuit 4, and the switch element by the control circuit 5 The relationship between the control signals S1 to S4 of M1 to M4 is shown.

  Explaining from the left side of the timing chart, first, the IGBT control signal Is is switched from OFF to ON (timing T1), and the surge voltage detection circuit 3 detects the generation of the recovery surge voltage in the diode D2. Then, the surge voltage detection circuit 3 outputs a detection signal K to the time storage circuit 4.

  Further, as shown in FIG. 1, the time control circuit Is receives the IGBT control signal Is as shown in FIG. 1. As shown in FIG. 2, the time storage circuit 4 switches the IGBT control signal Is from OFF to ON. The period from the timing T1 until the detection signal K is input is stored as the turn-on time tON, and this turn-on time tON is output to the control circuit 5 by the signal S5. Each time the IGBT is turned on, the time storage circuit 4 stores the turn-on time tON at the time of turn-on.

  Next, when the IGBT control signal Is is turned off from on (timing T2) and the surge voltage detection circuit 3 detects the generation of the turn-off surge voltage, the surge voltage detection circuit 3 sends the detection signal K to the detection signal K. Output to the time storage circuit 4.

  Further, as shown in FIG. 1, the time storage circuit 4 receives the IGBT control signal Is, and the time storage circuit 4 starts from the timing T2 when the IGBT control signal Is switches from on to off. The period until the detection signal K is input is stored as the turn-off time tOFF, and this turn-off time tOFF is output to the control circuit 5 by the signal S5. Each time the IGBT is turned off, the time storage circuit 4 stores a turn-off time tOFF at the time of turn-off.

  As described above, the time memory circuit 4 outputs the signal S5, which is information on the turn-on time tON or turn-off time tOFF in each turn-on / turn-off operation of the IGBT, to the control circuit 5, and the control circuit 5 The turn-on time tON or turn-off time tOFF in each turn-on / turn-off operation is recognized.

The control circuit 5 controls the operation of the switch elements M1 to M4 based on the turn-on time tON or the turn-off time tOFF.
First, the operation of the switch elements M1 and M3 at timing T3 when turning on will be described. The control circuit 5 turns on the switch element M1 by the signal S1, and outputs the signal S3 with a delay of the turn-on time tON. The switch element M3 is turned on.

Since the switch element M3 is turned on with a delay as described above, the effective gate resistance value is set large in the initial stage of the turn-on of the IGBT, and the recovery surge voltage at the turn-on can be lowered. After the turn-on time tON elapses, the effective gate resistance value is set to be small, enabling high-speed switching, and switching loss at turn-on can be reduced.
In this way, the trade-off characteristics between the surge voltage (recovery surge voltage) and the switching loss can be stably improved.
During the turn-on of the IGBT, the switch elements M2 and M4 are both turned off.

  On the other hand, the operation of the switch elements M2 and M4 at the timing T4 at the time of turn-off will be described. The control circuit 5 keeps turning on the switch element M2 by the signal S2, while the switch circuit M4 is turned off by the signal S4. It is turned on only for tOFF, and is turned off after the turn-off time tOFF has elapsed.

As described above, the switching element M4 is turned on only for the turn-off time tOFF, so that the effective gate resistance value is set small at the initial stage of the IGBT turn-off, enabling high-speed switching and reducing the switching loss at the turn-off time. Can do. Then, after the turn-off time tOFF has elapsed, the effective gate resistance value is set to be large, and the turn-off surge voltage at the time of turn-off can be reduced.
In this way, the trade-off characteristics between the surge voltage (turn-off surge voltage) and the switching loss can be stably improved.
Note that the switch elements M1 and M3 are both turned off during the turn-off of the IGBT.

  The control circuit 5 outputs the signal S3 with reference to the turn-on time tON at the previous IGBT turn-on. That is, in the example of FIG. 2, the turn-on time stored in the time storage circuit 4 at the timing T1 when the IGBT is turned on immediately before the turn-on time tON (n) at the timing T3 by the signal S3. tON (n) is used.

  Similarly, the control circuit 5 outputs the signal S4 with reference to the turn-off time tOFF at the previous IGBT turn-off. That is, in the example of FIG. 2, with respect to the turn-off time tOFF (n) at the timing T4 by the signal S4, the turn-off time stored in the time storage circuit 4 at the timing T2 at the turn-off time of the previous IGBT. tOFF (n) is used.

As described above, the output control of the signals S3 and 4 in the control circuit 5 is performed during the current turn-on or turn-off, the surge period (turn-on time tON, Alternatively, feedback control is performed by referring to the turn-off time tOFF).
In other words, at the next turn-on or turn-off, the surge period (turn-on time tON or turn-off time tOFF) at the current turn-on or turn-off is referred to.

  In addition, by performing feedback control in this way, the surge period is changed (variable), and the gate voltage waveform varies depending on the characteristics of the semiconductor element and the temperature characteristics, and the collector current value. It is possible to avoid the problem of control failure due to the fact that the control is performed, and it is possible to improve the control accuracy even when compared with the gate control in a fixed time set in advance.

In the feedback control in this embodiment, the effective gate resistance value is changed at the next turn-on or turn-off using the information at the current turn-on or turn-off. There is room for the time required for control.
For example, as shown in FIG. 4, when information on generation of turn-off / surge voltage at a certain turn-off time is used at a certain turn-off time, the detection circuit → control is performed in a shorter time than time tFB. It is necessary to complete the feedback control from the circuit to the driving circuit, and in reality, it is very difficult to complete the feedback control in a time shorter than the time tFB.
In this respect, in this embodiment, since information on the turn-off surge voltage (turn-off time tOFF) at the time of the previous turn-off is used, a general-purpose detection circuit (response time about 150 ns), control circuit (response time about 30 ns), Even if a drive circuit (response time of about 150 ns) is used, the feedback control can be sufficiently completed. Further, by utilizing the fact that the response times of these circuits are fixed, it becomes possible to perform a finer design for the total response time related to gate drive control.

  In normal motor control, a sufficiently high value is used as the switching frequency with respect to the frequency of the motor current, and the difference in collector current between adjacent switching is a value that can be ignored. You can think of it. For this reason, there is no problem in using the value of the surge period (turn-on time tON, turn-off time tOFF) at the previous switching for controlling the effective gate resistance value at a certain switching time.

1 is a circuit diagram of a gate drive circuit according to Embodiment 1. FIG. The figure which shows the voltage and electric current value etc. which change based on the on / off control signal of IGBT. The figure shown about the waveform of a recovery surge voltage. The figure shown about the waveform of a turn-off surge voltage.

Explanation of symbols

1 IGBT
2 IGBT
DESCRIPTION OF SYMBOLS 3 Surge voltage detection circuit 4 Time memory circuit 5 Control circuit D1 * D2 Diode M1-M4 Switch element R1-R4 Resistance S1-S5 Signal 10 Gate drive circuit

Claims (10)

Stores the surge period from the turn-on or turn-off command timing of the voltage-driven semiconductor element to the surge voltage generation timing,
A method for driving a voltage-driven semiconductor element, wherein an effective gate resistance value of the voltage-driven semiconductor element is changed at the next turn-on or turn-off based on the surge period stored at the time of turn-on or turn-off stored this time. The effective gate resistance value is
At the turn-on of the voltage-driven semiconductor element,
In the surge period, it is set large,
After the elapse of the surge period, it is set small.
The voltage-driven semiconductor element driving method according to claim 1. The effective gate resistance value is
At the time of turn-off of the voltage driven semiconductor element,
In the surge period, it is set small,
After the surge period has elapsed, it is set large.
3. The voltage-driven semiconductor element driving method according to claim 1, wherein the voltage-driven semiconductor element is driven. The detection of the surge voltage generation timing is performed by detecting the timing at which the differential value of the collector current of the voltage-driven semiconductor element is minimized or the timing at which the differential value of the gate-emitter voltage is minimized. Done,
4. The voltage-driven semiconductor element driving method according to claim 1, wherein the voltage-driven semiconductor element is driven. The effective gate resistance value is changed by connecting a plurality of gate resistors in parallel,
It is done by switching the presence or absence of energization of any gate resistance,
The method for driving a voltage-driven semiconductor element according to any one of claims 1 to 4, wherein: Means for detecting generation of a surge voltage at each switching of the voltage-driven semiconductor element performed in response to a control signal;
Means for storing a surge period from a turn-on or turn-off command timing of the voltage-driven semiconductor element to the surge voltage generation timing;
At the time of next turn-on or turn-off, the timing for changing the effective gate resistance value of the voltage-driven semiconductor element is determined based on the surge period at the time of turn-on or turn-off stored this time by means for storing the surge period Means to
Means for changing the effective gate resistance value based on the timing of changing the effective gate resistance value;
A gate drive circuit for a voltage-driven semiconductor element, comprising: The effective gate resistance value is
At the turn-on of the voltage-driven semiconductor element,
In the surge period, it is set large,
After the elapse of the surge period, it is set small.
The gate drive circuit of the voltage drive type semiconductor device according to claim 6. The effective gate resistance value is
At the time of turn-off of the voltage driven semiconductor element,
In the surge period, it is set small,
After the surge period has elapsed, it is set large.
8. A gate drive circuit for a voltage-driven semiconductor device according to claim 6 or 7, The means for detecting the generation of the surge voltage is to detect the timing at which the differential value of the collector current of the voltage-driven semiconductor element is minimized, or the timing at which the differential value of the voltage between the gate and the emitter is minimized, Detect the timing of surge voltage generation,
9. The gate drive circuit for a voltage-driven semiconductor element according to claim 6, wherein the gate drive circuit is a voltage-driven semiconductor element. The means for changing the effective gate resistance value is configured to change the effective gate resistance value by connecting a plurality of gate resistors in parallel and switching the presence or absence of energization of any of the gate resistances.
10. The gate drive circuit for a voltage-driven semiconductor element according to claim 6, wherein the gate drive circuit is a voltage-driven semiconductor element.

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