JP7249302B2 - semiconductor equipment - Google Patents

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JP7249302B2
JP7249302B2 JP2020049561A JP2020049561A JP7249302B2 JP 7249302 B2 JP7249302 B2 JP 7249302B2 JP 2020049561 A JP2020049561 A JP 2020049561A JP 2020049561 A JP2020049561 A JP 2020049561A JP 7249302 B2 JP7249302 B2 JP 7249302B2
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electrode
wire
conductive member
bonding
bonding portion
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JP2021150513A (en
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武史 今村
玉峰 魏
利恒 飯嶋
淳 細川
博明 岸
伸也 嶋村
恭久 新徳
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Electronic Devices and Storage Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Wire Bonding (AREA)

Description

本発明の実施形態は、半導体装置に関する。 TECHNICAL FIELD Embodiments of the present invention relate to semiconductor devices.

アナログ系の半導体チップは、扱う電流量が増大し、電極間を接続するワイヤについても広径化が求められている。しかしながら、電子部品においては同時に省面積化の要請もあるため、これらを共に実現する必要がある。 Analog semiconductor chips handle an increased amount of electric current, and there is a demand for wider wires for connecting electrodes. However, since there is also a demand for area saving at the same time in electronic parts, it is necessary to achieve both of them.

特開２００１－１５６１０７号公報Japanese Patent Application Laid-Open No. 2001-156107

本発明の実施形態は、ワイヤボンディング部の省面積化を実現可能な半導体チップ及び半導体装置を提供する。 Embodiments of the present invention provide a semiconductor chip and a semiconductor device capable of realizing a reduction in the area of wire bonding portions.

実施形態に係る半導体チップは、チップ本体と、第１電極と、第２電極と、第１導電部材を備える。前記第１電極は、前記チップ本体の上面に設けられる。前記第２電極は、前記チップ本体の上面に設けられ、前記第１電極から第１方向に離隔している。前記第２電極の前記第１方向における長さは、前記第１方向における前記第１電極の長さよりも長い。前記第１導電部材は、前記第１電極の上面に接する。 A semiconductor chip according to an embodiment includes a chip body, a first electrode, a second electrode, and a first conductive member. The first electrode is provided on the top surface of the chip body. The second electrode is provided on the top surface of the chip body and separated from the first electrode in the first direction. The length of the second electrode in the first direction is longer than the length of the first electrode in the first direction. The first conductive member is in contact with the upper surface of the first electrode.

実施形態に係る半導体チップは、チップ本体と、第１電極と、第２電極と、第１導電部材と、第２導電部材を備える。前記第１電極は、前記チップ本体の上面に設けられる。前記第２電極は、前記チップ本体の上面に設けられ、前記第１電極から第１方向に離隔する。前記第１導電部材は、前記第１電極の上面に接する。前記第２導電部材は、前記第２電極の上面に接する。前記第２導電部材の上端の位置は、前記第１導電部材の上端の位置よりも低い。 A semiconductor chip according to an embodiment includes a chip body, a first electrode, a second electrode, a first conductive member, and a second conductive member. The first electrode is provided on the top surface of the chip body. The second electrode is provided on the top surface of the chip body and separated from the first electrode in the first direction. The first conductive member is in contact with the upper surface of the first electrode. The second conductive member is in contact with the upper surface of the second electrode. The position of the upper end of the second conductive member is lower than the position of the upper end of the first conductive member.

実施形態に係る半導体装置は、前記半導体チップと、第１ワイヤと、第２ワイヤとを備える。前記第１ワイヤは、第１ボンディング部が前記第１導電部材に接する。前記第２ワイヤは、前記第２電極に接続される。 A semiconductor device according to an embodiment includes the semiconductor chip, a first wire, and a second wire. A first bonding portion of the first wire is in contact with the first conductive member. The second wire is connected to the second electrode.

実施形態に係る半導体装置は、半導体チップと、第１ワイヤと、第２ワイヤとを備える。前記半導体チップは、チップ本体と、第１電極と、第２電極と、第１導電部材とを有する。前記第１電極は、前記チップ本体の上面に設けられる。前記第２電極は、前記チップ本体の上面に設けられ、前記第１電極から第１方向に離隔する。前記第１導電部材は、前記第１電極の上面に接する。前記第１ワイヤは、第１ボンディング部が前記第１導電部材に接する。前記第２ワイヤは、前記第２電極に接続される。前記第１方向における前記第１導電部材の長さは、前記第１方向における前記第１ボンディング部の長さよりも短い。 A semiconductor device according to an embodiment includes a semiconductor chip, a first wire, and a second wire. The semiconductor chip has a chip body, a first electrode, a second electrode, and a first conductive member. The first electrode is provided on the top surface of the chip body. The second electrode is provided on the top surface of the chip body and separated from the first electrode in the first direction. The first conductive member is in contact with the upper surface of the first electrode. A first bonding portion of the first wire is in contact with the first conductive member. The second wire is connected to the second electrode. The length of the first conductive member in the first direction is shorter than the length of the first bonding portion in the first direction.

第１実施形態に係る半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment; FIG. 第１実施形態に係る半導体チップを示す一部拡大斜視図である。1 is a partially enlarged perspective view showing a semiconductor chip according to a first embodiment; FIG. 図２に示すＡ－Ａ'線による断面図である。3 is a cross-sectional view taken along line AA' shown in FIG. 2; FIG. 第１実施形態に係る半導体装置のボールボンディングを示す拡大図である。4 is an enlarged view showing ball bonding of the semiconductor device according to the first embodiment; FIG. 比較例に係る半導体装置を示す断面図である。FIG. 10 is a cross-sectional view showing a semiconductor device according to a comparative example; 第２実施形態に係る半導体装置を示す断面図である。It is a cross-sectional view showing a semiconductor device according to a second embodiment.

以下に、各実施形態について図面を参照しつつ説明する。
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。さらに、本願明細書と各図において、既出の図に関して説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。 Each embodiment will be described below with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each portion, the size ratio between portions, and the like are not necessarily the same as the actual ones. Also, even when the same parts are shown, the dimensions and ratios may be different depending on the drawing. Furthermore, in the present specification and each figure, the same reference numerals are given to the same elements as those explained with respect to the previous figures, and detailed explanation thereof will be omitted as appropriate.

（第１実施形態）
図１は、本実施形態に係る半導体装置を示す平面図である。図２は、本実施形態に係る半導体チップを示す一部拡大斜視図である。図３は、図２に示すＡ－Ａ’線による断面図である。 (First embodiment)
FIG. 1 is a plan view showing a semiconductor device according to this embodiment. FIG. 2 is a partially enlarged perspective view showing the semiconductor chip according to this embodiment. FIG. 3 is a cross-sectional view taken along line AA' shown in FIG.

図１、図２に示すように、本実施形態の半導体装置１０１は、例えばアナログ回路を構成する半導体チップ１と、外部接続用の配線が設けられたリードフレーム６と、これらを接続する複数の第１ワイヤ４１及び複数の第２ワイヤ４２と、を含む。半導体チップ１は、リードフレーム６上に固定されて配置されている。半導体チップ１は、チップ本体１１と、複数の第１電極２１と、複数の第２電極２２と、複数の導電部材３１と、を有する。チップ本体１１は、互いに対向する上面１１Ａ及び下面１１Ｂと、上面１１Ａ及び下面１１Ｂに接する４つの側面１１Ｃから成る略立方体形状である。 As shown in FIGS. 1 and 2, the semiconductor device 101 of the present embodiment includes a semiconductor chip 1 forming, for example, an analog circuit, a lead frame 6 provided with wiring for external connection, and a plurality of wires connecting them. A first wire 41 and a plurality of second wires 42 are included. A semiconductor chip 1 is fixedly arranged on a lead frame 6 . The semiconductor chip 1 has a chip body 11 , multiple first electrodes 21 , multiple second electrodes 22 , and multiple conductive members 31 . The chip body 11 has a substantially cubic shape including an upper surface 11A and a lower surface 11B facing each other and four side surfaces 11C in contact with the upper surface 11A and the lower surface 11B.

本明細書においては、説明の便宜上、半導体チップ１の厚み方向において、チップ本体１１の下面１１Ｂから上面１１Ａに向かう方向を「上」といい、上面１１Ａから下面１１Ｂに向かう方向を「下」という。 In this specification, for convenience of explanation, in the thickness direction of the semiconductor chip 1, the direction from the lower surface 11B to the upper surface 11A of the chip body 11 is called "up", and the direction from the upper surface 11A to the lower surface 11B is called "down". .

チップ本体１１は、例えばアナログ制御回路を内含する。第１電極２１、第２電極２２は、チップ本体１１の上面１１Ａにそれぞれ複数設けられている。第１電極２１及び第２電極２２は、上面１１Ａにおいて交互に配列されている。図２に示す例では、第１電極２１及び第２電極２２は、上面１１Ａの端縁に沿って２列に配列されている。第１電極２１、第２電極２２は、板形状を成し、チップ本体１１に内包されたアナログ制御回路にそれぞれ接続されている。第１電極２１の上面には、導電部材３１が配置されている。第２電極２２の上面には、導電部材３１は配置されていない。第１電極２１及び第２電極２２の配列方向において、上面に導電部材３１が設けられた第１電極２１の幅は、上面に導電部材３１が設けられていない第２電極２２の幅よりも小さい。
また、上面１１Ａには、第１電極２１及び第２電極２２を囲んだ保護膜（図示せず）が設けられている。保護膜は、上面が第１電極２１、第２電極２２の上面２１ａ、２２ａよりやや上に位置し、上面２１ａ、２２ａの端縁を覆い、それ以外の部分は覆っていない。保護膜は、例えばポリイミドを含んでいる。 The chip body 11 includes, for example, an analog control circuit. A plurality of the first electrodes 21 and the second electrodes 22 are provided on the upper surface 11A of the chip body 11, respectively. The first electrodes 21 and the second electrodes 22 are alternately arranged on the upper surface 11A. In the example shown in FIG. 2, the first electrodes 21 and the second electrodes 22 are arranged in two rows along the edge of the upper surface 11A. The first electrode 21 and the second electrode 22 are plate-shaped and are connected to an analog control circuit included in the chip body 11 . A conductive member 31 is arranged on the upper surface of the first electrode 21 . The conductive member 31 is not arranged on the upper surface of the second electrode 22 . In the arrangement direction of the first electrode 21 and the second electrode 22, the width of the first electrode 21 with the conductive member 31 provided on the top surface is smaller than the width of the second electrode 22 with the conductive member 31 not provided on the top surface. .
A protective film (not shown) surrounding the first electrode 21 and the second electrode 22 is provided on the upper surface 11A. The top surface of the protective film is located slightly above the top surfaces 21a and 22a of the first electrode 21 and the second electrode 22, covers the edges of the top surfaces 21a and 22a, and does not cover the other portions. The protective film contains polyimide, for example.

第１ワイヤ４１は、第１電極２１とリードフレーム６の対応する電極を曲線状に繋いでいる。第２ワイヤ４２は、第２電極２２とリードフレーム６の対応する電極を曲線状に繋いでいる。第１ワイヤ４１の両端には、半導体チップ１の第１電極２１に接続された第１ボンディング部４１ａと、リードフレーム６に接続された第２ボンディング部がそれぞれ形成されている。第２ワイヤ４２の両側には、半導体チップ１の第１電極２１に接続された第１ボンディング部４２ａと、リードフレーム６に接続された第２ボンディング部がそれぞれ形成されている。第１ワイヤ４１の第１ボンディング部４１ａは、導電部材３１の上面に接合されて第１電極２１と接続されている。第２ワイヤ４２の第１ボンディング部４２ａは、第２電極２２の上面に接合されている。第１、第２ワイヤ４１、４２の第２ボンディング部は、リードフレーム６の各部に接続されている。このようにして、半導体チップ１の第１電極２１及び第２電極２２は、第１ワイヤ４１及び第２ワイヤ４２を介して、リードフレーム６に接続されている。 The first wire 41 connects the first electrode 21 and the corresponding electrode of the lead frame 6 in a curved shape. The second wire 42 connects the second electrode 22 and the corresponding electrode of the lead frame 6 in a curved shape. A first bonding portion 41 a connected to the first electrode 21 of the semiconductor chip 1 and a second bonding portion connected to the lead frame 6 are formed at both ends of the first wire 41 . A first bonding portion 42 a connected to the first electrode 21 of the semiconductor chip 1 and a second bonding portion connected to the lead frame 6 are formed on both sides of the second wire 42 . A first bonding portion 41 a of the first wire 41 is bonded to the upper surface of the conductive member 31 and connected to the first electrode 21 . A first bonding portion 42 a of the second wire 42 is bonded to the upper surface of the second electrode 22 . Second bonding portions of the first and second wires 41 and 42 are connected to respective portions of the lead frame 6 . Thus, the first electrode 21 and the second electrode 22 of the semiconductor chip 1 are connected to the lead frame 6 via the first wire 41 and the second wire 42 .

以下、本実施形態に係る半導体チップについて詳述する。
図３に示すように、第１電極２１と第２電極２２は、チップ本体１１の上面１１Ａにおいて隣り合って配置されている。本明細書においては、説明の便宜上、上面１１Ａにおいて第１電極２１と第２電極２２が並んだ方向のうちの一方向を「Ｘ方向」といい、上面１１ＡにおいてＸ方向に垂直な方向を「Ｙ方向」といい、半導体チップ１の厚み方向を「Ｚ方向」という。第１電極２１と第２電極２２は、Ｘ方向に互いに離隔し、Ｘ方向において交互にピッチＰ１で配置されている。 The semiconductor chip according to this embodiment will be described in detail below.
As shown in FIG. 3 , the first electrode 21 and the second electrode 22 are arranged adjacent to each other on the top surface 11A of the chip body 11 . In this specification, for convenience of explanation, one of the directions in which the first electrodes 21 and the second electrodes 22 are arranged on the upper surface 11A is referred to as the "X direction", and the direction perpendicular to the X direction on the upper surface 11A is referred to as the "X direction." The thickness direction of the semiconductor chip 1 is called the "Z direction". The first electrodes 21 and the second electrodes 22 are separated from each other in the X direction and arranged alternately at a pitch P1 in the X direction.

なお、Ｚ方向から見て、半導体チップ１の端縁はＸ方向及びＹ方向に延びている。Ｘ方向に延びる端縁に沿った領域では、第１電極２１と第２電極２２はＸ方向に沿って配列されており、Ｙ方向に延びる端縁に沿った領域では、第１電極２１と第２電極２２はＹ方向に沿って配列されている。本実施形態では、Ｘ方向に配列された第１電極２１及び第２電極２２について説明するが、Ｙ方向に配列された第１電極２１及び第２電極２２についても、同様である。 When viewed from the Z direction, the edges of the semiconductor chip 1 extend in the X and Y directions. In the region along the edge extending in the X direction, the first electrodes 21 and the second electrodes 22 are arranged along the X direction. The two electrodes 22 are arranged along the Y direction. Although the first electrodes 21 and the second electrodes 22 arranged in the X direction will be described in this embodiment, the same applies to the first electrodes 21 and the second electrodes 22 arranged in the Y direction.

第１電極２１は、上面２１ａと上面２１ａから連続する４つの側面２１ｃの上側とを、チップ本体１１の上面１１Ａにおいて露出して設けられている。第２電極２２は、上面２２ａと上面２２ａに連続する４つの側面２２ｃの上側とを、チップ本体１１の上面１１Ａにおいて露出して設けられている。第１電極２１のＸ方向の長さＬ１は、第２電極２２のＸ方向の長さＬ２よりも小さい。第１電極２１のＹ方向の長さは、例えば、第２電極２２のＹ方向の長さに等しい。また、第１電極２１の上面２１ａと第２電極２２の上面２２ａは、上面１１Ａからの高さが同じである。第１電極２１及び第２電極２２は、例えばアルミニウムを含む。 The first electrode 21 is provided on the upper surface 11A of the chip body 11 so that the upper surface 21a and the upper side of four side surfaces 21c continuous from the upper surface 21a are exposed. The second electrode 22 is provided on the upper surface 11A of the chip body 11 so that the upper surface 22a and the upper side of the four side surfaces 22c continuous with the upper surface 22a are exposed. The X-direction length L1 of the first electrode 21 is smaller than the X-direction length L2 of the second electrode 22 . The Y-direction length of the first electrode 21 is, for example, equal to the Y-direction length of the second electrode 22 . Further, the upper surface 21a of the first electrode 21 and the upper surface 22a of the second electrode 22 have the same height from the upper surface 11A. The first electrode 21 and the second electrode 22 contain aluminum, for example.

Ｘ方向における第１電極２１と第２電極２２の距離は、電極間長さＥＤである。電極間長さＥＤは、相互の絶縁状態を維持するのに必要な最小絶縁長以上であればよい。以上により、第１電極２１と第２電極２２のピッチＰ１は、Ｌ１／２＋Ｌ２／２＋ＥＤとなる。 The distance between the first electrode 21 and the second electrode 22 in the X direction is the inter-electrode length ED. The inter-electrode length ED may be equal to or greater than the minimum insulation length required to maintain mutual insulation. As described above, the pitch P1 between the first electrode 21 and the second electrode 22 is L1/2+L2/2+ED.

導電部材３１は、例えば円柱形状であり、その表面は、上面３１ａと、上面３１ａに対向する下面３１ｂと、上面３１ａ及び下面３１ｂに連続する側面３１ｃと、を含む。導電部材３１は、例えば金または銅を含み、使用する第１ワイヤ４１と同一の金属を含むことが好ましい。導電部材３１は、第１電極２１の上面２１ａ上に例えばめっき法によって形成されている。これにより、導電部材３１の下面３１ｂは、第１電極２１の上面２１ａに接し、導電部材３１は、第１電極２１と接続されている。 The conductive member 31 has, for example, a cylindrical shape, and its surface includes an upper surface 31a, a lower surface 31b facing the upper surface 31a, and a side surface 31c continuous with the upper surface 31a and the lower surface 31b. The conductive member 31 contains gold or copper, for example, and preferably contains the same metal as the first wire 41 used. The conductive member 31 is formed on the upper surface 21a of the first electrode 21 by plating, for example. Thereby, the lower surface 31 b of the conductive member 31 is in contact with the upper surface 21 a of the first electrode 21 and the conductive member 31 is connected to the first electrode 21 .

導電部材３１の直径、すなわち、円柱形状の直径をｄ１とする。この場合、導電部材３１は、Ｘ方向長さ及びＹ方向長さがｄ１となる。また、チップ本体１１の上面１１Ａを基準とした導電部材３１の上面３１ａの高さ、すなわち、Ｚ方向の長さをｈ１とする。高さｈ１は、上面１１Ａを基準とした第２電極２２の上面２２ａの高さＨＥよりも高い。Ｚ方向から見て、導電部材３１の下面３１ｂは、第１電極２１の上面２１ａ内に収まっている。したがって、直径ｄ１は、第１電極２１のＸ方向の長さＬ１以下であって第１電極２１のＹ方向の長さ以下である。なお、導電部材３１の形状は円柱形状には限定されず、Ｚ方向に延びた形状であればよく、例えば、角柱形状であってもよい。 Let d1 be the diameter of the conductive member 31, that is, the diameter of the cylindrical shape. In this case, the conductive member 31 has an X-direction length and a Y-direction length of d1. The height of the upper surface 31a of the conductive member 31 with respect to the upper surface 11A of the chip body 11, that is, the length in the Z direction is h1. The height h1 is higher than the height HE of the upper surface 22a of the second electrode 22 with respect to the upper surface 11A. The lower surface 31b of the conductive member 31 is contained within the upper surface 21a of the first electrode 21 when viewed from the Z direction. Therefore, the diameter d1 is equal to or less than the length L1 of the first electrode 21 in the X direction and equal to or less than the length of the first electrode 21 in the Y direction. The shape of the conductive member 31 is not limited to a columnar shape, and may be any shape extending in the Z direction, for example, a prismatic shape.

本実施形態に係る半導体チップ１においては、導電部材３１が第１電極２１に設けられており、導電部材３１に第１ワイヤ４１の第１ボンディング部４１ａが接合される。これにより、第１ボンディング部４１ａは、第２ワイヤ４２の第１ボンディング部４２ａに対してＺ方向における位置がずれる。このため、Ｘ方向に張り出した第１ボンディング部４１ａ、４２ａ間の距離が長くなる。また、導電部材３１の直径ｄ１は、第１ワイヤ４１の直径Ｄ以上に設定すればよく、導電部材３１は、第１電極２１の上面２１ａに収まればよい。これにより、導電部材３１のＸ方向長さを、第１ワイヤ４１の直径Ｄ程度まで小さくすれば、第１電極２１のＸ方向長さＬ１を、第１ワイヤ４１の直径Ｄ程度まで小さくすることができる。これに対して、第２電極２２には、第２ワイヤ４２の第１ボンディング部４２ａが収まる程度の広さが必要である。よって、第１電極２１のＸ方向長さＬ１は、第２電極２２のＸ方向長さＬ２よりも小さくできる。また、導電部材３１を第１電極２１上に形成しているので、第１電極２１のＸ方向長さＬ１を第１ボンディング部４１ａの最大直径ＭＤ１より小さくすることができる。 In the semiconductor chip 1 according to this embodiment, the conductive member 31 is provided on the first electrode 21 , and the first bonding portion 41 a of the first wire 41 is joined to the conductive member 31 . As a result, the first bonding portion 41a is displaced from the first bonding portion 42a of the second wire 42 in the Z direction. Therefore, the distance between the first bonding portions 41a and 42a projecting in the X direction is increased. Moreover, the diameter d1 of the conductive member 31 may be set equal to or larger than the diameter D of the first wire 41, and the conductive member 31 may be accommodated on the upper surface 21a of the first electrode 21. FIG. As a result, if the X-direction length of the conductive member 31 is reduced to about the diameter D of the first wire 41, the X-direction length L1 of the first electrode 21 can be reduced to about the diameter D of the first wire 41. can be done. On the other hand, the second electrode 22 needs to be wide enough to accommodate the first bonding portion 42a of the second wire 42 . Therefore, the X-direction length L1 of the first electrode 21 can be made smaller than the X-direction length L2 of the second electrode 22 . Moreover, since the conductive member 31 is formed on the first electrode 21, the X-direction length L1 of the first electrode 21 can be made smaller than the maximum diameter MD1 of the first bonding portion 41a.

以下、本実施形態に係る半導体装置について詳述する。
第１ワイヤ４１と第２ワイヤ４２は、金または銅を含む。直径Ｄは、例えば１８μｍ～３０μｍであり、例えば導電部材３１の直径ｄ１以下である。第１ワイヤ４１の第１ボンディング部４１ａは、導電部材３１の上面３１ａにボールボンディングによって接合されている。第１ボンディング部４１ａの形状は、予め形成された例えば球状体の下面中央を上面３１ａに押しつけながら接合されることによって、ＸＹ面に沿って広がった形状となる。第１ボンディング部４１ａの直径は、Ｚ方向の略中央において、最大直径ＭＤ１となる。第１ボンディング部４１ａは、導電部材３１の上面３１ａよりも大きくなっている。最大直径ＭＤ１は、例えば、第１ワイヤ４１の直径Ｄの２倍以上２．５倍以下である。 The semiconductor device according to this embodiment will be described in detail below.
The first wire 41 and the second wire 42 contain gold or copper. The diameter D is, for example, 18 μm to 30 μm, and is equal to or smaller than the diameter d1 of the conductive member 31, for example. A first bonding portion 41a of the first wire 41 is bonded to the upper surface 31a of the conductive member 31 by ball bonding. The shape of the first bonding portion 41a becomes a shape that spreads along the XY plane, for example, by bonding while pressing the center of the lower surface of a pre-formed spherical body against the upper surface 31a. The diameter of the first bonding portion 41a becomes the maximum diameter MD1 at substantially the center in the Z direction. The first bonding portion 41 a is larger than the top surface 31 a of the conductive member 31 . The maximum diameter MD1 is, for example, two times or more and 2.5 times or less the diameter D of the first wire 41 .

第１ボンディング部４１ａの最大直径ＭＤ１の部分よりも下の部分である下部４１ａａは、導電部材３１の側面３１ｃの上部及び上面３１ａを覆っている。これにより、第１ワイヤ４１と導電部材３１は、十分な接触面積を確保して接続されている。本形状は、ボールボンディング条件によって変更できるので、この形状に限られない。例えば、下部４１ａａは、導電部材３１の上面３１ａが押し込まれることにより、上面３１ａを覆い、かつ、上面３１ａの端縁を超えた状態で接合されてもよい。また、下部４１ａａは、上面３１ａの端縁を超えて、側面３１ｃの上部にわずかに対面していてもよい。さらに、下部４１ａａは、上面３１ａ及び側面３１ｃの上部に沿って上方に僅かに凹んでいてもよい。 A lower portion 41aa, which is a portion below the portion having the maximum diameter MD1 of the first bonding portion 41a, covers the upper portion of the side surface 31c of the conductive member 31 and the upper surface 31a. Thereby, the first wire 41 and the conductive member 31 are connected while ensuring a sufficient contact area. This shape is not limited to this shape because it can be changed depending on the ball bonding conditions. For example, the lower portion 41aa may cover the upper surface 31a by pushing the upper surface 31a of the conductive member 31, and may be joined in a state beyond the edge of the upper surface 31a. Also, the lower portion 41aa may slightly face the upper portion of the side surface 31c beyond the edge of the upper surface 31a. Further, the lower portion 41aa may be slightly recessed upward along the upper portions of the upper surface 31a and side surfaces 31c.

ボンディング後の第１ボンディング部４１ａのＺ方向の厚みｔ１は、例えば、１０μｍ以上２０μｍ以下である。下部４１ａａの上面１１Ａからの高さをＨ１とする。上述の如く、導電部材３１の上面３１ａの上面１１Ａからの高さは、ｈ１である。高さＨ１は、高さｈ１よりも下部４１ａａの中央が僅かに凹んだ分低くなっている。
第１ワイヤ４１の第２ボンディング部は、リードフレーム６の対応する部分に、例えばウエッジボンディングによって接合されている。 A thickness t1 in the Z direction of the first bonding portion 41a after bonding is, for example, 10 μm or more and 20 μm or less. Let H1 be the height of the lower portion 41aa from the upper surface 11A. As described above, the height of the upper surface 31a of the conductive member 31 from the upper surface 11A is h1. The height H1 is lower than the height h1 by the amount that the center of the lower portion 41aa is slightly recessed.
A second bonding portion of the first wire 41 is bonded to a corresponding portion of the lead frame 6 by wedge bonding, for example.

第２ワイヤ４２の第１ボンディング部４２ａは、第２電極２２の上面２２ａにボールボンディングによって接合されている。第１ボンディング部４２ａの形状は、予め形成された球状体を第２電極２２の上面２２ａに上から押しつけながら接合されることにより、ＸＹ面に平行に広がった形状である。第１ボンディング部４２ａは、第２電極２２の上面２２ａに収まって形成されている。下面４２ａａは、第２電極２２の上面２２ａに接した面である。このようにして、第２ワイヤ４２の第１ボンディング部４２ａは、第２電極２２と接続されている。 A first bonding portion 42a of the second wire 42 is bonded to the upper surface 22a of the second electrode 22 by ball bonding. The shape of the first bonding portion 42a is a shape that spreads in parallel with the XY plane by bonding while pressing a previously formed spherical body against the upper surface 22a of the second electrode 22 from above. The first bonding portion 42 a is formed so as to fit on the upper surface 22 a of the second electrode 22 . The lower surface 42 aa is a surface in contact with the upper surface 22 a of the second electrode 22 . Thus, the first bonding portion 42 a of the second wire 42 is connected to the second electrode 22 .

第１ボンディング部４２ａは、ＸＹ面において第２ワイヤ４２の最大直径ＭＤ２となる。最大直径ＭＤ２は、例えば、ワイヤ直径Ｄの２倍以上２．５倍以下である。また、最大直径ＭＤ２は、第２電極２２のＸ方向長さＬ２及び第２電極２２のＹ方向長さより小さい。ボンディング後の第１ボンディング部４２ａの上下方向の厚みｔ２は、１０μｍ以上２０μｍ以下である。 The first bonding portion 42a has the maximum diameter MD2 of the second wire 42 on the XY plane. The maximum diameter MD2 is, for example, two to 2.5 times the wire diameter D. Also, the maximum diameter MD2 is smaller than the X-direction length L2 of the second electrode 22 and the Y-direction length of the second electrode 22 . The vertical thickness t2 of the first bonding portion 42a after bonding is 10 μm or more and 20 μm or less.

チップ本体１１の上面１１Ａを基準とした第１ボンディング部４２ａの上端の高さをＨ２とする。高さＨ２は、第１ワイヤ４１の第１ボンディング部４１ａの下部４１ａａの高さＨ１よりも低い。また、導電部材３１の上面３１ａの高さｈ１は、第２ワイヤ４２の第１ボンディング部４２ａの高さＨ２よりも高い。さらに、第１ワイヤ４１の第１ボンディング部４１ａと第２ワイヤの第１ボンディング部４２ａの距離であるボンディング間距離ＢＢ１は、相互の絶縁状態を維持するのに必要な最小絶縁長以上である。
第２ワイヤ部の第２ボンディング部は、リードフレーム６の対応する位置に、例えばウエッジボンディングによって接合されている。 The height of the upper end of the first bonding portion 42a with respect to the upper surface 11A of the chip body 11 is assumed to be H2. The height H2 is lower than the height H1 of the lower portion 41aa of the first bonding portion 41a of the first wire 41 . Also, the height h1 of the upper surface 31a of the conductive member 31 is higher than the height H2 of the first bonding portion 42a of the second wire 42 . Furthermore, the inter-bonding distance BB1, which is the distance between the first bonding portion 41a of the first wire 41 and the first bonding portion 42a of the second wire, is greater than or equal to the minimum insulation length required to maintain mutual insulation.
A second bonding portion of the second wire portion is bonded to a corresponding position of the lead frame 6 by wedge bonding, for example.

以上により、最大直径ＭＤ１となる第１ボンディング部４１ａは、直径Ｄである第２ワイヤ４２とＸ方向に並んで配置され、第２ワイヤ４２の最大直径ＭＤ２となる第１ボンディング部４２ａは、Ｘ方向長さがｄ１となる導電部材３１とＸ方向に並んで配置されている。また、最大直径ＭＤ１、ＭＤ２となる第１ボンディング部４１ａ、４２ａ同士は、Ｘ方向及びＺ方向に離隔して形成されている。 As described above, the first bonding portion 41a having the maximum diameter MD1 is arranged side by side with the second wire 42 having the diameter D in the X direction, and the first bonding portion 42a having the maximum diameter MD2 of the second wire 42 is arranged in the X direction. It is arranged side by side with the conductive member 31 whose direction length is d1 in the X direction. Also, the first bonding portions 41a and 42a having the maximum diameters MD1 and MD2 are formed apart from each other in the X direction and the Z direction.

以下、本実施形態に係る半導体装置１０１の製造方法について説明する。
半導体チップ１をリードフレーム６に載置して固定する。チップ本体１１の下面１１Ｂを下にしてリードフレーム６の所定箇所に載置する。半導体チップの複数の第１、第２電極２１、２２とリードフレーム６における対応する複数の部分を、それぞれワイヤボンディングによって接続する。 A method for manufacturing the semiconductor device 101 according to this embodiment will be described below.
A semiconductor chip 1 is placed on a lead frame 6 and fixed. The chip body 11 is placed on a predetermined position of the lead frame 6 with the lower surface 11B of the chip body 11 facing downward. The plurality of first and second electrodes 21 and 22 of the semiconductor chip and the corresponding portions of the lead frame 6 are connected by wire bonding.

図４は、本実施形態に係る半導体装置のボールボンディングを示す拡大図である。第２電極２２に、第２ワイヤ４２を接合する。ワイヤボンディングには、中空部にボンディング前の第１、第２ワイヤ４１、４２を含むワイヤを通したキャピラリＣＰを使用する。キャピラリＣＰの先端から突出させた第２ワイヤ４２の先端に、例えば電気トーチから放電することによって第２ワイヤ４２の先端を溶融させて、球状体を形成する。球状体の直径は、例えば、第２ワイヤ４２の直径Ｄの約２倍である。第２ワイヤ４２の先端の球状体を、第２電極２２の上面２２ａに接触させて荷重と超音波を印加することによって第２ワイヤ４２の先端を第２電極２２の上面２２ａに接合する。これにより第２ワイヤ４２の第１ボンディング部４２ａが第２電極２２の上面２２ａに形成される。 FIG. 4 is an enlarged view showing ball bonding of the semiconductor device according to this embodiment. A second wire 42 is joined to the second electrode 22 . For wire bonding, a capillary CP is used in which wires including the first and second wires 41 and 42 before bonding are passed through the hollow portion. The tip of the second wire 42 protruding from the tip of the capillary CP is melted by, for example, electric discharge from an electric torch to form a spherical body. The diameter of the spherical body is, for example, approximately twice the diameter D of the second wire 42 . The spherical body at the tip of the second wire 42 is brought into contact with the upper surface 22a of the second electrode 22, and a load and ultrasonic waves are applied to bond the tip of the second wire 42 to the upper surface 22a of the second electrode 22. Thereby, the first bonding portion 42 a of the second wire 42 is formed on the upper surface 22 a of the second electrode 22 .

キャピラリＣＰを引き上げながら第２ワイヤ４２を繰り出し、第２電極２２に対応するリードフレーム６の部分にキャピラリＣＰの先端から出た第２ワイヤ４２の一部分を接触させ、荷重と超音波を印加して接合し、クランパで第２ワイヤ４２を挟んだ状態でキャピラリＣＰを引き上げてテールカットする。これにより、第２ワイヤ４２を介して第２電極２２とリードフレーム６が接続される。 The second wire 42 is let out while pulling up the capillary CP, a part of the second wire 42 protruding from the tip of the capillary CP is brought into contact with the part of the lead frame 6 corresponding to the second electrode 22, and a load and ultrasonic waves are applied. After joining, the capillary CP is pulled up with the clamper holding the second wire 42 to cut the tail. Thereby, the second electrode 22 and the lead frame 6 are connected via the second wire 42 .

次に、導電部材３１に第１ワイヤ４１を接合する。キャピラリＣＰの先端から突出させた第１ワイヤ４１の先端にも、同様に球状体を形成する。この球状体を導電部材３１の上面３１ａに接触させて同様に接合し、第１ワイヤ４１の第１ボンディング部４１ａが導電部材３１の上面３１ａに接合される。次に、キャピラリＣＰから第１ワイヤ４１を繰り出して、リードフレーム６の対応する部分に接触させて接合し、同様にテールカットする。これにより、第１ワイヤ４１と導電部材３１を介して第１電極２１とリードフレーム６の対応する部分が接続される。 Next, the first wire 41 is joined to the conductive member 31 . Similarly, the tip of the first wire 41 projecting from the tip of the capillary CP is also formed into a spherical body. This spherical body is brought into contact with the upper surface 31 a of the conductive member 31 and bonded in the same manner, and the first bonding portion 41 a of the first wire 41 is bonded to the upper surface 31 a of the conductive member 31 . Next, the first wire 41 is let out from the capillary CP, brought into contact with the corresponding portion of the lead frame 6 to be joined, and tail-cut in the same manner. As a result, the corresponding portions of the first electrode 21 and the lead frame 6 are connected via the first wire 41 and the conductive member 31 .

なお、本実施形態においては、第２ワイヤ４２を第２電極２２に接合した後、第１ワイヤ４１を導電部材３１に接合する例を説明したが、この順番は逆でもよい。但し、チップ本体１１の上面１１Ａを基準とすると、第２電極２２の上面２２ａは導電部材３１の上面３１ａよりも低いため、第１ワイヤ４１を導電部材に接合した後、第２ワイヤ４２を第２電極２２に接合すると、第２ワイヤ４２の接合時に、第１ワイヤ４１の第１ボンディング部４１ａが障害となり、作業性が低下する場合がある。これに対して、第２ワイヤ４２を第２電極２２に接合した後、第１ワイヤ４１を導電部材３１に接合すると、第１ワイヤ４１を導電部材３１にボンディングする際に、第２ワイヤ４２の第１ボンディング部４２ａが障害になりにくく、作業が容易である。また、本実施形態においては、ボールボンディングの作業性のために、導電部材３１のＸ方向長さとなる直径ｄ１を、第１ワイヤ４１及び第２ワイヤ４２の直径Ｄ以上としているが、これに限られない。導電部材３１のＸ方向長さとなる直径ｄ１は、ワイヤの直径Ｄ未満にしてもよい。 In this embodiment, the second wire 42 is joined to the second electrode 22, and then the first wire 41 is joined to the conductive member 31. However, this order may be reversed. However, when the upper surface 11A of the chip body 11 is used as a reference, the upper surface 22a of the second electrode 22 is lower than the upper surface 31a of the conductive member 31. Therefore, after the first wire 41 is joined to the conductive member, the second wire 42 is connected to the second wire 42. If the two electrodes 22 are joined, the first bonding portion 41a of the first wire 41 may become an obstacle when the second wire 42 is joined, which may reduce workability. On the other hand, if the first wire 41 is joined to the conductive member 31 after the second wire 42 is joined to the second electrode 22 , the second wire 42 is The first bonding portion 42a is unlikely to become an obstacle, and the work is easy. Further, in the present embodiment, the diameter d1, which is the X-direction length of the conductive member 31, is set to be equal to or larger than the diameter D of the first wire 41 and the second wire 42 for the sake of ball bonding workability. can't The diameter d1, which is the X-direction length of the conductive member 31, may be less than the diameter D of the wire.

以下、本実施形態に係る効果について説明する。
本実施形態に係る半導体チップ１は、導電部材３１を第１電極２１の上面２１ａに設け、導電部材３１の上面３１ａをワイヤ接合面にしている。これにより、第１電極２１の少なくともＸ方向長さを第１ボンディング部４１ａよりも小さくすることで、第１、第２電極２１、２２のピッチＰ１も小さくし、省面積化することができる。また、導電部材３１の上面３１ａは、隣接する第２電極２２のワイヤ接合面である上面２２ａよりも高くして、隣接するＸ方向に張り出した第１ボンディング部４１ａ、４２ａの位置を上下方向にずらしてボンディング間距離ＢＢ１を長くすることができる。したがって、本実施形態によれば、半導体チップ１の絶縁性を維持しながらも省面積化することができる。 The effects of this embodiment will be described below.
In the semiconductor chip 1 according to this embodiment, the conductive member 31 is provided on the upper surface 21a of the first electrode 21, and the upper surface 31a of the conductive member 31 is used as the wire bonding surface. Accordingly, by making at least the X-direction length of the first electrode 21 smaller than that of the first bonding portion 41a, the pitch P1 between the first and second electrodes 21 and 22 can also be made small, and the area can be saved. In addition, the upper surface 31a of the conductive member 31 is set higher than the upper surface 22a, which is the wire bonding surface of the adjacent second electrode 22, so that the positions of the adjacent first bonding portions 41a and 42a projecting in the X direction are vertically aligned. By shifting, the inter-bonding distance BB1 can be lengthened. Therefore, according to the present embodiment, it is possible to save the area while maintaining the insulating properties of the semiconductor chip 1 .

また、本実施形態に係る半導体装置１０１は、最大直径ＭＤ１となる第１ワイヤ４１の第１ボンディング部４１ａと第２ワイヤ４２の直径Ｄの部分を、Ｘ方向に並んで配置し、最大直径ＭＤ２となる第２ワイヤ４２の第１ボンディング部４２ａとＸ方向長さがｄ１となる導電部材３１を、Ｘ方向に並んで配置する。これにより、半導体チップ１及び半導体装置１０１のワイヤボンディング箇所の省面積化及び省容積化することができる。 Further, in the semiconductor device 101 according to the present embodiment, the first bonding portion 41a of the first wire 41 having the maximum diameter MD1 and the portion having the diameter D of the second wire 42 are arranged side by side in the X direction, and the maximum diameter MD2 The first bonding portion 42a of the second wire 42 and the conductive member 31 having an X-direction length of d1 are arranged side by side in the X-direction. As a result, it is possible to reduce the area and volume of wire bonding portions of the semiconductor chip 1 and the semiconductor device 101 .

また、本実施形態に係る半導体装置１０１は、ボールボンディング作業によって第１ボンディング部４１ａは、導電部材３１の上面３１ａを覆い、かつ、上面３１ａの端縁を超えた状態で接合することができる。これにより、第１ボンディング部４１ａと導電部材３１の接合強度が良好となる。また、第１ボンディング部４１ａの下部４１ａａが上面３１ａによって僅かに上方に凹ませた場合は、更に接合強度が良好となる。さらに、第１ボンディング部４１ａが、導電部材３１の側面３１ｃの上部まで覆った場合は、第１ボンディング部４１ａと導電部材３１との接触面積が増加するため、接合強度をさらに良好にすることができるとともに、接触抵抗を低減することができる。 Further, in the semiconductor device 101 according to the present embodiment, the first bonding portion 41a can cover the upper surface 31a of the conductive member 31 and can be joined beyond the edge of the upper surface 31a by the ball bonding operation. Thereby, the bonding strength between the first bonding portion 41a and the conductive member 31 is improved. Moreover, when the lower portion 41aa of the first bonding portion 41a is slightly recessed upward by the upper surface 31a, the bonding strength is further improved. Furthermore, when the first bonding portion 41a covers up to the upper portion of the side surface 31c of the conductive member 31, the contact area between the first bonding portion 41a and the conductive member 31 increases, so that the bonding strength can be further improved. In addition, the contact resistance can be reduced.

また、本実施形態においては、導電部材３１の直径ｄ１を、第１ワイヤ４１の直径Ｄ以上であって直径Ｄに近い値に設定し、第１電極２１のＸ方向長さＬ１を、導電部材３１の直径ｄ１より大きくかつ直径ｄ１に近い値に設定している。これにより、第１ボンディング部４１ａを導電部材３１に押し付けるワイヤボンディング作業の安定性を確保しつつ、半導体装置１０１の省面積化を図ることができる。 Further, in the present embodiment, the diameter d1 of the conductive member 31 is set to a value equal to or larger than the diameter D of the first wire 41 and close to the diameter D, and the X-direction length L1 of the first electrode 21 is set to It is set to a value larger than the diameter d1 of 31 and close to the diameter d1. As a result, the area of the semiconductor device 101 can be saved while ensuring the stability of the wire bonding operation for pressing the first bonding portion 41a against the conductive member 31. FIG.

次に、導電部材を使用しない比較例について説明する。
図５は、比較例に係る半導体装置を示す断面図である。本比較例に係る半導体チップ９においては、本比較例の第１電極２０１と第２電極２０２は、本実施形態の第２電極２２と同一の形状であり、Ｘ方向の長さはＬ２である。第１電極２０１と第２電極２０２は、チップ本体１１の上面１１ＡにおいてＸ方向にピッチＰＰで並んでいる。第１電極２０１と第２電極２０２間の電極間長さは、本実施形態と同様にＥＤである。 Next, a comparative example using no conductive member will be described.
FIG. 5 is a cross-sectional view showing a semiconductor device according to a comparative example. In the semiconductor chip 9 according to this comparative example, the first electrode 201 and the second electrode 202 of this comparative example have the same shape as the second electrode 22 of this embodiment, and the length in the X direction is L2. . The first electrode 201 and the second electrode 202 are arranged on the upper surface 11A of the chip body 11 at a pitch PP in the X direction. The inter-electrode length between the first electrode 201 and the second electrode 202 is ED as in the present embodiment.

第１電極２０１は、上面２０１ａに第１ワイヤ４０１が接続され、第２電極２０２は、上面２０２ａに第２ワイヤ４０２が接続されている。第１ワイヤ４０１と第２ワイヤ４０２は、直径Ｄのワイヤを使用する。第１ワイヤ４０１は、第１電極２０１の上面２０１ａに直接ボールボンディングされ、第２ワイヤ４０２は、第２電極２０２の上面２０２ａに直接ボールボンディングされている。第１ワイヤ４０１の第１ボンディング部４０１ａの最大直径、及び、第２ワイヤ４０２の第１ボンディング部４０２ａの最大直径は、本実施形態の第２ワイヤ４２の第１ボンディング部４２ａと同様に、最大直径ＭＤ２である。よって、第１ボンディング部４０１ａのＺ方向における位置と、第１ボンディング部４０２ａのＺ方向の位置は同じである。このため、第１ボンディング部４０１ａと第１ボンディング部４０２ａの接触を回避するためには、第１電極２０１及び第２電極２０２のＸ方向における長さＬ２を、最大直径ＭＤ２より大きくする必要がある。この結果、半導体チップ９が大型化する。これに対し、本実施形態におけるＸ方向長さＬ１は、直径Ｄより大きくかつ直径Ｄに近似させた直径ｄ１より大きくすればよいので、Ｌ２に比して小さくできる。この結果、半導体チップ１を小型化できる。 The first electrode 201 has a first wire 401 connected to its upper surface 201a, and the second electrode 202 has a second wire 402 connected to its upper surface 202a. Wires of diameter D are used for the first wire 401 and the second wire 402 . The first wire 401 is directly ball-bonded to the top surface 201 a of the first electrode 201 , and the second wire 402 is directly ball-bonded to the top surface 202 a of the second electrode 202 . The maximum diameter of the first bonding portion 401a of the first wire 401 and the maximum diameter of the first bonding portion 402a of the second wire 402 are the same as the first bonding portion 42a of the second wire 42 of the present embodiment. It has a diameter MD2. Therefore, the position of the first bonding portion 401a in the Z direction is the same as the position of the first bonding portion 402a in the Z direction. Therefore, in order to avoid contact between the first bonding portion 401a and the first bonding portion 402a, the length L2 in the X direction of the first electrode 201 and the second electrode 202 needs to be larger than the maximum diameter MD2. . As a result, the semiconductor chip 9 becomes large. On the other hand, the X-direction length L1 in this embodiment may be larger than the diameter D and larger than the diameter d1 approximated to the diameter D, so it can be made smaller than L2. As a result, the semiconductor chip 1 can be miniaturized.

また、比較例における第１電極２０１と第２電極２０２のピッチＰＰは、２×Ｌ２／２＋ＥＤとなり、本実施形態の第１電極２１と第２電極２２のピッチＰ１より大きい。 Also, the pitch PP between the first electrode 201 and the second electrode 202 in the comparative example is 2×L2/2+ED, which is larger than the pitch P1 between the first electrode 21 and the second electrode 22 in this embodiment.

また、比較例においては、最大直径ＭＤ２となる第１、第２ワイヤ４０１、４０２の第１ボンディング部４０１ａ、４０２ａは、Ｘ方向に離隔し、第１、第２ワイヤ４０１、４０２の直径Ｄとなる部分同士がＸ方向に大きく離隔しているので、ワイヤボンディング箇所の占有面積及び占有容積が大きい。 In the comparative example, the first bonding portions 401a and 402a of the first and second wires 401 and 402 having the maximum diameter MD2 are spaced apart in the X direction so that the diameter D of the first and second wires 401 and 402 Since these portions are separated greatly in the X direction, the area and volume occupied by the wire bonding portion are large.

さらに、比較例における第１ボンディング部４０１ａ、４０２ａは、第１電極２０１と第２電極２０２の上面２０１ａ、２０２ａに対して面で接合し、第１ボンディング部４０１ａ、４０２ａの下面４０１ａａ、４０２ａａは、平坦な面である。これに対し、本実施形態における第１ボンディング部４１ａは、下部４１ａａを導電部材３１の上面３１ａによって僅かに凹ませた場合は、省面積化しながらも、接合強度を強化し、接触抵抗を低減することができる。 Furthermore, the first bonding portions 401a and 402a in the comparative example are surface-bonded to the upper surfaces 201a and 202a of the first electrode 201 and the second electrode 202, and the lower surfaces 401aa and 402aa of the first bonding portions 401a and 402a are It is a flat surface. In contrast, when the lower portion 41aa of the first bonding portion 41a in the present embodiment is slightly recessed by the upper surface 31a of the conductive member 31, the bonding strength is enhanced and the contact resistance is reduced while saving the area. be able to.

（第２実施形態）
本実施形態は、第１の実施形態と比較して、第２電極上にも導電部材が設けられている点が異なっている。 (Second embodiment)
This embodiment differs from the first embodiment in that a conductive member is also provided on the second electrode.

図６は、第２実施形態に係る半導体装置を示す断面図である。図６に示すように、本実施形態に係る半導体チップ２は、第１導電部材３２と第２導電部材３３を含む。第１導電部材３２と第２導電部材３３の高さは、相互に異なっている。第１導電部材３２は、第１電極２１に接合され、第１ワイヤ４１がボンディングされている。第２導電部材３３は、第２電極２３に接合され、第２ワイヤ４３がボンディングされている。 FIG. 6 is a cross-sectional view showing the semiconductor device according to the second embodiment. As shown in FIG. 6, the semiconductor chip 2 according to this embodiment includes a first conductive member 32 and a second conductive member 33 . The heights of the first conductive member 32 and the second conductive member 33 are different from each other. The first conductive member 32 is joined to the first electrode 21 and the first wire 41 is bonded. The second conductive member 33 is joined to the second electrode 23 and the second wire 43 is bonded.

本実施形態に係る半導体チップ２においては、第２電極２３上にも第２導電部材３３が設けられているため、第２電極２３のＸ方向の長さを第１電極２１と同様に短くすることができる。したがって、第２電極２３は、Ｘ方向の長さを第１電極２１と同様にＬ１にする。Ｘ方向に並んだ第１電極２１と第２電極２３の間の電極間長さは、第１実施形態と同じように絶縁性を担保するため、ＥＤとする。したがって、第１電極２１と第２電極２３のＸ方向のピッチＰ２は、Ｌ１＋ＥＤとなる。 In the semiconductor chip 2 according to the present embodiment, since the second conductive member 33 is also provided on the second electrode 23, the length of the second electrode 23 in the X direction is shortened similarly to the first electrode 21. be able to. Therefore, the length of the second electrode 23 in the X direction is set to L<b>1 like the first electrode 21 . The inter-electrode length between the first electrode 21 and the second electrode 23 arranged in the X direction is set to ED in order to ensure insulation as in the first embodiment. Therefore, the pitch P2 in the X direction between the first electrode 21 and the second electrode 23 is L1+ED.

第２導電部材３３は例えば円柱形状であり、その表面は上面３３ａと、上面３３ａに対向する下面３３ｂと、上面３３ａ及び下面３３ｂに接する側面３３ｃからなる。第２導電部材３３は、下面３３ｂを第２電極２３の上面２３ａに接している。これにより、第２導電部材３３は、第２電極２３と接続されている。 The second conductive member 33 has, for example, a columnar shape, and has an upper surface 33a, a lower surface 33b facing the upper surface 33a, and side surfaces 33c in contact with the upper surface 33a and the lower surface 33b. The second conductive member 33 has a lower surface 33 b in contact with the upper surface 23 a of the second electrode 23 . Thereby, the second conductive member 33 is connected to the second electrode 23 .

Ｚ方向から見て、第２導電部材３３の下面３３ｂは、第２電極２３の上面２３ａ内に収まっている。第２導電部材３３の直径は、例えば第１導電部材３２の直径と同じｄ１であり、第２導電部材３３は、Ｘ方向長さ及びＹ方向長さがｄ１となる。直径ｄ１は、第２電極２３のＸ方向長さＬ１以下であって第２電極２３のＹ方向長さ以下である。また、直径ｄ１は、使用する第２ワイヤ４３の直径Ｄ以上であることが好ましい。 The lower surface 33b of the second conductive member 33 is contained within the upper surface 23a of the second electrode 23 when viewed from the Z direction. The diameter of the second conductive member 33 is, for example, d1, which is the same as the diameter of the first conductive member 32, and the second conductive member 33 has an X-direction length and a Y-direction length of d1. The diameter d1 is equal to or less than the X-direction length L1 of the second electrode 23 and equal to or less than the Y-direction length of the second electrode 23 . Also, the diameter d1 is preferably equal to or greater than the diameter D of the second wire 43 used.

第２導電部材３３の上面３３ａの高さ、すなわち、Ｚ方向における上面１１Ａと上面３３ａとの距離をｈ４とする。また、第１導電部材３２の上面３２ａの高さ、すなわち、Ｚ方向における上面１１Ａと上面３２ａとの距離をｈ３とする。高さｈ４は高さｈ３よりも低い。高さｈ３と高さｈ４との差は、後述する第２ワイヤ４３の第１ボンディング部４３ａの厚さｔ１と最小絶縁長の和以上である。厚さｔ１は、規格によって定められ、例えば１０μｍ以上である。 Let h4 be the height of the upper surface 33a of the second conductive member 33, that is, the distance between the upper surface 11A and the upper surface 33a in the Z direction. The height of the upper surface 32a of the first conductive member 32, that is, the distance between the upper surface 11A and the upper surface 32a in the Z direction is h3. Height h4 is lower than height h3. The difference between the height h3 and the height h4 is equal to or greater than the sum of the thickness t1 of the first bonding portion 43a of the second wire 43 described below and the minimum insulation length. The thickness t1 is defined by standards and is, for example, 10 μm or more.

本実施形態に係る半導体チップ２は、第１電極２１に高さｈ３である第１導電部材３２を設け、第１導電部材３２に第１ワイヤ４１を接合し、第２電極２３に高さｈ４である第２導電部材３３を設け、第２導電部材３３に第２ワイヤ４３を接合している。これにより、第１ボンディング部４１ａと第１ボンディング部４３ａの距離をＺ方向に長くして、絶縁性を保っている。また、Ｘ方向においては、第１導電部材３２と第２導電部材３３の直径ｄ１を、第１ワイヤ４１と第２ワイヤ４３の直径Ｄに近い値まで小さくし、第１電極２１と第２電極２３のＸ方向長さＬ１を、直径ｄ１より長く、かつ、直径ｄ１に近い値にすることができる。 In the semiconductor chip 2 according to the present embodiment, the first electrode 21 is provided with the first conductive member 32 having a height of h3, the first wire 41 is joined to the first conductive member 32, and the second electrode 23 is provided with a height of h4. is provided, and the second wire 43 is joined to the second conductive member 33 . As a result, the distance between the first bonding portion 41a and the first bonding portion 43a is increased in the Z direction to maintain insulation. In the X direction, the diameter d1 of the first conductive member 32 and the second conductive member 33 is reduced to a value close to the diameter D of the first wire 41 and the second wire 43, and the first electrode 21 and the second electrode The X-direction length L1 of 23 can be set to a value longer than the diameter d1 and close to the diameter d1.

本実施形態に係る半導体装置１０２においては、第２ワイヤ４３の第１ボンディング部４３ａは、第２導電部材３３の上面３３ａにボールボンディングによって接合されている。第１、第２ワイヤ４１、４３の第１ボンディング部４１ａ、４３ａの形状は、第１実施形態の第１ワイヤ４１の第１ボンディング部４１ａと同一条件により接合されて形成される。よって、第１ボンディング部４１ａ、４３ａは、略中央において最大直径ＭＤ１を構成する。第２ワイヤ４３の第１ボンディング部４３ａと、Ｘ方向に隣接する第１導電部材３２の最短距離ＢＣは、最小絶縁長以上である。 In the semiconductor device 102 according to this embodiment, the first bonding portion 43a of the second wire 43 is bonded to the upper surface 33a of the second conductive member 33 by ball bonding. The shapes of the first bonding portions 41a and 43a of the first and second wires 41 and 43 are formed by bonding under the same conditions as the first bonding portion 41a of the first wire 41 of the first embodiment. Therefore, the first bonding portions 41a and 43a have a maximum diameter MD1 at substantially the center. The shortest distance BC between the first bonding portion 43a of the second wire 43 and the first conductive member 32 adjacent in the X direction is equal to or greater than the minimum insulation length.

第２ワイヤ４３の第１ボンディング部４３ａの上端の上面１１Ａからの高さＨ２は、第１ワイヤ４１の第１ボンディング部４１ａの下部４１ａａの上面１１Ａからの高さＨ１よりも低い。例えば、Ｈ１とＨ２の差は、最小絶縁長ＩＬ以上であることが好ましい。 The height H2 of the upper end of the first bonding portion 43a of the second wire 43 from the upper surface 11A is lower than the height H1 of the lower portion 41aa of the first bonding portion 41a of the first wire 41 from the upper surface 11A. For example, the difference between H1 and H2 is preferably equal to or greater than the minimum insulation length IL.

第１ボンディング部４１ａ、４３ａの間の長さであるボンディング間距離ＢＢ２は、最小絶縁長以上の長さである。また、第１ボンディング部４１ａと第２ワイヤ４３との最短距離ＢＷは、最小絶縁長以上の長さである。また、第１ボンディング部４１ａ、４３ａの一部は、Ｚ方向から見て重なり合っている。 A bonding-to-bonding distance BB2, which is the length between the first bonding portions 41a and 43a, is equal to or greater than the minimum insulation length. Also, the shortest distance BW between the first bonding portion 41a and the second wire 43 is equal to or longer than the minimum insulation length. Also, parts of the first bonding portions 41a and 43a overlap each other when viewed in the Z direction.

第１電極２１と第２電極２３は、同一の寸法に限らず、異なる寸法であってもよい。第１導電部材３２と第２導電部材３３の直径及び最大直径は、同一に限らず、異なる大きさであってもよい。 The first electrode 21 and the second electrode 23 are not limited to have the same dimensions, and may have different dimensions. The diameter and maximum diameter of the first conductive member 32 and the second conductive member 33 are not limited to the same, and may be different sizes.

以下に、本実施形態に係る半導体装置１０２の製造方法について説明する。
初めに、第１実施形態と同様に、上面１１Ａからの高さが低い第２導電部材３３に第２ワイヤ４３を接合していき、上面１１Ａからの高さが高い第１導電部材３２に第１ワイヤ４１を接合していく。 A method for manufacturing the semiconductor device 102 according to this embodiment will be described below.
First, as in the first embodiment, the second wire 43 is joined to the second conductive member 33 whose height from the upper surface 11A is low, and then the second wire 43 is joined to the first conductive member 32 whose height from the upper surface 11A is high. 1 wire 41 is spliced.

以下に、本実施形態に係る効果について説明する。
本実施形態に係る半導体チップ２は、第２導電部材３３を第２電極２３の上面２３ａにも設け、第２導電部材３３の上面３３ａをワイヤ接合面にしている。これにより、第２電極２３についても、少なくともＸ方向長さを第１ボンディング部４３ａよりも小さくして、第１、第２電極２１、２３のピッチＰ２を更に小さくして省面積化することができる。また、隣接する第１ボンディング部４１ａ、４３ａの位置を上下方向にずらしてボンディング間距離ＢＢ１を長くすることができる。本実施形態によれば、半導体チップ２の絶縁性を維持しながらも更に省面積化することができる。 The effects of this embodiment will be described below.
In the semiconductor chip 2 according to this embodiment, the second conductive member 33 is also provided on the upper surface 23a of the second electrode 23, and the upper surface 33a of the second conductive member 33 is used as the wire bonding surface. As a result, the second electrode 23 also has at least the length in the X direction smaller than that of the first bonding portion 43a, and the pitch P2 between the first and second electrodes 21 and 23 can be further reduced to save the area. can. Further, the positions of the adjacent first bonding portions 41a and 43a can be vertically shifted to increase the inter-bonding distance BB1. According to this embodiment, it is possible to further reduce the area while maintaining the insulating properties of the semiconductor chip 2 .

本実施形態に係る半導体装置１０２は、第１ワイヤ４１の第１ボンディング部４１ａと第２ワイヤ４３の直径Ｄの部分を、Ｘ方向に並んで配置し、第２ワイヤ４３の第１ボンディング部４３ａとＸ方向長さがｄ１である第１導電部材３２を、Ｘ方向に並んで配置するので、ワイヤボンディング箇所の省面積化及び省容積化をすることができるとともに、絶縁性を維持することができる。 In the semiconductor device 102 according to the present embodiment, the first bonding portion 41a of the first wire 41 and the portion of the diameter D of the second wire 43 are arranged side by side in the X direction, and the first bonding portion 43a of the second wire 43 is arranged. and the first conductive member 32 having an X-direction length of d1 are arranged side by side in the X-direction, so that it is possible to reduce the area and volume of the wire bonding portion and maintain the insulation. can.

本実施形態に係る半導体装置１０２は、上方から見て、第１ボンディング部４１ａ、４３ａの少なくとも一部は、互いに重なり合うように配置しているので、省面積化を図ることができる。 In the semiconductor device 102 according to the present embodiment, since at least a part of the first bonding portions 41a and 43a are arranged so as to overlap each other when viewed from above, area saving can be achieved.

本実施形態における上記以外の構成、製造方法、及び、効果は、第１の実施形態と同様である。 The configuration, manufacturing method, and effects of this embodiment other than those described above are the same as those of the first embodiment.

本発明の実施形態によれば、ワイヤボンディング部の省面積化を実現可能な半導体チップ及び半導体装置を実現することができる。 According to the embodiments of the present invention, it is possible to realize a semiconductor chip and a semiconductor device capable of realizing a reduction in the area of the wire bonding portion.

以上、具体例を参照しつつ、本発明の実施形態について説明した。しかし、本発明の実施形態は、これらの具体例に限定されるものではない。例えば、半導体チップに含まれる導電部材、ワイヤ、電極の形状、材質、配置の具体的な構成に関しては、当業者が公知の範囲から適宜選択することにより本発明を同様に実施し、同様の効果を得ることができる限り、本発明の範囲に包含される。各具体例のいずれか２つ以上の要素を技術的に可能な範囲で組み合わせたものも、本発明の要旨を包含する限り本発明の範囲に含まれる。 The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the invention are not limited to these specific examples. For example, a person skilled in the art can carry out the present invention in the same manner by appropriately selecting the specific configuration of the shape, material, and arrangement of the conductive members, wires, and electrodes included in the semiconductor chip from the ranges known to those skilled in the art, and the same effects can be obtained. is included in the scope of the present invention as long as it is possible to obtain Any combination of two or more elements of each specific example within the technically possible range is also included in the scope of the present invention as long as it encompasses the gist of the present invention.

本発明のいくつかの実施形態を説明したが、これらの実施形態は例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

１、２、９…半導体チップ
６…リードフレーム
１１…チップ本体
１１Ａ…上面
１１Ｂ…下面
１１Ｃ…側面
２１…第１電極
２２、２３…第２電極
２１ａ、２２ａ、２３ａ…上面
２１ｃ、２２ｃ，２３ｃ…側面
３１…導電部材
３２…第１導電部材
３３…第２導電部材
３１ａ、３２ａ、３３ａ…上面
３１ｂ、３２ｂ、３３ｂ…下面
３１ｃ、３２ｃ、３３ｃ…側面
４１…第１ワイヤ
４２、４３…第２ワイヤ
４１ａ、４２ａ、４３ａ…第１ボンディング部
４１ａａ、４３ａａ…下部
４２ａａ…下面
１０１、１０２、１０９…半導体装置
２０１…第１電極
２０２…第２電極
２０１ａ、２０２ａ…上面
２０１ｃ、２０２ｃ…側面
４０１…第１ワイヤ
４０２…第２ワイヤ
４０１ａ、４０２ａ…第１ボンディング部
ＢＢ１、ＢＢ２、ＢＣ、ＢＷ…距離
ＣＰ…キャピラリ
Ｄ…ワイヤの直径
ｄ１…導電部材の直径
ＥＤ…電極間長さ
Ｈ１、Ｈ２、ＨＥ…高さ
ｈ１、ｈ３、ｈ４…高さ
Ｌ１、Ｌ２…長さ
ＭＤ１、ＭＤ２…最大直径
Ｐ１、Ｐ２、ＰＰ…ピッチ
ｔ１、ｔ２…厚さ DESCRIPTION OF SYMBOLS 1, 2, 9... Semiconductor chip 6... Lead frame 11... Chip body 11A... Upper surface 11B... Lower surface 11C... Side surface 21... First electrode 22, 23... Second electrode 21a, 22a, 23a... Upper surface 21c, 22c, 23c... Side surface 31 Conductive member 32 First conductive member 33 Second conductive member 31a, 32a, 33a Upper surface 31b, 32b, 33b Lower surface 31c, 32c, 33c Side surface 41 First wire 42, 43 Second wire 41a, 42a, 43a... First bonding part 41aa, 43aa... Lower part 42aa... Lower surface 101, 102, 109... Semiconductor device 201... First electrode 202... Second electrode 201a, 202a... Upper surface 201c, 202c... Side surface 401... First first Wire 402 Second wire 401a, 402a First bonding portion BB1, BB2, BC, BW Distance CP Capillary D Wire diameter d1 Conductive member diameter ED Length between electrodes H1, H2, HE Height Height h1, h3, h4... Height L1, L2... Length MD1, MD2... Maximum diameter P1, P2, PP... Pitch t1, t2... Thickness

Claims (7)

半導体チップと、
第１ワイヤと、
第２ワイヤと、
を備え、
前記半導体チップは、
チップ本体と、
前記チップ本体の上面に設けられた第１電極と、
前記チップ本体の上面に設けられ、前記第１電極から第１方向に離隔し、前記第１方向における長さが前記第１方向における前記第１電極の長さよりも長い第２電極と、
前記第１電極の上面に接した第１導電部材と、
を有し、
前記第１ワイヤの第１ボンディング部は前記第１導電部材に接し、
前記第２ワイヤは前記第２電極に接続された半導体装置。 a semiconductor chip;
a first wire;
a second wire;
with
The semiconductor chip is
a chip body;
a first electrode provided on the top surface of the chip body;
a second electrode provided on the upper surface of the chip body, separated from the first electrode in a first direction, and having a length in the first direction longer than the length of the first electrode in the first direction;
a first conductive member in contact with the upper surface of the first electrode;
has
a first bonding portion of the first wire is in contact with the first conductive member;
The semiconductor device, wherein the second wire is connected to the second electrode . 前記第１導電部材の上端の位置は、前記第２電極の上面の位置よりも高い請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the upper end of said first conductive member is higher than the upper surface of said second electrode. 前記第１方向における前記第１導電部材の長さは、前記第１方向における前記第１電極の長さよりも短い請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the length of said first conductive member in said first direction is shorter than the length of said first electrode in said first direction. チップ本体と、前記チップ本体の上面に設けられた第１電極と、前記チップ本体の上面に設けられ、前記第１電極から第１方向に離隔した第２電極と、前記第１電極の上面に接した第１導電部材と、を有する半導体チップと、
第１ボンディング部が前記第１導電部材に接した第１ワイヤと、
前記第２電極に接続された第２ワイヤと、
を備え、
前記第１方向における前記第１導電部材の長さは、前記第１方向における前記第１ボンディング部の長さよりも短い半導体装置。 a chip body; a first electrode provided on an upper surface of the chip body; a second electrode provided on the upper surface of the chip body and separated from the first electrode in a first direction; a semiconductor chip having a first conductive member in contact;
a first wire having a first bonding portion in contact with the first conductive member;
a second wire connected to the second electrode;
with
A semiconductor device in which the length of the first conductive member in the first direction is shorter than the length of the first bonding portion in the first direction. 前記第１導電部材の形状は柱状であり、
前記第１ボンディング部は、前記第１導電部材の側面の上部及び上面を覆う請求項１～４のいずれか１つに記載の半導体装置。 The shape of the first conductive member is columnar,
5. The semiconductor device according to claim 1, wherein the first bonding portion covers an upper side surface and an upper surface of the first conductive member. 前記第１方向における前記第１電極の長さは、前記第１方向における前記第１ボンディング部の長さよりも短い請求項１～５のいずれか１つに記載の半導体装置。 6. The semiconductor device according to claim 1, wherein the length of said first electrode in said first direction is shorter than the length of said first bonding portion in said first direction. 前記第１導電部材の前記第１方向の長さは、前記第１ワイヤの直径以上であり、前記第１電極の前記第１方向の長さよりも小さい請求項１～６のいずれか１つに記載の半導体装置。 The length of the first conductive member in the first direction is equal to or greater than the diameter of the first wire and smaller than the length of the first electrode in the first direction. The semiconductor device described.
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