JP7235410B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7235410B2 JP7235410B2 JP2019526392A JP2019526392A JP7235410B2 JP 7235410 B2 JP7235410 B2 JP 7235410B2 JP 2019526392 A JP2019526392 A JP 2019526392A JP 2019526392 A JP2019526392 A JP 2019526392A JP 7235410 B2 JP7235410 B2 JP 7235410B2
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- oxide
- insulator
- conductor
- region
- transistor
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Description
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図1は、本発明の一態様に係るトランジスタ200、およびトランジスタ200周辺の上面図および断面図である。
図1に示すように、トランジスタ200は、絶縁体214と、絶縁体216と、導電体205(導電体205a、および導電体205b)と、絶縁体220と、絶縁体222と、絶縁体224と、絶縁体224の上に配置された酸化物230(酸化物230a、および酸化物230b)と、酸化物230cと、絶縁体250と、導電体260(導電体260a、および導電体260b)と、絶縁体270と、絶縁体272と、絶縁体275と、を有する。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばSOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、酸化物半導体として機能する金属酸化物(以下、酸化物半導体ともいう。)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud-Aligned Composite)-OSの構成について説明する。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC-OS(c-axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc-OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a-like OS:amorphous-like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記金属酸化物をトランジスタのチャネル形成領域に用いる場合について説明する。
ここで、金属酸化物中における各不純物の影響について説明する。
次に、図1に示す、本発明に係るトランジスタ200を有する半導体装置について、作製方法を図4乃至図24を用いて説明する。また、図4乃至図24において、各図の(A)は上面図を示す。また、各図の(B)は、(A)に示すA1-A2の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル長方向の断面図でもある。また、各図の(C)は、(A)にA3-A4の一点鎖線で示す部位に対応する断面図であり、トランジスタ200のチャネル幅方向の断面図でもある。なお、各図の(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図26(A)、図26(B)、および図26(C)は、本発明の一態様に係るトランジスタ200、容量素子100、およびトランジスタ200周辺の上面図、および断面図である。なお、本明細書では、1つの容量素子、および少なくとも1つのトランジスタを有する記憶装置をセルと称する。
本発明の一態様の半導体装置は、トランジスタ200と、容量素子100、および層間膜として機能する絶縁体280、絶縁体282および絶縁体283を有する。また、トランジスタ200と電気的に接続し、プラグとして機能する導電体240(導電体240a、および導電体240b)とを有する。
トランジスタ200の構造は、先の実施の形態で説明した半導体装置が有するトランジスタを用いればよい。なお、図26に示すトランジスタ200は一例であり、その構造に限定されず、回路構成や駆動方法に応じて適切なトランジスタを用いればよい。
図26に示すように、容量素子100は、トランジスタ200と共通の構造を有する構成である。本実施の形態では、トランジスタ200の酸化物230に設けられた領域231bを、容量素子100の電極の一方として機能する容量素子100の例について示す。
ここで、本実施の形態のセルアレイの一例を、図27、および図28に示す。例えば、図26に示すトランジスタ200、および容量素子100を有するセル600を、行列、またはマトリクス状に配置することで、セルアレイを構成することができる。
本実施の形態では、半導体装置の一形態を、図30乃至図35を用いて説明する。
図30、図31および図32に示す記憶装置は、トランジスタ300と、トランジスタ200、および容量素子100を有している。図30および図32は、トランジスタ200およびトランジスタ300のチャネル長方向の断面図である。図31には、トランジスタ300およびトランジスタ300近傍のチャネル幅方向の断面図を示す。
本発明の一態様の記憶装置は、図30に示すようにトランジスタ300、トランジスタ200、容量素子100を有する。トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ300、およびトランジスタ200の上方に設けられている。
以下では、図32を用いて、本発明の一態様に係る記憶装置の一例について説明する。
図33に示す半導体装置は、トランジスタ400と、トランジスタ200、および容量素子100を有する記憶装置である。以下に、記憶装置としての一形態を、図33を用いて説明する。
図33(B)は、容量素子100、トランジスタ200、およびトランジスタ400を有する記憶装置の断面図である。なお、図33に示す記憶装置において、先の実施の形態、および<記憶装置1の構造>に示した半導体装置、および記憶装置を構成する構造と同機能を有する構造には、同符号を付記する。
図34に示す半導体装置は、トランジスタ300、トランジスタ200、トランジスタ400および容量素子100を有する記憶装置である。以下に、記憶装置としての一形態を、図34を用いて説明する。
本実施の形態では、上記実施の形態に示す半導体装置を用いたインバータ回路について説明を行う。なお、本明細書中において、高電源電圧をHレベル(又はVDD)、低電源電圧をLレベル(又はGND)と呼ぶ場合がある。
図36(A)に示す回路INVは、容量素子C1と、直列に接続されたトランジスタM1、トランジスタM2およびトランジスタM3と、を有する。回路INVは、インバータ回路としての機能を有する。
本実施の形態では、図37乃至図39を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ。)、および容量素子が適用されている記憶装置の一例として、NOSRAMについて説明する。NOSRAM(登録商標)とは「Nonvolatile Oxide Semiconductor RAM」の略称であり、ゲインセル型(2T型、3T型)のメモリセルを有するRAMを指す。なお、以下において、NOSRAMのようにOSトランジスタを用いたメモリ装置を、OSメモリと呼ぶ場合がある。
図37にNOSRAMの構成例を示す。図37に示すNOSRAM1600は、メモリセルアレイ1610、コントローラ1640、行ドライバ1650、列ドライバ1660、出力ドライバ1670を有する。なお、NOSRAM1600は、1のメモリセルで多値データを記憶する多値NOSRAMである。
図38(A)はメモリセル1611の構成例を示す回路図である。メモリセル1611は2T型のゲインセルであり、メモリセル1611はワード線WWL、RWL、ビット線BL、ソース線SL、配線BGLに電気的に接続されている。メモリセル1611は、ノードSN、OSトランジスタMO61、トランジスタMP61、容量素子C61を有する。OSトランジスタMO61は書き込みトランジスタである。トランジスタMP61は読み出しトランジスタであり、例えばpチャネル型Siトランジスタで構成される。容量素子C61はノードSNの電圧を保持するための保持容量である。ノードSNはデータの保持ノードであり、ここではトランジスタMP61のゲートに相当する。
本実施の形態では、図40乃至図46を用いて、本発明の一態様に係る、OSトランジスタ、および容量素子が適用されている記憶装置の一例として、DOSRAMについて説明する。DOSRAMも、NOSRAMと同様に、OSメモリが適用されている。
図40にDOSRAMの構成例を示す。図40に示すように、DOSRAM1400は、コントローラ1405、行回路1410、列回路1415、メモリセルおよびセンスアンプアレイ1420(以下、「MC-SAアレイ1420」と呼ぶ。)を有する。
MC-SAアレイ1420は、メモリセルアレイ1422をセンスアンプアレイ1423上に積層した積層構造をもつ。グローバルビット線GBLL、GBLRはメモリセルアレイ1422上に積層されている。DOSRAM1400では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。
コントローラ1405は、DOSRAM1400の動作全般を制御する機能を有する。コントローラ1405は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路1410、列回路1415の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。
行回路1410は、MC-SAアレイ1420を駆動する機能を有する。デコーダ1411はアドレス信号をデコードする機能を有する。ワード線ドライバ回路1412は、アクセス対象行のワード線WLを選択する選択信号を生成する。
列回路1415は、データ信号WDA[31:0]の入力を制御する機能、データ信号RDA[31:0]の出力を制御する機能を有する。データ信号WDA[31:0]は書き込みデータ信号であり、データ信号RDA[31:0]は読み出しデータ信号である。
上記で説明したDOSRAMのメモリセルにOSトランジスタを適用することで、メモリセルに用いられる容量素子の容量を小さくすることが可能になり、DOSRAMはデータの書き込みを高速に実行することができる。以下では、このことについて、例を挙げて説明を行う。
本実施の形態では、図47から図50を用いて、本発明の一態様に係る、OSトランジスタ、および容量素子が適用されている半導体装置の一例として、FPGA(フィールドプログラマブルゲートアレイ)について説明する。本実施の形態のFPGAは、コンフィギュレーションメモリ、およびレジスタにOSメモリが適用されている。ここでは、このようなFPGAを「OS-FPGA」と呼ぶ。
図47(A)にOS-FPGAの構成例を示す。図47(A)に示すOS-FPGA3110は、マルチコンテキスト構造によるコンテキスト切り替え、細粒度パワーゲーティング、NOFF(ノーマリーオフ)コンピューティングが可能である。OS-FPGA3110は、コントローラ(Controller)3111、ワードドライバ(Word driver)3112、データドライバ(Data driver)3113、プログラマブルエリア(Programmable area)3115を有する。
“H”の信号storeがOS-FF3140に入力されると、シャドウレジスタ3142はFF3141のデータをバックアップする。ノードN36は、ノードQのデータが書き込まれることで、“L”となり、ノードNB36は、ノードQBのデータが書き込まれることで、“H”となる。しかる後、パワーゲーティングが実行され、パワースイッチ3127をオフにする。FF3141のノードQ、QBのデータは消失するが、電源オフであっても、シャドウレジスタ3142はバックアップしたデータを保持する。
パワースイッチ3127をオンにし、PLE3121に電源を供給する。しかる後、“H”の信号loadがOS-FF3140に入力されると、シャドウレジスタ3142はバックアップしているデータをFF3141に書き戻す。ノードN36は“L”であるので、ノードN37は“L”が維持され、ノードNB36は“H”であるので、ノードNB37は“H”となる。よって、ノードQは“H”になり、ノードQBは“L”になる。つまり、OS-FF3140はバックアップ動作時の状態に復帰する。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータや、ノート型のコンピュータや、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図51にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。
本実施の形態では、図52を用いて、上記実施の形態に示す半導体装置を適用した、AIシステムについて説明を行う。
<AIシステムの応用例>
本実施の形態では、上記実施の形態に示すAIシステムの応用例について図53を用いて説明を行う。
本実施の形態は、上記実施の形態に示すAIシステムが組み込まれたICの一例を示す。
<電子機器>
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図55および図56に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。
Claims (14)
- チャネル形成領域に酸化物を有するトランジスタ、層間膜、および第1の導電体を有し、
前記トランジスタは、第1の絶縁体上の前記酸化物と、前記酸化物上の第2の導電体と、前記酸化物と前記第2の導電体の間に設けられ、かつ前記第2の導電体の側面と接するように設けられた第2の絶縁体と、前記第2の絶縁体を間に挟み、前記第2の導電体の側面に設けられた、第3の絶縁体と、を有し、
前記酸化物は、第1の領域、第2の領域、および第3の領域を有し、
前記第1の領域は、前記第2の導電体と重なり、
前記第2の領域は、前記第1の領域と、前記第3の領域と、の間に設けられ、
前記第3の領域は、前記第2の領域よりも低抵抗であり、
前記第2の領域は、前記第1の領域よりも低抵抗であり、
前記層間膜は、前記第1の絶縁体上、および前記酸化物上に設けられ、
前記第1の導電体は、前記第3の領域と電気的に接続され、
前記第3の領域は、前記第3の絶縁体、前記第1の導電体、および前記層間膜のいずれか一と重なり、
前記第3の絶縁体の上面は、前記層間膜の上面と略一致する半導体装置。 - チャネル形成領域に酸化物を有するトランジスタ、容量、層間膜、および第1の導電体を有し、
前記トランジスタは、第1の絶縁体上の前記酸化物と、前記酸化物上の第2の導電体と、前記酸化物と前記第2の導電体の間に設けられ、かつ前記第2の導電体の側面と接するように設けられた第2の絶縁体と、前記第2の絶縁体を間に挟み、前記第2の導電体の側面に設けられた、第3の絶縁体と、を有し、
前記酸化物は、第1の領域、一対の第2の領域、および一対の第3の領域を有し、
前記第1の領域は、前記第2の導電体と重なり、
前記第1の領域は、一対の前記第2の領域の間に設けられ、
前記第1の領域、および一対の前記第2の領域は、一対の前記第3の領域の間に設けられ、
前記第3の領域は、前記第2の領域よりも低抵抗であり、
前記第2の領域は、前記第1の領域よりも低抵抗であり、
前記層間膜は、前記第1の絶縁体上、および前記酸化物上に設けられ、
前記第1の導電体は、一対の前記第3の領域の一方と電気的に接続され、
前記容量は、一対の前記第3の領域の他方と電気的に接続され、
前記第3の絶縁体の上面は、前記層間膜の上面と略一致する半導体装置。 - 請求項2において、
一対の前記第3の領域の他方は、前記容量の一方の電極として機能する半導体装置。 - 請求項2において、
前記層間膜は、一対の前記第3の領域の他方の少なくとも一部を露出する開口を有し、
前記容量は、前記開口において、
一対の前記第3の領域の他方上の第4の絶縁体と、前記第4の絶縁体上の第3の導電体と、を有し、
一対の前記第3の領域の他方は、前記容量の一方の電極として機能し、
前記第4の絶縁体は、前記容量の誘電体として機能し、
前記第3の導電体は、前記容量の他方の電極として機能する半導体装置。 - 請求項4において、
前記第3の導電体は、前記開口内に埋め込まれるように形成されている半導体装置。 - 請求項1または請求項2において、
前記酸化物は、Inと、元素M(MはAl、Ga、Y、またはSn)と、Znと、を含む半導体装置。 - 請求項6において、
前記酸化物は、原子数比において、前記元素Mよりも前記Inの方が多い半導体装置。 - 請求項1または請求項2において、
前記第3の領域は、前記第2の領域より、キャリア密度が大きく、
前記第2の領域は、前記第1の領域より、キャリア密度が大きい半導体装置。 - 請求項1または請求項2において、
前記第3の領域は、アルミニウム、ルテニウム、チタン、タンタル、クロム、およびタングステンの少なくとも一を有する半導体装置。 - 請求項9において、
前記第3の領域は、さらに窒素を有する半導体装置。 - 請求項1または請求項2において、
前記第2の領域は、前記第1の領域よりもアルゴン濃度が高い半導体装置。 - 請求項1または請求項2において、
前記第1の領域は、前記第2の領域よりも水素濃度が低い半導体装置。 - 請求項1または請求項2において、
前記第1の領域は、前記第2の領域及び前記第3の領域よりも水素濃度が低い半導体装置。 - 請求項1または請求項2において、
前記トランジスタは、ノーマリオフ型である半導体装置。
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