JP7224940B2 - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

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JP7224940B2
JP7224940B2 JP2019015071A JP2019015071A JP7224940B2 JP 7224940 B2 JP7224940 B2 JP 7224940B2 JP 2019015071 A JP2019015071 A JP 2019015071A JP 2019015071 A JP2019015071 A JP 2019015071A JP 7224940 B2 JP7224940 B2 JP 7224940B2
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智明 五井
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Kyocera Corp
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Description

本開示は、電解貴金属めっきが施された導体パターンを有する印刷配線板の製造方法に関するものである。 TECHNICAL FIELD The present disclosure relates to a method of manufacturing a printed wiring board having a conductive pattern plated with electrolytic noble metal.

従来、印刷配線板に各導体パターンからなる回路パターンを形成後、さらにソルダーレジストをパターン形成した後、回路パターンの金ワイヤーや半田を接合す特定面に電解ニッケルめっき及び金めっきを施すことが行われている。
特許文献1、2に記載されるように、電解めっきを施した後に、不要となった電解めっき用のリード線の一部を除去して切断することが行われる。
特許文献1にあっては、電解めっき工程時にリード線を覆っていた耐めっき被膜(めっきレジスト)を剥離してリード線を露出させエッチングにより同リード線を除去する。
特許文献2にあっては、電解めっき工程時にリード線を覆っていたソルダーレジストをレーザーで除去してリード線を露出させエッチングにより同リード線を除去する。
Conventionally, after forming a circuit pattern consisting of each conductor pattern on a printed wiring board and then forming a solder resist pattern, electrolytic nickel plating and gold plating are applied to specific surfaces of the circuit pattern to which gold wires and solder are to be joined. It is
As described in Patent Literatures 1 and 2, after performing electrolytic plating, a part of the lead wire for electrolytic plating that is no longer needed is removed and cut.
In Patent Document 1, a plating resistant film (plating resist) covering the lead wire is peeled off during the electroplating process to expose the lead wire, and the lead wire is removed by etching.
In Patent Document 2, the solder resist covering the lead wires is removed with a laser during the electroplating process, the lead wires are exposed, and the lead wires are removed by etching.

特開昭59-188997号公報JP-A-59-188997 特開2004-183043号公報Japanese Patent Application Laid-Open No. 2004-183043

しかしながら、以上の従来技術にあっても以下のような問題があった。
特許文献1に記載されるようなめっきレジストで電解めっき用のリード線を覆う場合を考える。
例えば、めっきレジストのエッジを導体上に配置した場合、レジスト下にめっき液が浸透し、電解めっき用のリード線もめっきされ、電解めっき用のリード線をエッチングで除去できなくなる。したがって、めっき施設予定部のエッジをめっきレジストで形成できない。そのため、ソルダーレジストによりめっき施設予定部のエッジを形成する。
したがって、ソルダーレジストのパターン形成のほかに、めっきレジストのパターン形成、めっきレジストの除去という工程が増加する。
めっきレジストとソルダーレジストに一定以上のオーバーラップを確保できない場合、めっきレジストとソルダーレジストの密着が不十分になり、めっきレジストが剥がれ、レジストの役割を果たさなくなる。
したがって、めっきレジストのエッジを導体上に配置できず、ソルダーレジスト上に配置する必要があり、めっきレジストとソルダーレジストに、一定以上のオーバーラップが必要である。オーバーラップ分の余地を確保する設計が必要となり、高密度配線設計に対して支障となり得る。
However, even with the above-described prior art, there are the following problems.
Consider a case where lead wires for electroplating are covered with a plating resist as described in Patent Document 1. FIG.
For example, when the edge of the plating resist is placed on the conductor, the plating solution penetrates under the resist, and the lead wire for electrolytic plating is also plated, making it impossible to remove the lead wire for electrolytic plating by etching. Therefore, the edge of the planned portion of the plating facility cannot be formed with the plating resist. Therefore, the edge of the planned plating facility is formed with a solder resist.
Therefore, in addition to pattern formation of the solder resist, steps of pattern formation of the plating resist and removal of the plating resist are added.
If the plating resist and the solder resist do not overlap each other to a certain extent, the adhesion between the plating resist and the solder resist becomes insufficient, and the plating resist peels off, failing to fulfill its role as a resist.
Therefore, the edge of the plating resist cannot be placed on the conductor and must be placed on the solder resist, and the plating resist and the solder resist must overlap each other to a certain degree or more. A design that secures a margin for overlap is required, which may hinder high-density wiring design.

特許文献2に記載されるような電解めっき用のリード線を覆っていたソルダーレジストをレーザーで除去する場合を考える。
ソルダーレジストを除去し、かつソルダーレジストと同様に樹脂である絶縁層を除去しないレーザーの出力設定は不可能である。
しがって、特許文献2に記載されるようにソルダーレジストをレーザーで除去する際、レーザーで絶縁層を除去しすぎないように遮蔽層(特許文献2のダミーパターン)が必要になる。遮蔽層を設けないと、最外導体層直下の内層導体層までレーザーが到達する可能性があり、断線させる恐れがある。
したがって、レーザー加工部に遮蔽層をパターン形成する工程負担がある。また、遮蔽層により印刷配線板の厚みが増す。実回路でない導体パターンが印刷配線板中に残り、高密度配線設計に対して支障となり得る。
Consider a case where a solder resist covering a lead wire for electrolytic plating as described in Patent Document 2 is removed with a laser.
It is impossible to set a laser output that removes the solder resist and does not remove the insulating layer, which is a resin like the solder resist.
Therefore, when removing the solder resist with a laser as described in Patent Document 2, a shielding layer (dummy pattern in Patent Document 2) is required to prevent excessive removal of the insulating layer by the laser. If the shielding layer is not provided, the laser may reach the inner conductor layer directly below the outermost conductor layer, possibly causing disconnection.
Therefore, there is a process burden for patterning the shielding layer on the laser-processed portion. Also, the shielding layer increases the thickness of the printed wiring board. A conductor pattern that is not an actual circuit remains in the printed wiring board, which can be a hindrance to high-density wiring design.

本開示の1つの態様の印刷配線板の製造方法は、ソルダーレジストから露出した特定面に電解貴金属めっきが施された回路導体を有する印刷配線板を製造する方法であって、
基板上の前記回路導体に接続する同基板上の電解めっき用のリード線を覆うとともに前記特定面を露出させたソルダーレジストをマスクにして、前記リード線を介して前記回路導体を所定電位に通電させて前記特定面に電解貴金属めっきを施し、
その後、前記リード線を覆う所定範囲のソルダーレジストを切削加工により除去し、前記切削加工の後、前記電解貴金属めっきを覆うとともに、前記所定範囲を露出させたエッチングレジストを形成し、次いで、前記エッチングレジストをマスクにしてエッチングすることにより、前記所定範囲内の前記リード線を除去することで前記リード線を前記回路導体から切断する。
A method for manufacturing a printed wiring board according to one aspect of the present disclosure is a method for manufacturing a printed wiring board having a circuit conductor in which a specific surface exposed from a solder resist is subjected to electrolytic noble metal plating,
Using the solder resist that covers lead wires for electroplating on the substrate connected to the circuit conductors on the substrate and exposes the specific surface as a mask, the circuit conductors are energized to a predetermined potential through the lead wires. and subjecting the specific surface to electrolytic precious metal plating,
Thereafter, a predetermined range of solder resist covering the lead wire is removed by cutting, and after the cutting, an etching resist is formed to cover the electrolytic precious metal plating and expose the predetermined range, and then the etching is performed. Etching is performed using the resist as a mask to remove the lead wire within the predetermined range, thereby cutting the lead wire from the circuit conductor.

本開示の印刷配線板の製造方法によれば、ソルダーレジストを電解めっき時のマスクとし、電解めっき工程後のソルダーレジストの部分的除去を切削加工により行うので、下記の効果が得られる。
ソルダーレジストによる電解めっき時のマスクのエッジを導体上に配置しても、マスク下にめっき液が浸透しない。
ソルダーレジストのパターン形成のほかに、めっきレジストのパターン形成、めっきレジストの除去という工程は不要となり工程が簡素化する。
また、ソルダーレジストとは別に設けられるめっきレジストとのオーバーラップの考慮は不要となり、高密度配線を実現しやすい。
電解めっき用のリード線上のソルダーレジストの除去は、切削加工で行うので、レーザー加工ストップ用の遮蔽層は不要となり、高密度配線を実現しやすい。
According to the printed wiring board manufacturing method of the present disclosure, the solder resist is used as a mask during electroplating, and the solder resist is partially removed by cutting after the electroplating process, so the following effects are obtained.
Even if the edge of the mask for electroplating with solder resist is placed on the conductor, the plating solution does not penetrate under the mask.
In addition to solder resist pattern formation, the steps of plating resist pattern formation and plating resist removal become unnecessary, simplifying the process.
In addition, consideration of overlap with a plating resist provided separately from the solder resist becomes unnecessary, making it easy to achieve high-density wiring.
Since the removal of the solder resist on the lead wire for electroplating is performed by cutting, a shielding layer for stopping laser processing is not required, making it easy to achieve high-density wiring.

一つの実施の形態の印刷配線板の製造方法を説明する断面図である。It is a sectional view explaining a manufacturing method of a printed wiring board of one embodiment. 一つの実施の形態の印刷配線板の製造方法を説明する断面図である。It is a sectional view explaining a manufacturing method of a printed wiring board of one embodiment. 一つの実施の形態の印刷配線板の製造方法を説明する断面図である。It is a sectional view explaining a manufacturing method of a printed wiring board of one embodiment. 一つの実施の形態の印刷配線板の製造方法を説明する断面図である。It is a sectional view explaining a manufacturing method of a printed wiring board of one embodiment. 一つの実施の形態の印刷配線板の製造方法を説明する断面図である。It is a sectional view explaining a manufacturing method of a printed wiring board of one embodiment. 一つの実施の形態の印刷配線板の製造方法を説明する断面図である。It is a sectional view explaining a manufacturing method of a printed wiring board of one embodiment. 比較例の印刷配線板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the printed wiring board of a comparative example. 比較例の印刷配線板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the printed wiring board of a comparative example. 比較例の印刷配線板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the printed wiring board of a comparative example. 比較例の印刷配線板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the printed wiring board of a comparative example. 比較例の印刷配線板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the printed wiring board of a comparative example. 比較例の印刷配線板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the printed wiring board of a comparative example. 比較例の印刷配線板の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the printed wiring board of a comparative example.

本開示の実施形態の印刷配線板の製造方法について図面を参照して説明する。
図1に示すように基板10上の一主面上に形成された回路導体11及び電解めっき用のリード線12を覆うソルダーレジスト13を形成する。但し、回路導体11上の貴金属めっきを施す予定の特定面11aは露出させる。電解めっき用のリード線12は回路導体11に接続している。なお、基板10は、必要により内部に回路導体層を有した多層基板とされる。
A method for manufacturing a printed wiring board according to an embodiment of the present disclosure will be described with reference to the drawings.
As shown in FIG. 1, a solder resist 13 is formed to cover the circuit conductors 11 and lead wires 12 for electroplating formed on one main surface of the substrate 10 . However, the specific surface 11a of the circuit conductor 11, which is to be plated with noble metal, is exposed. A lead wire 12 for electrolytic plating is connected to the circuit conductor 11 . The substrate 10 is a multi-layer substrate having a circuit conductor layer inside if necessary.

以上のように基板10上の回路導体11に接続する同基板10上の電解めっき用のリード線12を覆うとともに特定面11aを露出させたソルダーレジスト13をマスクにして、図2に示すように特定面11aに電解貴金属めっき14を施す。その際、リード線12を介して回路導体11を所定電位に通電させて特定面に電解貴金属めっきを析出させる。
電解貴金属めっき14としては、ニッケルめっき、金めっきの順で形成する。ニッケルめっきを2μm以上の膜厚に形成し、次いで金めっきを、0.2μm以上の膜厚に形成する。
As described above, the solder resist 13 covering the lead wires 12 for electroplating on the substrate 10 connected to the circuit conductors 11 on the substrate 10 and exposing the specific surface 11a is used as a mask, as shown in FIG. Electrolytic precious metal plating 14 is applied to the specific surface 11a. At this time, the circuit conductor 11 is energized to a predetermined potential via the lead wire 12 to deposit the electrolytic precious metal plating on the specific surface.
As the electrolytic noble metal plating 14, nickel plating and gold plating are formed in this order. A nickel plating is formed to a thickness of 2 μm or more, and then a gold plating is formed to a thickness of 0.2 μm or more.

次に、図3に示すようにリード線12を覆う所定範囲15のソルダーレジスト13を切削加工により除去する。切削加工は、NCドリル又はNCルーターにより行うことが好ましい。数値制御(NC(numerical control))により切削深さを精度よく制御することで下層への過剰切削を防止できる。
所定範囲15は、リード線12を切断するために必要な除去箇所のほか、その周囲をマージンとして含める。
切削加工により、ソルダーレジスト13及びその下のリード線12の表層を切削する。続けてリード線12とその下層の絶縁層(基板10)との界面に達するまで切削加工を進めることで、リード線12を除去する。
このように、同切削加工により所定範囲15内のリード線12を除去することでリード線12を回路導体11から切断する。
但し、切削加工のみでは、基板10の反りや凹凸により、リード線12を除去しきれない場合もある。
そこで、図3に示すようにリード線12の切削残りがあり得る場合、及びリード線12とその下層の絶縁層(基板10)との界面に達する前に切削加工を終了してリード線12を積極的に残した場合は、本切削工程の後、以下に説明するエッチングにより所定範囲15内のリード線12を完全に除去する。
Next, as shown in FIG. 3, a predetermined range 15 of the solder resist 13 covering the lead wires 12 is removed by cutting. Cutting is preferably performed with an NC drill or NC router. Excessive cutting of lower layers can be prevented by accurately controlling the cutting depth using numerical control (NC).
The predetermined range 15 includes the removed portion necessary for cutting the lead wire 12 and the periphery thereof as a margin.
By cutting, the solder resist 13 and the surface layer of the lead wires 12 thereunder are cut. Subsequently, the lead wire 12 is removed by proceeding with cutting until the interface between the lead wire 12 and the underlying insulating layer (substrate 10) is reached.
Thus, the lead wire 12 is cut off from the circuit conductor 11 by removing the lead wire 12 within the predetermined range 15 by the same cutting.
However, there are cases where the lead wires 12 cannot be completely removed by cutting alone due to the warp or unevenness of the substrate 10 .
Therefore, as shown in FIG. 3, when the lead wire 12 is left uncut, and before the lead wire 12 reaches the interface between the lead wire 12 and the underlying insulating layer (substrate 10), the cutting process is terminated to remove the lead wire 12. If left intentionally, the lead wire 12 within the predetermined range 15 is completely removed by etching described below after the main cutting step.

それにはまず、図4に示すように電解貴金属めっき14を覆うとともに所定範囲15を露出させたエッチングレジスト16を形成する。エッチングレジスト16としてはドライフィルムが好適に用いられる。
次にエッチングレジスト16をマスクにしてエッチングすることにより所定範囲15内のリード線12を除去する(図5)。
次に、エッチングレジスト16を剥離して除去する(図6)。
First, as shown in FIG. 4, an etching resist 16 covering the electrolytic precious metal plating 14 and exposing a predetermined area 15 is formed. A dry film is preferably used as the etching resist 16 .
Next, the lead wire 12 within a predetermined range 15 is removed by etching using the etching resist 16 as a mask (FIG. 5).
Next, the etching resist 16 is peeled off and removed (FIG. 6).

以上により、ソルダーレジスト13から露出した特定面11aに電解貴金属めっき14が施された回路導体11を有する印刷配線板1(図6)を製造することができる。 As described above, the printed wiring board 1 (FIG. 6) having the circuit conductors 11 with the electrolytic precious metal plating 14 applied to the specific surfaces 11a exposed from the solder resist 13 can be manufactured.

図7から図13に比較例の工程を示す。これは、特許文献1に記載されるような電解めっき工程時にリード線を覆っていた耐めっき被膜(めっきレジスト)を剥離してリード線を露出させエッチングにより同リード線を除去する方法である。 7 to 13 show steps of a comparative example. This is a method of exposing the lead wire by peeling off the plating resistant film (plating resist) covering the lead wire during the electrolytic plating process as described in Patent Document 1, and then removing the lead wire by etching.

比較例にあっては、図7に示すようにソルダーレジスト13は、回路導体11の電解めっきを施す予定の特定面11aのほか、電解めっき用のリード線12(少なくとも切断のために必要な個所)も露出させる。
次に図8に示すように、ドライフィルムなどによるめっきレジスト21を形成して、ソルダーレジスト13から露出しているリード線12をマスキングする。
次に、図9に示すようにソルダーレジスト13及びめっきレジスト21をマスクとして特定面11a上に電解貴金属めっき14を施す。
次に、図10に示すようにめっきレジスト21を剥離して除去する。
次に、図11に示すようにドライフィルムなどによるエッチングレジスト16を形成し、電解貴金属めっき14をマスキングする。
次に、図12に示すようにソルダーレジスト13及びエッチングレジスト16をマスクとしてエッチングによりリード線12を除去する。
次に、図13に示すようにエッチングレジスト16を剥離して除去する。
In the comparative example, as shown in FIG. 7, the solder resist 13 is applied not only to the specific surface 11a of the circuit conductor 11 to be electroplated, but also to the lead wires 12 for electroplating (at least the portions required for cutting). ) are also exposed.
Next, as shown in FIG. 8, a plating resist 21 such as a dry film is formed to mask the lead wires 12 exposed from the solder resist 13 .
Next, as shown in FIG. 9, using the solder resist 13 and the plating resist 21 as a mask, electrolytic precious metal plating 14 is applied to the specific surface 11a.
Next, as shown in FIG. 10, the plating resist 21 is stripped and removed.
Next, as shown in FIG. 11, an etching resist 16 such as a dry film is formed to mask the electrolytic precious metal plating 14 .
Next, as shown in FIG. 12, the lead wires 12 are removed by etching using the solder resist 13 and the etching resist 16 as masks.
Next, as shown in FIG. 13, the etching resist 16 is stripped and removed.

以上説明した比較例によれば、ソルダーレジスト13のパターン形成のほかに、めっきレジスト21のパターン形成、めっきレジスト21の除去という工程が必要となる。
これに対して上述した本実施形態によれば、ソルダーレジスト13のパターン形成のほかに、めっきレジストのパターン形成、めっきレジストの除去という工程は不要となり工程が簡素化する。
以上説明した比較例によれば、ソルダーレジスト13とめっきレジスト21とをオーバーラップさせる必要があり、オーバーラップ分の余地を確保する設計が必要となって高密度配線設計に対して支障となり得る。
これに対して本実施形態によれば、ソルダーレジストとは別に設けられるめっきレジストとのオーバーラップの考慮は不要となり、高密度配線を実現しやすい。
According to the comparative example described above, in addition to the pattern formation of the solder resist 13, the steps of pattern formation of the plating resist 21 and removal of the plating resist 21 are required.
On the other hand, according to the present embodiment described above, in addition to the pattern formation of the solder resist 13, the steps of pattern formation of the plating resist and removal of the plating resist are not required, thereby simplifying the process.
According to the comparative example described above, it is necessary to overlap the solder resist 13 and the plating resist 21, and a design is required to secure a margin for the overlap, which may hinder high-density wiring design.
On the other hand, according to the present embodiment, there is no need to consider overlap with the plating resist provided separately from the solder resist, and high-density wiring can be easily realized.

また、本実施形態によれば、ソルダーレジスト13による電解めっき時のマスクのエッジを導体上に配置しても、ソルダーレジスト13下にめっき液が浸透しない。したがって、特定面11aに精度よく電解貴金属めっき14を施すことができる。 Further, according to the present embodiment, even if the edge of the mask for electroplating with the solder resist 13 is placed on the conductor, the plating solution does not permeate under the solder resist 13 . Therefore, the electrolytic precious metal plating 14 can be accurately applied to the specific surface 11a.

また、特許文献2に記載されるような電解めっき用のリード線を覆っていたソルダーレジストをレーザーで除去する方法に比較すると次の通りである。
すなわち、本実施形態によれば、電解めっき用のリード線12上のソルダーレジスト13の除去は、切削加工で行うので、レーザー加工ストップ用の遮蔽層は不要となる。同遮蔽層が無くても、基板10内の下層配線を断線させてしまうことが無い。
同遮蔽層が不要となることで、同遮蔽層の代わりに実回路に含まれる配線パターンを配置できるから、高密度配線を実現しやすい。
In addition, comparison with the method of removing the solder resist covering lead wires for electrolytic plating as described in Patent Document 2 with a laser is as follows.
That is, according to this embodiment, since the removal of the solder resist 13 on the lead wire 12 for electroplating is performed by cutting, a shielding layer for stopping laser processing is not required. Even without the shielding layer, the lower layer wiring in the substrate 10 will not be disconnected.
Since the shielding layer becomes unnecessary, the wiring pattern included in the actual circuit can be arranged instead of the shielding layer, so that high-density wiring can be easily realized.

以上本開示の実施形態を説明したが、この実施形態は、例として示したものであり、この他の様々な形態で実施が可能であり、発明の要旨を逸脱しない範囲で、構成要素の省略、置き換え、変更を行うことができる。 Although the embodiment of the present disclosure has been described above, this embodiment is shown as an example and can be implemented in various other forms. , can be replaced and changed.

1 印刷配線板
10 基板
11 回路導体
11a 特定面
12 電解めっき用のリード線
13 ソルダーレジスト
15 所定範囲
16 エッチングレジスト
21 めっきレジスト
Reference Signs List 1 printed wiring board 10 substrate 11 circuit conductor 11a specific surface 12 lead wire for electrolytic plating 13 solder resist 15 predetermined range 16 etching resist 21 plating resist

Claims (6)

ソルダーレジストから露出した特定面に、電解貴金属めっきが施された回路導体を有する印刷配線板を製造する方法であって、
基板上の前記回路導体に接続する同基板上の電解めっき用のリード線を覆うとともに、前記特定面を露出させたソルダーレジストをマスクにして、前記リード線を介して前記回路導体を所定電位に通電させて前記特定面に電解貴金属めっきを施し、
その後、前記リード線を覆う所定範囲のソルダーレジストを切削加工により除去し、前記切削加工の後、前記電解貴金属めっきを覆うとともに、前記所定範囲を露出させたエッチングレジストを形成し、次いで、前記エッチングレジストをマスクにしてエッチングすることにより、前記所定範囲内の前記リード線を除去することで、前記リード線を前記回路導体から切断する印刷配線板の製造方法。
A method for manufacturing a printed wiring board having circuit conductors electrolytically plated with noble metal on a specific surface exposed from a solder resist,
Covering lead wires for electrolytic plating on the substrate connected to the circuit conductors on the substrate and exposing the specific surface of the solder resist is used as a mask to set the circuit conductors to a predetermined potential through the lead wires. Energizing to apply electrolytic precious metal plating to the specific surface,
Thereafter, a predetermined range of solder resist covering the lead wire is removed by cutting, and after the cutting, an etching resist is formed to cover the electrolytic precious metal plating and expose the predetermined range, and then the etching is performed. A method of manufacturing a printed wiring board , wherein etching is performed using a resist as a mask to remove the lead wire within the predetermined range, thereby cutting the lead wire from the circuit conductor.
前記電解貴金属めっきは、ニッケルめっき、金めっきの順で形成する請求項に記載の印刷配線板の製造方法。 2. The method of manufacturing a printed wiring board according to claim 1 , wherein said electrolytic precious metal plating is formed in order of nickel plating and gold plating. 前記ニッケルめっきを2μm以上の膜厚に形成する請求項に記載の印刷配線板の製造方法。 3. The method of manufacturing a printed wiring board according to claim 2 , wherein the nickel plating is formed to a film thickness of 2 [mu]m or more. 前記金めっきを、0.2μm以上の膜厚に形成する請求項又は請求項に記載の印刷配線板の製造方法。 4. The method of manufacturing a printed wiring board according to claim 2 , wherein the gold plating is formed to have a film thickness of 0.2 [mu]m or more. 前記切削加工は、NCドリルにより行う請求項1から請求項のうちいずれか一に記載の印刷配線板の製造方法。 5. The method of manufacturing a printed wiring board according to claim 1 , wherein said cutting is performed by an NC drill. 前記切削加工は、NCルーターにより行う請求項1から請求項のうちいずれか一に記載の印刷配線板の製造方法。 5. The method of manufacturing a printed wiring board according to claim 1 , wherein said cutting is performed by an NC router.
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Citations (1)

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JP2004207745A (en) 2002-12-23 2004-07-22 Samsung Electro Mech Co Ltd Ball grid array substrate and its manufacturing method

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JPS5559795A (en) * 1978-10-30 1980-05-06 Nippon Electric Co Printed circuit board and method of manufacturing same
JPH03183190A (en) * 1989-12-12 1991-08-09 Satosen Co Ltd Manufacture of printed-circuit board

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