JP7171315B2 - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Description

The present invention relates to a multilayer ceramic capacitor and its manufacturing method.

The maximum capacitance of recent high-density multilayer ceramic capacitors is approaching, for example, 1000 μF. Thus, the capacitance of the multilayer ceramic capacitor approaches the area of the electrolytic capacitor. However, with the current capacity density, it is difficult to realize such a capacity unless it has a large shape. In order to construct this large-sized ceramic laminate as a sintered body, a highly continuous, low-expansion material is required without impairing the continuity of the internal electrode layers with respect to the sintering temperature gap between the internal electrode layers and the dielectric layers. It is important to obtain a structure of

For example, initial firing is performed at a temperature of 700° C. or lower at a heating rate of 30° C./60 s to 50° C./60 s to induce rapid nickel sintering and improve the connectivity of the internal electrodes of the multilayer ceramic capacitor. is considered (see, for example, Patent Document 1).

JP 2014-82435 A

However, since the large-sized multilayer ceramic capacitor contains a large amount of binder, there is a problem that high-speed firing at the sintering temperature peak portion cannot be realized if priority is given to removing the binder. In addition, when high-speed firing is prioritized, residual stress accumulates in the chip due to the effects of degassing, etc., causing structural defects.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer ceramic capacitor having a large size, a high capacitance, and a high CR product, and a method for manufacturing the same.

In a laminated ceramic capacitor according to the present invention, dielectric layers containing ceramic as a main component and internal electrode layers are alternately laminated, and the plurality of laminated internal electrode layers are alternately exposed at two opposite end faces. and a pair of external electrodes formed on the two end faces, wherein the total weight of the laminated chip and the pair of external electrodes is 131 mg or more , having a size of 3225 or more, and in a cross section perpendicular to the first direction at the center of the first direction where the two end surfaces face each other in the laminated chip, the center of the internal electrode layer in the width direction and the Let T1 be the height of the laminated chip in the lamination direction, T2 be the height passing through the end points of the internal electrode layers in the second direction that is the width direction of the internal electrode layers, and T2 be the height passing through the end points of the internal electrode layers in the second direction that is the width direction of the internal electrode layers. When the width in the second direction is W1 and the width in the second direction passing through the center of the stacking direction is W2, (T1−T2)/T1 is +0.9% or more and +4.4% or less . Yes, (W1-W2)/W1 is −0.8% or more and +2.8% or less , the number of layers of the internal electrode layers with respect to T1 is 250 layers/mm or more, and the continuity rate of the internal electrode layers is 86% or more .

In the above laminated ceramic capacitor, in the cross section, the ratio of the area of the capacitive regions where internal electrode layers exposed on different end faces face each other to the total area may be 80% or more.

In the laminated ceramic capacitor described above, the number of internal electrode layers stacked with respect to T1 may be 400 layers/mm or more.

A method for manufacturing a laminated ceramic capacitor according to the present invention comprises alternately laminating ceramic dielectric layer green sheets and internal electrode-forming conductive pastes, and alternately opposing the laminated plurality of internal electrode-forming conductive pastes. forming a substantially rectangular parallelepiped ceramic laminate by exposing two end faces; obtaining a laminated chip by sintering the ceramic laminate; and plating an underlying layer on the two end faces of the laminated chip. and forming a pair of external electrodes by processing, wherein the total weight of the laminated chip and the pair of external electrodes is 131 mg or more , and the laminated chip has a size of 3225 or more, In a cross section perpendicular to the first direction at the center of the first direction where the two end faces face each other, the width direction center of the internal electrode layer obtained from the conductive paste for forming an internal electrode and the height of the laminated chip In the case of T1, the number of stacked internal electrode layers with respect to T1 is 250 layers/mm or more, and the step of firing the ceramic laminate includes a first half temperature raising step and a second half temperature raising step, (Temperature increase rate in the second half temperature increase step )/(Temperature increase rate in the first half temperature increase step) is set to 62.5 or more , and the temperature increase rate in the first half temperature increase step is set to 200°C/hr or more . The heating time in the first half temperature raising step is set to 1 hour or more and 16 hours or less, and the temperature raising time in the second half temperature raising step is set to 0.01 minute or more to 10 minutes or less . In the manufacturing method described above, the temperature at which the rate of temperature increase in the first half of the temperature increase step is switched to the rate of temperature increase in the latter half of the temperature increase step may be 1000±200°C. Another laminated ceramic capacitor according to the present invention has a dielectric layer containing ceramic as a main component and an internal electrode layer alternately laminated, and a plurality of the laminated internal electrode layers are alternately arranged on two end surfaces facing each other. A laminated chip having a substantially rectangular parallelepiped shape which is formed to be exposed, and a pair of external electrodes formed on the two end faces, wherein the total weight of the laminated chip and the pair of external electrodes is 131 mg or more . In the laminated chip, the height in the lamination direction of the laminated chip at the center in the width direction of the internal electrode layer in a cross section perpendicular to the first direction at the center of the first direction where the two end faces face each other is T1, the height passing through the end points of the internal electrode layers in the second direction that is the width direction of the internal electrode layers is T2, and the width in the second direction passing through any of the outermost internal electrode layers is When W1 is the width in the second direction passing through the center of the stacking direction and W2 is the width, (T1−T2)/T1 is +0.9% or more and +4.4% or less , and (W1−W2)/ W1 is −0.8% or more and +2.8% or less , T1 is 2.8 mm or more, the number of stacked internal electrode layers with respect to T1 is 250 layers/mm or more, and the internal electrode layers are continuous. A multilayer ceramic capacitor having a rate of 86% or more .

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a multilayer ceramic capacitor having a large size, a high capacitance, and a high CR product, and a method for manufacturing the same.

1 is a partial cross-sectional perspective view of a laminated ceramic capacitor; FIG. FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1; FIG. 2 is a cross-sectional view taken along line BB of FIG. 1; It is a figure showing a continuity rate. FIG. 2 is a cross-sectional view corresponding to the BB line cross-section of FIG. 1; FIG. 4 is a diagram illustrating Area1 and Area2; It is a figure which illustrates the flow of the manufacturing method of a laminated ceramic capacitor. It is a figure which illustrates a baking process. It is a figure which shows a measurement result. (a) and (b) are diagrams illustrating cracks and fissures.

Hereinafter, embodiments will be described with reference to the drawings.

(embodiment)
FIG. 1 is a partial cross-sectional perspective view of a laminated ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA of FIG. 3 is a cross-sectional view taken along line BB of FIG. 1. FIG. As illustrated in FIGS. 1 to 3, the laminated ceramic capacitor 100 includes a rectangular parallelepiped laminated chip 10 and external electrodes 20a and 20b provided on two opposing end surfaces of the laminated chip 10. As shown in FIGS. Of the four surfaces of the laminated chip 10 other than the two end surfaces, two surfaces other than the top surface and the bottom surface in the stacking direction are referred to as side surfaces. The external electrodes 20a and 20b extend on the upper surface, lower surface and two side surfaces of the laminated chip 10 in the lamination direction. However, the external electrodes 20a and 20b are separated from each other. In FIG. 1, the X-axis direction (first direction) is the length direction of the laminated chip 10, the direction in which the two end faces of the laminated chip 10 face each other, and the external electrodes 20a and 20b face each other. direction. The Y-axis direction (second direction) is the width direction of the internal electrode layers 12 . The Z-axis direction is the stacking direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

A laminated chip 10 has a structure in which dielectric layers 11 containing a ceramic material functioning as a dielectric and internal electrode layers 12 containing a base metal material are alternately laminated. The edge of each internal electrode layer 12 is alternately exposed to the end face provided with the external electrode 20a of the laminated chip 10 and the end face provided with the external electrode 20b. Thereby, each internal electrode layer 12 is alternately connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated with internal electrode layers 12 interposed therebetween. In the laminated body of the dielectric layers 11 and the internal electrode layers 12 , the internal electrode layer 12 is arranged as the outermost layer in the lamination direction, and the upper and lower surfaces of the laminated body are covered with the cover layer 13 . The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as the main component of the dielectric layer 11 and the ceramic material.

The size of the multilayer ceramic capacitor 100 is, for example, length 1.6 mm, width 0.8 mm, and height 0.8 mm, or length 2.0 mm, width 1.25 mm, and height 1.25 mm, or 3.2 mm long, 1.6 mm wide and 1.6 mm high, or 3.2 mm long, 2.5 mm wide and 2.5 mm high, or 4.5 mm long and 3.2 mm wide , 2.5 mm in height, but are not limited to these sizes.

The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). As the internal electrode layers 12, noble metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), and alloys containing these may be used. The dielectric layer 11 is mainly composed of, for example, a ceramic material having a perovskite structure represented by the general formula _ABO3 . Note that the perovskite structure contains ABO _3-α deviating from the stoichiometric composition. For example, the ceramic materials include BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), and Ba _1-xy forming a perovskite structure. Ca _x Sr _y Ti _1-z Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like can be used.

As illustrated in FIG. 2, the area where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is the area that produces the capacitance in the multilayer ceramic capacitor 100. . Therefore, this area is called a capacity area 14 . That is, the capacitive region 14 is a region where two adjacent internal electrode layers 12 connected to different external electrodes face each other.

A region in which the internal electrode layers 12 connected to the external electrode 20a face each other without interposing the internal electrode layers 12 connected to the external electrode 20b is called an end margin region 15 . The end margin region 15 is also a region where the internal electrode layers 12 connected to the external electrode 20b face each other without interposing the internal electrode layers 12 connected to the external electrode 20a. That is, the end margin region 15 is a region in which the internal electrode layers 12 connected to the same external electrode face each other without interposing the internal electrode layers 12 connected to different external electrodes. The end margin region 15 is a region that does not produce capacitance.

As exemplified in FIG. 3 , in the laminated chip 10 , a region extending from two side surfaces of the laminated chip 10 to the internal electrode layers 12 is called a side margin region 16 . That is, the side margin region 16 is a region provided so as to cover the end portions of the plurality of internal electrode layers 12 laminated in the laminated structure extending to the two side surfaces.

The maximum capacitance of recent high-density multilayer ceramic capacitors is approaching, for example, 1000 μF. Thus, the capacitance of the multilayer ceramic capacitor approaches the area of the electrolytic capacitor. However, with the current capacity density, it is difficult to realize such a capacity unless it has a large shape.

On the other hand, the dielectric layer 11 is obtained, for example, by sintering raw material powder of a main component ceramic having a perovskite structure. The internal electrode layers 12 are obtained by firing the raw material powder of the main component metal. There is a difference between the sintering start temperature of the raw material powder of the main component ceramic and the sintering start temperature of the raw material powder of the main component metal. In order to construct a large-sized ceramic laminate as a sintered body, the continuity of the internal electrode layers 12 must be highly continuous without impairing the continuity of the internal electrode layers 12 with respect to the sintering start temperature gap between the dielectric layers 11 and the internal electrode layers 12 . , it is important to obtain a low-expansion structure.

FIG. 4 is a diagram showing the continuity rate. As exemplified in FIG. 4, in an observation region of length L0 in an internal electrode layer 12, the lengths L1, L2, . ΣLn/L0 can be defined as the continuity of the layer.

For example, it is conceivable to induce sintering of the metal components of the internal electrode layers and improve the connectivity of the internal electrode layers by rapidly increasing the temperature during the heating process of the firing process. However, since large-sized multilayer ceramic capacitors contain a large amount of binder, there is a problem that high-speed sintering at the sintering temperature peak portion cannot be achieved if the rate of temperature increase is suppressed to give priority to binder removal. In addition, when high-speed firing is prioritized, residual stress accumulates in the chip due to the effects of degassing, etc., causing structural defects. Therefore, the multilayer ceramic capacitor 100 according to the present embodiment has a configuration that achieves a large size, high capacitance, and high CR product by adjusting the temperature rise rate in the firing process, for example. Here, the CR product represents the product of the capacitance value of the multilayer ceramic capacitor 100 and the insulation resistance.

First, each dimension of the multilayer ceramic capacitor 100 is defined. FIG. 5 is a cross-sectional view corresponding to the BB line cross section of FIG. The cross section of FIG. 5 is a cross section passing through the center of the laminated chip 10 in the length direction (X-axis direction). In the laminated chip 10, the height in the lamination direction (Z-axis direction) passing through the center of the internal electrode layer 12 in the width direction (Y-axis direction) is defined as a height T1. In the laminated chip 10, the height in the Z-axis direction passing through the end points of the internal electrode layers 12 in the Y-axis direction is defined as a height T2. If the end points of the internal electrode layers 12 in the Y-axis direction are uneven, the height T2 is the height in the Z-axis direction at the average position of the end points of the internal electrode layers 12 . In the laminated chip 10, the width in the Y-axis direction passing through the outermost internal electrode layer 12 is defined as a width W1. Also, in the laminated chip 10, the width in the Y-axis direction passing through the center in the Z-axis direction is defined as a width W2.

First, in the present embodiment, a multilayer ceramic capacitor 100 having a large weight and a large shape is targeted. Specifically, the weight of the laminated ceramic capacitor 100 (total weight of the laminated chip 10 and the external electrodes 20a and 20b) is set to 130 mg or more. Alternatively, the weight of the laminated ceramic capacitor 100 is set to 150 mg or more. Alternatively, the weight of the multilayer ceramic capacitor 100 is set to 330 mg or more.

Further, in the present embodiment, the target is a high-capacity multilayer ceramic capacitor 100 having a large number of internal electrode layers 12 laminated. Specifically, the number of layers of the internal electrode layers 12 with respect to the height T1 is 250 layers/mm or more. Alternatively, the number of layers of the internal electrode layers 12 with respect to the height T1 is 350 layers/mm or more. Alternatively, the number of layers of the internal electrode layers 12 with respect to the height T1 is set to 400 layers/mm or more. Alternatively, the number of layers of the internal electrode layers 12 with respect to the height T1 is 450 layers/mm or more.

Also, the multilayer ceramic capacitor 100 according to this embodiment has a high continuity rate in order to achieve a high capacitance. Specifically, the continuity rate of the internal electrode layers 12 is 85% or more. From the viewpoint of high capacity, the continuity rate of the internal electrode layers 12 is preferably 90% or more, more preferably 95% or more.

In such a large-sized and high-capacity multilayer ceramic capacitor 100, the smaller the difference between the height T1 and the height T2 and the smaller the difference between the width W1 and the width W2, the more the residual stress of the multilayer ceramic capacitor 100 is suppressed. This suppresses the occurrence of structural defects and increases the insulation resistance. Therefore, in the present embodiment, the range of (T1-T2)/T1 is defined, and the range of (W1-W2)/W1 is defined. Specifically, (T1-T2)/T1 is set to 0% or more and +4.5% or less. Also, (W1-W2)/W1 is set to −1.0% or more and +3.0% or less. According to this configuration, the CR product can be sufficiently increased in the large-sized, high-capacity multilayer ceramic capacitor 100 .

From the viewpoint of suppressing the residual stress of the multilayer ceramic capacitor 100, it is preferable that the difference between the height T1 and the height T2 is even smaller. Therefore, (T1-T2)/T1 is preferably 0% or more and +3.0% or less, more preferably 0% or more and +1.5% or less. Also, it is preferable that the difference between the width W1 and the width W2 is even smaller. Therefore, (W1-W2)/W1 is preferably -1.0% or more and +1.0% or less, and more preferably 0% or more and +1.0% or less.

In the cross section of FIG. 5, the higher the ratio of the area of the capacitor region 14, the higher the capacitance. Therefore, as exemplified in FIG. 6, the cross-sectional area of the capacitor region 14 in the cross-section of FIG. 5 is assumed to be Area1. Assume that the cross-sectional area of the entire laminated chip 10 is Area2. In this case, Area1/Area2 is preferably 80% or more, more preferably 85% or more.

Next, a method for manufacturing the laminated ceramic capacitor 100 will be described. FIG. 7 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100. As shown in FIG.

(Raw material powder preparation process)
First, as illustrated in FIG. 7, a dielectric material for forming the dielectric layer 11 is prepared. The A-site and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of sintered particles of _ABO3 . For example, BaTiO ₃ is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO ₃ can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. As methods for synthesizing the ceramic constituting the dielectric layer 11, various methods are conventionally known, such as a solid phase method, a sol-gel method, a hydrothermal method, and the like. Any of these can be employed in the present embodiment.

A predetermined additive compound is added to the obtained ceramic powder according to the purpose. Additive compounds include Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb ( terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)) oxides, as well as Co (cobalt), Ni, Li (lithium), B (boron) , Na (sodium), K (potassium) and Si (silicon) oxides or glasses.

In this embodiment, preferably, a compound containing an additive compound is first mixed with ceramic particles forming the dielectric layer 11 and calcined at 820 to 1150.degree. The resulting ceramic particles are then wet mixed with additive compounds, dried and ground to prepare a ceramic powder. For example, the ceramic powder obtained as described above may be pulverized to adjust the particle size, or combined with a classification process to adjust the particle size.

Next, a reverse pattern material for forming the end margin regions 15 and the side margin regions 16 is prepared. A predetermined additive compound is added according to the purpose to the ceramic powder of barium titanate obtained by the same process as the manufacturing process of the dielectric material. Additive compounds include oxides of Mg, Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb), Co, Ni, Li, B, Examples include Na, K and Si oxides or glasses.

In the present embodiment, preferably, a compound containing an additive compound is first mixed with the ceramic particles forming the end margin regions 15 and the side margin regions 16, and calcined at 820 to 1150.degree. The resulting ceramic particles are then wet mixed with additive compounds, dried and ground to prepare a ceramic powder. For example, the ceramic powder obtained as described above may be pulverized to adjust the particle size, or combined with a classification process to adjust the particle size.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet-mixed. Using the obtained slurry, for example, a strip-shaped dielectric green sheet having a thickness of 0.8 μm or less is coated on a base material by, for example, a die coater method or a doctor blade method, and dried.

Next, by printing a metal conductive paste for forming internal electrodes containing an organic binder on the surface of the dielectric green sheet by screen printing, gravure printing, etc., the internal electrodes are alternately led out to a pair of external electrodes having different polarities. A layer pattern (first pattern) is placed. Ceramic particles are added to the metal conductive paste as a common material. Although the main component of the ceramic particles is not particularly limited, it is preferably the same as the main component ceramic of the dielectric layer 11 . For example, BaTiO ₃ having an average particle size of 50 nm or less may be uniformly dispersed.

Next, a binder such as ethyl cellulose and an organic solvent such as terpineol are added to the reverse pattern material, and the mixture is kneaded in a roll mill to obtain a reverse pattern paste. On the dielectric green sheet, a reverse pattern (second pattern) is arranged by printing a reverse pattern paste in the peripheral area where the internal electrode layer pattern is not printed, and the gap with the internal electrode layer pattern is filled.

After that, the dielectric green sheet on which the internal electrode layer pattern and the reverse pattern are printed is punched into a predetermined size, and the punched dielectric green sheet is separated from the base material, and the internal electrode layer 12 and the dielectric are separated from each other. The internal electrode layers 12 are alternately exposed on both longitudinal end faces of the dielectric layers 11 so that the layers 11 alternate with each other, and the edges of the internal electrode layers 12 are alternately exposed to a pair of external electrodes 20a and 20b having different polarities. A predetermined number of layers are laminated as follows. A cover sheet to be the cover layer 13 is crimped to the top and bottom of the laminated dielectric green sheets, cut into a predetermined chip size, and subjected to binder removal treatment in an _N2 atmosphere at 250 to 500.degree. After that, a metal conductive paste, which will be the external electrodes 20a and 20b, is applied to both sides of the cut laminate by a dipping method or the like and dried. Thereby, a molded body of the laminated ceramic capacitor 100 is obtained.

(Baking process)
By firing the molded body thus obtained in a reducing atmosphere at a high temperature with an oxygen partial pressure of 10 ⁻⁵ to 10 ⁻⁸ atm, each compound is sintered and grains grow. Thus, the laminated ceramic capacitor 100 is obtained. In the present embodiment, as exemplified in FIG. 8, in the first half of the temperature rising process, the temperature rising rate B is slowed down to sufficiently remove carbon, and in the second half of the temperature rising process, the temperature rising rate A is increased. to proceed with sintering.

For example, in the first half of the temperature raising process, the heat treatment is sufficiently performed at a low temperature of 200° C. to 1000° C. in the reducing atmosphere. In order to suppress the influence of carbon during firing, the heating rate B is made sufficiently slow. For example, the heating rate B is preferably 800° C./hr or less, more preferably 500° C./hr or less. Moreover, the heating time in the first half of the heating step is preferably 1 hour or more and 16 hours or less, more preferably 2 hours or more and 8 hours or less. From the viewpoint of productivity, the temperature increase rate B is 200° C./hr or more.

Subsequently, in the latter half temperature raising step, sintering proceeds at a high temperature of 1000° C. or higher in the reducing atmosphere. In order to suppress the spheroidization of the metal component in the internal electrode layer 12, the heating rate A is made sufficiently fast. For example, the temperature increase rate A is preferably 10000° C./hr or more, and more preferably 50000° C./hr or more. In addition, the heating time in the latter heating step is preferably 0.01 minutes or more and 10 minutes or less, more preferably 0.1 minutes or more and 1 minute or less. In addition, it is preferable to set an upper limit to the rate of temperature increase A so as not to cause insufficient heat transfer to the firing jig. For example, the temperature increase rate A is preferably 100000° C./hr or less.

In the present embodiment, the heating rate A/heating rate B is set to 60 or more in order to sufficiently slow the heating rate in the first half of the heating process and sufficiently speed up the heating rate in the latter half of the heating process. and In order to sufficiently slow down the first half of the temperature rising process and sufficiently speed up the second half of the temperature rising process, the temperature rising rate A/heating rate B is preferably 200 or more, more preferably 400 or more. preferable.

When the temperature rise rate A/heat rate B is 60 or more, when focusing on the temperature in the middle from the start of temperature rise until the maximum temperature is reached, (the temperature rise from the middle temperature to the maximum temperature speed)/(temperature rising speed from room temperature to the intermediate temperature) is 60 or more. For example, when Ni is used for the internal electrode layers 12, the intermediate temperature can be 1000±200° C., and may be 1000° C.

The heating rate can be changed, for example, by changing the conveying speed of the roller hearth kiln in the middle. Alternatively, the rate of temperature increase can be changed by sequentially introducing the materials into firing furnaces having different temperatures using a belt conveyor or the like.

After that, the temperature range of 1100° C. to 1300° C. is maintained and sintering proceeds sufficiently. After that, the firing process is completed by lowering the temperature.

(Reoxidation treatment step)
After that, reoxidation treatment may be performed at 600° C. to 1000° C. in an N ₂ gas atmosphere.

(Plating process)
After that, metal coating such as Cu, Ni, and Sn may be applied to the external electrodes 20a and 20b by plating.

According to the manufacturing method according to the present embodiment, in the firing step, the ratio (A/B) between the temperature increase rate A in the latter temperature increase step and the temperature increase rate B in the first temperature increase step is set to 60 or more. Thus, the rate of temperature rise in the first half becomes sufficiently slow, and the rate of temperature rise in the second half becomes sufficiently fast. As a result, carbon can be sufficiently removed in the first half of the heating step, so that the influence of carbon during firing can be suppressed. As a result, residual stress can be suppressed, and structural defects can be suppressed. In addition, in the latter half of the heating step, the metal component of the internal electrode layers 12 can be sufficiently suppressed from becoming spherical. Thereby, a high continuous rate can be obtained. As described above, the CR product can be sufficiently increased in the large-sized, high-capacity multilayer ceramic capacitor 100 .

Hereinafter, multilayer ceramic capacitors according to the embodiments were produced and their characteristics were examined.

(Examples 1 to 10, Comparative Examples 1 to 3)
Necessary additives were added to the barium titanate powder, and the mixture was sufficiently wet-mixed and pulverized in a ball mill to obtain a dielectric material. A dielectric green sheet was prepared by adding an organic binder and a solvent to a dielectric material and using a doctor blade method. The coating thickness of the dielectric green sheet was 0.8 μm, polyvinyl butyral (PVB) or the like was used as the organic binder, and ethanol, toluic acid, or the like was added as the solvent. In addition, a plasticizer and the like were added. Next, an internal electrode-forming conductive paste containing powder of the main component metal of the internal electrode layers 12, a binder, a solvent, and, if necessary, other auxiliary agents was prepared. The organic binder and solvent of the conductive paste for forming the internal electrodes were different from those used for the dielectric green sheets. A conductive paste for forming internal electrodes was screen-printed on the dielectric sheet. A reverse pattern paste was printed on the portion where the internal electrode forming conductive paste was not printed to fill the steps of the internal electrode forming conductive paste. As the reverse pattern paste, for example, the same material as the dielectric layer green sheet can be used. Sheets printed with the conductive paste for forming the internal electrodes and the reverse pattern paste were stacked, and cover sheets were stacked on the top and bottom of the sheets. After that, a ceramic laminate was obtained by thermocompression bonding and cut into a predetermined shape.

In Example 1, the number of laminations was set to 1,700. In Example 2, the number of laminations was set to 1,200. In Example 3, the number of laminations was set to 1,100. In Example 4, the number of laminations was set to 700. In Comparative Examples 1 and 2, the number of laminations was set to 1,700. In Comparative Example 3, the number of laminations was set to 1,200. In Comparative Examples 4 and 5, the number of laminations was set to 1,100. In Comparative Examples 6 and 9, the number of laminations was set to 900. In Comparative Example 7, the number of laminations was set to 700. In Comparative Example 8, the number of laminations was set to 600.

After removing the binder from the obtained ceramic laminate in an _N2 atmosphere, a metal paste containing a metal filler containing Ni as a main component, a common material, a binder and a solvent was applied from both end surfaces to each side surface of the ceramic laminate. , dried.

After that, in a reducing atmosphere with a hydrogen concentration of 0.08%, the first half of the temperature rising process (heating rate B) from room temperature to 1000 ° C. is performed, and the latter half of the temperature rising process (heating rate B) from 1000 ° C. to about 1300 ° C. A) was performed. In Examples 1 to 4 and Comparative Examples 1 and 5 to 8, the heating rate B was set to 400° C./hr. In Comparative Examples 2 to 4 and 9, the heating rate B was set to 2000° C./hr. In Examples 1 to 4, the heating rate A was 25000° C./hr. In Comparative Example 1, the temperature increase rate A was set to 15000°C. In Comparative Examples 2 to 4 and 9, the heating rate A was 10000° C./hr. In Comparative Examples 5 to 8, the heating rate A was 1000° C./hr. Therefore, in Examples 1 to 4, A/B was set to 62.5. In Comparative Example 1, A/B was set to 37.5. In Comparative Examples 2 to 4 and 9, A/B was set to 5. In Comparative Examples 5 to 8, A/B was set to 2.5. After that, the temperature was maintained at 1300° C. for 5 minutes to obtain a sintered body.

After the sintered body is re-oxidized under _N2 atmosphere at 800° C., it is plated to form a Cu-plated layer 22, a Ni-plated layer 23 and an Sn-plated layer 24 on the surface of the underlying layer 21, and laminated. A ceramic capacitor 100 was obtained. 100 samples were prepared for each of Examples 1 to 4 and Comparative Examples 1 to 9. The obtained multilayer ceramic capacitor 100 had a shape of 4532 (length 4.5 mm, width 3.2 mm, height 2.5 mm) in Example 1 and Comparative Examples 1, 2 and 4. 4 and Comparative Examples 3 and 5 to 8 have 3225 shapes (length 3.2 mm, width 2.5 mm, height 2.5 mm), and Comparative Example 9 has 3216 shapes (length 3.2 mm, width 1 .6 mm, height 1.6 mm).

(analysis)
FIG. 9 shows the measurement results of Examples 1-4 and Comparative Examples 1-9. First, in Examples 1 to 4 and Comparative Examples 1 to 9, height T1, height T2, width W1 and width W2 were measured. For these measurements, VHX-1000 manufactured by Keyence Corporation was used. In Example 1 and Comparative Examples 1 and 2, the height T1 was 3.5 mm. In Examples 2-4 and Comparative Examples 3-8, the height T1 was 2.8 mm. In Comparative Example 9, the height T1 was 1.9 mm.

In Example 1 and Comparative Examples 1 and 2, the number of layers/T1 was 486 layers/mm. In Example 2 and Comparative Example 3, the number of layers/T1 was 429 layers/mm. In Example 3 and Comparative Examples 4 and 5, the number of layers/T1 was 393 layers/mm. In Example 4 and Comparative Example 7, the number of layers/T1 was 250 layers/mm. In Comparative Example 6, the number of layers/T1 was 321 layers/mm. In Comparative Example 8, the number of layers/T1 was 214 layers/mm. In Comparative Example 9, the number of layers/T1 was 474 layers/mm.

In Example 1 and Comparative Examples 1 and 2, the average weight was 347 mmg. In Example 2 and Comparative Example 3, the average weight was 155 mg. In Example 3 and Comparative Example 5, the average weight was 153 mg. In Example 4 and Comparative Example 7, the average weight was 131 mg. In Comparative Example 4, the average weight was 320 mg. In Comparative Example 6, the average weight was 147 mg. In Comparative Example 8, the average weight was 128 mg. In Comparative Example 9, the average weight was 73 mg.

In Example 1, (W1-W2)/W1 was 2.8%. In Example 2, (W1-W2)/W1 was 0.9%. In Example 3, (W1-W2)/W1 was -0.8%. In Example 4, (W1-W2)/W1 was 0.6%. In Comparative Example 1, (W1-W2)/W1 was 3.2%. In Comparative Example 2, (W1-W2)/W1 was 4.3%. In Comparative Example 3, (W1-W2)/W1 was 3.2%. In Comparative Example 4, (W1-W2)/W1 was 3.6%. In Comparative Example 5, (W1-W2)/W1 was 3.2%. In Comparative Example 6, (W1-W2)/W1 was 2.8%. In Comparative Example 7, (W1-W2)/W1 was 2.1%. In Comparative Example 8, (W1-W2)/W1 was 2.3%. In Comparative Example 9, (W1-W2)/W1 was 1.5%.

In Example 1, (T1-T2)/T1 was 4.4%. In Example 2, (T1-T2)/T1 was 2.8%. In Example 3, (T1-T2)/T1 was 1.2%. In Example 4, (T1-T2)/T1 was 0.9%. In Comparative Example 1, (T1-T2)/T1 was 4.8%. In Comparative Example 2, (T1-T2)/T1 was 10.8%. In Comparative Example 3, (T1-T2)/T1 was 5.3%. In Comparative Example 4, (T1-T2)/T1 was 7.1%. In Comparative Example 5, (T1-T2)/T1 was 4.7%. In Comparative Example 6, (T1-T2)/T1 was 4.6%. In Comparative Example 7, (T1-T2)/T1 was 4.8%. In Comparative Example 8, (T1-T2)/T1 was 4.0%. In Comparative Example 9, (T1-T2)/T1 was 3.7%.

Thus, in Examples 1 to 4, 0%≦(T1−T2)/T1≦+4.5% and −1.0%≦(W1−W2)/W1≦+3.0%. This is probably because the A/B ratio was set to 60 or more, so that the rate of temperature rise in the first half was sufficiently slow and the rate of temperature rise in the second half was sufficiently high. On the other hand, in Comparative Examples 1 to 7, at least one of 0% ≤ (T1 - T2) / T1 ≤ +4.5% and -1.0% ≤ (W1 - W2) / W1 ≤ +3.0% did not meet the conditions of This is probably because the A/B ratio was set to less than 60, so that the heating rate in the first half was not sufficiently slow or the heating rate in the second half was not sufficiently fast. In Comparative Examples 8 and 9, the conditions of 0%≦(T1−T2)/T1≦+4.5% and −1.0%≦(W1−W2)/W1≦+3.0% were satisfied. It is considered that this is because the influence of the sintering temperature gap between the dielectric layers 11 and the internal electrode layers 12 was suppressed because the weight was less than 130 mg. In Comparative Example 8, the fact that Area1/Area2 was less than 80% also contributed to suppressing the influence of the sintering temperature gap between the dielectric layers 11 and the internal electrode layers 12 .

Next, structural defects in Examples 1-4 and Comparative Examples 1-9 were investigated. Structural defects were examined for cracks in firing exemplified in FIG. 10(a) and cracks in binder removal exemplified in FIG. 10(b). A crack in firing is a structural defect in which a crack 50 is formed in a part of the cover layer 13 or the side margin. A crack in binder removal is a structural defect in which a crack 60 is generated from the side margin region 16 to the capacitor region. Structural defects occurred in Comparative Examples 2-4. It is considered that this is because at least one of the difference between the height T1 and the height T2 and the difference between the width W1 and the width W2 increases, resulting in an increase in the residual stress. In addition, it is considered that carbon could not be sufficiently removed because the heating rate B was set to a high rate of 2000° C./hr.

Next, the continuity rates of Examples 1-4 and Comparative Examples 1-9 were investigated. In any of Examples 1 to 4, the continuous rate was a high value of 85% or more. This is probably because the A/B ratio was set to 60 or more, so that the rate of temperature rise in the second half was sufficiently high. On the other hand, in Comparative Examples 1 to 7, the continuous rate was a low value of less than 85%. It is believed that this is because the A/B ratio of less than 60 did not sufficiently increase the rate of temperature rise in the second half. In addition, in Comparative Examples 8 and 9, the continuous rate was a high value of 85% or more. It is considered that this is because the influence of the sintering temperature gap between the dielectric layers 11 and the internal electrode layers 12 was suppressed because the weight was less than 130 mg. In Comparative Example 8, the fact that Area1/Area2 was less than 80% also contributed to suppressing the influence of the sintering temperature gap between the dielectric layers 11 and the internal electrode layers 12 .

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations can be made within the scope of the gist of the present invention described in the scope of claims. Change is possible.

REFERENCE SIGNS LIST 10 laminated chip 11 dielectric layer 12 internal electrode layer 13 cover layer 14 capacitance region 15 end margin region 16 side margin region 20a, 20b external electrode 100 laminated ceramic capacitor

Claims (6)

Dielectric layers containing ceramic as a main component and internal electrode layers are alternately laminated, and the plurality of laminated internal electrode layers are formed so as to be exposed on two end faces that are alternately opposed to each other, and have a substantially rectangular parallelepiped shape. a laminated chip having
a pair of external electrodes formed on the two end faces,
the total weight of the laminated chip and the pair of external electrodes is 131 mg or more , and the size is 3225 or more;
In the laminated chip, the height in the lamination direction of the laminated chip at the center of the width direction of the internal electrode layer in the cross section perpendicular to the first direction at the center of the first direction where the two end faces face each other is T1 Let T2 be the height passing through the end points of the internal electrode layers in the second direction, which is the width direction of the internal electrode layers, and W1 be the width in the second direction passing through any of the outermost internal electrode layers. , where the width in the second direction passing through the center of the stacking direction is W2, (T1-T2)/T1 is +0.9% or more and +4.4% or less , and (W1-W2)/W1 is -0.8% or more and +2.8% or less ,
The number of layers of the internal electrode layers with respect to T1 is 250 layers / mm or more,
A multilayer ceramic capacitor, wherein the continuity rate of the internal electrode layers is 86% or more . 2. The multilayer ceramic capacitor according to claim 1, wherein, in the cross section, the ratio of the area of the capacitive regions where the internal electrode layers exposed on different end faces face each other to the total area is 80% or more. 3. The multilayer ceramic capacitor according to claim 1, wherein the number of internal electrode layers stacked with respect to T1 is 400 layers/mm or more. Ceramic dielectric layer green sheets and internal electrode forming conductive pastes are alternately laminated, and a plurality of laminated conductive pastes for forming internal electrodes are alternately exposed on two opposite end faces, thereby forming a substantially rectangular parallelepiped shape. forming a ceramic laminate;
obtaining a laminated chip by firing the ceramic laminate;
forming a pair of external electrodes by plating on the underlying layers of the two end faces of the laminated chip,
the total weight of the laminated chip and the pair of external electrodes is 131 mg or more , and the size is 3225 or more;
In the laminated chip, in a cross section perpendicular to the first direction at the center of the first direction in which the two end faces face each other, the width direction center of the internal electrode layer obtained from the conductive paste for forming the internal electrode and the lamination When the height of the chip is T1, the number of stacked internal electrode layers with respect to T1 is 250 layers/mm or more,
The step of firing the ceramic laminate includes a first half temperature raising step and a second half temperature raising step,
(Temperature increase rate in the second half temperature increase step )/(Temperature increase rate in the first half temperature increase step) is set to 62.5 or more ,
The heating rate in the first half heating step is set to 200° C./hr or more ,
The heating time of the heating step in the first half is set to 1 hour or more and 16 hours or less,
A method for manufacturing a laminated ceramic capacitor, wherein the heating time in the second heating step is set to 0.01 minute or more and 10 minutes or less . 5. The method of manufacturing a multilayer ceramic capacitor according to claim 4, wherein the temperature for switching from the temperature increase rate in the first half temperature increase process to the temperature increase rate in the second temperature increase process is 1000±200.degree. Dielectric layers containing ceramic as a main component and internal electrode layers are alternately laminated, and the plurality of laminated internal electrode layers are formed so as to be exposed on two end faces that are alternately opposed to each other, and have a substantially rectangular parallelepiped shape. a laminated chip having
a pair of external electrodes formed on the two end faces,
The total weight of the laminated chip and the pair of external electrodes is 131 mg or more ,
In the laminated chip, the height in the lamination direction of the laminated chip at the center of the width direction of the internal electrode layer in the cross section perpendicular to the first direction at the center of the first direction where the two end faces face each other is T1 Let T2 be the height passing through the end points of the internal electrode layers in the second direction, which is the width direction of the internal electrode layers, and W1 be the width in the second direction passing through any of the outermost internal electrode layers. , where the width in the second direction passing through the center of the stacking direction is W2, (T1-T2)/T1 is +0.9% or more and +4.4% or less , and (W1-W2)/W1 is -0.8% or more and +2.8% or less ,
T1 is 2.8 mm or more,
The number of layers of the internal electrode layers with respect to T1 is 250 layers / mm or more,
A multilayer ceramic capacitor, wherein the continuity rate of the internal electrode layers is 86% or more .

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