JP2018139253A - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor in which difference of sinter contraction behavior between a capacity region and a side margin area can be made small enough, and to provide a manufacturing method thereof.SOLUTION: A multilayer ceramic capacitor includes a lamination structure formed so that a dielectric layer 11 mainly composed of ceramic, and an internal electrode layer 12 are laminated alternately, while having a substantially rectangular parallelepiped shape, so that laminated multiple internal electrode layers are exposed alternately to two end faces facing each other, and a ceramic-based side margin area 16 provided so that the laminated multiple internal electrode layers in the lamination structure cover two lateral faces other than the two end faces. Respective concentrations of Mn, Si, B to the main ceramic in the side margin area are higher than the respective concentrations of Mn, Si, B to the main ceramic in the dielectric layer of lamination structure.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

  In recent years, along with miniaturization of electronic devices such as smartphones and mobile phones, miniaturization of electronic components to be mounted is rapidly progressing. For example, in a multilayer ceramic capacitor, the dielectric layer and the internal electrode layer have been made thinner in order to reduce the chip size while ensuring predetermined characteristics.

  As the dielectric layers are made thinner, the number of dielectric layers tends to increase. For example, a multilayer ceramic capacitor has a structure in which dielectric layers and internal electrode layers are alternately stacked. However, the internal electrode layer does not cover the entire dielectric layer so that the internal electrode layer is not exposed from the side surface of the chip, and is formed only up to a position inside the periphery of the dielectric layer. A step is formed between the capacitor region in which the electrode layer is stacked and the side margin region in which the dielectric layer is stacked without the internal electrode layer. When the number of stacked dielectric layers increases, structural defects such as delamination due to the step are likely to occur.

  As a measure to solve such a problem, for example, after printing the internal electrode pattern on the ceramic green sheet, the reverse pattern of the ceramic paste is printed on the portion where the internal electrode pattern is not printed, thereby absorbing the step. A method has been proposed.

  However, in the case of the above method, a fine gap is generated between the end portion of the internal electrode layer and the side margin region due to the difference in sintering shrinkage behavior between the capacitance region and the side margin region during firing. In this case, a problem arises that moisture such as moisture penetrates into the gap and causes poor moisture resistance.

  Then, the method of making the difference of a sintering shrinkage | contraction behavior small by covering the surface of the ceramic powder used for the ceramic green sheet for level | step difference absorption with a glass film is disclosed (for example, refer patent document 1). Alternatively, a method has been disclosed in which moisture resistance is improved by making the Mg concentration in the side gap portion higher than the Mg concentration in the effective layer portion that contributes to capacity formation (see, for example, Patent Document 2).

JP 2004-96010 A JP 2010-103566 A

  However, with the above technique, the difference in sintering shrinkage behavior between the capacity region and the side margin region may not be sufficiently reduced.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor capable of sufficiently reducing the difference in sintering shrinkage behavior between the capacity region and the side margin region, and a method for manufacturing the same. To do.

  In the multilayer ceramic capacitor according to the present invention, dielectric layers mainly composed of ceramic and internal electrode layers are alternately stacked to have a substantially rectangular parallelepiped shape, and the plurality of stacked internal electrode layers are alternately stacked. A laminated structure formed so as to be exposed at two opposing end faces, and a plurality of the internal electrode layers laminated in the laminated structure are provided so as to cover ends extending to two side faces other than the two end faces, and ceramic And a concentration of Mn, Si, B relative to the main component ceramic in the side margin region is Mn, Si, B relative to the main component ceramic in the dielectric layer of the laminated structure. It is characterized by being higher than the respective concentrations of B.

  In the multilayer ceramic capacitor, barium titanate may be used as a main component ceramic of the side margin region and the dielectric layer.

  In the multilayer ceramic capacitor, the main component of the internal electrode layer may be nickel.

  The method for manufacturing a multilayer ceramic capacitor according to the present invention includes a first step of arranging a first pattern of a metal conductive paste on a green sheet containing main component ceramic particles, and a peripheral region of the metal conductive paste on the green sheet. A second step of disposing a second pattern containing main component ceramic particles, and a third step of firing a ceramic laminate obtained by laminating a plurality of laminate units obtained in the second step. The respective concentrations of Mn, Si and B with respect to the main component ceramic in the second pattern are higher than the respective concentrations of Mn, Si and B with respect to the main component ceramic in the green sheet.

  In the method for manufacturing a multilayer ceramic capacitor, the Mn concentration relative to the main component ceramic in the second pattern may be 0.5 atm% or more and 2.5 atm% or less.

  In the method for manufacturing a multilayer ceramic capacitor, the Si concentration relative to the main component ceramic in the second pattern may be 1.5 atm% or more and 2.5 atm% or less.

  In the method for manufacturing a multilayer ceramic capacitor, the B concentration with respect to the main component ceramic in the second pattern may be 0.2 atm% or more and 0.3 atm% or less.

  In the method for manufacturing the multilayer ceramic capacitor, the main component ceramic of the green sheet and the second pattern may be barium titanate.

  In the method for manufacturing a multilayer ceramic capacitor, the main component metal of the first pattern may be nickel.

  According to the present invention, the difference in sintering shrinkage behavior between the capacity region and the side margin region can be sufficiently reduced.

It is a partial section perspective view of a multilayer ceramic capacitor. It is the sectional view on the AA line of FIG. It is the BB sectional view taken on the line of FIG. The cross section of the side margin region is enlarged. It is a figure which illustrates the flow of the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows a measurement result.

  Hereinafter, embodiments will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. 2 is a cross-sectional view taken along line AA in FIG. 3 is a cross-sectional view taken along line BB in FIG. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a rectangular parallelepiped shape and external electrodes 20 a and 20 b provided on two opposing end faces of the multilayer chip 10. Of the four surfaces other than the two end surfaces of the multilayer chip 10, two surfaces other than the upper surface and the lower surface in the stacking direction are referred to as side surfaces. The external electrodes 20 a and 20 b extend on the upper surface, the lower surface, and the two side surfaces of the multilayer chip 10 in the stacking direction. However, the external electrodes 20a and 20b are separated from each other.

  The multilayer chip 10 has a configuration in which dielectric layers 11 including a ceramic material functioning as a dielectric and internal electrode layers 12 including a base metal material are alternately stacked. The edge of each internal electrode layer 12 is alternately exposed on the end surface of the multilayer chip 10 where the external electrode 20a is provided and the end surface where the external electrode 20b is provided. Thereby, each internal electrode layer 12 is alternately conducted to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are stacked via the internal electrode layer 12. In the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is disposed as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered with the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layer 11 and the ceramic material.

  The size of the multilayer ceramic capacitor 100 is, for example, a length of 0.2 mm, a width of 0.125 mm, and a height of 0.125 mm, or a length of 0.4 mm, a width of 0.2 mm, a height of 0.2 mm, or a length. 0.6 mm, width 0.3 mm, height 0.3 mm, or length 1.0 mm, width 0.5 mm, height 0.5 mm, or length 3.2 mm, width 1.6 mm, height The length is 1.6 mm, or the length is 4.5 mm, the width is 3.2 mm, and the height is 2.5 mm, but is not limited to these sizes.

The internal electrode layer 12 is mainly composed of a base metal such as Ni (nickel), Cu (copper), or Sn (tin). As the internal electrode layer 12, a noble metal such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), or an alloy containing these may be used. The dielectric layer 11 includes, for example, a ceramic material having a perovskite structure represented by the general formula ABO ₃ as a main component. Note that the perovskite structure includes ABO _3-α deviating from the stoichiometric composition. For example, as the ceramic material, BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), Ba _1-xy which forms a perovskite structure. _{Ca x Sr y Ti 1-z} Zr z O 3 (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1) , or the like can be used.

  As illustrated in FIG. 2, a region where the internal electrode layer 12 connected to the external electrode 20 a and the internal electrode layer 12 connected to the external electrode 20 b face each other is a region in which electric capacity is generated in the multilayer ceramic capacitor 100. . Therefore, this area is referred to as a capacity area 14. That is, the capacitance region 14 is a region where two adjacent internal electrode layers 12 connected to different external electrodes face each other.

  A region where the internal electrode layers 12 connected to the external electrode 20a are opposed to each other without the internal electrode layer 12 connected to the external electrode 20b is referred to as an end margin region 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without the internal electrode layer 12 connected to the external electrode 20a is also the end margin region 15. That is, the end margin region 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without the internal electrode layers 12 connected to different external electrodes. The end margin area 15 is an area where no capacity is generated.

  As illustrated in FIG. 3, in the multilayer chip 10, an area from the two side surfaces of the multilayer chip 10 to the internal electrode layer 12 is referred to as a side margin area 16. That is, the side margin region 16 is a region provided so as to cover the end portions of the plurality of internal electrode layers 12 stacked in the stacked structure extending to the two side surfaces.

  FIG. 4 is an enlarged view of the side margin region 16. The side margin region 16 has a structure in which the dielectric layers 11 and the reverse pattern layers 17 are alternately stacked in the stacking direction of the dielectric layers 11 and the internal electrode layers 12 in the capacitor region 14. Each dielectric layer 11 in the capacitance region 14 and each dielectric layer 11 in the side margin region 16 are continuous layers. According to this configuration, a step between the capacitance region 14 and the side margin region 16 is suppressed.

  The capacity region 14 and the side margin region 16 are obtained by firing ceramic raw material powder. However, during firing, a difference in sintering shrinkage behavior occurs between the internal electrode layer 12 and the reverse pattern layer 17 due to the difference in sinterability between the metal and the ceramic material. Specifically, the sinterability of the internal electrode layer 12 is higher than the sinterability of the reverse pattern layer 17. Thereby, a fine gap may be generated between the end portion of the internal electrode layer 12 and the reverse pattern layer 17. If moisture such as moisture penetrates into this gap, there may be a problem that it causes poor moisture resistance. Here, high sinterability can be defined as a low shrinkage (densification) completion temperature.

  Therefore, in this embodiment, the sintering aid concentration of the reverse pattern layer 17 is higher than the sintering aid concentration of the dielectric layer 11. Specifically, the respective concentrations of Mn (manganese), Si (silicon) and B (boron) in the reverse pattern layer 17 are higher than the respective concentrations of Mn, Si and B in the dielectric layer 11. . In this configuration, the sinterability of the reverse pattern layer 17 is increased, and the difference in sintering shrinkage behavior between the reverse pattern layer 17 and the internal electrode layer 12 is reduced. Thereby, the generation of a gap between the end portion of the internal electrode layer 12 and the reverse pattern layer 17 can be suppressed. In this case, moisture intrusion is suppressed and moisture resistance is improved. As a result, the life characteristics of the dielectric layer 11 are improved, and the reliability of the multilayer ceramic capacitor 100 is improved.

  When Mn, Si, and B diffuse from the reverse pattern layer 17 during firing, the respective concentrations of Mn, Si, and B in the entire side margin region 16 are Mn, Si, and B in the dielectric layer 11 in the capacitor region 14. And higher than the respective concentrations of B. In this case, the difference in sintering shrinkage behavior between the side margin region 16 and the capacity region 14 is reduced.

If the reverse pattern layer 17 has too much Mn, Mn diffuses into the dielectric layer 11 in the capacitor region 14, which may reduce the capacitance of the capacitor region 14. Therefore, it is preferable to set an upper limit on the Mn concentration in the reverse pattern layer 17. In the present embodiment, as an example, the Mn concentration in the reverse pattern layer 17 is preferably set to 2.5 atm% or less. The concentration (atm%) is a concentration when the B site of the main component ceramic having a perovskite structure represented by the general formula ABO ₃ is 100 atm%. The same shall apply hereinafter. On the other hand, if there is too little Mn in the reverse pattern layer 17, high reverse sinterability is not obtained in the reverse pattern layer 17, and there is a gap between the end of the internal electrode layer 12 and the reverse pattern layer 17 as the grains grow. May occur, and the life characteristics of the dielectric layer 11 may be deteriorated. Therefore, it is preferable to provide a lower limit for the Mn concentration in the reverse pattern layer 17. In the present embodiment, as an example, the Mn concentration in the reverse pattern layer 17 is preferably set to 0.5 atm% or more.

  If there is too much Si in the reverse pattern layer 17, the grain growth region of the reverse pattern layer 17 reaches the vicinity of the end of the internal electrode layer 12, stress is generated in the internal electrode layer 12, and structural defects are generated in the internal electrode layer 12. In addition, the life characteristics may be deteriorated. Therefore, it is preferable to set an upper limit on the Si concentration in the reverse pattern layer 17. In the present embodiment, as an example, the Si concentration in the reverse pattern layer 17 is preferably 2.5 atm% or less. On the other hand, if there is too little Si in the reverse pattern layer 17, a high sinterability cannot be obtained in the reverse pattern layer 17, and a gap is generated between the end portion of the internal electrode layer 12 and the reverse pattern layer 17, thereby causing a dielectric. There exists a possibility that the lifetime characteristic of the layer 11 may fall. Therefore, it is preferable to provide a lower limit for the Si concentration in the reverse pattern layer 17. In the present embodiment, as an example, the Si concentration in the reverse pattern layer 17 is preferably 1.2 atm% or more.

  If there is too much B in the reverse pattern layer 17, the grain growth region of the reverse pattern layer 17 reaches the vicinity of the end of the internal electrode layer 12, stress is generated in the internal electrode layer 12, and structural defects are generated in the internal electrode layer 12. In addition, the life characteristics may be deteriorated. Therefore, it is preferable to set an upper limit on the B concentration in the reverse pattern layer 17. In the present embodiment, as an example, the B concentration in the reverse pattern layer 17 is preferably set to 0.3 atm% or less. On the other hand, if the amount of B in the reverse pattern layer 17 is too small, a high sinterability cannot be obtained in the reverse pattern layer 17 and a gap is generated between the end portion of the internal electrode layer 12 and the reverse pattern layer 17. There exists a possibility that the lifetime characteristic of the layer 11 may fall. Therefore, it is preferable to set a lower limit for the B concentration in the reverse pattern layer 17. In the present embodiment, as an example, the B concentration in the reverse pattern layer 17 is preferably set to 0.15 atm% or more.

  Then, the manufacturing method of the multilayer ceramic capacitor 100 is demonstrated. FIG. 5 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100.

(Raw material powder production process)
First, as illustrated in FIG. 5, a dielectric material for forming the dielectric layer 11 is prepared. The A site element and the B site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO ₃ particles. For example, BaTiO ₃ is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO ₃ can be generally obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. As a method for synthesizing the ceramic constituting the dielectric layer 11, various methods are conventionally known, for example, a solid phase method, a sol-gel method, a hydrothermal method, and the like. Any of these may be employed in the present embodiment.

  A predetermined additive compound is added to the obtained ceramic powder according to the purpose. As additive compounds, Mn, V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Dy (dysprosium), Tm (thulium), Ho (holmium), Tb (terpium), Yb (ytterbium), Sm (samarium), Eu (eurobium), Gd (gadolinium), and Er (erbium) oxides, and Co (cobalt), Ni, Li (lithium), B, Na (sodium), K (potassium) And Si oxide or glass. In the present embodiment, at least a Mn source, a Si source, and a B source are added to the obtained ceramic powder.

  In the present embodiment, preferably, first, the ceramic particles constituting the dielectric layer 11 are mixed with a compound containing an additive compound and calcined at 820 to 1150 ° C. Subsequently, the obtained ceramic particles are wet-mixed with an additive compound, dried and pulverized to prepare a ceramic powder. For example, the average particle diameter of the ceramic powder is preferably 50 to 300 nm from the viewpoint of thinning the dielectric layer 11. For example, the ceramic powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification treatment to adjust the particle size.

  Next, a reverse pattern material for forming the side margin region 16 is prepared. Depending on the purpose, a predetermined additive compound is added to the barium titanate ceramic powder obtained by the same process as that for producing the dielectric material. Examples of additive compounds include Mn, V, Cr, rare earth elements (Y, Dy, Tm, Ho, Tb, Yb, Sm, Eu, Gd, and Er), and Co, Ni, Li, B, Na. , K and Si oxides or glasses. In the present embodiment, at least a Mn source, a Si source, and a B source are added to the obtained ceramic powder. Also, the amount of each of Mn, Si and B added is increased compared to the dielectric material.

  In the present embodiment, preferably, the ceramic particles constituting the side margin region 16 are first mixed with a compound containing an additive compound and calcined at 820 to 1150 ° C. Subsequently, the obtained ceramic particles are wet-mixed with an additive compound, dried and pulverized to prepare a ceramic powder. For example, the average particle size of the ceramic powder is preferably 50 to 300 nm according to the material. For example, the ceramic powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification treatment to adjust the particle size.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer such as dioctyl phthalate (DOP) are added to the obtained dielectric material and wet mixed. Using the obtained slurry, for example, a band-shaped dielectric green sheet having a thickness of 0.8 μm or less is applied on a substrate by, for example, a die coater method or a doctor blade method and dried.

Next, internal electrodes that are alternately drawn out to a pair of external electrodes having different polarities by printing a metal conductive paste containing an organic binder on the surface of the dielectric green sheet by screen printing, gravure printing, or the like. A layer pattern (first pattern) is arranged. Ceramic particles are added as a co-material to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. For example, BaTiO ₃ having an average particle diameter of 50 nm or less may be uniformly dispersed.

  Next, an ethyl cellulose-based binder and a terpineol-based organic solvent were added to the reverse pattern material and kneaded by a roll mill to obtain a reverse pattern paste. On the dielectric green sheet, a reverse pattern (second pattern) is arranged by printing a reverse pattern paste in a peripheral region where the internal electrode layer pattern is not printed, thereby filling a step with the internal electrode layer pattern.

  Thereafter, the dielectric green sheet on which the internal electrode layer pattern and the reverse pattern are printed is punched to a predetermined size, and the punched dielectric green sheet is peeled off from the internal electrode layer 12 and the dielectric. The internal electrode layers 12 are alternately drawn out to a pair of external electrodes 20a and 20b having different polarities so that the edges of the internal electrode layers 12 are alternately exposed at both end surfaces in the length direction of the dielectric layer 11 so that the layers 11 are alternated. As described above, a predetermined number of layers (for example, 100 to 500 layers) are stacked. A cover sheet to be the cover layer 13 is pressure-bonded to the upper and lower sides of the laminated dielectric green sheets, cut into a predetermined chip size (for example, 1.0 mm × 0.5 mm), and then a metal conductive paste to be the external electrodes 20a and 20b is applied. Then, it is applied to both sides of the cut laminate by a dip method and dried. Thereby, a molded body of the multilayer ceramic capacitor 100 is obtained.

(Baking process)
The molded body thus obtained was subjected to binder removal treatment in an N ₂ atmosphere at 250 to 500 ° C., and then at 1100 to 1300 ° C. for 10 minutes in a reducing atmosphere having an oxygen partial pressure of 10 ⁻⁵ to 10 ⁻⁸ atm. By firing for 2 hours, each compound sinters and grows. In this way, the multilayer ceramic capacitor 100 is obtained.

(Reoxidation process)
It may then be subjected to re-oxidizing treatment at 600 ° C. to 1000 ° C. in _{an N 2} gas atmosphere.
(Plating process)
Thereafter, a metal coating such as Cu, Ni, or Sn may be applied to the external electrodes 20a and 20b by plating.

  According to the manufacturing method according to this embodiment, the respective concentrations of Mn, Si and B with respect to the main component ceramic in the reverse pattern material are higher than the respective concentrations of Mn, Si and B with respect to the main component ceramic in the dielectric material. Become. In this case, the sinterability of the reverse pattern layer 17 increases, and the difference in sintering shrinkage behavior between the reverse pattern layer 17 and the internal electrode layer 12 decreases. That is, the difference in sintering shrinkage behavior between the side margin region 16 and the capacitance region 14 is reduced. Thereby, the generation of a gap between the end portion of the internal electrode layer 12 and the reverse pattern layer 17 can be suppressed. In this case, moisture intrusion is suppressed and moisture resistance is improved. As a result, the life characteristics of the dielectric layer 11 are improved, and the reliability of the multilayer ceramic capacitor 100 is improved.

  In addition, when there is too much Mn with respect to the main component ceramic in a reverse pattern material, there exists a possibility that the capacity | capacitance of the capacity | capacitance area | region 14 may fall because Mn diffuses into the dielectric material layer 11 of the capacity | capacitance area | region 14. FIG. Therefore, it is preferable to set an upper limit on the Mn concentration relative to the main component ceramic in the reverse pattern material. In this embodiment, as an example, it is preferable to adjust so that the Mn concentration in the reverse pattern material is 2.5 atm% or less. On the other hand, if the Mn with respect to the main component ceramic in the reverse pattern material is too small, a high sinterability cannot be obtained in the reverse pattern layer 17, and the end portion of the internal electrode layer 12 and the reverse pattern layer 17 are accompanied by grain growth. There is a possibility that a gap is generated between them, and the life characteristics of the dielectric layer 11 may be deteriorated. Therefore, it is preferable to set a lower limit for the Mn concentration relative to the main component ceramic in the reverse pattern material. In the present embodiment, as an example, it is preferable to adjust so that the Mn concentration in the reverse pattern material is 0.5 atm% or more. From the viewpoint of making the dielectric layer 11 have both good capacity and good lifetime characteristics, it is more preferable to adjust the Mn concentration in the reverse pattern material to be 2.25 atm% ± 0.25 atm%.

  When there is too much Si for the main component ceramic in the reverse pattern material, the grain growth region of the reverse pattern layer 17 reaches the vicinity of the end of the internal electrode layer 12, and stress is generated in the internal electrode layer 12, so that the internal electrode layer 12 is structured. Defects may be generated and the life characteristics may be reduced. Therefore, it is preferable to set an upper limit on the Si concentration with respect to the main component ceramic in the reverse pattern material. In the present embodiment, as an example, it is preferable to adjust so that the Si concentration in the reverse pattern material is 2.5 atm% or less. On the other hand, if the Si with respect to the main component ceramic in the reverse pattern material is too small, a high sinterability cannot be obtained in the reverse pattern layer 17 and a gap is generated between the end of the internal electrode layer 12 and the reverse pattern layer 17. The life characteristics of the dielectric layer 11 may be deteriorated. Therefore, it is preferable to set a lower limit on the Si concentration with respect to the main component ceramic in the reverse pattern material. In the present embodiment, as an example, it is preferable to adjust so that the Si concentration in the reverse pattern material is 1.5 atm% or more. From the viewpoint of achieving both suppression of grain growth in the reverse pattern layer 17 and good sinterability, it is more preferable to adjust the Si concentration in the reverse pattern material to be 2.25 atm% ± 0.25 atm%.

  If there is too much B with respect to the main component ceramic in the reverse pattern material, the grain growth region of the reverse pattern layer 17 reaches the vicinity of the end of the internal electrode layer 12, and stress is generated in the internal electrode layer 12 to form a structure in the internal electrode layer 12. Defects may be generated and the life characteristics may be reduced. Therefore, it is preferable to set an upper limit to the B concentration with respect to the main component ceramic in the reverse pattern material. In this embodiment, as an example, it is preferable to adjust so that the B concentration in the reverse pattern material is 0.3 atm% or less. On the other hand, if the B with respect to the main component ceramic in the reverse pattern material is too small, a high sinterability cannot be obtained in the reverse pattern layer 17 and a gap is generated between the end of the internal electrode layer 12 and the reverse pattern layer 17. The life characteristics of the dielectric layer 11 may be deteriorated. Therefore, it is preferable to set a lower limit for the B concentration with respect to the main component ceramic in the reverse pattern material. In the present embodiment, as an example, it is preferable to adjust so that the B concentration in the reverse pattern material is 0.2 atm% or more. From the viewpoint of achieving both suppression of grain growth in the reverse pattern layer 17 and good sinterability, it is more preferable to adjust the B concentration in the reverse pattern material to be 0.25 atm% ± 0.05 atm%.

  Hereinafter, the multilayer ceramic capacitor according to the embodiment was produced, and the characteristics were examined.

(Examples 1-12)
(Production of dielectric material)
For barium titanate powder (average particle size 0.1 μm) 100 atm%, Ho concentration is 0.75 atm%, Mn concentration is 0.08 atm%, V concentration is 0.09 atm%, Si concentration is 1.15 atm%, Ho ₂ O ₃ , MnCO ₃ , V ₂ O ₃ , SiO ₂ , and B ₂ O ₃ are weighed so that the B concentration becomes 0.13 atm%, and a dielectric material is obtained by sufficiently wet-mixing and grinding with a ball mill. It was.

(Production of reverse pattern material)
In Examples 1 to 12, Ho ₂ O ₃ and V ₂ were adjusted so that the Ho concentration was 0.75 atm% and the V concentration was 0.09 atm% with respect to 100 atm% of barium titanate powder (average particle size 0.1 μm). O ₃ was weighed. MnCO ₃ was adjusted so that the Mn concentration in the reverse pattern material was 2.00 atm% in Example 1, 2.25 atm% in Example 2, 2.50 atm% in Example 3, and 3.00 atm% in Example 4. Weighed. In Examples 1 to 4, SiO ₂ and B ₂ O ₃ were weighed so that the Si concentration in the reverse pattern material was 2.00 atm% and the B concentration was 0.25 atm%. The SiO ₂ concentration in the reverse pattern material was 1.50 atm% in Example 5, 2.00 atm% in Example 6, 2.50 atm% in Example 7, and 3.00 atm% in Example 8. Was weighed. In Examples 5 to 8, MnCO ₃ and B ₂ O ₃ were weighed so that the Mn concentration in the reverse pattern material was 2.25 atm% and the B concentration was 0.25 atm%. B concentration in the reverse pattern material, 0.20Atm% in Example 9, 0.25 atm% in Example 10, 0.30atm% in Example 11, so that 0.50 atm% in Example 12, _{B 2} O ₃ was weighed. In Examples 9 to 12, MnCO ₃ and SiO ₂ were weighed so that the Mn concentration in the reverse pattern material was 2.25 atm% and the Si concentration was 2.00 atm%. Thereafter, the mixture was sufficiently wet-mixed and pulverized with a ball mill to obtain a reverse pattern material.

(Preparation of reverse pattern paste)
The reverse pattern paste was obtained by adding ethyl cellulose type as an organic binder and terpineol type as a solvent to the reverse pattern material and kneading with a roll mill.

(Production of multilayer ceramic capacitor)
A 1.2 μm green sheet was prepared by a doctor blade method by adding butyral as an organic binder and toluene and ethyl alcohol as solvents to the dielectric material. An internal electrode paste was screen-printed on the obtained sheet to form an internal electrode, and a reverse pattern paste was screen-printed on a portion without the internal electrode to fill the steps of the internal electrode. 250 printed sheets were stacked, and 30 μm of cover sheets were stacked on the top and bottom. Then, the laminated body was obtained by thermocompression bonding and cut into a predetermined shape. A Ni external electrode is formed on the obtained laminate by a dip method, and after a binder removal treatment in an N ₂ atmosphere, firing is performed at 1250 ° C. in a reducing atmosphere (O ₂ partial pressure: 10 ⁻⁵ to 10 ⁻⁸ atm). Thus, a sintered body was obtained. The shape dimensions were 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height. The sintered body was subjected to a re-oxidation treatment under a N ₂ atmosphere at 800 ° C., and then plated, and the surface of the external electrode terminal was coated with Cu, Ni, and Sn to obtain a multilayer ceramic capacitor. Note that, after firing, the thickness of the Ni internal electrode was 1.0 μm.

(Comparative Example 1)
In Comparative Example 1, in the process of producing the reverse pattern material, the Ho concentration is 0.75 atm%, the Mn concentration is 2.25 atm%, and the V concentration with respect to 100 atm% of the barium titanate powder (average particle diameter 0.1 μm). Of Ho ₂ O ₃ , MnCO ₃ , V ₂ O ₃ , SiO ₂ , and B ₂ O ₃ were weighed so that 0.09 atm%, Si concentration was 1.00 atm%, and B concentration was 0.25 atm%. . Other conditions were the same as in Examples 1-12.

(Comparative Example 2)
In Comparative Example 2, in the step of producing the reverse pattern material, the Ho concentration in the reverse pattern layer 17 after firing was 0.75 atm% and the Mn concentration with respect to 100 atm% of the barium titanate powder (average particle diameter 0.1 μm). Is 2.25 atm%, V concentration is 0.09 atm%, Si concentration is 2.00 atm%, and B concentration is 0.10 atm%, Ho ₂ O ₃ , MnCO ₃ , V ₂ O ₃ , SiO ₂ , And B ₂ O ₃ were weighed. Other conditions were the same as in Examples 1-12.

(analysis)
HALT (Highly Accelerated Limit Test) defect rate and capacity acquisition rate were measured for Examples 1 to 12 and Comparative Examples 1 and 2. In the measurement of the HALT defective rate, 125 ° C-12Vdc-120min-100 HALT tests were carried out, a short defective rate of less than 10% passed (◯), 10% or more and less than 20% (△), 20 % Or more was regarded as rejected (x). In measuring the capacity acquisition rate, the capacity was measured with an LCR meter. This measured value and the dielectric constant of the dielectric material (preparing a disk-shaped sintered body of φ = 10 mm × T = 1 mm using only the dielectric material and measuring the capacitance to calculate the dielectric constant) The design value calculated from the crossing area, dielectric ceramic layer thickness, and the number of laminated layers is compared. If the capacity acquisition rate (measured value / design value × 100) is 90% to 105%, pass (○) is 90% Those less than (△).

  FIG. 6 is a diagram showing the measurement results. In any of Examples 1 to 12, the HALT defect rate was less than 20%. This is because the sinterability of the reverse pattern layer 17 is increased because the respective concentrations of Mn, Si and B in the reverse pattern material are higher than the respective concentrations of Mn, Si and B in the dielectric material. This is presumably because the difference in sintering shrinkage behavior between the pattern layer 17 and the internal electrode layer 12 is reduced. On the other hand, in Comparative Examples 1 and 2, the HALT defect rate exceeded 20%. In Comparative Example 1, since the Si concentration in the reverse pattern material is lower than the Si concentration in the dielectric material, the sinterability of the reverse pattern layer 17 is lowered, and the reverse pattern layer 17 and the internal electrode layer 12 are sintered. This is probably because the difference in shrinkage behavior could not be made sufficiently small. In Comparative Example 2, since the B concentration in the reverse pattern material is lower than the B concentration in the dielectric material, the sinterability of the reverse pattern layer 17 is lowered, and the reverse pattern layer 17 and the internal electrode layer 12 are sintered. This is probably because the difference in shrinkage behavior could not be made sufficiently small.

  In addition, the capacity acquisition rate of Examples 1 to 3 was higher than that of Example 4. From this result, it is considered that Mn diffusion into the dielectric layer 11 could be suppressed by setting the Mn concentration in the reverse pattern material to 2.5 atm% or less.

  Moreover, the HALT defect rate of Examples 5-7 became low with respect to Example 8. From this result, it is considered that the grain growth of the reverse pattern layer 17 can be suppressed by setting the Si concentration in the reverse pattern material to 2.5 atm% or less. Moreover, from the result that the HALT defect rate of Examples 5-7 became low, it is considered that high sinterability is obtained in the reverse pattern layer 17 by setting the Si concentration in the reverse pattern material to 1.5 atm% or more. .

  Further, the HALT defect rate of Examples 9 to 11 was lower than that of Example 12. From this result, it is considered that the grain growth of the reverse pattern layer 17 can be suppressed by setting the B concentration in the reverse pattern material to 0.3 atm% or less. Further, from the result that the HALT defect rate of Examples 9 to 11 is low, it is considered that high sinterability was obtained in the reverse pattern layer 17 by setting the B concentration in the reverse pattern material to 0.2 atm% or more. It is done.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Multilayer chip 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 14 Capacitance area | region 15 End margin area | region 16 Side margin area | region 17 Reverse pattern layer 20a, 20b External electrode 100 Multilayer ceramic capacitor

Claims (9)

Dielectric layers mainly composed of ceramics and internal electrode layers are alternately stacked so as to have a substantially rectangular parallelepiped shape, and the plurality of stacked internal electrode layers are exposed on two opposing end surfaces. A formed laminated structure;
A plurality of internal electrode layers stacked in the stacked structure are provided so as to cover ends extending to two side surfaces other than the two end surfaces, and a side margin region mainly composed of ceramic,
Each concentration of Mn, Si, B with respect to the main component ceramic in the side margin region is higher than each concentration of Mn, Si, B with respect to the main component ceramic in the dielectric layer of the laminated structure. Multilayer ceramic capacitor.   The multilayer ceramic capacitor according to claim 1, wherein a main component ceramic of the side margin region and the dielectric layer is barium titanate.   The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layer has nickel as a main component. A first step of disposing a first pattern of a metal conductive paste on a green sheet containing main component ceramic particles;
A second step of disposing a second pattern containing main component ceramic particles in a peripheral region of the metal conductive paste on the green sheet;
A third step of firing a ceramic laminate obtained by laminating a plurality of lamination units obtained in the second step, and
A multilayer ceramic capacitor characterized in that each concentration of Mn, Si, B with respect to the main component ceramic in the second pattern is higher than each concentration of Mn, Si, B with respect to the main component ceramic in the green sheet. Production method.   5. The method for manufacturing a multilayer ceramic capacitor according to claim 4, wherein the Mn concentration in the second pattern with respect to the main component ceramic is 0.5 atm% or more and 2.5 atm% or less.   6. The method of manufacturing a multilayer ceramic capacitor according to claim 4, wherein the Si concentration in the second pattern with respect to the main component ceramic is 1.5 atm% or more and 2.5 atm% or less.   7. The method for manufacturing a multilayer ceramic capacitor according to claim 4, wherein a B concentration with respect to the main component ceramic in the second pattern is 0.2 atm% or more and 0.3 atm% or less. .   The method for manufacturing a multilayer ceramic capacitor according to any one of claims 4 to 7, wherein the main component ceramic of the green sheet and the second pattern is barium titanate.   The method for manufacturing a multilayer ceramic capacitor according to claim 4, wherein the main component metal of the first pattern is nickel.

Images