JP2020035878A - Laminated ceramic capacitor and manufacturing method therefor - Google Patents

Abstract

To provide a large-sized, large capability laminated ceramic capacitor with a large CR product, and a manufacturing method therefor.SOLUTION: A laminated ceramic capacitor includes: a laminated chip in which a dielectric layer and an inner electrode layer are alternately laminated, and the inner electrode layer is formed to be exposed on alternately facing two end faces; and a pair of outer electrodes formed on the two end faces. A total weight is 130 mg or more. When defining T1 as a height in the lamination direction in a cross section, perpendicular to a first direction at the center of the first direction facing the two end faces; T2 as a height which passes through an end point of the inner electrode layer in a second direction, that is, a width direction of the inner electrode layer; W1 as a width in the second direction passing through the inner electrode layer of either of outermost layers; and W2 as a width in the second direction passing through the center of a lamination direction, (T1-T2)/T1 is 0% or more and +4.5% or less, (W1-W2)/W1 is -1.0% or more and +3.0% or less, the number of laminations of the inner electrode layer to T1 is 250 layers/mm or more, and a continuation rate of the inner electrode layer is 85% or more.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

  In recent years, the maximum capacitance of a multilayer ceramic capacitor having a high multilayer density is approaching, for example, 1000 μF. Thus, the capacitance of the multilayer ceramic capacitor is close to the area of the electrolytic capacitor. However, it is difficult to realize the capacity unless the current capacity density is large. In order to configure this large-sized ceramic laminate as a sintered body, the sintering temperature gap between the internal electrode layer and the dielectric layer requires high continuity and low expansion without impairing the continuity of the internal electrode layer. It is important to obtain a structure of

  For example, by performing initial firing at a temperature rising rate of 30 ° C./60 s to 50 ° C./60 s at a temperature of 700 ° C. or less, rapid nickel sintering is induced, and the connectivity of the internal electrodes of the multilayer ceramic capacitor is improved. (For example, see Patent Document 1).

JP 2014-82435 A

  However, since a large-sized multilayer ceramic capacitor contains a large amount of a binder, there is a problem that high-speed sintering at a sintering temperature peak portion cannot be realized when giving priority to binder removal. Further, if high-speed firing is prioritized, residual stress accumulates in the chip due to degassing and the like, and there is a problem that structural defects are generated.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor having a large shape, a high capacitance, a high CR product, and a method of manufacturing the same.

  In the multilayer ceramic capacitor according to the present invention, a dielectric layer mainly composed of ceramics and internal electrode layers are alternately laminated, and a plurality of the laminated internal electrode layers are exposed on two end faces alternately facing each other. A stacked chip having a substantially rectangular parallelepiped shape, and a pair of external electrodes formed on the two end surfaces, wherein the total weight of the stacked chip and the pair of external electrodes is 130 mg or more, In the laminated chip, in a cross section perpendicular to the first direction at a center of the first direction in which the two end faces are opposed to each other, a height in the laminating direction of the laminated chip is T1, and a width direction of the internal electrode layer is a width direction. The height passing through the end point of the internal electrode layer in two directions is defined as T2, the width in the second direction is defined as passing through one of the outermost internal electrode layers, and the width in the second direction is defined as W1. (W1-W2) / W1 is -1.0% or more and + 3.0% or less when (T1-T2) / T1 is 0% or more and + 4.5% or less. The number of laminations of the internal electrode layers with respect to T1 is 250 layers / mm or more, and the continuity of the internal electrode layers is 85% or more.

  In the multilayer ceramic capacitor, a ratio of the area of the capacitance region in which the internal electrode layers exposed to different end faces face each other to the entire area in the cross section may be 80% or more.

  In the multilayer ceramic capacitor, the number of the internal electrode layers stacked on T1 may be 400 layers / mm or more.

  In the method for manufacturing a multilayer ceramic capacitor according to the present invention, a ceramic dielectric layer green sheet and a conductive paste for forming an internal electrode are alternately laminated, and a plurality of laminated conductive pastes for forming an internal electrode are alternately opposed to each other. A step of forming a substantially rectangular parallelepiped ceramic laminate by exposing to the two end faces, a step of obtaining a laminated chip by firing the ceramic laminate, and plating on a base layer of the two end faces of the laminated chip. Forming a pair of external electrodes by processing, wherein the total weight of the laminated chip and the pair of external electrodes is 130 mg or more, and in the laminated chip, the first end in the first direction in which the two end faces face each other. In a section perpendicular to the first direction at the center, when the height of the laminated chip is T1, the number of the internal electrode layers laminated with respect to T1 And 250 layers / mm or more, when firing the ceramic laminate, characterized in that a more than 60 (heating rate in the second half) / (heating rate in the first half).

  According to the present invention, it is possible to provide a multilayer ceramic capacitor having a large shape, a high capacitance, and a high CR product, and a method for manufacturing the same.

FIG. 3 is a partial cross-sectional perspective view of the multilayer ceramic capacitor. FIG. 2 is a sectional view taken along line AA of FIG. 1. FIG. 2 is a sectional view taken along line BB of FIG. 1. It is a figure showing a continuation rate. FIG. 2 is a sectional view corresponding to a section taken along line BB of FIG. 1. FIG. 3 is a diagram illustrating an example of Area1 and Area2. It is a figure which illustrates the flow of the manufacturing method of a multilayer ceramic capacitor. It is a figure which illustrates a baking process. It is a figure showing a measurement result. (A) And (b) is a figure which illustrates a crack and a crack.

  Hereinafter, embodiments will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the embodiment. FIG. 2 is a sectional view taken along line AA of FIG. FIG. 3 is a sectional view taken along line BB of FIG. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a rectangular parallelepiped shape, and external electrodes 20 a and 20 b provided on any two opposite end surfaces of the multilayer chip 10. Note that, of the four surfaces other than the two end surfaces of the laminated chip 10, two surfaces other than the upper surface and the lower surface in the laminating direction are referred to as side surfaces. The external electrodes 20a and 20b extend on the upper surface, the lower surface, and two side surfaces of the laminated chip 10 in the laminating direction. However, the external electrodes 20a and 20b are separated from each other. In FIG. 1, the X-axis direction (first direction) is the length direction of the laminated chip 10 and the direction in which the two end faces of the laminated chip 10 face each other, and the external electrodes 20a and 20b face each other. Direction. The Y-axis direction (second direction) is the width direction of the internal electrode layer 12. The Z-axis direction is the stacking direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

  The laminated chip 10 has a configuration in which a dielectric layer 11 containing a ceramic material functioning as a dielectric and an internal electrode layer 12 containing a base metal material are alternately laminated. The edge of each internal electrode layer 12 is exposed alternately on the end face of the laminated chip 10 where the external electrode 20a is provided and on the end face where the external electrode 20b is provided. Thereby, each internal electrode layer 12 is electrically connected to the external electrode 20a and the external electrode 20b alternately. As a result, the multilayer ceramic capacitor 100 has a configuration in which the plurality of dielectric layers 11 are stacked via the internal electrode layers 12. In the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is disposed on the outermost layer in the laminating direction, and the upper and lower surfaces of the laminate are covered by the cover layer 13. The cover layer 13 contains a ceramic material as a main component. For example, the material of the cover layer 13 is the same as the dielectric layer 11 and the main component of the ceramic material.

  The size of the multilayer ceramic capacitor 100 is, for example, 1.6 mm in length, 0.8 mm in width, 0.8 mm in height, or 2.0 mm in length, 1.25 mm in width, 1.25 mm in height, or 3.2 mm long, 1.6 mm wide, 1.6 mm high, or 3.2 mm long, 2.5 mm wide, 2.5 mm high, or 4.5 mm long, 3.2 mm wide , Height 2.5 mm, but is not limited to these sizes.

The internal electrode layer 12 contains a base metal such as Ni (nickel), Cu (copper), or Sn (tin) as a main component. As the internal electrode layer 12, a noble metal such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), or an alloy containing these may be used. The dielectric layer 11 contains, for example, a ceramic material having a perovskite structure represented by the general formula ABO ₃ as a main component. Note that the perovskite structure includes ABO _3-α deviating from the stoichiometric composition. For example, as the ceramic material, BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), Ba _1-xy forming a perovskite structure _{Ca x Sr y Ti 1-z} Zr z O 3 (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1) , or the like can be used.

  As illustrated in FIG. 2, a region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where the capacitance is generated in the multilayer ceramic capacitor 100. . Therefore, this region is referred to as a capacitance region 14. That is, the capacitance region 14 is a region where two adjacent internal electrode layers 12 connected to different external electrodes face each other.

  A region where the internal electrode layers 12 connected to the external electrode 20a face each other without interposing the internal electrode layer 12 connected to the external electrode 20b is referred to as an end margin region 15. A region where the internal electrode layers 12 connected to the external electrodes 20b face each other without interposing the internal electrode layers 12 connected to the external electrodes 20a is also an end margin region 15. That is, the end margin region 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without interposing the internal electrode layers 12 connected to different external electrodes. The end margin region 15 is a region where no capacitance is generated.

  As illustrated in FIG. 3, a region from the two side surfaces of the laminated chip 10 to the internal electrode layer 12 in the laminated chip 10 is referred to as a side margin region 16. That is, the side margin region 16 is a region in which the plurality of internal electrode layers 12 stacked in the above-described stacked structure are provided so as to cover the ends extending to the two side surfaces.

  In recent years, the maximum capacitance of a multilayer ceramic capacitor having a high multilayer density is approaching, for example, 1000 μF. Thus, the capacitance of the multilayer ceramic capacitor is close to the area of the electrolytic capacitor. However, it is difficult to realize the capacity unless the current capacity density is large.

  On the other hand, the dielectric layer 11 is obtained, for example, by firing raw material powder of a main component ceramic having a perovskite structure. The internal electrode layer 12 is obtained by firing a raw material powder of a main component metal. There is a difference between the sintering start temperature of the raw material powder of the main component ceramic and the sintering start temperature of the raw material powder of the main component metal. In order to form a large-sized ceramic laminate as a sintered body, the continuity of the internal electrode layer 12 should be maintained at a high level with respect to the sintering start temperature gap between the dielectric layer 11 and the internal electrode layer 12 without impairing the continuity. It is important to obtain a low expansion structure.

  FIG. 4 is a diagram illustrating the continuation rate. As illustrated in FIG. 4, in an observation region having a length L0 in a certain internal electrode layer 12, the lengths L1, L2,... ΣLn / L0 can be defined as the continuity of the layer.

  For example, it is conceivable that by rapidly increasing the temperature in the heating process of the firing step, sintering of the metal component of the internal electrode layer is induced and the connectivity of the internal electrode layer is improved. However, since a large-sized multilayer ceramic capacitor contains a large amount of binder, there is a problem that high-speed sintering at a sintering temperature peak portion cannot be realized when the rate of temperature rise is suppressed to give priority to binder removal. Further, if high-speed firing is prioritized, residual stress accumulates in the chip due to degassing and the like, and there is a problem that structural defects are generated. Thus, the multilayer ceramic capacitor 100 according to the present embodiment has a configuration that realizes a large CR, a large capacity, and a high CR product, for example, by adjusting a temperature rising rate in a firing step. Here, the CR product represents the product of the capacitance value of the multilayer ceramic capacitor 100 and the insulation resistance.

  First, each dimension of the multilayer ceramic capacitor 100 is defined. FIG. 5 is a cross-sectional view corresponding to a cross section taken along line BB of FIG. The cross section in FIG. 5 is a cross section passing through the center in the length direction (X-axis direction) of the laminated chip 10. In the multilayer chip 10, the height in the stacking direction (Z-axis direction) passing through the center of the internal electrode layer 12 in the width direction (Y-axis direction) is defined as height T1. In the multilayer chip 10, the height in the Z-axis direction passing through the end point of the internal electrode layer 12 in the Y-axis direction is defined as height T2. When the end points of the internal electrode layers 12 vary in the Y-axis direction, the height T2 is the height in the Z-axis direction at the average position of the end points of the internal electrode layers 12. In the multilayer chip 10, the width in the Y-axis direction passing through the outermost internal electrode layer 12 is defined as a width W1. In the multilayer chip 10, the width in the Y-axis direction passing through the center in the Z-axis direction is defined as a width W2.

  First, the present embodiment is directed to a large-sized multilayer ceramic capacitor 100 having a large weight. Specifically, the weight of the multilayer ceramic capacitor 100 (the total weight of the multilayer chip 10 and the external electrodes 20a and 20b) is 130 mg or more. Alternatively, the weight of the multilayer ceramic capacitor 100 is 150 mg or more. Alternatively, the weight of the multilayer ceramic capacitor 100 is 330 mg or more.

  Further, the present embodiment is directed to a high-capacity multilayer ceramic capacitor 100 having a large number of laminated internal electrode layers 12. Specifically, the number of stacked internal electrode layers 12 with respect to the height T1 is 250 layers / mm or more. Alternatively, the number of stacked internal electrode layers 12 with respect to the height T1 is 350 layers / mm or more. Alternatively, the number of stacked internal electrode layers 12 with respect to the height T1 is 400 layers / mm or more. Alternatively, the number of stacked internal electrode layers 12 with respect to the height T1 is 450 layers / mm or more.

  In addition, the multilayer ceramic capacitor 100 according to the present embodiment has a high continuity ratio in order to realize a high capacitance. Specifically, the continuity of the internal electrode layers 12 is 85% or more. From the viewpoint of high capacity, the continuity of the internal electrode layer 12 is preferably 90% or more, and more preferably 95% or more.

  In such a large-sized and high-capacity multilayer ceramic capacitor 100, the smaller the difference between the height T1 and the height T2 and the smaller the difference between the width W1 and the width W2, the more the residual stress of the multilayer ceramic capacitor 100 is suppressed. As a result, the occurrence of structural defects is suppressed, and the insulation resistance is increased. Therefore, in the present embodiment, the range of (T1−T2) / T1 is defined, and the range of (W1−W2) / W1 is defined. Specifically, (T1−T2) / T1 is set to 0% or more and + 4.5% or less. Further, (W1−W2) / W1 is set to −1.0% or more and + 3.0% or less. According to this configuration, in the large-sized and high-capacity multilayer ceramic capacitor 100, the CR product can be sufficiently increased.

  From the viewpoint of suppressing the residual stress of the multilayer ceramic capacitor 100, the difference between the height T1 and the height T2 is preferably smaller. Therefore, (T1−T2) / T1 is preferably 0% or more and + 3.0% or less, and more preferably 0% or more and + 1.5% or less. Further, it is preferable that the difference between the width W1 and the width W2 is further smaller. Therefore, (W1−W2) / W1 is preferably −1.0% or more and + 1.0% or less, and more preferably 0% or more and + 1.0% or less.

  In the cross section of FIG. 5, the higher the ratio of the area of the capacitance region 14, the higher the capacitance. Therefore, as exemplified in FIG. 6, the cross-sectional area of the capacitance region 14 in the cross section of FIG. The sectional area of the entire laminated chip 10 is Area2. In this case, Area1 / Area2 is preferably 80% or more, and more preferably 85% or more.

  Next, a method for manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 7 is a diagram illustrating a flow of a method of manufacturing the multilayer ceramic capacitor 100.

(Raw material powder production process)
First, as illustrated in FIG. 7, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO ₃ particles. For example, BaTiO ₃ is a tetragonal compound having a perovskite structure and has a high dielectric constant. This BaTiO ₃ can be generally obtained by reacting a titanium material such as titanium dioxide and a barium material such as barium carbonate to synthesize barium titanate. As a method for synthesizing the ceramic constituting the dielectric layer 11, various methods are conventionally known, such as a solid phase method, a sol-gel method, and a hydrothermal method. In the present embodiment, any of these can be adopted.

  A predetermined additive compound is added to the obtained ceramic powder according to the purpose. The additive compounds include Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), and Tb ( Oxides of terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium), and Co (cobalt), Ni, Li (lithium), B (boron) , Na (sodium), K (potassium) and Si (silicon) oxides or glasses.

  In the present embodiment, preferably, first, a compound containing an additive compound is mixed with the ceramic particles constituting the dielectric layer 11 and calcined at 820 to 1150 ° C. Subsequently, the obtained ceramic particles are wet-mixed with an additive compound, dried and pulverized to prepare a ceramic powder. For example, the ceramic powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size.

  Next, a reverse pattern material for forming the end margin region 15 and the side margin region 16 is prepared. A predetermined additive compound is added to the barium titanate ceramic powder obtained by a process similar to the above-described process for producing the dielectric material, depending on the purpose. Examples of the additional compounds include Mg, Mn, V, Cr, oxides of rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), and Co, Ni, Li, B, Oxides or glasses of Na, K and Si.

  In the present embodiment, preferably, first, a compound containing an additive compound is mixed with ceramic particles constituting the end margin region 15 and the side margin region 16 and calcined at 820 to 1150 ° C. Subsequently, the obtained ceramic particles are wet-mixed with an additive compound, dried and pulverized to prepare a ceramic powder. For example, the ceramic powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer are added to the obtained dielectric material and wet-mixed. Using the obtained slurry, for example, a strip-shaped dielectric green sheet having a thickness of 0.8 μm or less is coated on the substrate by a die coater method or a doctor blade method, and dried.

Next, a metal conductive paste for forming an internal electrode including an organic binder is printed on the surface of the dielectric green sheet by screen printing, gravure printing, or the like, so that the internal electrodes are alternately drawn to a pair of external electrodes having different polarities. A layer pattern (first pattern) is arranged. Ceramic particles are added to the metal conductive paste as a common material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. For example, BaTiO ₃ having an average particle diameter of 50 nm or less may be uniformly dispersed.

  Next, a binder such as ethyl cellulose and an organic solvent such as terpineol are added to the reverse pattern material and kneaded by a roll mill to obtain a reverse pattern paste. On the dielectric green sheet, a reverse pattern (second pattern) is arranged by printing a reverse pattern paste in a peripheral area where the internal electrode layer pattern is not printed, thereby filling a step with the internal electrode layer pattern.

Thereafter, the dielectric green sheet on which the internal electrode layer pattern and the reverse pattern are printed is punched into a predetermined size, and the punched dielectric green sheet is peeled off from the internal electrode layer 12 and the dielectric material with the base material peeled off. The internal electrode layer 12 is alternately drawn out to a pair of external electrodes 20a and 20b having different polarities so that the inner electrode layer 12 is alternately arranged with the layer 11 and the edges are alternately exposed at both longitudinal end surfaces of the dielectric layer 11. Thus, a predetermined number of layers are stacked. A cover sheet to be the cover layer 13 is pressure-bonded to the upper and lower sides of the laminated dielectric green sheet, cut into a predetermined chip size, and subjected to a binder removal treatment in an N ₂ atmosphere at 250 to 500 ° C. Thereafter, a metal conductive paste to be the external electrodes 20a and 20b is applied to both side surfaces of the cut laminate by a dipping method or the like and dried. Thereby, a molded body of the multilayer ceramic capacitor 100 is obtained.

(Firing process)
The thus obtained molded body is fired at a high temperature in a reducing atmosphere having an oxygen partial pressure of 10 ⁻⁵ to 10 ⁻⁸ atm, whereby each compound is sintered and grown. Thus, the multilayer ceramic capacitor 100 is obtained. In the present embodiment, as illustrated in FIG. 8, in the first half of the heating step, the heating rate B is slowed to sufficiently remove carbon, and in the second half of the heating step, the heating rate A is increased. Sintering.

  For example, in the first half of the temperature raising step, the heat treatment is sufficiently performed at a low temperature of 200 ° C. to 1000 ° C. in the reducing atmosphere. In order to suppress the influence of carbon at the time of firing, the heating rate B is sufficiently reduced. For example, the heating rate B is preferably set to 800 ° C./hr or less, and more preferably the heating rate B is set to 500 ° C./hr or less. Further, the temperature raising time in the first temperature raising step is preferably from 1 hour to 16 hours, more preferably from 2 hours to 8 hours. In addition, from the viewpoint of productivity, it is preferable to set a lower limit for the temperature raising rate B. For example, the heating rate B is preferably 200 ° C./hr or more.

  Subsequently, in the latter half of the temperature raising step, sintering is carried out at a high temperature of 1000 ° C. or higher in the above reducing atmosphere. In order to suppress the spheroidization of the metal component in the internal electrode layer 12, the heating rate A is made sufficiently fast. For example, the heating rate A is preferably set to 10,000 ° C./hr or more, and more preferably, the heating rate A is set to 50,000 ° C./hr or more. Further, the temperature raising time in the latter half of the temperature raising step is preferably 0.01 minutes or more and 10 minutes or less, more preferably 0.1 minutes or more and 1 minute or less. Note that it is preferable to set an upper limit for the temperature raising rate A so that insufficient heat transfer to the firing jig does not occur. For example, the heating rate A is preferably 100,000 ° C./hr or less.

  In the present embodiment, the heating rate A / heating rate B is set to 60 or more in order to sufficiently lower the heating rate in the first heating step and sufficiently increase the heating rate in the second heating step. And In order to sufficiently delay the first half of the temperature raising step and sufficiently early the second half of the temperature raising step, the heating rate A / heating rate B is preferably 200 or more, more preferably 400 or more. preferable.

  When the heating rate A / heating rate B is equal to or greater than 60, the temperature rising from the start of heating to the maximum temperature is considered as (the temperature rising from the intermediate temperature to the maximum temperature). (Speed) / (rate of temperature rise from room temperature to the intermediate temperature) is 60 or more. For example, when Ni is used for the internal electrode layer 12, the intermediate temperature can be 1000 ± 200 ° C., or may be 1000 ° C.

  The heating rate can be changed, for example, by changing the transfer speed of the roller hearth type baking furnace halfway. Alternatively, the rate of temperature rise can be changed by sequentially introducing the materials into firing furnaces having different temperatures by a belt conveyor or the like.

  Thereafter, the temperature range of 1100 ° C. to 1300 ° C. is maintained and sintering is sufficiently advanced. Thereafter, by lowering the temperature, the firing step is completed.

(Reoxidation process)
Thereafter, a reoxidation treatment may be performed at 600 ° C. to 1000 ° C. in an N ₂ gas atmosphere.

(Plating process)
Thereafter, the external electrodes 20a and 20b may be coated with metal such as Cu, Ni, and Sn by plating.

  According to the manufacturing method according to the present embodiment, in the firing step, the ratio (A / B) of the temperature increase rate A in the second half temperature increase step to the temperature increase rate B in the first half temperature increase step is 60 or more. Thus, the heating rate in the first half is sufficiently slow, and the heating rate in the second half is sufficiently fast. Thereby, carbon can be sufficiently removed in the first half of the temperature raising step, so that the influence of carbon during firing can be suppressed. As a result, residual stress can be suppressed, and structural defects can be suppressed. In the latter half of the temperature raising step, the spheroidization of the metal component of the internal electrode layer 12 can be sufficiently suppressed. Thereby, a high continuity rate can be obtained. From the above, in the large-sized and high-capacity multilayer ceramic capacitor 100, the CR product can be sufficiently increased.

  Hereinafter, the multilayer ceramic capacitor according to the embodiment was manufactured and its characteristics were examined.

(Examples 1 to 10, Comparative Examples 1 to 3)
The necessary additives were added to the barium titanate powder, and the mixture was sufficiently wet-mixed and pulverized with a ball mill to obtain a dielectric material. An organic binder and a solvent were added to the dielectric material, and a dielectric green sheet was produced by a doctor blade method. The coating thickness of the dielectric green sheet was set to 0.8 μm, polyvinyl butyral (PVB) or the like was used as an organic binder, and ethanol, toluene acid, or the like was added as a solvent. In addition, a plasticizer and the like were added. Next, a conductive paste for forming an internal electrode containing a powder of a main component metal of the internal electrode layer 12, a binder, a solvent, and, if necessary, other auxiliaries was prepared. The organic binder and the solvent of the conductive paste for forming the internal electrode were different from those of the dielectric green sheet. A conductive paste for forming an internal electrode was screen-printed on the dielectric sheet. A reverse pattern paste was printed on a portion where the conductive paste for forming an internal electrode was not printed to fill in a step of the conductive paste for forming an internal electrode. As the reverse pattern paste, for example, the same material as the dielectric layer green sheet can be used. Sheets on which the conductive paste for forming an internal electrode and the reverse pattern paste were printed were overlapped, and cover sheets were respectively stacked above and below the sheets. Thereafter, a ceramic laminate was obtained by thermocompression bonding and cut into a predetermined shape.

  In Example 1, the number of layers was set to 1700. In Example 2, the number of laminations was 1200. In Example 3, the number of layers was set to 1100. In Example 4, the number of layers was set to 700. In Comparative Examples 1 and 2, the number of layers was 1700. In Comparative Example 3, the number of laminations was 1200. In Comparative Examples 4 and 5, the number of layers was 1100. In Comparative Examples 6 and 9, the number of layers was 900. In Comparative Example 7, the number of layers was 700. In Comparative Example 8, the number of layers was set to 600.

After debinding the obtained ceramic laminate in an N ₂ atmosphere, a metal paste containing a metal filler containing Ni as a main component, a common material, a binder and a solvent is applied from both end faces to each side face of the ceramic laminate. And dried.

  Thereafter, in the reducing atmosphere having a hydrogen concentration of 0.08%, the first half of the temperature raising step (temperature rising rate B) from room temperature to 1000 ° C. is performed, and the second half temperature raising step from 1000 ° C. to about 1300 ° C. (temperature rising rate) A) was performed. In Examples 1 to 4 and Comparative Examples 1 to 5 to 8, the heating rate B was 400 ° C./hr. In Comparative Examples 2 to 4 and 9, the heating rate B was set to 2000 ° C./hr. In Examples 1 to 4, the heating rate A was 25000 ° C./hr. In Comparative Example 1, the heating rate A was 15000 ° C. In Comparative Examples 2 to 4, 9, the heating rate A was 10,000 ° C./hr. In Comparative Examples 5 to 8, the heating rate A was set to 1000 ° C./hr. Therefore, in Examples 1 to 4, A / B was set to 62.5. In Comparative Example 1, A / B was set to 37.5. In Comparative Examples 2 to 4, 9, A / B was set to 5. In Comparative Examples 5 to 8, A / B was set to 2.5. Thereafter, the temperature was maintained at 1300 ° C. for 5 minutes to obtain a sintered body.

After re-oxidizing the sintered body under the condition of 800 ° C. in an N ₂ atmosphere, plating is performed to form a Cu plating layer 22, a Ni plating layer 23, and a Sn plating layer 24 on the surface of the underlayer 21, and the laminate is laminated. A ceramic capacitor 100 was obtained. Each of the samples according to Examples 1 to 4 and Comparative Examples 1 to 9 was prepared. The shape and dimensions of the obtained multilayer ceramic capacitor 100 are 4532 shapes (4.5 mm in length, 3.2 mm in width, and 2.5 mm in height) in Example 1 and Comparative Examples 1, 2, and 4. 4 and Comparative Examples 3 to 5 have a 3225 shape (3.2 mm in length, 2.5 mm in width, and 2.5 mm in height), and Comparative Example 9 has a 3216 shape (3.2 mm in length and 1 in width). 0.6 mm, height 1.6 mm).

(analysis)
FIG. 9 is a diagram showing the measurement results of Examples 1 to 4 and Comparative Examples 1 to 9. First, in Examples 1 to 4 and Comparative Examples 1 to 9, the height T1, the height T2, the width W1, and the width W2 were measured. For these measurements, VHX-1000 manufactured by KEYENCE CORPORATION was used. In Example 1 and Comparative Examples 1 and 2, the height T1 was 3.5 mm. In Examples 2 to 4 and Comparative Examples 3 to 8, the height T1 was 2.8 mm. In Comparative Example 9, the height T1 was 1.9 mm.

  In Example 1 and Comparative Examples 1 and 2, the number of layers / T1 was 486 layers / mm. In Example 2 and Comparative Example 3, the number of layers / T1 was 429 layers / mm. In Example 3 and Comparative Examples 4 and 5, the number of layers / T1 was 393 layers / mm. In Example 4 and Comparative Example 7, the number of layers / T1 was 250 layers / mm. In Comparative Example 6, the number of layers / T1 was 321 layers / mm. In Comparative Example 8, the number of layers / T1 was 214 layers / mm. In Comparative Example 9, the number of layers / T1 was 474 layers / mm.

  In Example 1 and Comparative Examples 1 and 2, the average of the weight was 347 mmg. In Example 2 and Comparative Example 3, the average of the weight was 155 mg. In Example 3 and Comparative Example 5, the average of the weight was 153 mg. In Example 4 and Comparative Example 7, the average of the weight was 131 mg. In Comparative Example 4, the average of the weight was 320 mg. In Comparative Example 6, the average of the weight was 147 mg. In Comparative Example 8, the average of the weight was 128 mg. In Comparative Example 9, the average of the weight was 73 mg.

  In Example 1, (W1−W2) / W1 was 2.8%. In Example 2, (W1−W2) / W1 was 0.9%. In Example 3, (W1−W2) / W1 was −0.8%. In Example 4, (W1−W2) / W1 was 0.6%. In Comparative Example 1, (W1-W2) / W1 was 3.2%. In Comparative Example 2, (W1-W2) / W1 was 4.3%. In Comparative Example 3, (W1−W2) / W1 was 3.2%. In Comparative Example 4, (W1-W2) / W1 was 3.6%. In Comparative Example 5, (W1-W2) / W1 was 3.2%. In Comparative Example 6, (W1-W2) / W1 was 2.8%. In Comparative Example 7, (W1-W2) / W1 was 2.1%. In Comparative Example 8, (W1−W2) / W1 was 2.3%. In Comparative Example 9, (W1-W2) / W1 was 1.5%.

  In Example 1, (T1-T2) / T1 was 4.4%. In Example 2, (T1-T2) / T1 was 2.8%. In Example 3, (T1-T2) / T1 was 1.2%. In Example 4, (T1-T2) / T1 was 0.9%. In Comparative Example 1, (T1-T2) / T1 was 4.8%. In Comparative Example 2, (T1-T2) / T1 was 10.8%. In Comparative Example 3, (T1-T2) / T1 was 5.3%. In Comparative Example 4, (T1-T2) / T1 was 7.1%. In Comparative Example 5, (T1-T2) / T1 was 4.7%. In Comparative Example 6, (T1-T2) / T1 was 4.6%. In Comparative Example 7, (T1-T2) / T1 was 4.8%. In Comparative Example 8, (T1-T2) / T1 was 4.0%. In Comparative Example 9, (T1-T2) / T1 was 3.7%.

  Thus, in Examples 1 to 4, 0% ≦ (T1−T2) /T1≦+4.5%, and −1.0% ≦ (W1−W2) /W1≦+3.0%. This is considered to be because the A / B ratio was set to 60 or more, so that the rate of temperature rise in the first half was sufficiently slow and the rate of temperature rise in the second half was sufficiently fast. On the other hand, in Comparative Examples 1 to 7, at least one of 0% ≦ (T1−T2) /T1≦+4.5% and −1.0% ≦ (W1−W2) /W1≦+3.0%. Did not meet the conditions. This is considered to be because the A / B ratio was less than 60, so that the temperature rising rate in the first half was not sufficiently low or the heating rate in the second half was not sufficiently fast. In Comparative Examples 8 and 9, the conditions of 0% ≦ (T1−T2) /T1≦+4.5% and −1.0% ≦ (W1−W2) /W1≦+3.0% were satisfied. This is considered to be because the influence of the sintering temperature gap between the dielectric layer 11 and the internal electrode layer 12 was suppressed because the weight was less than 130 mg. In Comparative Example 8, it is considered that the influence of Area1 / Area2 being less than 80% was also affected, and the influence of the sintering temperature gap between the dielectric layer 11 and the internal electrode layer 12 was suppressed.

  Next, structural defects of Examples 1 to 4 and Comparative Examples 1 to 9 were examined. Structural defects were examined for cracks in the firing illustrated in FIG. 10A and cracks in the binder removal illustrated in FIG. 10B. Cracks in firing are structural defects in which the cover layer 13 or a part of the side margin has a crack 50. The crack in the binder removal is a structural defect in which a crack 60 has occurred from the side margin region 16 to the capacitance region. In Comparative Examples 2 to 4, structural defects occurred. This is considered to be because the residual stress was increased by at least one of the difference between the height T1 and the height T2 and the difference between the width W1 and the width W2. Further, it is considered that the carbon was not sufficiently removed because the heating rate B was increased to 2000 ° C./hr.

  Next, the continuity of Examples 1 to 4 and Comparative Examples 1 to 9 was examined. In all of Examples 1 to 4, the continuity ratio was a high value of 85% or more. This is considered to be because the A / B ratio was set to 60 or more, whereby the rate of temperature rise in the latter half became sufficiently fast. On the other hand, in Comparative Examples 1 to 7, the continuity ratio was a low value of less than 85%. This is presumably because the A / B ratio was less than 60, so that the heating rate in the latter half did not become sufficiently fast. In Comparative Examples 8 and 9, the continuity ratio was a high value of 85% or more. This is considered to be because the influence of the sintering temperature gap between the dielectric layer 11 and the internal electrode layer 12 was suppressed because the weight was less than 130 mg. In Comparative Example 8, it is considered that the influence of Area1 / Area2 being less than 80% was also affected, and the influence of the sintering temperature gap between the dielectric layer 11 and the internal electrode layer 12 was suppressed.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to the specific embodiments, and various modifications and changes may be made within the scope of the present invention described in the appended claims. Changes are possible.

DESCRIPTION OF SYMBOLS 10 Laminated chip 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 14 Capacitance area 15 End margin area 16 Side margin area 20a, 20b External electrode 100 Multilayer ceramic capacitor

Claims (4)

A dielectric layer containing ceramic as a main component and an internal electrode layer are alternately stacked, and the stacked plurality of internal electrode layers are formed so as to be exposed at two alternately opposite end faces, and have a substantially rectangular parallelepiped shape. A laminated chip having
A pair of external electrodes formed on the two end faces,
The total weight of the laminated chip and the pair of external electrodes is 130 mg or more;
In the laminated chip, in a cross section perpendicular to the first direction at a center of the first direction in which the two end faces are opposed to each other, a height in the laminating direction of the laminated chip is T1, and a width direction of the internal electrode layer is a width direction. The height passing through the end point of the internal electrode layer in two directions is defined as T2, the width in the second direction is defined as passing through the outermost one of the internal electrode layers, and the width in the second direction is defined as W1. When the width is W2, (T1-T2) / T1 is 0% or more and + 4.5% or less, and (W1-W2) / W1 is -1.0% or more and + 3.0% or less. ,
The number of stacked internal electrode layers relative to T1 is 250 layers / mm or more;
A multilayer ceramic capacitor, wherein the continuity of the internal electrode layers is 85% or more.   2. The multilayer ceramic capacitor according to claim 1, wherein, in the cross section, a ratio of an area of the capacitance region in which the internal electrode layers exposed to different end surfaces face each other to the entire area is 80% or more. 3.   3. The multilayer ceramic capacitor according to claim 1, wherein the number of the internal electrode layers laminated on T1 is 400 layers / mm or more. 4. By alternately laminating the ceramic dielectric layer green sheets and the conductive paste for forming the internal electrodes, and exposing the plurality of conductive pastes for forming the internal electrodes alternately to two opposite end surfaces, a substantially rectangular parallelepiped shape is obtained. Forming a ceramic laminate,
A step of obtaining a laminated chip by firing the ceramic laminate,
Forming a pair of external electrodes by plating on the underlying layer on the two end faces of the laminated chip,
The total weight of the laminated chip and the pair of external electrodes is 130 mg or more;
In the laminated chip, when the height of the laminated chip is T1 in a cross section perpendicular to the first direction at the center of the first direction in which the two end surfaces face each other, the number of laminated internal electrode layers with respect to T1 is 250 layers / mm or more,
A method of manufacturing a multilayer ceramic capacitor, wherein when firing the ceramic laminated body, (the temperature rising rate in the latter half) / (the temperature rising rate in the first half) is 60 or more.

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