JP7138190B2 - ネットワークスイッチのキュー - Google Patents

ネットワークスイッチのキュー Download PDF

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Publication number
JP7138190B2
JP7138190B2 JP2020555898A JP2020555898A JP7138190B2 JP 7138190 B2 JP7138190 B2 JP 7138190B2 JP 2020555898 A JP2020555898 A JP 2020555898A JP 2020555898 A JP2020555898 A JP 2020555898A JP 7138190 B2 JP7138190 B2 JP 7138190B2
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Japan
Prior art keywords
queue
entries
bit
entry
memory
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Application number
JP2020555898A
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English (en)
Japanese (ja)
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JPWO2019199817A5 (https=
JP2021521529A (ja
JP2021521529A5 (https=
Inventor
ドッドソン スミス アラン
カリヤナスンダラム ヴィドヒャナサン
ピー． ブルッサール ブライアン
ディー． ダンリー グレゴリー
エス． パテル チンタン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2021521529A publication Critical patent/JP2021521529A/ja
Publication of JPWO2019199817A5 publication Critical patent/JPWO2019199817A5/ja
Publication of JP2021521529A5 publication Critical patent/JP2021521529A5/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/28—Flow control; Congestion control in relation to timing considerations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/52—Queue scheduling by attributing bandwidth to queues
    • H04L47/522—Dynamic queue service slot or variable bandwidth allocation
    • H04L47/524—Queue skipping
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/52—Queue scheduling by attributing bandwidth to queues
    • H04L47/525—Queue scheduling by attributing bandwidth to queues by redistribution of residual bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/56—Queue scheduling implementing delay-aware scheduling
    • H04L47/564—Attaching a deadline to packets, e.g. earliest due date first
    • H04L47/566—Deadline varies as a function of time spent in the queue
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6235—Variable service order
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/624—Altering the ordering of packets in an individual queue
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9031—Wraparound memory, e.g. overrun or underrun detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System (AREA)
JP2020555898A 2018-04-12 2019-04-09 ネットワークスイッチのキュー Active JP7138190B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/951,844 2018-04-12
US15/951,844 US10601723B2 (en) 2018-04-12 2018-04-12 Bandwidth matched scheduler
PCT/US2019/026571 WO2019199817A1 (en) 2018-04-12 2019-04-09 Queue in a network switch

Publications (4)

Publication Number Publication Date
JP2021521529A JP2021521529A (ja) 2021-08-26
JPWO2019199817A5 JPWO2019199817A5 (https=) 2022-07-28
JP2021521529A5 JP2021521529A5 (https=) 2022-07-28
JP7138190B2 true JP7138190B2 (ja) 2022-09-15

Family

ID=66248826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020555898A Active JP7138190B2 (ja) 2018-04-12 2019-04-09 ネットワークスイッチのキュー

Country Status (6)

Country Link
US (1) US10601723B2 (https=)
EP (1) EP3777059B1 (https=)
JP (1) JP7138190B2 (https=)
KR (1) KR102456086B1 (https=)
CN (1) CN112189324B (https=)
WO (1) WO2019199817A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11294678B2 (en) 2018-05-29 2022-04-05 Advanced Micro Devices, Inc. Scheduler queue assignment
KR102728641B1 (ko) * 2019-04-01 2024-11-12 주식회사 사피온코리아 버퍼 메모리, 이를 이용하는 연산 장치 및 시스템
US11334384B2 (en) * 2019-12-10 2022-05-17 Advanced Micro Devices, Inc. Scheduler queue assignment burst mode
US11948000B2 (en) 2020-10-27 2024-04-02 Advanced Micro Devices, Inc. Gang scheduling for low-latency task synchronization
US12436696B2 (en) 2022-09-29 2025-10-07 Advanced Micro Devices, Inc. On-demand regulation of memory bandwidth utilization to service requirements of display

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017173884A (ja) 2016-03-18 2017-09-28 日本電気株式会社 メモリアクセス制御装置、情報処理システム、メモリアクセス制御方法、及び、プログラム

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JPH05108476A (ja) * 1991-10-18 1993-04-30 Fujitsu Ltd 主記憶制御装置
US6246680B1 (en) 1997-06-30 2001-06-12 Sun Microsystems, Inc. Highly integrated multi-layer switch element architecture
US7406554B1 (en) 2000-07-20 2008-07-29 Silicon Graphics, Inc. Queue circuit and method for memory arbitration employing same
US6782461B2 (en) 2002-02-25 2004-08-24 Intel Corporation Dynamically adjustable load-sharing circular queues
US20040151197A1 (en) * 2002-10-21 2004-08-05 Hui Ronald Chi-Chun Priority queue architecture for supporting per flow queuing and multiple ports
US7689793B1 (en) 2003-05-05 2010-03-30 Marvell Israel (M.I.S.L.) Ltd. Buffer management architecture
US20080320274A1 (en) * 2007-06-19 2008-12-25 Raza Microelectronics, Inc. Age matrix for queue dispatch order
US8090892B2 (en) * 2009-06-12 2012-01-03 Freescale Semiconductor, Inc. Ordered queue and methods therefor
US9286075B2 (en) * 2009-09-30 2016-03-15 Oracle America, Inc. Optimal deallocation of instructions from a unified pick queue
US9008113B2 (en) 2010-12-20 2015-04-14 Solarflare Communications, Inc. Mapped FIFO buffering
US9397961B1 (en) 2012-09-21 2016-07-19 Microsemi Storage Solutions (U.S.), Inc. Method for remapping of allocated memory in queue based switching elements
US9378168B2 (en) 2013-09-18 2016-06-28 International Business Machines Corporation Shared receive queue allocation for network on a chip communication
US9979668B2 (en) * 2014-12-22 2018-05-22 Intel Corporation Combined guaranteed throughput and best effort network-on-chip
EP3238395A4 (en) * 2014-12-24 2018-07-25 Intel Corporation Apparatus and method for buffering data in a switch
US10178011B2 (en) 2016-02-10 2019-01-08 Hewlett Packard Enterprise Development Lp Network traffic management via network switch QoS parameters analysis
US10250530B2 (en) * 2016-03-08 2019-04-02 Mellanox Technologies Tlv Ltd. Flexible buffer allocation in a network switch
US10607623B2 (en) * 2018-01-12 2020-03-31 Ribbon Communications Operating Company, Inc. Methods and apparatus for supporting communication of content streams using efficient memory organization

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2017173884A (ja) 2016-03-18 2017-09-28 日本電気株式会社 メモリアクセス制御装置、情報処理システム、メモリアクセス制御方法、及び、プログラム

Also Published As

Publication number Publication date
US10601723B2 (en) 2020-03-24
EP3777059B1 (en) 2022-08-17
WO2019199817A1 (en) 2019-10-17
JP2021521529A (ja) 2021-08-26
US20190319891A1 (en) 2019-10-17
KR102456086B1 (ko) 2022-10-18
CN112189324B (zh) 2023-09-26
EP3777059A1 (en) 2021-02-17
KR20200139812A (ko) 2020-12-14
CN112189324A (zh) 2021-01-05

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