EP3777059B1 - Queue in a network switch - Google Patents

Queue in a network switch Download PDF

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Publication number
EP3777059B1
EP3777059B1 EP19719094.5A EP19719094A EP3777059B1 EP 3777059 B1 EP3777059 B1 EP 3777059B1 EP 19719094 A EP19719094 A EP 19719094A EP 3777059 B1 EP3777059 B1 EP 3777059B1
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EP
European Patent Office
Prior art keywords
queue
entries
bit vector
memory
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP19719094.5A
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German (de)
English (en)
French (fr)
Other versions
EP3777059A1 (en
Inventor
Alan Dodson Smith
Vydhyanathan Kalyanasundharam
Bryan P. Broussard
Greggory D. Donley
Chintan S. PATEL
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/28—Flow control; Congestion control in relation to timing considerations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/52—Queue scheduling by attributing bandwidth to queues
    • H04L47/522—Dynamic queue service slot or variable bandwidth allocation
    • H04L47/524—Queue skipping
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/52—Queue scheduling by attributing bandwidth to queues
    • H04L47/525—Queue scheduling by attributing bandwidth to queues by redistribution of residual bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/56—Queue scheduling implementing delay-aware scheduling
    • H04L47/564—Attaching a deadline to packets, e.g. earliest due date first
    • H04L47/566—Deadline varies as a function of time spent in the queue
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6235—Variable service order
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/624—Altering the ordering of packets in an individual queue
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9031—Wraparound memory, e.g. overrun or underrun detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling

Definitions

  • processor architectures include more than one processing unit (e.g., CPU, GPU, etc.) or processing core
  • one or two additional processing units or cores coupled to a memory may not necessarily provide a sufficient level of parallelism to provide a desired level of performance.
  • traditional bus-based and crossbar interconnect architectures generally do not scale well as the number of processing units increases. Consequently, as the number of processing units increase, the delay in supplying instructions and data to the processing units also increases.
  • a computing system includes one or more clients.
  • clients include a generalpurpose central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a multimedia engine, and so on.
  • CPU generalpurpose central processing unit
  • GPU graphics processing unit
  • APU accelerated processing unit
  • multimedia engine a multimedia engine
  • these one or more clients generate access requests for the data stored in a memory while processing program instructions.
  • the multiple clients are combined in a single die, such as a system-on-a-chip (SOC).
  • SOC system-on-a-chip
  • communication fabric 110 transfers traffic between CPU 160, GPU 162, and Multimedia Engine 166.
  • Fabric 110 also transfers traffic between memories 150 and 152 and clients such as CPU 160, GPU 162 and Multimedia Engine 166.
  • network traffic includes network messages for obtaining requested data
  • one or more of interfaces 112, 114, 116, 130 and 132 and network switches 170-178 translate target addresses of requested data.
  • interface logic When packets are received and transmitted by network switch 200, interface logic (not shown) manages communication protocols.
  • interfaces (not shown) between buffer 210, control queue 220 and packet memory 230 include wires with one or more buffers to transmit and receive data.
  • no sequential elements are used between buffer 210, control queue 220 and packet memory 230, since packets are processed within a clock cycle. Therefore, schedulers 222 select queue entries of control queue 220, and within a clock cycle, the selected queue entries are deallocated, the corresponding memory entries in packet memory 230 are deallocated, buffer entries in buffer 210 are updated, and write pointer 214 is updated. Additionally, within the clock cycle, control queue 220 shifts remaining allocated queue entries toward an end of the queue such that the remaining allocated queue entries are located in a contiguous manner in control queue 220.
  • Combinatorial logic 350 receives the shift vector states 330. Additionally, combinatorial logic 350 receives queue state 340. Queue state 340 are the outputs of queue entries in a collapsible queue. In the illustrated implementation, the collapsible queue includes 6 entries. Queue entry 0 stores data "A,” queue entry 1 stores data "B,” and so forth. Queue entries 0-5 store data A to F. Combinatorial logic 350 generates the queue updated state values 360 based on the received inputs. In an implementation, queue updated state values 360 are sent to the collapsible queue to be stored after reordering. In various implementations, the propagation delay from receiving shift vector states 310 from external schedulers to sending the queue updated state values 360 to the collapsible queue for storage is a single clock cycle.
  • External schedulers select queue entries to deallocate in a queue.
  • these external schedulers also generate a bit vector including both a first segment of bits, each bit storing a first value, and a second segment of bits, each bit storing a second value.
  • shift vector 312 which is also referred to as shift vector SVo, is a bit vector with 6 bits.
  • the value SVo[4] is binary 1, and therefore, ⁇ SV 1 ⁇ [4] has the same value as SVi[5], rather than SV 1 [4].
  • the value of SVi[5] is 1. Therefore, ⁇ SV 1 ⁇ [4] has the value 1.
  • the value SVo[5] is binary 1, and therefore, ⁇ SV 1 ⁇ [5] has a given value provided. In some implementations, the value is the same as SV 1 [5].
  • the value of SVi[5] is 1. Therefore, ⁇ SV 1 ⁇ [5] has the value 1.
  • Logic 320 performs similar steps to generate transformed shift vector values 336, which is also referred to as ⁇ SV 2 ⁇ .
  • logic 320 uses values stored in each of ⁇ SV 1 ⁇ and SVo, rather than SVo alone. Therefore, logic 320 generates values for transformed shift vector ⁇ SV 1 ⁇ based on both values stored in one other received bit vector (i.e., SVo) and values stored in one other transformed bit vector (i.e., ⁇ SV 1 ⁇ ).
  • each bit position is assigned a value in a same bit position as SVi[0:5] or it is assigned a value in one incremented bit position based on a corresponding value of SVo[0:5] stored in a same bit position.
  • each bit position is assigned a value in a same bit position as SV 2 [0:5] or it is assigned a value in one of the next two incremented bit positions based on corresponding values of ⁇ SV 1 ⁇ [0:5] and SV 0 [0:5].
  • Logic 350 receives the transformed bit vector values 330 and transforms the positions of the values of queue state 340 in a similar manner as described above. The result is shown as queue update state values 360. As shown, queue entries 2, 4 and 5 have been deallocated and the queue entries have been collapsed. The backslash "/" shown in the queue entries indicates available queue entries for allocation.
  • Transform queue entry logic 500 is also referred to as logic 500.
  • logic 500 is used as logic 350 (of FIG. 3 ).
  • multiplexers 510A-510F receive a bit vector, which includes a bit from each of data A-F stored in queue entries.
  • the data size of data A-F can be one of a variety of data sizes stored in a queue.
  • the actual bit position is not shown, since, in an implementation, logic 500 is replicated for each bit stored in the queue entries.
  • a bit from each of data A to F is received on data input lines 502A-502F.
  • Multiplexers 510A-510F receive bit vector SVo[0:5] on select input lines 512A-512F. Multiplexers 510A-510F provide an intermediate bit vector on the output lines 520A-520F, which are sent as data inputs to multiplexers 530A-530F.
  • Portions of the received data are stored in entries of a memory pointed to by the retrieved memory addresses (block 606).
  • the memory addresses and indications of the received data i.e., network messages
  • queue entries of a queue (block 608).
  • Messages to send out of the memory and on the network are selected (block 610).
  • queue entries storing indications of the selected messages are deallocated (block 612).
  • remaining allocated queue entries are shifted toward the end of the queue such that the remaining allocated queue entries are located in a contiguous manner in the queue (block 614).
  • Memory addresses and indications of received messages are stored in queue entries of a queue (block 702).
  • Messages to send on the network are selected (block 704).
  • Bit vectors are generated (block 706).
  • the generated bit vectors identify queue entries storing indications of the selected messages.
  • a bit vector except a first bit vector is selected (block 708). Referring to earlier examples, the bit vector SVo[0:5] was not selected for later transformation.
  • An amount of shifting is determined based upon values stored in one other generated bit vector (block 710).
  • the bit vector SVo[0:5] is sent to select lines of multiplexers as shown earlier in logic 400 (of FIG. 4 ).
  • An amount of shifting is also determined based upon values stored in one or more other transformed bit vectors (block 712).
  • the transformed bit vector ⁇ SV 0 ⁇ [0:5] is sent to select lines of multiplexers as shown earlier in logic 400 (of FIG. 4 ).
  • a transformed bit vector is generated for the selected bit vector (block 714).
  • the transformed bit vector is created by shifting each bit position in the selected bit vector toward a least significant bit position by the determined amount. In other implementations, values are shifted for each bit position toward the most significant bit position. If the last vector is not reached ("no" branch of the conditional block 716), then control flow of method 700 returns to block 708 where a vector except a first vector is selected. If the last vector is reached ("yes" branch of the conditional block 716), then generation of transformed bit vectors is completed (block 718). In some implementations, the generation of transformed bit vectors is performed within a single clock cycle.
  • a queue entry in the queue storing indications of received network messages is selected (block 802).
  • a bit position equal to the position of the queue entry in the queue is selected (block 804).
  • An amount of shifting is determined based upon values stored at the selected bit position in each of the transformed bit vectors (block 806).
  • logic 500 receives an unmodified bit vector and one or more transformed bit vectors on select lines of multiplexers for determining how many bit positions to shift bits of data stored in queue entries.
  • the number of transformed bit vectors to use is based on the radix of the network switch, which is the maximum number of queue entries to deallocate from the queue.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System (AREA)
EP19719094.5A 2018-04-12 2019-04-09 Queue in a network switch Active EP3777059B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/951,844 US10601723B2 (en) 2018-04-12 2018-04-12 Bandwidth matched scheduler
PCT/US2019/026571 WO2019199817A1 (en) 2018-04-12 2019-04-09 Queue in a network switch

Publications (2)

Publication Number Publication Date
EP3777059A1 EP3777059A1 (en) 2021-02-17
EP3777059B1 true EP3777059B1 (en) 2022-08-17

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EP19719094.5A Active EP3777059B1 (en) 2018-04-12 2019-04-09 Queue in a network switch

Country Status (6)

Country Link
US (1) US10601723B2 (https=)
EP (1) EP3777059B1 (https=)
JP (1) JP7138190B2 (https=)
KR (1) KR102456086B1 (https=)
CN (1) CN112189324B (https=)
WO (1) WO2019199817A1 (https=)

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US12436696B2 (en) 2022-09-29 2025-10-07 Advanced Micro Devices, Inc. On-demand regulation of memory bandwidth utilization to service requirements of display

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Also Published As

Publication number Publication date
US10601723B2 (en) 2020-03-24
WO2019199817A1 (en) 2019-10-17
JP2021521529A (ja) 2021-08-26
JP7138190B2 (ja) 2022-09-15
US20190319891A1 (en) 2019-10-17
KR102456086B1 (ko) 2022-10-18
CN112189324B (zh) 2023-09-26
EP3777059A1 (en) 2021-02-17
KR20200139812A (ko) 2020-12-14
CN112189324A (zh) 2021-01-05

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