JP7136200B2 - Semiconductor device, thermosetting resin composition and dicing die bonding integrated tape used for its manufacture - Google Patents

Semiconductor device, thermosetting resin composition and dicing die bonding integrated tape used for its manufacture Download PDF

Info

Publication number
JP7136200B2
JP7136200B2 JP2020518855A JP2020518855A JP7136200B2 JP 7136200 B2 JP7136200 B2 JP 7136200B2 JP 2020518855 A JP2020518855 A JP 2020518855A JP 2020518855 A JP2020518855 A JP 2020518855A JP 7136200 B2 JP7136200 B2 JP 7136200B2
Authority
JP
Japan
Prior art keywords
resin composition
thermosetting resin
molecular weight
semiconductor element
mass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020518855A
Other languages
Japanese (ja)
Other versions
JPWO2019220540A1 (en
Inventor
和弘 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Showa Denko Materials Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of JPWO2019220540A1 publication Critical patent/JPWO2019220540A1/en
Application granted granted Critical
Publication of JP7136200B2 publication Critical patent/JP7136200B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08LCOMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L33/00Compositions of homopolymers or copolymers of compounds having one or more unsaturated aliphatic radicals, each having only one carbon-to-carbon double bond, and only one being terminated by only one carboxyl radical, or of salts, anhydrides, esters, amides, imides or nitriles thereof; Compositions of derivatives of such polymers
    • C08L33/04Homopolymers or copolymers of esters
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08LCOMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08LCOMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L2203/00Applications
    • C08L2203/20Applications use in electrical or conductive gadgets
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08LCOMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L2312/00Crosslinking
    • C08L2312/04Crosslinking with phenolic resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/29386Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/29386Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/29387Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32106Disposition relative to the bonding area, e.g. bond pad the layer connector connecting one bonding area to at least two respective bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/83204Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1052Wire or wire-like electrical connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

Description

本開示は、半導体装置、並びに、その製造に使用する熱硬化性樹脂組成物及びダイシングダイボンディング一体型テープに関する。 TECHNICAL FIELD The present disclosure relates to a semiconductor device, and a thermosetting resin composition and a dicing-die-bonding integrated tape used for manufacturing the semiconductor device.

携帯電話等のデバイスの多機能化に伴い、半導体素子を多段に積層することによって高容量化したスタックドMCP(Multi Chip Package)が普及している。半導体素子の実装には、フィルム状接着剤が広く用いられている。フィルム状接着剤を使用した多段積層パッケージの一例としてワイヤ埋込型のパッケージが挙げられる。このパッケージは、基板上にワイヤボンド済みの半導体素子に対してフィルム状接着剤を圧着することによって当該半導体素子及びワイヤをフィルム状接着剤に埋め込む工程を経て製造される。 2. Description of the Related Art As devices such as mobile phones have become multi-functional, stacked MCPs (Multi Chip Packages), which have increased capacity by stacking semiconductor elements in multiple stages, have become popular. Film adhesives are widely used for mounting semiconductor elements. A wire-embedded package is an example of a multi-layered package using a film-like adhesive. This package is manufactured through a process of embedding the semiconductor element and wires in the film-like adhesive by pressing the film-like adhesive against the wire-bonded semiconductor element on the substrate.

上記スタックドMCP等の半導体装置に求められる重要な特性の一つとして接続信頼性が挙げられる。接続信頼性を向上させるために、耐熱性、耐湿性及び耐リフロー性等の特性を考慮したフィルム状接着剤の開発が行われている。例えば、特許文献1は熱硬化性成分とフィラーとを含有する厚さ10~250μmの接着シートを開示する。特許文献2はエポキシ樹脂とフェノール樹脂とを含む混合物及びアクリル共重合体を含む接着剤組成物を開示する。 One of the important characteristics required for semiconductor devices such as the stacked MCP is connection reliability. In order to improve connection reliability, film adhesives are being developed in consideration of properties such as heat resistance, moisture resistance and reflow resistance. For example, Patent Document 1 discloses an adhesive sheet with a thickness of 10-250 μm containing a thermosetting component and a filler. Patent Document 2 discloses an adhesive composition comprising a mixture comprising an epoxy resin and a phenolic resin and an acrylic copolymer.

半導体装置の接続信頼性は、接着面に空隙(ボイド)を発生させることなく半導体素子を実装できているか否かによっても大きく左右される。このため、空隙を発生させずに半導体素子を圧着できるように高流動なフィルム状接着剤を使用する、又は発生した空隙を半導体素子の封止工程で消失させることができるように溶融粘度の低いフィルム状接着剤を使用するなどの工夫がなされている。例えば特許文献3には低粘度且つ低タック強度の接着シートが開示されている。 The connection reliability of the semiconductor device is greatly affected by whether or not the semiconductor element can be mounted without generating voids on the bonding surface. For this reason, a film-like adhesive with high fluidity is used so that the semiconductor element can be pressure-bonded without generating voids, or a film adhesive with a low melt viscosity is used so that the generated voids can be eliminated in the sealing process of the semiconductor element. Ingenuity such as using a film-like adhesive has been made. For example, Patent Document 3 discloses an adhesive sheet with low viscosity and low tack strength.

国際公開第2005/103180号公報International Publication No. 2005/103180 特開2002-220576号公報JP-A-2002-220576 特開2009-120830号公報JP 2009-120830 A

上記特許文献1及び3の接着シートは、圧着時にワイヤを埋め込むため、高流動化を目的として比較的多量のエポキシ樹脂を含んでいる。このため、半導体装置の製造工程中に発生する熱により熱硬化が進行しやすい。これにより、接着フィルムが高弾性化して、換言すれば、封止時の高温高圧条件でも接着シートが変形しにくくなり、圧着時に形成された空隙が最終的に消失しないことがある。一方、上記特許文献2の接着剤組成物は、弾性率が低いため、封止工程で空隙を消失させることができるものの、粘度が高いことに起因して圧着時におけるワイヤの埋込性が不十分となりやすい。 The adhesive sheets of Patent Literatures 1 and 3 contain a relatively large amount of epoxy resin for the purpose of high fluidity in order to embed the wire at the time of crimping. For this reason, thermal curing is likely to proceed due to heat generated during the manufacturing process of the semiconductor device. As a result, the adhesive film becomes highly elastic, in other words, the adhesive sheet is less likely to deform even under high temperature and high pressure conditions during sealing, and the voids formed during pressure bonding may not eventually disappear. On the other hand, since the adhesive composition of Patent Document 2 has a low elastic modulus, it is possible to eliminate voids in the sealing process, but due to its high viscosity, it is difficult to embed the wire during crimping. likely to be sufficient.

近年、ワイヤ埋込型の半導体装置の動作の高速化が重要視されている。従来は積層された半導体素子の最上段に、半導体装置の動作を制御するコントローラチップが配置されていた。動作の高速化を実現するため、最下段にコントローラチップを配置した半導体装置のパッケージ技術が開発されている。このようなパッケージの一つの形態として、多段に積層した半導体素子のうち、二段目の半導体素子を圧着する際に比較的分厚いフィルム状接着剤を使用し、当該フィルム状接着剤の内部にコントローラチップを埋め込むパッケージが注目を集めている。このような用途に使用されるフィルム状接着剤は、コントローラチップ及びこれと回路パターンとを接続するワイヤ、並びに、基板表面の凹凸起因の段差を埋め込むことのできる高い流動性が求められる。特許文献1及び3の接着シートのような高流動の接着シートを使用することで、この課題を解決できる。 2. Description of the Related Art In recent years, increasing the operation speed of wire-embedded semiconductor devices has been emphasized. Conventionally, a controller chip for controlling the operation of a semiconductor device has been arranged on the uppermost layer of stacked semiconductor elements. In order to realize high-speed operation, a semiconductor device package technology has been developed in which a controller chip is arranged at the bottom. As one form of such a package, a relatively thick film-like adhesive is used when pressure-bonding the semiconductor element in the second layer among the semiconductor elements stacked in multiple layers, and the controller is placed inside the film-like adhesive. Packages that embed chips are attracting attention. The film-like adhesive used for such applications is required to have high fluidity so as to be able to fill in the wires connecting the controller chip and the circuit pattern, as well as the unevenness of the substrate surface. This problem can be solved by using a high-fluidity adhesive sheet such as the adhesive sheets of US Pat.

しかし、特許文献1及び3に記載の接着シートは硬化前に高い流動性を発現させる一方で、コントローラチップの埋め込み時に流動した樹脂が周辺の回路を汚染することもある。更に、埋め込み後の熱硬化により接着シートが流動し、チップの位置ずれが生じたり、埋め込みチップの端面から潮が引くように樹脂がチップ内側へ入り込んでいき、チップ端部から樹脂が無くなる「ヒケ」と呼ばれる現象が発生したりする(図8参照)。特に、近年、埋込性向上のために加圧条件下で熱硬化処理を行うことが多い。このように外部から圧力がある状態で熱が加われば埋込性が向上する一方で樹脂がより一層流動しやすくなり、上記のような問題が発生することが多い。 However, while the adhesive sheets described in Patent Documents 1 and 3 exhibit high fluidity before curing, the resin that has flowed when the controller chip is embedded may contaminate the surrounding circuits. In addition, the adhesive sheet flows due to heat curing after embedding, causing the position of the chip to shift, and the resin to enter the inside of the chip from the end face of the embedded chip, causing the resin to disappear from the end of the chip. ” occurs (see FIG. 8). In recent years, in particular, in order to improve the embedding property, heat curing treatment is often performed under pressure conditions. When heat is applied in such a state that pressure is applied from the outside, the embedding property is improved, but the resin is more likely to flow, which often causes the above-described problems.

本開示は、優れた接続信頼性を有する半導体装置を提供することを目的とする。また、本開示は、優れた接続信頼性を有する半導体装置を製造するのに有用な熱硬化性樹脂組成物及びこれからなる接着層を備えるダイシングダイボンディング一体型テープを提供することを目的とする。 An object of the present disclosure is to provide a semiconductor device having excellent connection reliability. Another object of the present disclosure is to provide a thermosetting resin composition useful for manufacturing a semiconductor device having excellent connection reliability and a dicing and die bonding integrated tape comprising an adhesive layer comprising the composition.

本発明者らは、コントローラチップがフィルム状接着剤の硬化物に埋め込まれた態様のパッケージを開発するため、フィルム状接着剤の樹脂の選定と物性の調整について鋭意研究を重ねた。その結果、本発明者らは、フィルム状接着剤の溶融粘度が埋め込み時の回路汚染及びその後の熱工程で発生するヒケと相関があること見出した。 In order to develop a package in which a controller chip is embedded in a cured film adhesive, the present inventors have extensively researched the selection of the resin of the film adhesive and the adjustment of physical properties. As a result, the present inventors found that the melt viscosity of the film-like adhesive correlates with circuit contamination at the time of embedding and sink marks that occur in the subsequent heating process.

本開示に係る半導体装置は、基板と、基板上に配置された第1の半導体素子と、基板における第1の半導体素子が配置された領域を覆うように配置されており、第1の半導体素子を封止している第1の封止層と、第1の封止層における基板の側と反対側の表面を覆うように配置されており、第1の半導体素子よりも大きい面積を有する第2の半導体素子とを備え、第1の封止層が熱硬化性樹脂組成物の硬化物からなり、熱硬化性樹脂組成物の120℃における溶融粘度が2500~11500Pa・sである。 A semiconductor device according to the present disclosure includes a substrate, a first semiconductor element arranged on the substrate, and a region of the substrate where the first semiconductor element is arranged. and a first sealing layer that is arranged to cover the surface of the first sealing layer opposite to the substrate side, and has an area larger than that of the first semiconductor element 2 semiconductor element, the first sealing layer is made of a cured product of a thermosetting resin composition, and the melt viscosity of the thermosetting resin composition at 120° C. is 2500 to 11500 Pa·s.

上記半導体装置は、第1の半導体素子(例えば、コントローラチップ)が熱硬化性樹脂組成物の硬化物に埋め込まれた態様であり、動作の高速化が可能である。第1の封止層が、120℃における溶融粘度が2500~11500Pa・sである熱硬化性樹脂組成物の硬化物であることで、基板又は第1の半導体素子との界面における空隙が十分に少ないとともに、基板の汚染及びヒケの問題の発生も十分に抑制されるため、基板と第1の半導体素子との優れた接続信頼性を達成できる。 The above-described semiconductor device has a mode in which the first semiconductor element (for example, a controller chip) is embedded in the cured product of the thermosetting resin composition, and can operate at high speed. The first sealing layer is a cured product of a thermosetting resin composition having a melt viscosity at 120 ° C. of 2500 to 11500 Pa s, so that the gap at the interface with the substrate or the first semiconductor element is sufficient. In addition, the problem of substrate contamination and sink marks is sufficiently suppressed, so that excellent connection reliability between the substrate and the first semiconductor element can be achieved.

本開示に係る半導体装置は、基板の表面に形成された回路パターンと、第1の半導体素子と回路パターンとを電気的に接続する第1のワイヤとを更に備えてもよい。本開示に係る半導体装置は、第2の半導体素子と回路パターンとを電気的に接続する第2のワイヤと、第2の半導体素子及び第2のワイヤを封止している第2の封止層とを更に備えてもよい。本開示に係る半導体装置は、第2の半導体素子の上に積層された第3の半導体素子を更に備えてもよい。 The semiconductor device according to the present disclosure may further include a circuit pattern formed on the surface of the substrate, and first wires electrically connecting the first semiconductor element and the circuit pattern. A semiconductor device according to the present disclosure includes a second wire that electrically connects a second semiconductor element and a circuit pattern, and a second sealing that seals the second semiconductor element and the second wire. and a layer. The semiconductor device according to the present disclosure may further include a third semiconductor element laminated on the second semiconductor element.

上記フィルム状接着剤を構成する熱硬化性樹脂組成物は、分子量10~1000の低分子量成分(例えば、エポキシ樹脂)と、分子量10万~100万の高分子量成分(例えば、アクリルゴム)とを含み、低分子量成分の含有量M1が当該熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して23~35質量部であり、高分子量成分の含有量M2が熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して25~45質量部であることが好ましい。このような組成の熱硬化性樹脂組成物を使用することで、低分子量成分が優れた埋込性に寄与し、他方、高分子量成分が過剰な流動に起因する問題の抑制に寄与する。熱硬化性樹脂組成物は、当該熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して低分子量成分と高分子量成分の合計量(M1+M2)が54~76質量部であることが好ましい。 The thermosetting resin composition constituting the film-like adhesive contains a low molecular weight component (eg, epoxy resin) with a molecular weight of 10 to 1,000 and a high molecular weight component (eg, acrylic rubber) with a molecular weight of 100,000 to 1,000,000. The content M1 of the low molecular weight component is 23 to 35 parts by mass with respect to 100 parts by mass of the resin component contained in the thermosetting resin composition, and the content M2 of the high molecular weight component is a thermosetting resin It is preferably 25 to 45 parts by mass with respect to 100 parts by mass of the resin component contained in the composition. By using a thermosetting resin composition having such a composition, the low molecular weight component contributes to excellent embedding properties, while the high molecular weight component contributes to suppression of problems caused by excessive flow. In the thermosetting resin composition, the total amount (M1+M2) of the low molecular weight component and the high molecular weight component is 54 to 76 parts by mass with respect to 100 parts by mass of the resin component contained in the thermosetting resin composition. is preferred.

なお、熱硬化性樹脂組成物に含まれる樹脂成分の分子量(重量平均分子量)は、ゲルパーミエーションクロマトグラフィー(GPC)で測定し、標準ポリスチレンによる検量線を用いて換算した値を意味する。 The molecular weight (weight average molecular weight) of the resin component contained in the thermosetting resin composition means a value measured by gel permeation chromatography (GPC) and converted using a standard polystyrene calibration curve.

基板としてその表面に回路パターンを有するものを使用する場合、本開示に係る半導体装置は、第1の半導体素子と回路パターンとを電気的に接続する第1のワイヤとを更に備えるものであってもよいし、第2の半導体素子と回路パターンとを電気的に接続する第2のワイヤと、第2の半導体素子及び第2のワイヤを封止している第2の封止層とを更に備えるものであってもよい。 When using a substrate having a circuit pattern on its surface, the semiconductor device according to the present disclosure further includes a first wire electrically connecting the first semiconductor element and the circuit pattern. Alternatively, a second wire electrically connecting the second semiconductor element and the circuit pattern, and a second sealing layer sealing the second semiconductor element and the second wire are further provided. It may be provided.

本開示に係る熱硬化性樹脂組成物は、当該熱硬化性樹脂組成物を加熱する硬化処理を経て、ワイヤの少なくとも一部及び半導体素子の少なくとも一方が硬化処理後の熱硬化性樹脂組成物に埋め込まれた状態とする工程を含む半導体装置の製造プロセスにおいて使用されるものであって、熱硬化性樹脂組成物の120℃における溶融粘度が2500~11500Pa・sである。上記熱硬化性樹脂組成物によれば、半導体素子等を埋め込み可能な流動性を有するとともに、埋め込み時の周辺回路の汚染及びその後の熱工程(熱硬化性樹脂組成物の熱硬化処理)における樹脂の過剰な流動に起因する問題を十分に抑制できる。 In the thermosetting resin composition according to the present disclosure, at least a part of the wire and at least one of the semiconductor elements are subjected to a curing treatment of heating the thermosetting resin composition, and the thermosetting resin composition after the curing treatment. It is used in the manufacturing process of a semiconductor device including a step of embedding, and the melt viscosity of the thermosetting resin composition at 120° C. is 2500 to 11500 Pa·s. According to the thermosetting resin composition, it has a fluidity that allows embedding of a semiconductor element or the like, and contamination of the peripheral circuit at the time of embedding and the subsequent heating process (thermosetting treatment of the thermosetting resin composition). can sufficiently suppress problems caused by excessive flow of

本開示に係るダイシングダイボンディング一体型テープは、粘着層と、上記熱硬化性樹脂組成物からなる接着層とを備える。 A dicing die bonding integrated tape according to the present disclosure includes an adhesive layer and an adhesive layer made of the thermosetting resin composition.

本開示によれば、優れた接続信頼性を有する半導体装置が提供されるとともに、その製造において使用される熱硬化性樹脂組成物及びこれからなる接着層を備えるダイシングダイボンディング一体型テープが提供される。この熱硬化性樹脂組成物は、コントローラチップ等の半導体素子及びワイヤの少なくとも一方を埋め込み可能な優れた埋込性を有するとともに、埋め込み時の周辺回路の汚染及びその後の熱工程における樹脂の過剰な流動に起因する問題を十分に抑制できる。 According to the present disclosure, a semiconductor device having excellent connection reliability is provided, and a thermosetting resin composition used in its manufacture and an integrated dicing and die bonding tape comprising an adhesive layer composed of it are provided. . This thermosetting resin composition has excellent embeddability capable of embedding at least one of a semiconductor element such as a controller chip and a wire, and prevents contamination of peripheral circuits during embedding and excess resin in subsequent thermal processes. Problems caused by flow can be sufficiently suppressed.

図1は半導体装置の一例を模式的に示す断面図である。FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device. 図2はフィルム状接着剤と第2の半導体素子とからなる積層体の一例を模式的に示す断面図である。FIG. 2 is a cross-sectional view schematically showing an example of a laminate composed of a film-like adhesive and a second semiconductor element. 図3は図1に示す半導体装置を製造する過程を模式的に示す断面図である。3A to 3C are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. 図4は図1に示す半導体装置を製造する過程を模式的に示す断面図である。4A to 4D are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. 図5は図1に示す半導体装置を製造する過程を模式的に示す断面図である。5A to 5D are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. 図6は図1に示す半導体装置を製造する過程を模式的に示す断面図である。6A to 6C are cross-sectional views schematically showing the process of manufacturing the semiconductor device shown in FIG. 図7(a)~図7(e)は、フィルム状接着剤と第2の半導体素子とからなる積層体を製造する過程を模式的に示す断面図である。7(a) to 7(e) are cross-sectional views schematically showing the process of manufacturing a laminate comprising a film-like adhesive and a second semiconductor element. 図8(a)は「ヒケ」と称される現象が生じていない構造体の断面を示す写真であり、図8(b)は「ヒケ」が生じている構造体(ヒケの深さ:140μm)の断面を示す写真である。FIG. 8(a) is a photograph showing a cross section of a structure in which a phenomenon called "sink marks" does not occur, and FIG. ) is a photograph showing a cross section. 図9(a)はボイドの発生の有無を評価するための構造体を模式的に示す断面図であり、図9(b)はボイドが発生していない構造体の写真であり、図9(c)はボイドが発生している構造体の写真である。FIG. 9(a) is a cross-sectional view schematically showing a structure for evaluating the presence or absence of voids, and FIG. 9(b) is a photograph of the structure without voids. c) is a photograph of a voided structure.

以下、図面を参照しながら本開示の実施形態について詳細に説明する。以下の説明では、同一又は相当部分には同一符号を付し、重複する説明は省略する。また、上下左右等の位置関係は、特に断らない限り、図面に示す位置関係に基づくものとする。更に、図面の寸法比率は図示の比率に限られるものではない。なお、本明細書における「(メタ)アクリル」の記載は、「アクリル」及びそれに対応する「メタクリル」を意味する。 Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and overlapping descriptions are omitted. In addition, unless otherwise specified, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to the illustrated ratios. In addition, the description of "(meth)acryl" in this specification means "acryl" and "methacryl" corresponding to it.

<半導体装置>
図1は本実施形態に係る半導体装置を模式的に示す断面図である。この図に示す半導体装置100は、基板10と、基板10の表面上に配置された第1の半導体素子Waと、第1の半導体素子Waを封止している第1の封止層20と、第1の半導体素子Waの上方に配置された第2の半導体素子Wbと、第2の半導体素子Wbを封止している第2の封止層40とを備える。
<Semiconductor device>
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to this embodiment. The semiconductor device 100 shown in this figure includes a substrate 10, a first semiconductor element Wa arranged on the surface of the substrate 10, and a first sealing layer 20 sealing the first semiconductor element Wa. , a second semiconductor element Wb disposed above the first semiconductor element Wa, and a second sealing layer 40 sealing the second semiconductor element Wb.

基板10は、表面に回路パターン10a,10bを有する。半導体装置100の反りを抑制する観点から、基板10の厚さは、例えば、90~180μmであり、90~140μmであってもよい。なお、基板10は有機基板であっても、リードフレーム等の金属基板であってもよい。 The substrate 10 has circuit patterns 10a and 10b on its surface. From the viewpoint of suppressing warping of the semiconductor device 100, the thickness of the substrate 10 is, for example, 90 to 180 μm, and may be 90 to 140 μm. The substrate 10 may be an organic substrate or a metal substrate such as a lead frame.

本実施形態において、第1の半導体素子Waは半導体装置100を駆動するためのコントローラチップである。第1の半導体素子Waは、回路パターン10a上に接着剤15を介して接着されており、また、第1のワイヤ11を介して回路パターン10bに接続されている。平面視における第1の半導体素子Waの形状は、例えば矩形(正方形又は長方形)である。第1の半導体素子Waの一辺の長さは、例えば、5mm以下であり、2~4mm又は1~4mmであってもよい。第1の半導体素子Waの厚さは、例えば、10~150μmであり、20~100μmであってもよい。 In this embodiment, the first semiconductor element Wa is a controller chip for driving the semiconductor device 100 . The first semiconductor element Wa is adhered onto the circuit pattern 10a via an adhesive 15, and is connected via the first wire 11 to the circuit pattern 10b. The shape of the first semiconductor element Wa in plan view is, for example, a rectangle (square or rectangle). The length of one side of the first semiconductor element Wa is, for example, 5 mm or less, and may be 2 to 4 mm or 1 to 4 mm. The thickness of the first semiconductor element Wa is, for example, 10 to 150 μm, and may be 20 to 100 μm.

第2の半導体素子Wbは、第1の半導体素子Waよりも大きい面積を有する。第2の半導体素子Wbは、第1の半導体素子Waの全体と回路パターン10bの一部とが覆われるように第1の封止層20を介して基板10上に搭載されている。平面視における第2の半導体素子Wbの形状は、例えば矩形(正方形又は長方形)である。第2の半導体素子Wbの一辺の長さは、例えば、20mm以下であり、4~20mm又は4~12mmであってもよい。第2の半導体素子Wbの厚さは、例えば、10~170μmであり、20~120μmであってもよい。第2の半導体素子Wbは、第2のワイヤ12を介して回路パターン10bに接続されるとともに封止層25により封止されている。 The second semiconductor element Wb has a larger area than the first semiconductor element Wa. The second semiconductor element Wb is mounted on the substrate 10 via the first sealing layer 20 so as to cover the entire first semiconductor element Wa and part of the circuit pattern 10b. The shape of the second semiconductor element Wb in plan view is, for example, a rectangle (square or rectangle). The length of one side of the second semiconductor element Wb is, for example, 20 mm or less, and may be 4 to 20 mm or 4 to 12 mm. The thickness of the second semiconductor element Wb is, for example, 10-170 μm, and may be 20-120 μm. The second semiconductor element Wb is connected to the circuit pattern 10b via the second wire 12 and sealed with the sealing layer 25 .

第1の封止層20はフィルム状接着剤20P(図2参照)の硬化物からなる。なお、図2に示すとおり、フィルム状接着剤20Pと第2の半導体素子Wbは実質的に同じサイズである。図2に示す積層体30は、フィルム状接着剤20Pと第2の半導体素子Wbとからなり、接着剤付き半導体チップとも称される。積層体30は、後述のとおり、ダイシング工程及びピックアップ工程を経ることによって作製される(図7参照)。 The first sealing layer 20 is made of a cured film adhesive 20P (see FIG. 2). Incidentally, as shown in FIG. 2, the film adhesive 20P and the second semiconductor element Wb have substantially the same size. A laminate 30 shown in FIG. 2 is composed of a film adhesive 20P and a second semiconductor element Wb, and is also referred to as a semiconductor chip with adhesive. The laminate 30 is produced through a dicing process and a pick-up process, as described later (see FIG. 7).

<半導体装置の製造方法>
半導体装置100の製造方法について説明する。まず、図3に示す構造体50を作製する。すなわち、基板10の表面上に接着剤15を介して第1の半導体素子Waを配置する。その後、第1の半導体素子Waと回路パターン10bとを第1のワイヤ11で電気的に接続する。
<Method for manufacturing a semiconductor device>
A method for manufacturing the semiconductor device 100 will be described. First, the structure 50 shown in FIG. 3 is produced. That is, the first semiconductor element Wa is arranged on the surface of the substrate 10 with the adhesive 15 interposed therebetween. After that, the first semiconductor element Wa and the circuit pattern 10b are electrically connected with the first wire 11. Next, as shown in FIG.

次に、図3及び図4に示すように、別途準備した積層体30のフィルム状接着剤20Pを基板10に対して押圧する。これによって、第1の半導体素子Wa及び第1のワイヤ11をフィルム状接着剤20Pに埋め込む。フィルム状接着剤20Pの厚さは、第1の半導体素子Waの厚さ等に応じて適宜設定すればよく、例えば、20~200μmの範囲であればよく、30~200μm又は40~150μmであってもよい。フィルム状接着剤20Pの厚さを上記範囲とすることで、第1の半導体素子Waと第2の半導体素子Wbの間隔(図5における距離G)を十分に確保することができる。距離Gは、例えば50μm以上であることが好ましく、50~75μm又は50~80μmであってもよい。 Next, as shown in FIGS. 3 and 4, the film adhesive 20P of the laminate 30 prepared separately is pressed against the substrate 10. Next, as shown in FIGS. As a result, the first semiconductor element Wa and the first wires 11 are embedded in the film adhesive 20P. The thickness of the film-like adhesive 20P may be appropriately set according to the thickness of the first semiconductor element Wa, etc. For example, the thickness may be in the range of 20 to 200 μm, such as 30 to 200 μm or 40 to 150 μm. may By setting the thickness of the film-like adhesive 20P within the above range, it is possible to secure a sufficient distance (distance G in FIG. 5) between the first semiconductor element Wa and the second semiconductor element Wb. The distance G is, for example, preferably 50 μm or more, and may be 50-75 μm or 50-80 μm.

フィルム状接着剤20Pの基板10に対して圧着は、例えば、80~180℃、0.01~0.50MPaの条件で、0.5~3.0秒間にわたって実施することが好ましい。 The pressure bonding of the film adhesive 20P to the substrate 10 is preferably performed, for example, under conditions of 80 to 180° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds.

次に、加熱によってフィルム状接着剤20Pを硬化させる。この硬化処理は、例えば、60~175℃、0.01~1.0MPaの条件で、5分間以上にわたって実施することが好ましい。これにより、フィルム状接着剤20Pの硬化物(第1の封止層20)で第1の半導体素子Waが封止される(図6参照)。フィルム状接着剤20Pの硬化処理は、ボイドの低減の観点から、加圧雰囲気下で実施してもよい。第2の半導体素子Wbと回路パターン10bとを第2のワイヤ12で電気的に接続した後、第2の封止層40によって第2の半導体素子Wbを封止することによって半導体装置100が完成する(図1参照)。 Next, the film adhesive 20P is cured by heating. This curing treatment is preferably carried out, for example, under conditions of 60 to 175° C. and 0.01 to 1.0 MPa for 5 minutes or longer. As a result, the first semiconductor element Wa is sealed with the cured film adhesive 20P (first sealing layer 20) (see FIG. 6). The curing treatment of the film adhesive 20P may be performed under a pressurized atmosphere from the viewpoint of reducing voids. After electrically connecting the second semiconductor element Wb and the circuit pattern 10b with the second wire 12, the second semiconductor element Wb is sealed with the second sealing layer 40 to complete the semiconductor device 100. (see Figure 1).

<接着剤付き半導体チップの作製方法>
図7(a)~図7(e)を参照しながら、図2に示す積層体30(接着剤付き半導体チップ)の作製方法の一例について説明する。まず、ダイシングダイボンディング一体型テープ8(以下、場合により「テープ8」という。)を所定の装置(不図示)に配置する。テープ8は、基材層1と粘着層2と接着層20Aとをこの順序で備える。基材層1は、例えば、ポリエチレンテレフタレートフィルム(PETフィルム)である。半導体ウェハWは、例えば、厚さ10~100μmの薄型半導体ウェハである。半導体ウェハWは、単結晶シリコンであってもよいし、多結晶シリコン、各種セラミック、ガリウム砒素等の化合物半導体であってもよい。
<Method for producing semiconductor chip with adhesive>
An example of a method for manufacturing the laminate 30 (semiconductor chip with adhesive) shown in FIG. 2 will be described with reference to FIGS. 7(a) to 7(e). First, a dicing die bonding integrated tape 8 (hereinafter sometimes referred to as "tape 8") is arranged in a predetermined device (not shown). The tape 8 comprises a base material layer 1, an adhesive layer 2 and an adhesive layer 20A in this order. The base material layer 1 is, for example, a polyethylene terephthalate film (PET film). The semiconductor wafer W is, for example, a thin semiconductor wafer with a thickness of 10-100 μm. The semiconductor wafer W may be monocrystalline silicon, polycrystalline silicon, various ceramics, or compound semiconductors such as gallium arsenide.

図7(a)及び図7(b)に示すように、半導体ウェハWの一方の面に接着層20Aが接するようにテープ8を貼り付ける。この工程は、好ましくは50~100℃、より好ましくは60~80℃の温度条件下で実施する。温度が50℃以上であると、半導体ウェハWを接着層20Aとの良好な密着性を得ることができ、100℃以下であると、この工程において接着層20Aが過度に流動することが抑制される。 As shown in FIGS. 7A and 7B, the tape 8 is attached to one surface of the semiconductor wafer W so that the adhesive layer 20A is in contact therewith. This step is preferably carried out at a temperature of 50-100°C, more preferably 60-80°C. When the temperature is 50° C. or higher, good adhesion between the semiconductor wafer W and the adhesive layer 20A can be obtained. be.

図7(c)に示すように、半導体ウェハW、粘着層2及び接着層20Aをダイシングする。これにより、半導体ウェハWが個片化されて半導体素子Wbとなる。接着層20Aも個片化されてフィルム状接着剤20Pとなる。ダイシング方法としては、回転刃又はレーザを用いる方法が挙げられる。なお、半導体ウェハWのダイシングに先立って半導体ウェハWを研削することによって薄膜化してもよい。 As shown in FIG. 7C, the semiconductor wafer W, adhesive layer 2 and adhesive layer 20A are diced. As a result, the semiconductor wafer W is separated into individual semiconductor elements Wb. The adhesive layer 20A is also singulated to form a film adhesive 20P. A dicing method includes a method using a rotary blade or a laser. In addition, the semiconductor wafer W may be thinned by grinding the semiconductor wafer W prior to the dicing of the semiconductor wafer W. FIG.

次に、粘着層2が例えばUV硬化型である場合、図7(d)に示すように、粘着層2に対して紫外線を照射することにより粘着層2を硬化させ、粘着層2とフィルム状接着剤20Pとの間の粘着力を低下させる。紫外線照射後、図7(e)に示されるように、常温又は冷却条件下において基材層1をエキスパンドすることによって半導体素子Waを互いに離間させつつ、ニードル42で突き上げることによって粘着層2から積層体30のフィルム状接着剤20Pを剥離させるとともに、積層体30を吸引コレット44で吸引してピックアップする。このようにして得られた積層体30は、図3に示す構造体50の製造に供される。 Next, when the adhesive layer 2 is, for example, a UV curable type, as shown in FIG. It reduces the adhesive strength with the adhesive 20P. After the ultraviolet irradiation, as shown in FIG. 7(e), the semiconductor elements Wa are separated from each other by expanding the base layer 1 under room temperature or cooling conditions, and the semiconductor elements Wa are pushed up with needles 42 to be laminated from the adhesive layer 2. The film adhesive 20P of the body 30 is peeled off, and the laminate 30 is sucked by the suction collet 44 and picked up. The laminate 30 thus obtained is used for manufacturing the structure 50 shown in FIG.

<熱硬化性樹脂組成物>
フィルム状接着剤20Pを構成する熱硬化性樹脂組成物について説明する。なお、フィルム状接着剤20Pは接着層20Aを個片化したものであり、両者は同じ熱硬化性樹脂組成物からなる。この熱硬化性樹脂組成物は、例えば、半硬化(Bステージ)状態を経て、その後の硬化処理によって完全硬化物(Cステージ)状態となり得るものである。
<Thermosetting resin composition>
The thermosetting resin composition that constitutes the film adhesive 20P will be described. The film-like adhesive 20P is obtained by dividing the adhesive layer 20A into individual pieces, and both are made of the same thermosetting resin composition. This thermosetting resin composition can, for example, go through a semi-cured (B stage) state and then become a fully cured (C stage) state by a subsequent curing treatment.

熱硬化性樹脂組成物は以下の成分を含むことが好ましい。
(a)熱硬化性樹脂(以下、単に「(a)成分」という場合がある。)
(b)高分子量成分(以下、単に「(b)成分」という場合がある。)
(c)無機フィラー(以下、単に「(c)成分」という場合がある。)
なお、本実施形態においては、(a)熱硬化性樹脂がエポキシ樹脂を含む場合、エポキシ樹脂(以下、単に「(a1)成分」という場合がある。)が「低分子量成分」に該当する。この場合、(a)熱硬化性樹脂は、エポキシ樹脂の硬化剤となり得るフェノール樹脂(以下、単に「(a2)成分」という場合がある。)を含むことが好ましい。
The thermosetting resin composition preferably contains the following components.
(a) Thermosetting resin (hereinafter sometimes simply referred to as "(a) component")
(b) high molecular weight component (hereinafter sometimes simply referred to as "(b) component")
(c) Inorganic filler (hereinafter sometimes simply referred to as "(c) component")
In the present embodiment, when (a) the thermosetting resin contains an epoxy resin, the epoxy resin (hereinafter sometimes simply referred to as "(a1) component") corresponds to the "low molecular weight component". In this case, (a) the thermosetting resin preferably contains a phenolic resin (hereinafter sometimes simply referred to as "(a2) component") that can serve as a curing agent for epoxy resins.

熱硬化性樹脂組成物は以下の成分を更に含んでもよい。
(d)カップリング剤(以下、単に「(d)成分」という場合がある。)
(e)硬化促進剤(以下、単に「(e)成分」という場合がある。)
The thermosetting resin composition may further contain the following components.
(d) Coupling agent (hereinafter sometimes simply referred to as "(d) component")
(e) curing accelerator (hereinafter sometimes simply referred to as "(e) component")

上記熱硬化性樹脂組成物は、分子量10~1000の低分子量成分((a1)成分)と、分子量10万~100万の高分子量成分((b)成分)との両方を含むことが好ましい。これらの成分を併用することで、低分子量成分が優れた埋込性に寄与し、他方、高分子量成分が過剰な流動に起因する問題の抑制に寄与する。 The thermosetting resin composition preferably contains both a low molecular weight component (component (a1)) having a molecular weight of 10 to 1,000 and a high molecular weight component (component (b)) having a molecular weight of 100,000 to 1,000,000. By using these components together, the low molecular weight component contributes to excellent embeddability, while the high molecular weight component contributes to suppression of problems caused by excessive flow.

低分子量成分の含有量M1は、熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して23~35質量部であることが好ましく、25~35質量部であることがより好ましい。低分子量成分の含有量M1が23質量部以上であることで、優れた埋込性を達成しやすく、他方、35質量部以下であることで、優れたピックアップ性を達成しやすいという効果が奏される。なお、低分子量成分の軟化点は50℃以下であることが好ましく、例えば、10~30℃であってもよい。 The content M1 of the low molecular weight component is preferably 23 to 35 parts by mass, more preferably 25 to 35 parts by mass with respect to 100 parts by mass of the resin component contained in the thermosetting resin composition. . When the content M1 of the low-molecular-weight component is 23 parts by mass or more, excellent embedding properties can be easily achieved, while when it is 35 parts by mass or less, excellent pick-up properties can be easily achieved. be done. The softening point of the low-molecular-weight component is preferably 50°C or less, and may be, for example, 10 to 30°C.

高分子量成分の含有量M2は、熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して25~45質量部であることが好ましく、30~40質量部であることがより好ましい。高分子量成分の含有量M2が25質量部以上であることで、過剰な流動に起因する問題(基板の汚染、ヒケ及び反り等)を抑制しやすく、他方、45質量部以下であることで、優れた埋込性を達成しやすいという効果が奏される。なお、高分子量成分の軟化点は50℃超100℃以下であることが好ましい。 The content M2 of the high molecular weight component is preferably 25 to 45 parts by mass, more preferably 30 to 40 parts by mass, with respect to 100 parts by mass of the resin component contained in the thermosetting resin composition. . When the content M2 of the high-molecular-weight component is 25 parts by mass or more, problems caused by excessive flow (substrate contamination, sink marks, warping, etc.) can be easily suppressed. The effect of easily achieving excellent embeddability is exhibited. The softening point of the high molecular weight component is preferably above 50°C and 100°C or less.

熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対し、低分子量成分と高分子量成分の合計量(M1+M2)は54~76質量部であることが好ましく、55~75質量部であることがより好ましい。この合計量が54質量部以上であることで、これらの成分を併用したことの効果が十分に発揮される傾向にあり、他方、76質量部以下であることで、優れたピックアップ性を達成しやすいという効果が奏される。なお、熱硬化性樹脂組成物に含まれる樹脂成分であって、低分子量成分及び高分子量成分以外のものとしては、主に、分子量が1001~9万9000の熱硬化性樹脂等が挙げられる。 The total amount of the low molecular weight component and the high molecular weight component (M1+M2) is preferably 54 to 76 parts by weight, preferably 55 to 75 parts by weight, with respect to 100 parts by weight of the resin component contained in the thermosetting resin composition. It is more preferable to have When the total amount is 54 parts by mass or more, the effect of the combined use of these components tends to be sufficiently exhibited, while when the total amount is 76 parts by mass or less, excellent pickup properties are achieved. It has the effect of making it easier. The resin components contained in the thermosetting resin composition other than the low molecular weight component and the high molecular weight component mainly include thermosetting resins having a molecular weight of 1,001 to 99,000.

熱硬化性樹脂組成物の120℃における溶融粘度は、接続信頼性の観点から、2500~11500Pa・sである。この溶融粘度が2500Pa・s以上であることで、圧着処理時等における基板10の汚染及びヒケの問題の発生を十分に抑制することができる。例えば、第2の半導体素子Wbと基板10との間に熱硬化性樹脂組成物の硬化物が存在しない領域(ヒケ)があると、その領域に第2の封止層40用の封止材が侵入し、これによって第2の半導体素子Wbが剥離しやすくなるという不具合が生じやすい。熱硬化性樹脂組成物の120℃における溶融粘度が11500Pa・s以下であることで、基板10又は第1の半導体素子Waとの界面における空隙を十分に少なくできる。この溶融粘度は、好ましくは5000~11000Pa・sであり、より好ましくは5000~10000Pa・sであり、更に好ましくは5000~9000Pa・sである。なお、溶融粘度は、ARES(TA Instruments社製)を用いてフィルム状に成形した熱硬化性樹脂組成物に5%の歪みを与えながら5℃/分の昇温速度で昇温させながら測定した場合の測定値を意味する。 The melt viscosity of the thermosetting resin composition at 120° C. is 2500 to 11500 Pa·s from the viewpoint of connection reliability. When the melt viscosity is 2500 Pa·s or more, it is possible to sufficiently suppress the problem of contamination and sink marks on the substrate 10 during pressure bonding. For example, if there is a region (sink mark) where the cured product of the thermosetting resin composition does not exist between the second semiconductor element Wb and the substrate 10, the sealing material for the second sealing layer 40 is formed in that region. invades the second semiconductor element Wb, which tends to cause a problem that the second semiconductor element Wb is easily peeled off. When the melt viscosity of the thermosetting resin composition at 120° C. is 11,500 Pa·s or less, voids at the interface with the substrate 10 or the first semiconductor element Wa can be sufficiently reduced. The melt viscosity is preferably 5,000 to 11,000 Pa·s, more preferably 5,000 to 10,000 Pa·s, still more preferably 5,000 to 9,000 Pa·s. The melt viscosity was measured while increasing the temperature at a rate of 5° C./min while giving a strain of 5% to the thermosetting resin composition molded into a film using ARES (manufactured by TA Instruments). Means the measured value of the case.

熱硬化性樹脂組成物の100℃における溶融粘度は、接続信頼性の観点から、3500~13500Pa・sであることが好ましい。この溶融粘度が3500Pa・s以上であることで、圧着処理時等における基板10の汚染及びヒケの問題の発生を十分に抑制することができる。他方、この溶融粘度が13500Pa・s以下であることで、基板10又は第1の半導体素子Waとの界面における空隙を十分に少なくできる。この溶融粘度は、好ましくは5500~10500Pa・sである。熱硬化性樹脂組成物の100℃及び120℃における溶融粘度を上記範囲内とするには、(a)熱硬化性樹脂、(b)高分子量成分及び(c)無機フィラーの量を適宜調整すればよい。 The melt viscosity at 100° C. of the thermosetting resin composition is preferably 3500 to 13500 Pa·s from the viewpoint of connection reliability. When the melt viscosity is 3500 Pa·s or more, it is possible to sufficiently suppress the occurrence of problems such as contamination of the substrate 10 and sink marks during compression bonding. On the other hand, when the melt viscosity is 13500 Pa·s or less, the voids at the interface with the substrate 10 or the first semiconductor element Wa can be sufficiently reduced. The melt viscosity is preferably 5500 to 10500 Pa·s. In order to make the melt viscosity of the thermosetting resin composition at 100 ° C. and 120 ° C. within the above range, the amounts of (a) thermosetting resin, (b) high molecular weight component and (c) inorganic filler should be appropriately adjusted. Just do it.

図9(a)は透明な基板10と、その上の第1の半導体素子Waと、第1の封止層20(フィルム状接着剤20Pの硬化物)と、その上の第2の半導体素子Wbとを備える構造体である。図9(b)及び図9(c)は透明な基板10の裏面側(図9(a)における矢印の方向)から撮影した写真である。図9(b)に示す構造体においては、フィルム状接着剤の埋込性が十分であり、ボイドが発生していない。これに対し、図9(c)に示す構造体においては、フィルム状接着剤の埋込性が不十分であり、ボイドVが発生している。 FIG. 9A shows a transparent substrate 10, a first semiconductor element Wa thereon, a first sealing layer 20 (hardened film-like adhesive 20P), and a second semiconductor element thereon. Wb. 9(b) and 9(c) are photographs taken from the back side of the transparent substrate 10 (in the direction of the arrow in FIG. 9(a)). In the structure shown in FIG. 9(b), the embedding property of the film-like adhesive is sufficient and voids are not generated. On the other hand, in the structure shown in FIG. 9(c), the embedding property of the film-like adhesive is insufficient, and voids V are generated.

熱硬化性樹脂組成物の硬化物(Cステージ)の180℃における貯蔵弾性率は、接続信頼性の観点から、10MPa以上であることが好ましく、25MPa以上であることがより好ましく、50MPa以上又は100MPa以上であってもよい。なお、この貯蔵弾性率の上限値は、例えば、600MPaであり、500MPaであってもよい。熱硬化性樹脂組成物の硬化物の180℃における貯蔵弾性率は、フィルム状接着剤を175℃の温度条件で硬化させたものを試料とし、動的粘弾性装置を使用して測定することができる。 The storage elastic modulus at 180° C. of the cured product (C stage) of the thermosetting resin composition is preferably 10 MPa or higher, more preferably 25 MPa or higher, and 50 MPa or higher or 100 MPa, from the viewpoint of connection reliability. or more. In addition, the upper limit of this storage elastic modulus is, for example, 600 MPa, and may be 500 MPa. The storage elastic modulus at 180°C of the cured product of the thermosetting resin composition can be measured using a dynamic viscoelasticity device using a film adhesive cured at a temperature of 175°C as a sample. can.

<(a)熱硬化性樹脂>
(a1)成分は、分子内にエポキシ基を有するものであれば、特に制限なく用いることができる。(a1)成分としては、例えば、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、ビスフェノールS型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビスフェノールAノボラック型エポキシ樹脂、ビスフェノールFノボラック型エポキシ樹脂、ジシクロペンタジエン骨格含有エポキシ樹脂、スチルベン型エポキシ樹脂、トリアジン骨格含有エポキシ樹脂、フルオレン骨格含有エポキシ樹脂、トリフェノールフェノールメタン型エポキシ樹脂、ビフェニル型エポキシ樹脂、キシリレン型エポキシ樹脂、ビフェニルアラルキル型エポキシ樹脂、ナフタレン型エポキシ樹脂、多官能フェノール類、アントラセン等の多環芳香族類のジグリシジルエーテル化合物などが挙げられる。これらは、1種を単独で又は2種以上を組み合わせて用いてもよい。これらの中でも、(a1)成分は、耐熱性の観点から、クレゾールノボラック型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、又はビスフェノールA型エポキシ樹脂であってもよい。
<(a) thermosetting resin>
Component (a1) can be used without any particular limitation as long as it has an epoxy group in its molecule. Examples of the component (a1) include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A novolak type epoxy resin, bisphenol F novolak type epoxy resin. Epoxy resins, dicyclopentadiene skeleton-containing epoxy resins, stilbene-type epoxy resins, triazine skeleton-containing epoxy resins, fluorene skeleton-containing epoxy resins, triphenolphenolmethane-type epoxy resins, biphenyl-type epoxy resins, xylylene-type epoxy resins, biphenylaralkyl-type epoxy resins Resins, naphthalene-type epoxy resins, polyfunctional phenols, diglycidyl ether compounds of polycyclic aromatics such as anthracene, and the like. You may use these individually by 1 type or in combination of 2 or more types. Among these, the component (a1) may be a cresol novolac type epoxy resin, a bisphenol F type epoxy resin, or a bisphenol A type epoxy resin from the viewpoint of heat resistance.

(a1)成分のエポキシ当量は、90~300g/eq、110~290g/eq、又は130~280g/eqであってよい。(a1)成分のエポキシ当量がこのような範囲にあると、フィルム状接着剤のバルク強度を維持しつつ、流動性を確保することができる傾向にある。 The epoxy equivalent weight of component (a1) may be 90-300 g/eq, 110-290 g/eq, or 130-280 g/eq. When the epoxy equivalent of the component (a1) is in this range, it tends to be possible to secure fluidity while maintaining the bulk strength of the film-like adhesive.

(a1)成分の含有量は、(a)成分、(b)成分、及び(c)成分の総質量100質量部に対して、5~50質量部、10~40質量部、又は20~30質量部であってよい。(a1)成分の含有量が5質量部以上であると、フィルム状接着剤の埋込性がより良好となる傾向にある。(a1)成分の含有量が50質量部以下であると、ブリードの発生をより抑制できる傾向にある。 The content of component (a1) is 5 to 50 parts by mass, 10 to 40 parts by mass, or 20 to 30 parts by mass with respect to 100 parts by mass of the total mass of components (a), (b), and (c). It may be parts by mass. When the content of the component (a1) is 5 parts by mass or more, the embedding property of the film adhesive tends to be better. When the content of component (a1) is 50 parts by mass or less, the occurrence of bleeding tends to be more suppressed.

(a2)成分は、分子内にフェノール性水酸基を有するものであれば特に制限なく用いることができる。(a2)成分としては、例えば、フェノール、クレゾール、レゾルシン、カテコール、ビスフェノールA、ビスフェノールF、フェニルフェノール、アミノフェノール等のフェノール類及び/又はα-ナフトール、β-ナフトール、ジヒドロキシナフタレン等のナフトール類とホルムアルデヒド等のアルデヒド基を有する化合物とを酸性触媒下で縮合又は共縮合させて得られるノボラック型フェノール樹脂、アリル化ビスフェノールA、アリル化ビスフェノールF、アリル化ナフタレンジオール、フェノールノボラック、フェノール等のフェノール類及び/又はナフトール類とジメトキシパラキシレン又はビス(メトキシメチル)ビフェニルから合成されるフェノールアラルキル樹脂、ナフトールアラルキル樹脂などが挙げられる。これらは、1種を単独で又は2種以上を組み合わせて用いてもよい。これらの中でも、(a2)成分は、吸湿性及び耐熱性の観点から、フェノールアラルキル樹脂、ナフトールアラルキル樹脂、又はノボラック型フェノール樹脂であってもよい。 Component (a2) can be used without any particular limitation as long as it has a phenolic hydroxyl group in the molecule. Component (a2) includes, for example, phenols such as phenol, cresol, resorcinol, catechol, bisphenol A, bisphenol F, phenylphenol and aminophenol, and/or naphthols such as α-naphthol, β-naphthol and dihydroxynaphthalene. Phenols such as novolac-type phenolic resins, allylated bisphenol A, allylated bisphenol F, allylated naphthalenediol, phenol novolak, and phenol obtained by condensing or co-condensing a compound having an aldehyde group such as formaldehyde in the presence of an acidic catalyst and/or phenol aralkyl resins and naphthol aralkyl resins synthesized from naphthols and dimethoxyparaxylene or bis(methoxymethyl)biphenyl. You may use these individually by 1 type or in combination of 2 or more types. Among these, the component (a2) may be a phenol aralkyl resin, a naphthol aralkyl resin, or a novolak-type phenol resin from the viewpoint of hygroscopicity and heat resistance.

(a2)成分の水酸基当量は、80~250g/eq、90~200g/eq、又は100~180g/eqであってよい。(a2)成分の水酸基当量がこのような範囲にあると、フィルム状接着剤の流動性を保ちつつ、接着力をより高く維持することができる傾向にある。 The hydroxyl equivalent of component (a2) may be 80-250 g/eq, 90-200 g/eq, or 100-180 g/eq. When the hydroxyl equivalent of the component (a2) is in this range, it tends to be possible to maintain a higher adhesive strength while maintaining the fluidity of the film-like adhesive.

(a2)成分の軟化点は、50~140℃、55~120℃、又は60~100℃であってよい。 The softening point of component (a2) may be 50-140°C, 55-120°C, or 60-100°C.

(a2)成分の含有量は、(a)成分、(b)成分、及び(c)成分の総質量100質量部に対して、5~50質量部、10~40質量部、又は20~30質量部であってよい。(a2)成分の含有量が5質量部以上であると、より良好な硬化性が得られる傾向にある。(a2)成分の含有量が50質量部以下であると、フィルム状接着剤の埋込性がより良好になる傾向にある。 The content of component (a2) is 5 to 50 parts by mass, 10 to 40 parts by mass, or 20 to 30 parts by mass with respect to 100 parts by mass of the total mass of components (a), (b), and (c). It may be parts by mass. When the content of component (a2) is 5 parts by mass or more, better curability tends to be obtained. When the content of the component (a2) is 50 parts by mass or less, the embedding property of the film adhesive tends to be better.

(a1)成分のエポキシ当量と(a2)成分の水酸基当量との比((a1)成分のエポキシ当量/(a2)成分の水酸基当量)は、硬化性の観点から、0.30/0.70~0.70/0.30、0.35/0.65~0.65/0.35、0.40/0.60~0.60/0.40、又は0.45/0.55~0.55/0.45であってよい。当該当量比が0.30/0.70以上であると、より充分な硬化性が得られる傾向にある。当該当量比が0.70/0.30以下であると、粘度が高くなり過ぎることを防ぐことができ、より充分な流動性を得ることができる。 The ratio of the epoxy equivalent of component (a1) to the hydroxyl equivalent of component (a2) (epoxy equivalent of component (a1)/hydroxy equivalent of component (a2)) is 0.30/0.70 from the viewpoint of curability. ~0.70/0.30, 0.35/0.65~0.65/0.35, 0.40/0.60~0.60/0.40, or 0.45/0.55~ It may be 0.55/0.45. When the corresponding amount ratio is 0.30/0.70 or more, more sufficient curability tends to be obtained. When the corresponding amount ratio is 0.70/0.30 or less, it is possible to prevent the viscosity from becoming too high and obtain more sufficient fluidity.

<(b)高分子量成分>
(b)成分は、ガラス転移温度(Tg)が50℃以下であるものが好ましい。
<(b) High molecular weight component>
Component (b) preferably has a glass transition temperature (Tg) of 50° C. or lower.

(b)成分としては、例えば、アクリル樹脂、ポリエステル樹脂、ポリアミド樹脂、ポリイミド樹脂、シリコーン樹脂、ブタジエン樹脂、アクリロニトリル樹脂及びこれらの変性体等が挙げられる。 Component (b) includes, for example, acrylic resins, polyester resins, polyamide resins, polyimide resins, silicone resins, butadiene resins, acrylonitrile resins and modified products thereof.

(b)成分は、流動性の観点から、アクリル樹脂を含んでいてもよい。ここで、アクリル樹脂とは、(メタ)アクリル酸エステルに由来する構成単位を含むポリマーを意味する。アクリル樹脂は、構成単位として、エポキシ基、アルコール性又はフェノール性水酸基、カルボキシル基等の架橋性官能基を有する(メタ)アクリル酸エステルに由来する構成単位を含むポリマーであることが好ましい。また、アクリル樹脂は、(メタ)アクリル酸エステルとアクリルニトリルとの共重合体等のアクリルゴムであってもよい。 The component (b) may contain an acrylic resin from the viewpoint of fluidity. Here, acrylic resin means a polymer containing structural units derived from (meth)acrylic acid ester. The acrylic resin is preferably a polymer containing, as a structural unit, a structural unit derived from a (meth)acrylic acid ester having a crosslinkable functional group such as an epoxy group, an alcoholic or phenolic hydroxyl group, or a carboxyl group. The acrylic resin may also be acrylic rubber such as a copolymer of (meth)acrylic acid ester and acrylonitrile.

アクリル樹脂のガラス転移温度(Tg)は、-50~50℃又は-30~30℃であってよい。アクリル樹脂のTgが-50℃以上であると、接着剤組成物の柔軟性が高くなり過ぎることを防ぐことができる傾向にある。これにより、ウェハダイシング時にフィルム状接着剤を切断し易くなり、バリの発生を防ぐことが可能となる。アクリル樹脂のTgが50℃以下であると、接着剤組成物の柔軟性の低下を抑えることができる傾向にある。これにより、フィルム状接着剤をウェハに貼り付ける際に、ボイドを充分に埋め込み易くなる傾向にある。また、ウェハの密着性の低下によるダイシング時のチッピングを防ぐことが可能となる。ここで、ガラス転移温度(Tg)は、DSC(熱示差走査熱量計)(例えば、株式会社リガク製「Thermo Plus 2」)を用いて測定した値を意味する。 The glass transition temperature (Tg) of the acrylic resin may be -50 to 50°C or -30 to 30°C. When the Tg of the acrylic resin is −50° C. or higher, it tends to be possible to prevent the flexibility of the adhesive composition from becoming too high. This makes it easier to cut the film-like adhesive during wafer dicing, making it possible to prevent the occurrence of burrs. When the Tg of the acrylic resin is 50°C or less, it tends to be possible to suppress a decrease in the flexibility of the adhesive composition. This tends to make it easier to sufficiently fill voids when the film-like adhesive is attached to the wafer. Also, it is possible to prevent chipping during dicing due to deterioration in adhesion of the wafer. Here, the glass transition temperature (Tg) means a value measured using a DSC (differential scanning calorimeter) (for example, "Thermo Plus 2" manufactured by Rigaku Corporation).

アクリル樹脂の重量平均分子量(Mw)は、10万~300万又は50万~200万であってよい。アクリル樹脂のMwがこのような範囲にあると、フィルム形成性、フィルム状における強度、可撓性、タック性等を適切に制御することができると共に、リフロー性に優れ、埋込性を向上することができる。ここで、Mwは、ゲルパーミエーションクロマトグラフィー(GPC)で測定し、標準ポリスチレンによる検量線を用いて換算した値を意味する。 The acrylic resin may have a weight average molecular weight (Mw) of 100,000 to 3,000,000 or 500,000 to 2,000,000. When the Mw of the acrylic resin is in such a range, the film formability, the strength in the form of a film, the flexibility, the tackiness, etc. can be appropriately controlled, and the reflow property is excellent, and the embedding property is improved. be able to. Here, Mw means a value measured by gel permeation chromatography (GPC) and converted using a standard polystyrene calibration curve.

アクリル樹脂の市販品としては、例えば、SG-70L、SG-708-6、WS-023 EK30、SG-280 EK23、HTR-860P-3CSP、HTR-860P-3CSP-3DB(いずれもナガセケムテックス株式会社製)が挙げられる。 Examples of commercially available acrylic resins include SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, HTR-860P-3CSP, HTR-860P-3CSP-3DB (all available from Nagase ChemteX Corporation). manufactured by the company).

(b)成分の含有量は、(a)成分、(b)成分、及び(c)成分の総質量100質量部に対して、5~70質量部、10~50質量部、又は15~30質量部であってよい。(b)成分の含有量が5質量部以上であると、成形時の流動性の制御及び高温での取り扱い性をより一層良好にすることができる。(b)成分の含有量が70質量部以下であると、埋込性をより一層良好にすることができる。 The content of component (b) is 5 to 70 parts by mass, 10 to 50 parts by mass, or 15 to 30 parts by mass with respect to 100 parts by mass of the total mass of components (a), (b), and (c). It may be parts by mass. When the content of the component (b) is 5 parts by mass or more, the fluidity control during molding and the handleability at high temperatures can be further improved. If the content of the component (b) is 70 parts by mass or less, the embeddability can be further improved.

<(c)無機フィラー>
(c)成分としては、例えば、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウム、酸化アルミニウム、窒化アルミニウム、ホウ酸アルミウィスカ、窒化ホウ素、シリカ等が挙げられる。これらは、1種を単独で又は2種以上を組み合わせて用いてもよい。これらの中でも、(c)成分は、樹脂との相溶性の観点から、シリカであってもよい。
<(c) inorganic filler>
Component (c) includes, for example, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, and boron nitride. , silica and the like. You may use these individually by 1 type or in combination of 2 or more types. Among these, the component (c) may be silica from the viewpoint of compatibility with the resin.

(c)成分の平均粒径は、接着性の向上の観点から、0.005~1μm又は0.05~0.5μmであってよい。ここで、平均粒径は、BET比表面積から換算することによって求められる値を意味する。 The average particle diameter of component (c) may be 0.005 to 1 μm or 0.05 to 0.5 μm from the viewpoint of improving adhesiveness. Here, the average particle diameter means a value obtained by converting from the BET specific surface area.

(c)成分の含有量は、(a)成分、(b)成分、及び(c)成分の総質量100質量部に対して、5~50質量部、15~45質量部、又は25~40質量部であってよい。(c)成分の含有量が5質量部以上であると、フィルム状接着剤の流動性がより向上する傾向にある。(c)成分の含有量が50質量部以下であると、フィルム状接着剤のダイシング性がより良好となる傾向にある。 The content of component (c) is 5 to 50 parts by mass, 15 to 45 parts by mass, or 25 to 40 parts by mass with respect to 100 parts by mass of the total mass of components (a), (b), and (c). It may be parts by mass. When the content of component (c) is 5 parts by mass or more, the fluidity of the film adhesive tends to be further improved. When the content of component (c) is 50 parts by mass or less, the dicing property of the film adhesive tends to be better.

<(d)カップリング剤>
(d)成分は、シランカップリング剤であってよい。シランカップリング剤としては、例えば、γ-ウレイドプロピルトリエトキシシラン、γ-メルカプトプロピルトリメトキシシラン、3-フェニルアミノプロピルトリメトキシシラン、3-(2-アミノエチル)アミノプロピルトリメトキシシラン等が挙げられる。これらは、1種を単独で又は2種以上を組み合わせて用いてもよい。
<(d) Coupling agent>
(d) Component may be a silane coupling agent. Silane coupling agents include, for example, γ-ureidopropyltriethoxysilane, γ-mercaptopropyltrimethoxysilane, 3-phenylaminopropyltrimethoxysilane, 3-(2-aminoethyl)aminopropyltrimethoxysilane, and the like. be done. You may use these individually by 1 type or in combination of 2 or more types.

(d)成分の含有量は、(a)成分、(b)成分、及び(c)成分の総質量100質量部に対して、0.01~5質量部であってよい。 The content of component (d) may be 0.01 to 5 parts by mass with respect to 100 parts by mass of the total mass of components (a), (b) and (c).

<(e)硬化促進剤>
(e)成分は、特に限定されず、一般に使用されるものを用いることができる。(e)成分としては、例えば、イミダゾール類及びその誘導体、有機リン系化合物、第二級アミン類、第三級アミン類、第四級アンモニウム塩等が挙げられる。これらは、1種を単独で又は2種以上を組み合わせて用いてもよい。これらの中でも、反応性の観点から(e)成分はイミダゾール類及びその誘導体であってもよい。
<(e) Curing accelerator>
Component (e) is not particularly limited, and commonly used components can be used. Component (e) includes, for example, imidazoles and their derivatives, organophosphorus compounds, secondary amines, tertiary amines, quaternary ammonium salts and the like. You may use these individually by 1 type or in combination of 2 or more types. Among these, imidazoles and derivatives thereof may be used as component (e) from the viewpoint of reactivity.

イミダゾール類としては、例えば、2-メチルイミダゾール、1-ベンジル-2-メチルイミダゾール、1-シアノエチル-2-フェニルイミダゾール、1-シアノエチル-2-メチルイミダゾール等が挙げられる。これらは、1種を単独で又は2種以上を組み合わせて用いてもよい。 Examples of imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole and the like. You may use these individually by 1 type or in combination of 2 or more types.

(e)成分の含有量は、(a)成分、(b)成分、及び(c)成分の総質量100質量部に対して、0.01~1質量部であってよい。 The content of component (e) may be 0.01 to 1 part by mass per 100 parts by mass of the total mass of components (a), (b) and (c).

[ダイシングダイボンディング一体型テープ及びその製造方法]
図7(a)に示すダイシングダイボンディング一体型テープ8及びその製造方法について説明する。テープ8の製造方法は、溶剤を含有する接着剤組成物のワニスを基材フィルム(不図示)上に塗布する工程と、塗布されたワニスを50~150℃で加熱乾燥することによって接着層20Aを形成する工程とを含む。
[Dicing die bonding integrated tape and its manufacturing method]
The dicing/die bonding integrated tape 8 shown in FIG. 7(a) and its manufacturing method will be described. The method for producing the tape 8 includes the steps of applying a varnish of an adhesive composition containing a solvent onto a base film (not shown), and drying the applied varnish by heating at 50 to 150 ° C. to form an adhesive layer 20A. and forming.

接着剤組成物のワニスは、例えば、(a)~(c)成分、必要に応じて(d)成分及び(e)成分を、溶剤中で混合又は混練することによって調製することができる。混合又は混練は、通常の撹拌機、らいかい機、三本ロール、ボールミル等の分散機を用い、これらを適宜組み合わせて行うことができる。 The varnish of the adhesive composition can be prepared, for example, by mixing or kneading components (a) to (c) and, if necessary, components (d) and (e) in a solvent. Mixing or kneading can be carried out by using an ordinary dispersing machine such as a stirrer, a kneading machine, a triple roll, a ball mill, or the like, and by appropriately combining these.

ワニスを作製するための溶剤は、上記各成分を均一に溶解、混練又は分散できるものであれば制限はなく、従来公知のものを使用することができる。このような溶剤としては、例えば、アセトン、メチルエチルケトン、メチルイソブチルケトン、シクロヘキサノン等のケトン系溶媒、ジメチルホルムアミド、ジメチルアセトアミド、Nメチルピロリドン、トルエン、キシレン等が挙げられる。乾燥速度が速く、価格が安い点でメチルエチルケトン、シクロヘキサノン等を使用することが好ましい。 The solvent for preparing the varnish is not limited as long as it can uniformly dissolve, knead or disperse the above components, and conventionally known solvents can be used. Examples of such solvents include ketone-based solvents such as acetone, methyl ethyl ketone, methyl isobutyl ketone and cyclohexanone, dimethylformamide, dimethylacetamide, N-methylpyrrolidone, toluene and xylene. It is preferable to use methyl ethyl ketone, cyclohexanone, etc., because of their high drying speed and low price.

基材フィルムとしては、特に制限はなく、例えば、ポリエステルフィルム、ポリプロピレンフィルム(OPPフィルム等)、ポリエチレンテレフタレートフィルム、ポリイミドフィルム、ポリエーテルイミドフィルム、ポリエーテルナフタレートフィルム、メチルペンテンフィルム等が挙げられる。 The base film is not particularly limited, and examples thereof include polyester film, polypropylene film (OPP film, etc.), polyethylene terephthalate film, polyimide film, polyetherimide film, polyether naphthalate film, methylpentene film and the like.

基材フィルムにワニスを塗布する方法としては、公知の方法を用いることができ、例えば、ナイフコート法、ロールコート法、スプレーコート法、グラビアコート法、バーコート法、カーテンコート法等が挙げられる。加熱乾燥の条件は、使用した溶剤が充分に揮散する条件であれば特に制限はないが、例えば、50~150℃で、1~30分間加熱して行うことができる。加熱乾燥は、50~150℃の範囲内の温度で段階的に昇温させて行ってもよい。ワニスに含まれる溶剤を加熱乾燥によって揮発させることによって基材フィルムと、接着層20Aとの積層フィルムを得ることができる。 As a method for applying the varnish to the substrate film, a known method can be used, and examples thereof include a knife coating method, a roll coating method, a spray coating method, a gravure coating method, a bar coating method, a curtain coating method, and the like. . The conditions for drying by heating are not particularly limited as long as the solvent used is sufficiently volatilized. Heat drying may be carried out by stepwise raising the temperature within the range of 50 to 150°C. By volatilizing the solvent contained in the varnish by heating and drying, a laminated film of the substrate film and the adhesive layer 20A can be obtained.

上記のようにして得た積層フィルムと、ダイシングテープ(基材層1と粘着層2の積層体)とを貼り合わせることによってテープ8を得ることができる。基材層1としては、例えば、ポリテトラフルオロエチレンフィルム、ポリエチレンテレフタレートフィルム、ポリエチレンフィルム、ポリプロピレンフィルム、ポリメチルペンテンフィルム、ポリイミドフィルム等のプラスチックフィルム等が挙げられる。また、基材層1は、必要に応じて、プライマー塗布、UV処理、コロナ放電処理、研磨処理、エッチング処理等の表面処理が行われていてもよい。粘着層2は、UV硬化型であってもよいし、感圧型であってもよい。テープ8は、粘着層2を覆う保護フィルム(不図示)を更に備えたものであってもよい。 The tape 8 can be obtained by laminating the laminate film obtained as described above and a dicing tape (laminated body of the base layer 1 and the adhesive layer 2). Examples of the substrate layer 1 include plastic films such as polytetrafluoroethylene film, polyethylene terephthalate film, polyethylene film, polypropylene film, polymethylpentene film, and polyimide film. Further, the substrate layer 1 may be subjected to surface treatment such as primer coating, UV treatment, corona discharge treatment, polishing treatment, etching treatment, etc., as necessary. The adhesive layer 2 may be UV curable or pressure sensitive. The tape 8 may further include a protective film (not shown) covering the adhesive layer 2 .

以上、本開示の実施形態について詳細に説明したが、本発明は上記実施形態に限定されるものではない。例えば、上記実施形態においては、二つの半導体素子Wa,Wbが積層された態様のパッケージを例示したが、第2の半導体素子Wbの上方に第3の半導体素子が積層されていてもよいし、その上方に更に一つ又は複数の半導体素子が積層されていてもよい。 Although the embodiments of the present disclosure have been described above in detail, the present invention is not limited to the above embodiments. For example, in the above embodiment, the package in which the two semiconductor elements Wa and Wb are stacked is illustrated, but a third semiconductor element may be stacked above the second semiconductor element Wb, One or more semiconductor elements may be stacked thereon.

以下、実施例を挙げて本開示についてより具体的に説明する。ただし、本発明は以下の実施例に限定されるものではない。 EXAMPLES Hereinafter, the present disclosure will be described more specifically with reference to Examples. However, the present invention is not limited to the following examples.

参考例1,実施例及び比較例1~3
表1及び表2に示す成分を含むワニス(計種類)を次のようにして調製した。すなわち、熱硬化性樹脂としてのエポキシ樹脂及びフェノール樹脂と、無機フィラーとを含む組成物にシクロヘキサノンを加えて撹拌した。これに、高分子量成分としてのアクリルゴムを加えて撹拌した後、カップリング剤と硬化促進剤とを更に加え、各成分が十分に均一になるまで撹拌することによってワニスを得た。
( Reference Example 1, Examples 2 to 5 and Comparative Examples 1 to 3 )
Varnishes ( 8 types in total) containing the components shown in Tables 1 and 2 were prepared as follows. Specifically, cyclohexanone was added to a composition containing an epoxy resin and a phenol resin as thermosetting resins and an inorganic filler, and the mixture was stirred. After adding acrylic rubber as a high-molecular-weight component to this and stirring, a coupling agent and a curing accelerator were further added, and the components were stirred until they were sufficiently uniform to obtain a varnish.

表1及び表2に記載の成分は以下のとおりである。
(エポキシ樹脂)
・YDF-8170C(商品名):東都化成(株)製、ビスフェノールF型エポキシ樹脂、エポキシ当量159、常温で液体、軟化点10~30℃、分子量100~1000(低分子量成分)
・YDCN-700-10(商品名):東都化成(株)製、クレゾールノボラック型エポキシ樹脂、エポキシ当量210、軟化点75~85℃)、分子量1000超
(フェノール樹脂)
・ミレックスXLC-LL(商品名):三井化学(株)製、フェノール樹脂、水酸基当量175、軟化点77℃、分子量1000超
(アクリルゴム)
・HTR-860P-3CSP:ナガセケムテックス(株)製、重量平均分子量80万(高分子量成分)
(無機フィラー)
・SC2050-HLG(商品名):アドマテックス(株)製、シリカフィラー分散液、平均粒径0.50μm
(硬化促進剤)
・キュアゾール2PZ-CN(商品名):四国化成工業(株)製、1-シアノエチル-2-フェニルイミダゾール
The components listed in Tables 1 and 2 are as follows.
(Epoxy resin)
・ YDF-8170C (trade name): manufactured by Toto Kasei Co., Ltd., bisphenol F type epoxy resin, epoxy equivalent 159, liquid at normal temperature, softening point 10 to 30 ° C., molecular weight 100 to 1000 (low molecular weight component)
・ YDCN-700-10 (trade name): manufactured by Tohto Kasei Co., Ltd., cresol novolac type epoxy resin, epoxy equivalent 210, softening point 75 to 85 ° C.), molecular weight over 1000 (phenolic resin)
・Mirex XLC-LL (trade name): Mitsui Chemicals, Inc., phenolic resin, hydroxyl equivalent 175, softening point 77°C, molecular weight over 1000 (acrylic rubber)
・ HTR-860P-3CSP: manufactured by Nagase ChemteX Co., Ltd., weight average molecular weight 800,000 (high molecular weight component)
(Inorganic filler)
・ SC2050-HLG (trade name): manufactured by Admatechs Co., Ltd., silica filler dispersion, average particle size 0.50 μm
(Curing accelerator)
・Curesol 2PZ-CN (trade name): 1-cyanoethyl-2-phenylimidazole manufactured by Shikoku Chemical Industry Co., Ltd.

上記成分を含むワニスを100メッシュのフィルターでろ過し、真空脱泡した。真空脱泡後のワニスを、離型処理を施したポリエチレンテレフタレート(PET)フィルム(厚さ38μm)上に塗布した。塗布したワニスを、90℃で5分間、続いて140℃で5分間の二段階で加熱乾燥した。こうして、基材フィルムとしてのPETフィルム上に、Bステージ状態にあるフィルム状接着剤(厚さ60μm)を備えた接着シートを得た。 The varnish containing the above components was filtered through a 100-mesh filter and vacuum defoamed. The varnish after vacuum defoaming was applied onto a release-treated polyethylene terephthalate (PET) film (thickness: 38 μm). The applied varnish was dried by heating in two steps, 90° C. for 5 minutes and then 140° C. for 5 minutes. In this way, an adhesive sheet comprising a PET film as a base film and a B-stage film-like adhesive (thickness: 60 μm) was obtained.

(フィルム状接着剤の溶融粘度の測定)
フィルム状接着剤の100℃及び120℃における溶融粘度は次の方法で測定した。すなわち、厚さ60μmのフィルム状接着剤を五枚積層することによって厚さを300μmとし、これを10mm×10mmのサイズに打ち抜くことによって測定用の試料を得た。動的粘弾性装置ARES(TA Instruments社製)に直径8mmの円形アルミプレート治具をセットし、更にここに上記試料をセットした。その後、35℃で5%の歪みを与えながら5℃/分の昇温速度で130℃まで昇温させながら測定し、100℃及び120℃のときの溶融粘度の値を記録した。表1及び表2に結果を示す。
(Measurement of melt viscosity of film adhesive)
The melt viscosities of film adhesives at 100°C and 120°C were measured by the following method. That is, five sheets of film-like adhesive with a thickness of 60 μm were laminated to obtain a thickness of 300 μm, which was then punched into a size of 10 mm×10 mm to obtain a sample for measurement. A circular aluminum plate jig with a diameter of 8 mm was set in a dynamic viscoelasticity device ARES (manufactured by TA Instruments), and the sample was further set thereon. After that, measurements were taken while the temperature was raised to 130°C at a heating rate of 5°C/min while applying a strain of 5% at 35°C, and the melt viscosity values at 100°C and 120°C were recorded. Tables 1 and 2 show the results.

(フィルム状接着剤の硬化物の弾性率の測定)
フィルム状接着剤の硬化物(175℃の温度条件で硬化させたもの)の180℃における弾性率を測定した。測定には動的粘弾性装置(製品名:Rheogel-E4000、株式会社ユービーエム製)を使用し、試料に対して引張り荷重をかけて、周波数10Hz、3℃/分の昇温速度で300℃まで昇温させ、180℃における弾性率を測定した。表1及び表2に結果を示す。
(Measurement of Elastic Modulus of Cured Film Adhesive)
The elastic modulus at 180° C. of a cured film adhesive (cured under a temperature condition of 175° C.) was measured. For the measurement, a dynamic viscoelasticity device (product name: Rheogel-E4000, manufactured by UBM Co., Ltd.) was used, a tensile load was applied to the sample, and the temperature was increased to 300 ° C. at a frequency of 10 Hz and a heating rate of 3 ° C./min. and measured the elastic modulus at 180°C. Tables 1 and 2 show the results.

Figure 0007136200000001
Figure 0007136200000001

Figure 0007136200000002
Figure 0007136200000002

<フィルム状接着剤の評価>
フィルム状接着剤について、以下の項目について評価を行った。
<Evaluation of Film Adhesive>
The film adhesive was evaluated on the following items.

[埋込性]
フィルム状接着剤の埋込性を次の方法により評価した。
(第1の半導体素子とフィルム状接着剤とからなる積層体の作製)
半導体ウェハ(直径:8インチ、厚さ:50μm)にダイシングダイボンディング一体型フィルムHR-9004-10(日立化成(株)製、接着層の厚さ10μm、粘着層の厚さ110μm)を貼り付けた。これをダイシングすることによって第1の半導体素子(コントローラチップ、サイズ:3.0mm×3.0mm)とフィルム状接着剤とからなる第1の積層体を得た。
(第2の半導体素子とフィルム状接着剤とからなる積層体の作製)
参考例、実施例及び比較例に係る各フィルム状接着剤(厚さ120μm)とダイシング用粘着フィルムとからなるダイシングダイボンディング一体型フィルムを作製した。これを半導体ウェハ(直径:8インチ、厚さ:30μm)に貼り付けた。これをダイシングすることによって第2の半導体素子(サイズ:7.5mm×7.5mm)とフィルム状接着剤とからなる第2の積層体を得た。
(第1及び第2の半導体素子の接着)
第1及び第2の半導体素子を圧着するための基板(表面の凹凸:最大6μm)を準備した。この基板にフィルム状接着剤を介して第1の半導体素子を、120℃、0.20MPa、2秒間の条件で圧着した後、120℃で2時間にわたって加熱することによってフィルム状接着剤を半硬化させた。
次に、第1の半導体素子を覆うように、評価対象のフィルム状接着剤を介して第2の半導体素子を、120℃、0.20MPa、2秒間の条件で圧着した。この際、先に圧着された第1の半導体素子と第2の半導体素子の中心位置が平面視で一致するように位置合わせをした。
上記のようにして得た構造体を加圧オーブンに投入し、35℃から3℃/分の昇温速度で140℃まで昇温させ、140℃で30分加熱した。加熱処理後の構造体を超音波映像装置SAT((株)日立パワーソリューションズ製、品番FS200II、プローブ:25MHz)にて分析することによって、埋込性を確認した。以下の基準で評価を行った。表3及び表4に結果を示す。
A:所定の断面におけるボイドの面積割合が5%未満。
B:所定の断面におけるボイドの面積割合が5%以上。
[Embedability]
The embedding property of the film adhesive was evaluated by the following method.
(Preparation of Laminate Consisting of First Semiconductor Element and Film Adhesive)
A dicing die bonding integrated film HR-9004-10 (manufactured by Hitachi Chemical Co., Ltd., adhesive layer thickness 10 μm, adhesive layer thickness 110 μm) is attached to a semiconductor wafer (diameter: 8 inches, thickness: 50 μm). rice field. By dicing this, a first laminate comprising a first semiconductor element (controller chip, size: 3.0 mm×3.0 mm) and a film adhesive was obtained.
(Preparation of Laminate Consisting of Second Semiconductor Element and Film Adhesive)
A dicing-die-bonding integrated film was prepared from each of the film-like adhesives (thickness: 120 μm) according to Reference Examples, Examples, and Comparative Examples, and an adhesive film for dicing. This was attached to a semiconductor wafer (diameter: 8 inches, thickness: 30 μm). By dicing this, a second laminate comprising a second semiconductor element (size: 7.5 mm×7.5 mm) and a film adhesive was obtained.
(Adhesion of first and second semiconductor elements)
A substrate (surface unevenness: maximum 6 μm) was prepared for pressure bonding of the first and second semiconductor elements. After pressing the first semiconductor element to this substrate via the film adhesive under conditions of 120° C., 0.20 MPa, and 2 seconds, the film adhesive is semi-cured by heating at 120° C. for 2 hours. let me
Next, the second semiconductor element was crimped under the conditions of 120° C., 0.20 MPa, and 2 seconds via the film-like adhesive to be evaluated so as to cover the first semiconductor element. At this time, alignment was performed so that the center positions of the first semiconductor element and the second semiconductor element, which had been pressure-bonded earlier, were aligned in a plan view.
The structure obtained as described above was placed in a pressure oven, heated from 35° C. to 140° C. at a rate of 3° C./min, and heated at 140° C. for 30 minutes. The embeddability was confirmed by analyzing the heat-treated structure with an ultrasonic imaging device SAT (manufactured by Hitachi Power Solutions Co., Ltd., product number FS200II, probe: 25 MHz). Evaluation was performed according to the following criteria. Tables 3 and 4 show the results.
A: The area ratio of voids in a given cross section is less than 5%.
B: The area ratio of voids in a predetermined cross section is 5% or more.

[パッケージ汚染及びヒケ発生の有無]
埋込性の評価に供した構造体の上部及び側面を顕微鏡で観察することによって、汚染の有無及びヒケ発生の有無を確認した。ヒケが発生した試料については、ヒケの深さ(起点:第2の半導体素子の端部)を測定した。表3及び表4に結果を示す。
[Presence or absence of package contamination and sink marks]
The presence or absence of contamination and the occurrence of sink marks were confirmed by observing the top and side surfaces of the structure subjected to embedding evaluation under a microscope. For the sample with sink marks, the depth of the sink marks (starting point: edge of the second semiconductor element) was measured. Tables 3 and 4 show the results.

[接着強度の測定]
フィルム状接着剤の硬化物のダイシェア強度(接着強度)を次の方法により測定した。まず、参考例、実施例及び比較例に係る各フィルム状接着剤(厚さ120μm)を半導体ウェハ(厚さ400μm)に70℃で貼り付けた。これをダイシングすることによって半導体素子(サイズ:5mm×5mm)とフィルム状接着剤とからなる積層体を得た。他方、表面にソルダーレジストインキ(AUS308)を塗布した基板を準備した。この表面にフィルム状接着剤を介して半導体素子を、120℃、0.1MPa、5秒間の条件で圧着した。その後、これを110℃で1時間にわたって加熱処理した後、更に、170℃で3時間にわたって加熱することによって、フィルム状接着剤を硬化させることによって測定用の試料を得た。この試料を85℃、60RH%条件の下、168時間放置した。その後、試料を25℃、50%RH条件下で30分間放置してから、250℃でダイシェア強度を測定し、これを接着強度とした。ダイシェア強度の測定にはDage社製の万能ボンドテスタ シリーズ4000を使用した。表3及び表4に結果を示す。
[Measurement of adhesive strength]
The die shear strength (adhesive strength) of the cured film adhesive was measured by the following method. First, each film adhesive (120 μm thick) according to Reference Example, Example and Comparative Example was attached to a semiconductor wafer (400 μm thick) at 70°C. By dicing this, a laminate consisting of a semiconductor element (size: 5 mm×5 mm) and a film-like adhesive was obtained. On the other hand, a substrate having a surface coated with a solder resist ink (AUS308) was prepared. A semiconductor element was press-bonded to this surface via a film-like adhesive under conditions of 120° C., 0.1 MPa, and 5 seconds. After that, this was heat-treated at 110° C. for 1 hour, and further heated at 170° C. for 3 hours to cure the film-like adhesive, thereby obtaining a sample for measurement. This sample was left for 168 hours under conditions of 85° C. and 60 RH%. After that, the sample was allowed to stand under conditions of 25° C. and 50% RH for 30 minutes, and then the die shear strength was measured at 250° C., which was defined as the adhesive strength. A Universal Bond Tester Series 4000 manufactured by Dage was used to measure the die shear strength. Tables 3 and 4 show the results.

[耐リフロー性の評価]
フィルム状接着剤の耐リフロー性を次の方法により評価した。まず、埋込性の評価に供した構造体と同様の構造体を作製した。構造体の第2の半導体素子をモールド用封止材(日立化成(株)製、商品名「CEL-9750ZHF10)で封止することによって、評価用のパッケージを得た。なお、樹脂封止の条件は175℃/6.7MPa/90秒とし、硬化の条件は175℃、5時間とした。
上記パッケージを24個準備し、これらをJEDECで定めた環境下(レベル3、30℃、60RH%、192時間)に曝して吸湿させた。続いて、IRリフロー炉(260℃、最高温度265℃)に吸湿後のパッケージを3回通過させた。以下の基準で評価を行った。表3及び表4に結果を示す。
A:パッケージの破損、厚みの変化、フィルム状接着剤と半導体素子との界面での剥離等が24個のパッケージのうち1個も観察されなかった。
B:パッケージの破損、厚みの変化、フィルム状接着剤と半導体素子との界面での剥離等が24個のパッケージのうち少なくとも1個観察された。
[Evaluation of reflow resistance]
The reflow resistance of the film adhesive was evaluated by the following method. First, a structure similar to the structure used for embedding evaluation was produced. A package for evaluation was obtained by encapsulating the second semiconductor element of the structure with a molding encapsulant (manufactured by Hitachi Chemical Co., Ltd., trade name “CEL-9750ZHF10”). The conditions were 175° C./6.7 MPa/90 seconds, and the curing conditions were 175° C. and 5 hours.
Twenty-four of the above packages were prepared and exposed to the environment specified by JEDEC (level 3, 30°C, 60 RH%, 192 hours) to absorb moisture. Subsequently, the moisture-absorbed package was passed through an IR reflow oven (260° C., maximum temperature 265° C.) three times. Evaluation was performed according to the following criteria. Tables 3 and 4 show the results.
A: None of the 24 packages showed damage, change in thickness, peeling at the interface between the film-like adhesive and the semiconductor element, and the like.
B: Breakage of the package, change in thickness, peeling at the interface between the film-like adhesive and the semiconductor element, etc. were observed in at least one of the 24 packages.

Figure 0007136200000003
Figure 0007136200000003

Figure 0007136200000004
Figure 0007136200000004

表3及び表4に示した結果から明らかなように、参考例1及び実施例2~5のフィルム状接着剤は、比較例1~3のフィルム状接着剤と比較して、加圧オーブンによる処理後において、埋込性に優れるとともにパッケージ汚染及びヒケの発生を抑えることができることが確認された。
As is clear from the results shown in Tables 3 and 4, the film-like adhesives of Reference Example 1 and Examples 2 to 5 were compared to the film-like adhesives of Comparative Examples 1 to 3, and the pressure oven After the treatment, it was confirmed that the embedding property was excellent and the occurrence of package contamination and sink marks could be suppressed.

本開示によれば、コントローラチップ等の半導体素子及びワイヤの少なくとも一方を埋め込み可能な流動性を有しつつ、埋め込み時の周辺回路の汚染、その後の熱工程における樹脂の過剰な流動に起因する問題を十分に抑制できる熱硬化性樹脂組成物並びにこれを用いて製造される半導体装置及びその製造方法が提供される。 According to the present disclosure, while having the fluidity to embed at least one of a semiconductor element such as a controller chip and a wire, problems caused by contamination of the peripheral circuit during embedding and excessive flow of resin in the subsequent thermal process Provided are a thermosetting resin composition capable of sufficiently suppressing , a semiconductor device manufactured using the same, and a method for manufacturing the same.

2…粘着層、8…ダイシングダイボンディング一体型テープ、10…基板、11…第1のワイヤ、12…第2のワイヤ、10a,10b…回路パターン、20…第1の封止層(フィルム状接着剤の硬化物)、20A…接着層、20P…フィルム状接着剤、40…第2の封止層、100…半導体装置、Wa…第1の半導体素子、Wb…第2の半導体素子 2... Adhesive layer, 8... Dicing die bonding integrated tape, 10... Substrate, 11... First wire, 12... Second wire, 10a, 10b... Circuit pattern, 20... First sealing layer (film-like Cured product of adhesive), 20A...adhesive layer, 20P...film adhesive, 40...second sealing layer, 100...semiconductor device, Wa...first semiconductor element, Wb...second semiconductor element

Claims (10)

基板と、
前記基板上に配置された第1の半導体素子と、
前記基板における前記第1の半導体素子が配置された領域を覆うように配置されており、前記第1の半導体素子を封止している第1の封止層と、
前記第1の封止層における前記基板の側と反対側の表面を覆うように配置されており、前記第1の半導体素子よりも大きい面積を有する第2の半導体素子と、
を備え、
前記第1の封止層が熱硬化性樹脂組成物の硬化物からなり、前記熱硬化性樹脂組成物の120℃における溶融粘度が5000~11500Pa・sである、半導体装置。
a substrate;
a first semiconductor element disposed on the substrate;
a first encapsulation layer arranged to cover a region of the substrate where the first semiconductor element is arranged and encapsulating the first semiconductor element;
a second semiconductor element arranged to cover the surface of the first sealing layer opposite to the substrate side and having an area larger than that of the first semiconductor element;
with
The semiconductor device, wherein the first sealing layer is made of a cured thermosetting resin composition, and the thermosetting resin composition has a melt viscosity of 5000 to 11500 Pa·s at 120°C.
前記熱硬化性樹脂組成物は、分子量10~1000の低分子量成分と、分子量10万~100万の高分子量成分とを含み、
前記低分子量成分の含有量M1が前記熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して23~35質量部であり、
前記高分子量成分の含有量M2が前記熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して25~45質量部である、請求項1に記載の半導体装置。
The thermosetting resin composition contains a low molecular weight component with a molecular weight of 10 to 1,000 and a high molecular weight component with a molecular weight of 100,000 to 1,000,000,
The content M1 of the low molecular weight component is 23 to 35 parts by mass with respect to 100 parts by mass of the resin component contained in the thermosetting resin composition,
2. The semiconductor device according to claim 1, wherein the content M2 of said high molecular weight component is 25 to 45 parts by mass with respect to 100 parts by mass of the resin component contained in said thermosetting resin composition.
前記熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して前記低分子量成分と前記高分子量成分の合計量が54~76質量部である、請求項2に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the total amount of said low molecular weight component and said high molecular weight component is 54 to 76 parts by mass with respect to 100 parts by mass of the resin component contained in said thermosetting resin composition. 前記基板の表面に形成された回路パターンと、
前記第1の半導体素子と前記回路パターンとを電気的に接続する第1のワイヤと、
を更に備える、請求項1~3のいずれか一項に記載の半導体装置。
a circuit pattern formed on the surface of the substrate;
a first wire electrically connecting the first semiconductor element and the circuit pattern;
4. The semiconductor device according to claim 1, further comprising:
前記第2の半導体素子と前記回路パターンとを電気的に接続する第2のワイヤと、
前記第2の半導体素子及び前記第2のワイヤを封止している第2の封止層と、
を更に備える、請求項4に記載の半導体装置。
a second wire electrically connecting the second semiconductor element and the circuit pattern;
a second encapsulation layer encapsulating the second semiconductor element and the second wire;
5. The semiconductor device of claim 4, further comprising:
前記第2の半導体素子の上に積層された第3の半導体素子を更に備える、請求項1~5のいずれか一項に記載の半導体装置。 6. The semiconductor device according to claim 1, further comprising a third semiconductor element laminated on said second semiconductor element. 半導体装置の製造プロセスにおいて使用される熱硬化性樹脂組成物であって、
前記製造プロセスが、前記熱硬化性樹脂組成物を加熱する硬化処理を経て、ワイヤの少なくとも一部及び半導体素子の少なくとも一方が硬化処理後の前記熱硬化性樹脂組成物に埋め込まれた状態とする工程を含み、
前記熱硬化性樹脂組成物の120℃における溶融粘度が5000~11500Pa・sである、熱硬化性樹脂組成物。
A thermosetting resin composition used in the manufacturing process of a semiconductor device,
In the manufacturing process, through a curing treatment of heating the thermosetting resin composition, at least a part of the wire and at least one of the semiconductor elements are embedded in the thermosetting resin composition after the curing treatment. including the process,
A thermosetting resin composition, wherein the thermosetting resin composition has a melt viscosity at 120° C. of 5,000 to 11,500 Pa·s.
分子量10~1000の低分子量成分と、
分子量10万~100万の高分子量成分と、
を含み、
前記低分子量成分の含有量M1が前記熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して23~35質量部であり、
前記高分子量成分の含有量M2が前記熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して25~45質量部である、請求項7に記載の熱硬化性樹脂組成物。
a low molecular weight component having a molecular weight of 10 to 1000;
a high molecular weight component having a molecular weight of 100,000 to 1,000,000;
including
The content M1 of the low molecular weight component is 23 to 35 parts by mass with respect to 100 parts by mass of the resin component contained in the thermosetting resin composition,
8. The thermosetting resin composition according to claim 7, wherein the content M2 of said high molecular weight component is 25 to 45 parts by mass with respect to 100 parts by mass of the resin component contained in said thermosetting resin composition.
当該熱硬化性樹脂組成物に含まれる樹脂成分の質量100質量部に対して前記低分子量成分と前記高分子量成分の合計量が54~76質量部である、請求項8に記載の熱硬化性樹脂組成物。 The thermosetting according to claim 8, wherein the total amount of the low molecular weight component and the high molecular weight component is 54 to 76 parts by mass with respect to 100 parts by mass of the resin component contained in the thermosetting resin composition. Resin composition. 粘着層と、
請求項7~9のいずれか一項に記載の熱硬化性樹脂組成物からなる接着層と、
を備える、ダイシングダイボンディング一体型テープ。
an adhesive layer;
An adhesive layer made of the thermosetting resin composition according to any one of claims 7 to 9,
A dicing die bonding integrated tape.
JP2020518855A 2018-05-15 2018-05-15 Semiconductor device, thermosetting resin composition and dicing die bonding integrated tape used for its manufacture Active JP7136200B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/018765 WO2019220540A1 (en) 2018-05-15 2018-05-15 Semiconductor device, thermosetting resin composition used for production thereof, and dicing die bonding integrated tape

Publications (2)

Publication Number Publication Date
JPWO2019220540A1 JPWO2019220540A1 (en) 2021-07-01
JP7136200B2 true JP7136200B2 (en) 2022-09-13

Family

ID=68539657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020518855A Active JP7136200B2 (en) 2018-05-15 2018-05-15 Semiconductor device, thermosetting resin composition and dicing die bonding integrated tape used for its manufacture

Country Status (6)

Country Link
JP (1) JP7136200B2 (en)
KR (1) KR102482629B1 (en)
CN (1) CN112204730A (en)
SG (1) SG11202011196SA (en)
TW (1) TWI799582B (en)
WO (1) WO2019220540A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022115581A (en) * 2021-01-28 2022-08-09 昭和電工マテリアルズ株式会社 Semiconductor device and manufacturing method thereof, thermosetting resin composition, adhesive film and dicing/die bonding integrated film
JP2022182532A (en) * 2021-05-28 2022-12-08 キオクシア株式会社 Semiconductor device and manufacturing method for the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010182816A (en) 2009-02-04 2010-08-19 Nitto Denko Corp Thermoset die bond film
JP2012191027A (en) 2011-03-11 2012-10-04 Sekisui Chem Co Ltd Semiconductor chip with adhesive layer, and method for manufacturing semiconductor device
JP2018014501A (en) 2017-08-07 2018-01-25 日立化成株式会社 Film-like adhesive, and dicing and die-bonding integrated type adhesive sheet

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5236134B2 (en) 2001-01-26 2013-07-17 日立化成株式会社 Adhesive composition, adhesive member, semiconductor mounting support member, semiconductor device, etc.
JP2005103180A (en) 2003-10-02 2005-04-21 Matsushita Electric Ind Co Ltd Washing machine
US7560821B2 (en) * 2005-03-24 2009-07-14 Sumitomo Bakelite Company, Ltd Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same
JP5524465B2 (en) 2007-10-24 2014-06-18 日立化成株式会社 Adhesive sheet, semiconductor device using the same, and manufacturing method thereof
JP2010118554A (en) * 2008-11-13 2010-05-27 Nec Electronics Corp Semiconductor device and method of manufacturing the same
WO2012067158A1 (en) * 2010-11-18 2012-05-24 日立化成工業株式会社 Film-like resin composition for sealing and filling semiconductor, method for manufacturing semiconductor device, and semiconductor device
JPWO2013133275A1 (en) * 2012-03-08 2015-07-30 日立化成株式会社 Adhesive sheet and method for manufacturing semiconductor device
JP2015120836A (en) * 2013-12-24 2015-07-02 日東電工株式会社 Adhesive film, dicing/die-bonding film, manufacturing method of semiconductor device and semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010182816A (en) 2009-02-04 2010-08-19 Nitto Denko Corp Thermoset die bond film
JP2012191027A (en) 2011-03-11 2012-10-04 Sekisui Chem Co Ltd Semiconductor chip with adhesive layer, and method for manufacturing semiconductor device
JP2018014501A (en) 2017-08-07 2018-01-25 日立化成株式会社 Film-like adhesive, and dicing and die-bonding integrated type adhesive sheet

Also Published As

Publication number Publication date
CN112204730A (en) 2021-01-08
KR20210008341A (en) 2021-01-21
WO2019220540A1 (en) 2019-11-21
SG11202011196SA (en) 2020-12-30
JPWO2019220540A1 (en) 2021-07-01
TW202010788A (en) 2020-03-16
KR102482629B9 (en) 2024-03-25
TWI799582B (en) 2023-04-21
KR102482629B1 (en) 2022-12-29

Similar Documents

Publication Publication Date Title
JP7298613B2 (en) Semiconductor device manufacturing method, thermosetting resin composition, and dicing/die bonding integrated film
JP2023017948A (en) Adhesive composition, film-like adhesive, adhesive sheet, and method for manufacturing semiconductor device
TWI791751B (en) Semiconductor device manufacturing method and adhesive film
CN113544229A (en) Adhesive composition, film-like adhesive, adhesive sheet, and method for manufacturing semiconductor device
JP7136200B2 (en) Semiconductor device, thermosetting resin composition and dicing die bonding integrated tape used for its manufacture
JP7322897B2 (en) Adhesive film, dicing/die bonding integrated film, and method for manufacturing semiconductor package
TWI829727B (en) Adhesive composition, film-like adhesive, adhesive sheet, and method for manufacturing semiconductor device
WO2022163465A1 (en) Semiconductor device, method for producing same, thermosetting resin composition, bonding film and integrated dicing/die bonding film
JP7028264B2 (en) Film-shaped adhesive and its manufacturing method, and semiconductor device and its manufacturing method
TWI827779B (en) Chip-bonding integrated film and method for manufacturing semiconductor device
JP7115537B2 (en) Semiconductor device manufacturing method and film adhesive
JP7283399B2 (en) Thermosetting resin composition, film adhesive, adhesive sheet, and method for manufacturing semiconductor device
WO2023152837A1 (en) Film-form adhesive, dicing and die-bonding two-in-one film, semiconductor device, and method for manufacturing same
WO2023157846A1 (en) Film-like adhesive and method for producing same, integrated dicing/die bonding film, and semiconductor device and method for producing same
WO2023181397A1 (en) Adhesive film for semiconductor, dicing die-bonding film, and method for manufacturing semiconductor device
TW202242057A (en) Film-like adhesive, integrated dicing/die bonding film, semiconductor device and method for producing same
TW202237786A (en) Adhesive agent composition, film-form adhesive agent, dicing/die-bonding integrated film, semiconductor device, and method for manufacturing same
TW202414550A (en) Semiconductor device manufacturing method, adhesive layer and die-cut die-bonding integrated film
JP2023142901A (en) Adhesive film for semiconductor, integration-type film for dicing and die bonding, and method for manufacturing semiconductor device
TW202323489A (en) Film adhesive, dicing and die-bonding two-in-one film, semiconductor device, and manufacturing method for same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210312

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220315

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220513

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20220513

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220802

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220815

R151 Written notification of patent or utility model registration

Ref document number: 7136200

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350