JP7130495B2 - load drive circuit - Google Patents

Description

The present invention relates to a low-side load drive circuit that controls current drawn from an output terminal to a ground terminal according to a drive signal.

DMOSFETs (Double Diffused MOSFETs) are widely used as drive transistors, taking advantage of their low loss and high withstand voltage characteristics when driving motors with large currents or securing noise and surge resistance for wired network I/O devices. It is

However, a DMOSFET has a body diode between the source and the drain, and a parasitic diode is formed between the semiconductor substrate and the drain when the DMOSFET is incorporated in a semiconductor integrated circuit. Therefore, when the voltage of the output terminal becomes a negative voltage due to an inductor load or a surge voltage, there is a problem that a sufficient breakdown voltage cannot be secured between the ground terminal and the output terminal.

Therefore, a method is known in which a backflow prevention diode is connected in series to the drain side of the load driving transistor to block the backflow of current when the output terminal becomes a negative voltage (see FIG. 11 of Non-Patent Document 1). ).

However, when a diode is inserted as in Non-Patent Document 1, the voltage between the output terminal and the ground terminal when the load driving transistor is turned on and the current is sucked from the output terminal is lower than in the case of only the load driving transistor. is increased by the forward voltage of the diode, resulting in increased power loss. Also, when viewed as a wired network I/O device, the voltage value of the low level signal does not drop sufficiently.

As a solution to this problem, it is conceivable to replace the backflow prevention diode connected in series with the drain of the load driving transistor with a DMOSFET and control the gate potential of the DMOSFET to prevent backflow (Patent Document 1). 2).

FIG. 7 shows the circuit. In FIG. 7, 2 is an output terminal (drain terminal in Patent Document 1), 3 is a control terminal (gate terminal in Patent Document 1), and 4 is a ground terminal (source terminal in Patent Document 1). In order to give the transistor Q21 a drain withstand voltage, a backflow prevention transistor Q22 made of an NchDMOSFET is inserted and connected between the transistor Q21 and the output terminal 2. A control transistor Q23 is connected. D21, D22, and D23 are gate protection diodes for transistors Q21, Q22, and Q23, respectively, BD21, BD22, and BD23 are body diodes for transistors Q21, Q22, and Q23, respectively, D24 is a diode string, and R21, R22, and R23 are resistors. .

In this circuit, when a positive voltage higher than the potential of the ground terminal 4 is applied to the control terminal 3, the transistors Q21 and Q22 are turned on and the output terminal 2 and the ground terminal 4 are electrically connected. Further, when the voltage of the control terminal 3 is the same as the potential of the ground terminal 4, the transistor Q21 is turned off and the connection between the output terminal 2 and the ground terminal 4 is cut off.

When a negative voltage with respect to the potential of ground terminal 4 is applied to output terminal 2, current flows from ground terminal 4 to output terminal 2 via body diode BD21 of transistor Q21 and resistors R21 and R22. A voltage generated in the resistor R21 by this current turns on the transistor Q23. As a result, the gate and source of the transistor Q22 are short-circuited, and the transistor Q22 is turned off to prevent backflow.

However, in the circuit of FIG. 7, when the transistor Q21 is turned off, the control terminal 3 is at the same potential as the ground terminal 4, and the output terminal 2 is at the same potential as the power supply voltage. In order to secure the withstand voltage between the terminals 3, it is necessary to specially insert the diode D24 and the resistor R23.

However, if the diode D24 and the resistor R23 are inserted, even if the voltage of the control terminal 3 is increased to turn on the transistor Q21, the voltage drop due to the diode D24 and the resistor R23 causes the gate of the transistor Q22 to reach the gate of the transistor Q21. Only a low voltage can be applied, and there is a problem that the ON resistance of the transistor Q22 cannot be lowered sufficiently.

Therefore, as shown in FIG. 8 (FIG. 4 of Patent Document 1), when a diode D24 is inserted between the drain of the transistor Q23 and the gate of the transistor Q22 in order to increase the gate voltage of the transistor Q22, a negative voltage is applied. Sometimes, the negative voltage value at which the transistor Q22 is turned off increases by the voltage applied to the diode D24, and a large reverse current flows when the negative voltage is applied compared to the circuit shown in FIG.

Furthermore, in FIG. 8, a polycrystalline silicon diode insulated from the semiconductor substrate is used as the diode D24 so as not to be clamped by a parasitic diode formed between the semiconductor substrate. Since the leakage current is large and the withstand voltage is low compared to the diode formed in the silicon crystal, there is a problem that it is necessary to connect many diodes in series in order to obtain a withstand voltage equivalent to that of the DMOSFET.

TIOL111 data sheet from TI, page 11, Figure 11, October 2017. Japanese Patent No. 3485655

SUMMARY OF THE INVENTION It is an object of the present invention to provide a load drive circuit that reduces power loss during normal operation and exhibits sufficient withstand voltage when the voltage at the output terminal becomes negative.

In order to achieve the above object, the invention according to claim 1 provides a first transistor comprising an NchDMOSFET whose source is connected to a ground terminal and whose gate is connected to a control terminal; a second transistor consisting of an NchDMOSFET connected to the drain of one transistor, the second transistor consisting of an NchMOSFET having a drain connected to the gate of the second transistor and a source connected to the source of the second transistor; 3 transistors, a fourth transistor consisting of an Nch depletion type DMOSFET whose gate and source are connected to the gate of the second transistor, and a fourth transistor consisting of an Nch depletion type DMOSFET whose gate and source are connected to the gate of the third transistor. a third diode connected between a power supply terminal and the drain of the fourth transistor such that the power supply terminal serves as an anode and the drain of the fourth transistor serves as a cathode; the ground terminal and the fifth transistor; a fourth diode connected between the drains of the transistors such that the ground terminal serves as an anode and the drain of the fifth transistor serves as a cathode; and a first resistor connected between the gate and source of the first transistor. , a second resistor connected between the gate and the source of the second transistor, and a third resistor connected between the gate and the source of the third transistor, all of the first to fifth transistors are formed on a common P-type semiconductor substrate.
The invention according to claim 2 comprises: a first transistor comprising an NchDMOSFET having a drain connected to an output terminal, a gate connected to a control terminal, and a source connected to a P-type semiconductor substrate; a second transistor consisting of an NchDMOSFET connected to the source of the first transistor, the NchMOSFET having a drain connected to the gate of the second transistor and a source connected to the source of the second transistor. a third transistor; a fourth transistor comprising an Nch depletion type DMOSFET whose gate and source are connected to the gate of said second transistor and whose drain is connected to a power supply terminal; and whose drain is connected to said ground terminal and whose gate and source are connected to said A fifth transistor composed of an Nch depletion type DMOSFET connected to the gate of the third transistor, a first resistor connected between the gate and source of the first transistor, and a gate and source of the second transistor. and a third resistor connected between the gate and source of the third transistor, wherein all of the first to fifth transistors are formed on the common P-type semiconductor substrate. It is characterized by
The invention according to claim 3 is the load drive circuit according to claim 1 or 2, wherein a first diode whose anode is connected to the source of the second transistor and whose cathode is connected to the gate of the second transistor; is connected to the source of the third transistor and the cathode is connected to the gate of the third transistor.
The invention according to claim 4 is the load drive circuit according to claim 2, in which the power supply terminal is arranged between the power supply terminal and the drain of the fourth transistor so that the power supply terminal becomes an anode and the drain of the fourth transistor becomes a cathode. and a third diode inserted into and connected to.
The invention according to claim 5 is the load drive circuit according to any one of claims 1 to 4, wherein the sixth transistor comprises an Nch depletion type DMOSFET whose gate and source are connected in common and which is connected in series with the fourth transistor. It is characterized by further comprising a transistor.
The invention according to claim 6 is characterized in that, in the load drive circuit according to any one of claims 1 to 5, the first and second transistors are replaced with discrete transistors.
The invention according to claim 7 is the load drive circuit according to any one of claims 1 to 6, wherein the third transistor is formed in a P-type well insulated from the P-type semiconductor substrate. and
The invention according to claim 8 is the load drive circuit according to claim 3 , wherein the first diode and the second diode are formed in a common P-type well insulated from the P-type semiconductor substrate, or It is characterized by being formed in a P-type well.

According to the present invention, in the normal operation in which the first transistor is controlled to be ON/OFF by the voltage of the control terminal, the second transistor is controlled to be ON and its ON resistance is small, so power loss can be reduced. Further, when a negative voltage is applied to the output terminal, the third transistor is turned on, thereby controlling the second transistor to be turned off, thereby preventing a large current from flowing backward. The drain of the third transistor that is turned on at this time is connected to the gate of the second transistor, and the source is connected to the source of the second transistor, so that the negative voltage value at which the second transistor is turned off when a negative voltage is applied does not increase. . Further, by forming the third transistor and the first and second diodes in a common P-type well insulated from the P-type semiconductor substrate, leakage current can be reduced and withstand voltage can be increased.

1 is a circuit diagram of a load driving circuit according to a first embodiment of the invention; FIG. FIG. 4 is a circuit diagram of a load drive circuit according to a second embodiment of the present invention; FIG. 11 is a circuit diagram of a load drive circuit according to a third embodiment of the present invention; It is a circuit diagram of a load drive circuit of a fourth embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor structure of a transistor Q3 of first to fourth embodiments; FIG. 4 is a cross-sectional view of a semiconductor structure of a diode D1 of first to fourth embodiments; 1 is a circuit diagram of a conventional load drive circuit; FIG. FIG. 10 is a circuit diagram of another conventional example of a load drive circuit;

<First embodiment>
FIG. 1 shows a load driving circuit according to the first embodiment. 1 is a power supply terminal to which voltage VIN is input, 2 is an output terminal to which voltage VOUT is output, 3 is a control terminal to which a control circuit (not shown) is connected, and 4 is a ground terminal.

Q1 is a transistor composed of an Nch DMOSFET whose source is connected to the ground terminal 4 and whose gate is connected to the control terminal 3 . The transistor Q1 functions as, for example, a low-side load driving element of a push-pull output circuit.

Q2 is a transistor composed of an Nch DMOSFET whose source is connected to the output terminal 2 and whose drain is connected to the drain of the transistor Q1. This transistor Q2 functions to prevent backflow when a negative voltage is applied.

Q3 is a transistor composed of an NchMOSFET whose drain is connected to the gate of transistor Q2 and whose source is connected to the source of transistor Q2. The transistor Q3 functions as an ON/OFF switch for the transistor Q2.

Q4 is a transistor composed of an Nch depletion type MOSFET whose gate and source are connected to the gate of transistor Q2. This transistor Q4 works for supplying a constant current of about 10 μA.

Q5 is a transistor composed of an Nch depletion type DMOSFET whose gate and source are connected to the gate of transistor Q3. This transistor Q5 also works for supplying a constant current of about 10 μA.

R1 is a bias resistor connected between the gate and source of the transistor Q1, R2 is a bias resistor connected between the gate and source of the transistor Q2, and R3 is a bias resistor connected between the gate and source of the transistor Q3. is.

D1 is a diode whose anode is connected to the source of transistor Q2 and whose cathode is connected to the gate of transistor Q2. This diode D1 serves as a gate protection clamp for transistor Q2.

D2 is a diode whose anode is connected to the source of transistor Q3 and whose cathode is connected to the gate of transistor Q3. This diode D2 serves as a gate protection clamp for transistor Q3.

D3 is a diode whose anode is connected to the power supply terminal 1 and whose cathode is connected to the drain of the transistor Q4, and D4 is a diode whose anode is connected to the ground terminal 4 and whose cathode is connected to the drain of the transistor Q5. These diodes D3 and D4 work for preventing backflow.

The transistors Q1 to Q5 described above are formed on a common P-type semiconductor substrate having the same potential as the ground terminal 4. FIG. Resistors R2 and R3 are formed of polycrystalline silicon resistors or metal thin film resistors insulated from the P-type semiconductor substrate by a dielectric layer.

FIG. 5 shows a cross section of the semiconductor structure of transistor Q3. 21 is a P type semiconductor substrate, 22 is an N type buried layer, 23 is an N type epitaxial layer, 24 is a P type well, 25 is an N type high concentration region, 26 is a gate electrode, 27 is an N type high concentration region, and 28. 29 is a drain electrode; 30 is a gate electrode; 31 is a source electrode; 32 is a back gate electrode;

Thus, by forming the transistor Q3 in the P-type well 24 insulated from the P-type semiconductor substrate 21 via the N-type semiconductor layers (the N-type buried layer 22 and the N-type epitaxial layer 23), the leakage The current can be small and the breakdown voltage can be made as high as that of the DMOSFET.

FIG. 6 shows the semiconductor structure of the diode D1. 41 is an N-type buried layer, 42 is an N-type epitaxial layer, 43 is a P-type well, 44 is an N-type high concentration region, 45 is a P-type high concentration region, 46 is a cathode electrode, and 47 is an anode electrode. The diode D1 has a P-type well 43 as an anode and an N-type high concentration region 44 as a cathode. Thus, the diode D1 is formed in the P-type well 43 insulated from the P-type semiconductor substrate 21 via the N-type semiconductor layers (the N-type buried layer 41 and the N-type epitaxial layer 42). Although not shown, the diode D2 is also formed with a similar structure. These diodes D1 and D2 may be formed using elements having the same structure as the transistor Q3 so that the source is the cathode and the gate and the drain are short-circuited to the P-type well to be the anode. Furthermore, diodes D1 and D2 may be formed in a common N-type well.

Thus, the diode D1 is formed in the P-type well 43 insulated from the P-type semiconductor substrate 21 via the N-type semiconductor layers (the N-type buried layer 41 and the N-type epitaxial layer 42), and the diode D2 is formed in the same way. , compared to the case of forming the diodes D1 and D2 with polycrystalline silicon, the leakage current can be reduced and the withstand voltage can be made as high as that of the DMOSFET, so there is no need to connect many diodes in series. do not have.

BD1, BD2, BD4, and BD5 are body diodes of the transistors Q1, Q2, Q4, and Q5, respectively, with anodes on the source side and cathodes on the drain side.

Parasitic diodes PD1 to PD5 and PDx are formed between the transistors Q1 to Q5 and the P-type semiconductor substrate 21 and between the P-type semiconductor substrate 21 and the ground terminal 4, respectively. The parasitic diode PD1 has its cathode connected to the drain of the transistor Q1. The parasitic diode PD2 has its cathode connected to the drain of the transistor Q2. The parasitic diode PD4 has a cathode connected to the drain of the transistor Q4, and the parasitic diode PD5 has a cathode connected to the drain of the transistor Q5. The anodes of these parasitic diodes PD1, PD2, PD4 and PD5 are connected to a ground terminal 4 having the same potential as the P-type semiconductor substrate. 1 and 5, the parasitic diode PD3 of the transistor Q3 and the parasitic diode PDx between the P-type semiconductor substrate 21 and the ground terminal 4 are connected anti-serially with their cathodes connected in common.

Next, operation in each state of the load drive circuit according to the first embodiment will be described. First, when the load drive circuit is in the OFF state, the potential of the control terminal 3 is at the low level, and the gate of the transistor Q1 is connected to the ground terminal 4 through the resistor R1, so that the transistor Q1 is in the OFF state, and the drain and source are in the OFF state. There is no continuity between Also, the path from the output terminal 2 to the ground terminal 4 via the diode D2 or the resistor R3 and the transistor Q5 and the diode D4 is not conductive because the diode D4 is reverse-biased, and no current flows through this path either. .

Therefore, no current flows from the output terminal 2 to the ground terminal 4. If a load is connected to the output terminal 2 and a power supply is connected to the load, the potential of the output terminal 2 is the power supply to which the load is connected. It becomes the voltage almost equal to the voltage.

Next, when the load drive circuit is in the ON state, the potential of the control terminal 3 is at a high level, the transistor Q1 is turned ON, and the drain and source are electrically connected. As a result, the constant current I4 from the transistor Q4 flows through the resistor R2 and the body diode BD2 of the transistor Q2 to the transistor Q1, and the gate potential of the transistor Q2 becomes a potential higher than the source potential of the transistor Q2 by "R2.times.I4."

For example, if I4=10 μA and R2=500 kΩ, the voltage between the gate and source of the transistor Q2 is 5 V, and if the threshold voltage of the transistor Q2 is 1 V, the transistor Q2 becomes conductive with a sufficiently low ON resistance. , the load drive circuit sinks current from the output terminal 2 to the ground terminal 4 via the transistors Q2 and Q1.

Assuming that the load current flowing through the output terminal 2 at this time is IL, the ON resistance of the transistor Q1 is Ron1, and the ON resistance of the transistor Q2 is Ron2, the voltage of the output terminal 2 is "(Ron1+Ron2)×(IL+I4)". Since "IL>>I4" is normal, the voltage can be approximated as "(Ron1+Ron2)×IL". For example, if Ron1=Ron2=0.5Ω and IL=0.1A, the voltage at the output terminal 2 is 0.1V.

This voltage value is approximately 0.75 V because in a conventional circuit (Non-Patent Document 1) that uses a diode instead of transistor Q2, it is the sum of the voltage drop across transistor Q1 and the forward voltage of that diode, about 0.7 V. This is a sufficiently low value compared to

Next, when the output terminal 2 has a negative voltage, the parasitic diodes PD1 to PD5 are connected as described above. The voltage drop across resistor R3 is small and transistor Q3 remains OFF.

Also, the constant current from the transistor Q4 flows to the output terminal 2 via the resistor R2, and a voltage drop sufficient to turn on the transistor Q2 is generated across the resistor R2. , a current flows to the output terminal 2 through the body diode BD1 of the transistor Q1 or the parasitic diode PD1. However, since the potential difference between the ground terminal 4 and the output terminal 2 is small, a current so large as to cause failure of the load driving circuit and the load does not flow.

When the potential of the output terminal 2 further increases in the negative direction, the voltage drop across the resistor R3 caused by the constant current of the transistor Q5 turns on the transistor Q3, and the constant current of the transistor Q4 flows through the transistor Q3. Therefore, the transistor Q2 is turned off, and the current flowing from the ground terminal 4 to the output terminal 2 via the body diode BD1 of the transistor Q1 or the parasitic diode PD1 is cut off.

Only the constant current of the transistor Q4 and the constant current of the transistor Q5 flow through the output terminal 2. Assuming that the constant current of the transistor Q5 is 10 .mu.A like the transistor Q4, the current IL flowing from the output terminal 2 is 20 .mu.A. It is not a current that causes the load drive circuit or the load connected to the output terminal 2 to fail.

In this embodiment, discrete DMOSFETs may be used instead of forming the transistors Q1 and Q2 on the common P-type semiconductor substrate 21 with the other transistors Q3 to Q5. In this case, the configuration including the parasitic diodes with the P-type semiconductor substrate 21 is a configuration without the parasitic diodes PD1 and PD2. exists, the operation of the circuit is the same as that of the present embodiment.

<Second embodiment>
FIG. 2 shows a load driving circuit according to a second embodiment. This embodiment differs from the first embodiment in that a transistor Q6 composed of an Nch depletion type DMOSFET having the same structure and size as the transistor Q4 is inserted between the source of the transistor Q4 and the drain of the transistor Q3. The drain of transistor Q6 is connected to the gate and source of transistor Q4, and the gate and source of transistor Q6 are connected to the drain of transistor Q3. Transistor Q6 functions as a constant current element like transistor Q4.

The load drive circuit of the second embodiment operates in the same manner as the load drive circuit of the first embodiment. Reserved by Q2 and Q5. A breakdown voltage between the power supply terminal 1 and the output terminal 2 is ensured by the transistors Q4 and Q6. Since the transistors Q2, Q5, Q4, and Q6 are elements formed on the common P-type semiconductor substrate 21, they have the same maximum structurally obtainable breakdown voltage.

By the way, since the voltage VIN of the power supply terminal 1 is higher than the potential of the ground terminal 1, the negative voltage withstand voltage of the load drive circuit is limited by the voltage VIN and the withstand voltage of the transistor Q4 without the transistor Q6 as in the first embodiment. be. If VIN=20V and the breakdown voltage of the transistor Q4 is 50V, the negative voltage breakdown voltage is -30V.

However, by inserting the transistor Q6, when a large negative voltage is applied, the drain of the transistor Q6 is clamped to the ground terminal 4 by the parasitic diode PD6 as shown in FIG. Q4 handles the negative voltage between the ground terminal 4 and the output terminal 2, and the transistor Q6 handles the negative voltage between the ground terminal 4 and the output terminal 2, so that the negative voltage withstand voltage can be expanded to -50V, which is equivalent to the device withstand voltage.

On the other hand, when the voltage VIN of the power supply terminal 1 is low, the advantage of increasing the negative voltage withstand voltage is reduced, and conversely, the voltage between the gate and the source of the transistor Q2 decreases by the operating voltage of the transistor Q6 when the load drive circuit is ON. As a result, the ON resistance of the transistor Q2 increases.

In this embodiment, discrete DMOSFETs may be used instead of forming the transistors Q1 and Q2 on the common P-type semiconductor substrate 21 with the other transistors Q3 to Q6. In this case, the configuration including the parasitic diodes with the P-type semiconductor substrate 21 is a configuration without the parasitic diodes PD1 and PD2. exists, the operation of the circuit is the same as that of the present embodiment.

<Third embodiment>
FIG. 3 shows a load driving circuit according to a third embodiment. This embodiment differs greatly from the first embodiment in that the load driving transistor is connected to the output terminal 2 side and the backflow prevention transistor is connected to the ground terminal side, and that the P-type semiconductor substrate 21 is connected to the ground terminal. 4 is different in potential.

Q11 is a transistor composed of an NchDMOSFET whose drain is connected to the output terminal 2, whose source is connected to the P-type semiconductor substrate 21, and whose gate is connected to the control terminal 3; The transistor Q11 functions as, for example, a low-side load driving element of a push-pull output circuit.

Q12 is a transistor composed of an Nch DMOSFET whose drain is connected to the ground terminal 2 and whose source is connected to the P-type semiconductor substrate 21; This transistor Q12 works as a backflow prevention.

Q13 is a transistor composed of an NchMOSFET whose drain is connected to the gate of transistor Q12 and whose source is connected to the source of transistor Q12. This transistor Q13 works for ON/OFF of the transistor Q12.

Q14 is a transistor composed of an Nch depletion type MOSFET whose gate and source are connected to the gate of transistor Q12. This transistor Q14 works to supply a constant current of about 10 .mu.A.

Q15 is a transistor composed of an Nch depletion type DMOSFET whose gate and source are connected to the gate of transistor Q13. This transistor Q15 works to supply a constant current of about 10 .mu.A.

R11 is a bias resistor connected between the gate and source of the transistor Q11, R12 is a bias resistor connected between the gate and source of the transistor Q12, and R13 is a bias resistor connected between the gate and source of the transistor Q13. is.

D11 is a diode whose anode is connected to the source of transistor Q12 and whose cathode is connected to the gate of transistor Q12. This diode D11 serves as a gate protection clamp for transistor Q12.

D12 is a diode whose anode is connected to the source of transistor Q13 and whose cathode is connected to the gate of transistor Q13. This diode D12 serves as a gate protection clamp for transistor Q13.

D13 is a diode whose anode is connected to power supply terminal 1 and whose cathode is connected to the drain of transistor Q14. This diode D13 works as a backflow prevention.

The transistors Q11 to Q15, the diodes D11 to D13, and the resistors R11 to R13 are formed on a common P-type semiconductor substrate 21 having a potential different from that of the ground terminal 4. FIG. In this embodiment, there are no restrictions on the structure of the resistors R12 and R13, and the P-type semiconductor layer forming the transistor Q13 and the diodes D12 and D13 may not be insulated from the P-type semiconductor substrate 21 either.

BD11, BD12, BD14, and BD15 are body diodes of the transistors Q11, Q12, Q14, and Q15, respectively, with anodes on the source side and cathodes on the drain side.

Parasitic diodes PD11-PD14 are formed between the transistors Q11-Q14 and the P-type semiconductor substrate 21, respectively. The parasitic diode PD11 has a cathode connected to the drain of the transistor Q11. The parasitic diode PD12 has a cathode connected to the ground terminal 4, the parasitic diode PD13 has a cathode connected to the drain of the transistor Q13, and the parasitic diode PD14 has a cathode connected to the drain of the transistor Q14. Anodes of the parasitic diodes PD11, PD12, PD13, and PD14 are connected to the P-type semiconductor substrate 21. FIG.

Next, operation in each state of the load drive circuit according to the third embodiment will be described. First, when the load drive circuit is in the OFF state, the potential of the control terminal 3 is at a low level, and the transistor Q11 is OFF because its gate is connected to the source through the resistor R11, and no conduction is made between the drain and the source. It does not sink current from the load through output terminal 2. Therefore, no current flows through diode D12 and resistor R13, and transistor Q13 is off.

On the other hand, a constant current is supplied from the power supply terminal 1 by the transistor Q14, and this current flows through the resistor R12 to generate a voltage between the gate and source of the transistor Q12. Assuming that the constant current I4 by the transistor Q14 is 10 μA, the resistance value of the resistor R12 is 500 kΩ, and the threshold voltage of the transistor Q12 is 1 V, the transistor Q12 is ON and the drain and source are in a conductive state. Since the transistor Q11 is OFF, the current flowing between the source and drain of the transistor Q12 is only the current of about 10 μA from the transistor Q14. .

Next, when the load drive circuit is in the ON state, the control terminal 3 is at a high level, the transistor Q11 is turned ON, and the drain and source are electrically connected. At this time, the transistor Q12 is also ON in the same manner as when the load drive circuit is OFF, and the current drawn from the load by the transistor Q11 through the output terminal 2 flows to the ground terminal 4 through the transistor Q12.

In parallel with the transistor Q12, there is a path from the body diode BD15 of the transistor Q15 to the ground terminal 4 via the diode D12 or the resistor R13. is 0.1 A, the potential difference between the P-type semiconductor substrate 21 and the ground terminal 4 is 0.05 V, most of the load current IL flows through the transistor Q12 instead of the transistor Q15, and the transistor Q13 is turned off. be kept.

Next, regarding the case where the output terminal 2 becomes a negative voltage, while the negative voltage value of the output terminal 2 is small, the voltage generated in the resistor R13 by the constant current of the transistor Q15 is also small, and the transistor Q13 remains OFF. Become. Therefore, the constant current from the transistor Q14 flows to the output terminal 2 via the resistor R12 and further via the transistor Q11 or the parasitic diode PD11. Therefore, a voltage drop sufficient to turn on the transistor Q12 occurs across the resistor R12, and the transistor Q12 is turned on. flows to the output terminal 2. However, since the potential difference between the ground terminal 4 and the output terminal 2 is small, a current so large as to cause failure of the load driving circuit and the load does not flow.

When the potential of the output terminal 2 further increases in the negative direction, the voltage drop across the resistor R13 caused by the constant current of the transistor Q15 turns on the transistor Q13, and the constant current of the transistor Q14 flows, so the transistor Q12 is turned off. , the current flowing from the ground terminal 4 to the output terminal 2 is cut off.

Only the constant currents of the transistors Q14 and Q15 flow through the output terminal 2. If the constant currents of the transistors Q14 and Q15 are respectively 10 μA, the current flowing into the output terminal 2 is 20 μA. It is not a current that will lead to failure.

In this embodiment, the transistors Q11 and Q12 may not be formed on the common P-type semiconductor substrate 21 with the other transistors Q13 to Q15, and discrete DMOSFETs may be used. In this case, the configuration including the parasitic diodes with the P-type semiconductor substrate 21 is a configuration without the parasitic diodes PD11 and PD12. exists, the operation of the circuit is the same as that of the present embodiment.

<Fourth embodiment>
FIG. 4 shows a load driving circuit according to a fourth embodiment. This embodiment differs from the third embodiment in that a transistor Q16 consisting of an Nch depletion type DMOSFET having the same structure and size as the transistor Q14 is inserted between the source of the transistor Q14 and the drain of the transistor Q13. The drain of transistor Q16 is connected to the gate and source of transistor Q14, and the gate and source of transistor Q16 are connected to the drain of transistor Q13. Transistor Q16 functions as a constant current element like transistor Q14.

The load drive circuit of the fourth embodiment operates in the same manner as the load drive circuit of the third embodiment. Secured by Q12 and Q15. A breakdown voltage between the power supply terminal 1 and the output terminal 2 is ensured by the transistors Q14 and Q16. Since the transistors Q12, Q15, Q14 and Q16 are elements formed on the common P-type semiconductor substrate 21, they have the same maximum withstand voltage structurally.

By the way, since the voltage VIN of the power supply terminal 1 is higher than the potential of the ground terminal 4, without the transistor Q16 as in the third embodiment, the negative voltage withstand voltage of the load drive circuit is the voltage VIN and the transistor Q14 or the parasitic diode PD14. Although it is limited by the breakdown voltage, it can be considered that it is limited by the breakdown voltage of the transistor Q14 because the breakdown voltage of the parasitic diode PD14 with the P-type semiconductor substrate 21 is generally higher than the breakdown voltage of the DMOSFET like the transistor Q14. . If VIN=20V, the withstand voltage of the transistor Q14 is 50V, and the withstand voltage of the parasitic diode PD14 is 80V, the negative voltage withstand voltage is -30V.

However, by inserting the transistor Q16 as shown in FIG. 4, equal voltages are applied to the transistors Q14 and Q16, respectively, and the negative voltage withstand voltage can be expanded to -60V limited by the parasitic diode PD14.

On the other hand, when the voltage VIN of the power supply terminal 1 is low, the advantage of increasing the negative voltage withstand voltage is reduced, and conversely, the gate-source voltage of the transistor Q12 decreases by the operating voltage of the transistor Q16 when the load drive circuit is ON. As a result, the ON resistance of the transistor Q12 increases.

In this embodiment, the transistors Q11 and Q12 may not be formed on the common P-type semiconductor substrate 21 with the other transistors Q13 to Q16, and discrete DMOSFETs may be used. In this case, the configuration including the parasitic diodes with the P-type semiconductor substrate 21 is a configuration without the parasitic diodes PD11 and PD12. exists, the operation of the circuit is the same as that of the present embodiment.

1: power supply terminal, 2: output terminal, 3: control terminal, 4: ground terminal 21: P-type semiconductor substrate, 22: N-type buried layer, 23: N-type epitaxial layer, 24: P-type well, 25: N type high concentration region 26: gate electrode 27: N type high concentration region 28: P type high concentration region 29: drain electrode 30: gate electrode 31: source electrode 32: back gate electrode 33: P 41: N-type buried layer 42: N-type epitaxial layer 43: P-type well 44: N-type high concentration region 45: P-type high concentration region 46: Cathode electrode 47: Anode electrode

Claims (8)

A first transistor made of an NchDMOSFET whose source is connected to a ground terminal and whose gate is connected to a control terminal; and a second transistor made of an NchDMOSFET whose source is connected to an output terminal and whose drain is connected to the drain of the first transistor. In a load drive circuit comprising
a third transistor comprising an NchMOSFET having a drain connected to the gate of the second transistor and a source connected to the source of the second transistor;
a fourth transistor comprising an Nch depletion type DMOSFET whose gate and source are connected to the gate of said second transistor;
a fifth transistor composed of an Nch depletion type DMOSFET whose gate and source are connected to the gate of said third transistor;
a third diode connected between a power supply terminal and the drain of the fourth transistor such that the power supply terminal is an anode and the drain of the fourth transistor is a cathode;
a fourth diode connected between the ground terminal and the drain of the fifth transistor such that the ground terminal is an anode and the drain of the fifth transistor is a cathode;
a first resistor connected between the gate and source of the first transistor;
a second resistor connected between the gate and source of the second transistor;
a third resistor connected between the gate and source of the third transistor;
, wherein all of the first to fifth transistors are formed on a common P-type semiconductor substrate. A first transistor comprising an NchDMOSFET whose drain is connected to the output terminal, whose gate is connected to the control terminal, and whose source is connected to the P-type semiconductor substrate, and whose drain is connected to the ground terminal and whose source is connected to the source of the first transistor. In a load drive circuit comprising a second transistor consisting of an Nch DMOSFET,
a third transistor comprising an NchMOSFET having a drain connected to the gate of the second transistor and a source connected to the source of the second transistor;
a fourth transistor comprising an Nch depletion type DMOSFET having a gate and a source connected to the gate of the second transistor and a drain connected to a power supply terminal;
a fifth transistor comprising an Nch depletion type DMOSFET having a drain connected to the ground terminal and a gate and source connected to the gate of the third transistor;
a first resistor connected between the gate and source of the first transistor;
a second resistor connected between the gate and source of the second transistor;
a third resistor connected between the gate and source of the third transistor;
, wherein all of the first to fifth transistors are formed on the common P-type semiconductor substrate. 3. The load drive circuit according to claim 1, wherein
a first diode having an anode connected to the source of the second transistor and a cathode connected to the gate of the second transistor;
a second diode having an anode connected to the source of the third transistor and a cathode connected to the gate of the third transistor;
A load driving circuit, further comprising: 3. The load driving circuit according to claim 2 ,
The load driver further comprises a third diode inserted between the power supply terminal and the drain of the fourth transistor so that the power supply terminal becomes an anode and the drain of the fourth transistor becomes a cathode. circuit. 5. The load driving circuit according to any one of claims 1 to 4,
A load driving circuit, further comprising a sixth transistor comprising an Nch depletion type DMOSFET having a gate and a source connected in common and connected in series with the fourth transistor. 6. The load driving circuit according to any one of claims 1 to 5,
A load driving circuit, wherein the first and second transistors are replaced with discrete transistors. 7. The load driving circuit according to any one of claims 1 to 6,
A load driving circuit, wherein the third transistor is formed in a P-type well insulated from the P-type semiconductor substrate. 4. The load driving circuit of claim 3, wherein
A load driving circuit, wherein said first diode and said second diode are formed in a common P-type well insulated from said P-type semiconductor substrate, or formed in different P-type wells.

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