CN111064457A - Method for conducting output stage MOS tube under low voltage - Google Patents
Method for conducting output stage MOS tube under low voltage Download PDFInfo
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- CN111064457A CN111064457A CN201811201289.8A CN201811201289A CN111064457A CN 111064457 A CN111064457 A CN 111064457A CN 201811201289 A CN201811201289 A CN 201811201289A CN 111064457 A CN111064457 A CN 111064457A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
- G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
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Abstract
A method for conducting an output-stage MOS tube under low voltage is beneficial to a power supply monitoring chip to realize that the power supply monitoring chip can give a rear-stage chip a correct voltage indication under extremely low power supply voltage, and is characterized in that for an output-stage module in the power supply monitoring chip, a substrate voltage of a substrate node of the output-stage module is regulated to form a MOS tube back gate effect, so that a first threshold voltage of the output-stage MOS tube in the output-stage module is reduced to a second threshold voltage, the first threshold voltage refers to the threshold voltage when the substrate voltage of the output-stage MOS tube is not regulated, the low voltage refers to the first threshold voltage of the output-stage MOS tube, and the second threshold voltage is lower than the low voltage, so that the output-stage MOS tube is conducted under the low voltage.
Description
Technical Field
The invention relates to a power supply monitoring chip technology, in particular to a method for conducting an output stage MOS tube under low voltage, wherein the low voltage means that the power supply voltage is smaller than the threshold voltage of the output stage MOS tube, and the threshold voltage of the output stage MOS tube is reduced by adjusting the substrate voltage at the substrate end of the output stage MOS tube by utilizing the MOS tube back gate effect so as to conduct the output stage MOS tube, thereby being beneficial to the power supply monitoring chip to realize accurate voltage indication for a rear stage chip under extremely low power supply voltage.
Background
For circuits such as power supply monitoring chips, the output pin is required to have the capability of providing a correct indication voltage even at a power supply voltage as low as possible, and to provide an output impedance low enough. In order to prevent power failure, a power supply monitoring chip is applied to monitor the system power supply voltage in most circuit systems, and when the power supply voltage is lower than the system working voltage, the power supply monitoring chip outputs a logic high level or a logic low level to a core circuit to realize circuit reset. The typical circuit comprises a plurality of core circuits connected in parallel, one end of each core circuit is connected with a power supply voltage, the other end of each core circuit is connected with a grounding terminal, each core circuit is provided with a reset pin, each reset pin is connected to a voltage normal indication pin of a power supply monitoring chip, one end of the power supply monitoring chip is connected with the power supply voltage, and the other end of the power supply monitoring chip is connected with the grounding terminal. This requires the power supply monitoring chip to provide a correct indication to the subsequent chip at a very low power supply voltage and to have a low enough output impedance to guarantee a logic level. For example, in a certain system, the power supply monitoring chip is required to output a logic low level when the voltage is 0.7V, and the pin voltage is required to be lower than 0.2V when the sink current is 30 uA. The existing method comprises the steps of increasing the area of an output stage MOS tube as much as possible, improving the width-to-length ratio of the MOS tube, and reducing the on-resistance, for example, increasing the total channel width of the output MOS while adopting the minimum channel length, so as to increase the width-to-length ratio and reduce the on-resistance; or the MOS tube with lower threshold voltage is adopted through process adjustment. However, the inventor finds that the method for improving the width-to-length ratio of the MOS transistor needs to increase the circuit area of the output stage MOS transistor, and the method can be realized only when the power supply voltage is higher than the threshold voltage of the output stage MOS transistor, but cannot be realized when the power supply voltage is lower than the threshold voltage of the output stage MOS transistor. This adds significantly to the cost of MOS transistors that use lower threshold voltages. The inventor believes that if a gate back effect (i.e. an effect of a threshold voltage change caused by a substrate voltage) of a MOS transistor is applied to an output stage circuit, the threshold voltage of the output stage MOS transistor can be lowered to turn on the output stage MOS transistor by adjusting the substrate voltage at the substrate terminal of the output stage MOS transistor. In view of the above, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a method for conducting an output-stage MOS tube under low voltage, wherein the low voltage means that the power voltage is smaller than the threshold voltage of the output-stage MOS tube, and the threshold voltage of the output-stage MOS tube is reduced by adjusting the substrate voltage at the substrate end of the output-stage MOS tube by utilizing the back gate effect of the MOS tube so as to conduct the output-stage MOS tube, thereby being beneficial to a power supply monitoring chip to realize accurate voltage indication for a rear-stage chip under extremely low power voltage.
The technical scheme of the invention is as follows:
a method for conducting an output stage MOS tube under low voltage is characterized in that for an output stage module in a power supply monitoring chip, a substrate voltage of a substrate node of the output stage module is adjusted to form a MOS tube back gate effect, so that a first threshold voltage of the output stage MOS tube in the output stage module is reduced to a second threshold voltage, the first threshold voltage refers to a threshold voltage when the substrate voltage of the output stage MOS tube is not adjusted, the low voltage refers to a threshold voltage when the power supply voltage is smaller than the first threshold voltage of the output stage MOS tube, and the second threshold voltage is lower than the low voltage, so that the output stage MOS tube is conducted under the low voltage.
The output stage module comprises an output end and a grid node, the grid node is connected with the grid control module, and a substrate node of the output stage module is connected with the substrate voltage control module.
The substrate voltage control module comprises a second resistor and a third resistor, one end of the second resistor is connected with a power supply end, the other end of the second resistor is connected with one end of the third resistor, the other end of the third resistor is connected with a source electrode of the output stage MOS tube, a substrate voltage node is arranged between the second resistor and the third resistor, the substrate voltage node is respectively connected with the substrate node of the output stage module and a drain electrode of the third MOS tube, a grid electrode of the third MOS tube is connected with the substrate voltage control circuit, and the source electrode of the third MOS tube is connected with the source electrode of the output stage MOS tube.
The grid control module comprises a first resistor, one end of the first resistor is connected with a power supply end, the other end of the first resistor is respectively connected with a grid node of the output stage module and a drain electrode of the second MOS tube, a source electrode of the second MOS tube is connected with a source electrode of the output stage MOS tube, and a grid electrode of the second MOS tube is connected with the output control circuit.
And the output stage MOS tube adopts an NMOS tube or a PMOS tube.
The output stage module comprises a push-pull output circuit, and the push-pull output circuit is connected with the output end of the output stage module.
The push-pull output circuit comprises a fourth PMOS (P-channel metal oxide semiconductor) tube and an output stage MOS tube, wherein the source electrode of the output stage MOS tube is connected with a grounding end, the grid electrode of the output stage MOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with a grid electrode control module, the drain electrode of the output stage MOS tube and the drain electrode of the fourth PMOS tube are connected with the output end of the output stage module, the source electrode of the fourth PMOS tube is connected with a power supply end, and the substrate of the output stage MOS tube and the substrate of the fourth PMOS tube are respectively connected with a substrate voltage control circuit.
The invention has the following technical effects: according to the method for conducting the output stage MOS tube under the low voltage, the output impedance of the output stage can be reduced under the extremely low power voltage by adjusting the substrate voltage, correct indication voltage is provided, the dependence on the process is overcome, and the area of the output stage can be reduced. The purpose of the technology is to reduce the threshold voltage of the MOS tube by controlling the substrate voltage, realize the conduction of the output stage at low voltage and provide smaller output impedance. Although the technical solution of the present invention is to adopt a combination of a substrate voltage control circuit and an output stage MOS transistor in consideration of a power supply voltage lower than a normal MOS transistor threshold voltage, the technical essence thereof is substrate voltage regulation.
The invention has the following characteristics: 1. the circuit provides a correct indication level under an extremely low power supply voltage by controlling the substrate potential of the output MOS. 2. The output stage is made to have a very small on-resistance. 3. The limit of process conditions is overcome, and the circuit function is realized.
Drawings
Fig. 1 is a schematic diagram of an applied circuit structure of a method for turning on an output stage MOS transistor at a low voltage according to the present invention.
The reference numbers are listed below: 1-a gate control module; 2-an output stage module; 3-substrate voltage control module; 4-substrate voltage control circuit; 5-an output control circuit; r1 — first resistance or pull-up resistance; r2 — second resistance; r3 — third resistance; m1-output stage MOS tube or first MOS tube; m2-second MOS tube; m3-third MOS tube; VDD-Power supply terminal or supply voltage; an OUT-output terminal; a G-gate node; b-a substrate node; v1-substrate voltage node.
Detailed Description
The invention is described below with reference to the accompanying drawing (fig. 1).
Fig. 1 is a schematic diagram of an applied circuit structure of a method for turning on an output stage MOS transistor at a low voltage according to the present invention. As shown in fig. 1, for an output stage module 2 in a power supply monitoring chip, a substrate voltage of a substrate node of the output stage module 2 is adjusted to form a MOS back gate effect, so that a first threshold voltage of an output stage MOS transistor M1 in the output stage module 2 is reduced to a second threshold voltage, where the first threshold voltage refers to a threshold voltage when the substrate voltage of the output stage MOS transistor M1 is not adjusted, the low voltage refers to a threshold voltage when the substrate voltage of the output stage MOS transistor M1 is less than the first threshold voltage of the output stage MOS transistor M1, and the second threshold voltage is lower than the low voltage, so that the output stage MOS transistor M1 is turned on at the low voltage. The output stage module 2 comprises an output end OUT and a grid node G, the grid node G is connected with the grid control module 1, and a substrate node B of the output stage module 2 is connected with the substrate voltage control module 3. The substrate voltage control module 3 includes a second resistor R2 and a third resistor R3, one end of the second resistor R2 is connected to a power supply terminal VDD, the other end of the second resistor R2 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to a source of the output stage MOS transistor M1, a substrate voltage node V1 is between the second resistor R2 and the third resistor R3, the substrate voltage node V1 is respectively connected to a substrate node B of the output stage module 2 and a drain of the third MOS transistor M3, a gate of the third MOS transistor M3 is connected to the substrate voltage control circuit 4, and a source of the third MOS transistor M3 is connected to a source of the output stage MOS transistor M1. The gate control module 1 includes a first resistor R1, one end of the first resistor R1 is connected to a power supply terminal VDD, the other end of the first resistor R1 is respectively connected to the gate node G of the output stage module 2 and the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the source of the output stage MOS transistor M1, and the gate of the second MOS transistor M2 is connected to the output control circuit 5.
The output stage MOS transistor M1 adopts an NMOS transistor or a PMOS transistor. The output stage module comprises a push-pull output circuit, and the push-pull output circuit is connected with the output end of the output stage module. The push-pull output circuit comprises a fourth PMOS (P-channel metal oxide semiconductor) tube and an output stage MOS tube, wherein the source electrode of the output stage MOS tube is connected with a grounding end, the grid electrode of the output stage MOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with a grid electrode control module, the drain electrode of the output stage MOS tube and the drain electrode of the fourth PMOS tube are connected with the output end of the output stage module, the source electrode of the fourth PMOS tube is connected with a power supply end, and the substrate of the output stage MOS tube and the substrate of the fourth PMOS tube are respectively connected with a substrate voltage control circuit.
Fig. 1 shows a specific embodiment of the present invention. The circuit is divided into three parts, namely a grid control module 1, an output stage module 2 and a substrate voltage control module 3. The invention aims to overcome the limitation of power supply voltage, to make an output stage conductive under the condition of extremely low power supply voltage and to make the output stage have smaller on-resistance. When the power supply voltage is too small, the MOS tubes of the grid control circuit and the substrate voltage control circuit are both in a turn-off state. The substrate voltage of the output stage MOS transistor M1 is divided by resistors to obtain a voltage V1 ═ R3 × VDD/(R2+ R3), and the threshold voltage of the output stage MOS transistor M1 is reduced according to the back gate effect of the MOS transistor. And the gate voltage of the output stage MOS transistor M1 is pulled up to the power supply voltage VDD through the first resistor R1. By adjusting the proportion of the second resistor R2 and the third resistor R3, the output stage is conducted, and proper output impedance is obtained. When the power supply voltage is high enough, all the MOS tubes in the circuit can overcome the threshold voltage to work normally, and the output control circuit controls the second MOS tube M2 to be switched on or switched off, so that the grid control of the output stage is realized. The substrate voltage control circuit works to pull the substrate voltage of the output stage MOS tube M1 down to ground or a proper voltage, control the on-resistance of the output stage and prevent the diode forward conduction of the substrate of the output stage MOS tube M1 to the source and drain terminals caused by the overhigh substrate voltage. The invention has the advantages of no need of special process, overcoming the limitation of process conditions, ensuring the conduction of the output MOS and reducing the conduction impedance under extremely low power supply voltage.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.
Claims (7)
1. A method for conducting an output stage MOS tube under low voltage is characterized in that for an output stage module in a power supply monitoring chip, a substrate voltage of a substrate node of the output stage module is adjusted to form a MOS tube back gate effect, so that a first threshold voltage of the output stage MOS tube in the output stage module is reduced to a second threshold voltage, the first threshold voltage refers to a threshold voltage when the substrate voltage of the output stage MOS tube is not adjusted, the low voltage refers to a threshold voltage when the power supply voltage is smaller than the first threshold voltage of the output stage MOS tube, and the second threshold voltage is lower than the low voltage, so that the output stage MOS tube is conducted under the low voltage.
2. The method of claim 1, wherein the output stage module comprises an output terminal and a gate node, the gate node is connected to a gate control module, and a substrate node of the output stage module is connected to a substrate voltage control module.
3. The method according to claim 2, wherein the substrate voltage control module comprises a second resistor and a third resistor, one end of the second resistor is connected to a power supply terminal, the other end of the second resistor is connected to one end of the third resistor, the other end of the third resistor is connected to a source of the output stage MOS transistor, a substrate voltage node is formed between the second resistor and the third resistor, the substrate voltage node is respectively connected to a substrate node of the output stage module and a drain of the third MOS transistor, a gate of the third MOS transistor is connected to the substrate voltage control circuit, and a source of the third MOS transistor is connected to a source of the output stage MOS transistor.
4. The method according to claim 2, wherein the gate control module comprises a first resistor, one end of the first resistor is connected to a power supply terminal, the other end of the first resistor is connected to the gate node of the output stage module and the drain of a second MOS transistor, respectively, the source of the second MOS transistor is connected to the source of the output stage MOS transistor, and the gate of the second MOS transistor is connected to the output control circuit.
5. The method according to claim 1, wherein the output stage MOS transistor is an NMOS transistor or a PMOS transistor.
6. The method for turning on the output stage MOS transistor under the low voltage according to claim 1, wherein the output stage module comprises a push-pull output circuit, and the push-pull output circuit is connected with the output end of the output stage module.
7. The method according to claim 6, wherein the push-pull output circuit comprises a fourth PMOS transistor and the output MOS transistor, a source of the output MOS transistor is connected to a ground terminal, a gate of the output MOS transistor and a gate of the fourth PMOS transistor are both connected to the gate control module, a drain of the output MOS transistor and a drain of the fourth PMOS transistor are both connected to the output terminal of the output module, a source of the fourth PMOS transistor is connected to a power supply terminal, and a substrate of the output MOS transistor and a substrate of the fourth PMOS transistor are respectively connected to the substrate voltage control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811201289.8A CN111064457A (en) | 2018-10-16 | 2018-10-16 | Method for conducting output stage MOS tube under low voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811201289.8A CN111064457A (en) | 2018-10-16 | 2018-10-16 | Method for conducting output stage MOS tube under low voltage |
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| Publication Number | Publication Date |
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| CN111064457A true CN111064457A (en) | 2020-04-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811201289.8A Withdrawn CN111064457A (en) | 2018-10-16 | 2018-10-16 | Method for conducting output stage MOS tube under low voltage |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112803721A (en) * | 2020-12-30 | 2021-05-14 | 合肥视涯技术有限公司 | Voltage converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030132778A1 (en) * | 2002-01-15 | 2003-07-17 | Matsushita Electric Industrial Co., Ltd. | Level shift circuit |
| US20050035960A1 (en) * | 2003-07-30 | 2005-02-17 | Hideto Kobayashi | Display apparatus driving circuitry |
| CN101505094A (en) * | 2009-03-05 | 2009-08-12 | 浙江大学 | Electric power supply module for portable equipment |
| CN106027030A (en) * | 2016-05-19 | 2016-10-12 | 中国电子科技集团公司第二十四研究所 | High-speed high-linearity fully-differential follower |
-
2018
- 2018-10-16 CN CN201811201289.8A patent/CN111064457A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030132778A1 (en) * | 2002-01-15 | 2003-07-17 | Matsushita Electric Industrial Co., Ltd. | Level shift circuit |
| US20050035960A1 (en) * | 2003-07-30 | 2005-02-17 | Hideto Kobayashi | Display apparatus driving circuitry |
| CN101505094A (en) * | 2009-03-05 | 2009-08-12 | 浙江大学 | Electric power supply module for portable equipment |
| CN106027030A (en) * | 2016-05-19 | 2016-10-12 | 中国电子科技集团公司第二十四研究所 | High-speed high-linearity fully-differential follower |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112803721A (en) * | 2020-12-30 | 2021-05-14 | 合肥视涯技术有限公司 | Voltage converter |
| US11614762B2 (en) | 2020-12-30 | 2023-03-28 | Seeya Optronics Co., Ltd. | Voltage converter |
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Application publication date: 20200424 |