JP2014003514A - Semiconductor device and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is low in manufacturing cost.SOLUTION: The semiconductor device (40, 1_1-1_n, 2_1-2_n) comprises on a semiconductor substrate: a power transistor (MN0) disposed between a first external terminal (LDD) and a second external terminal (GND); a clamp circuit (14) disposed between the first external terminal and a gate electrode of the power transistor; and a resistance circuit (15) disposed between the gate electrode of the power transistor and the second external terminal. The semiconductor device further comprises: a first, N channel MIS transistor (MN1) having a source electrode and a back gate electrode connected to the first external terminal, and a drain electrode connected to a drain electrode of the power transistor; a first resistive element (R1) disposed between a gate electrode and the source electrode of the first MIS transistor; and a second resistive element (R2) disposed between the gate electrode and the drain electrode of the first MIS transistor.

Description

  The present invention relates to a semiconductor device and a communication system, and more particularly to a technique effective when applied to a semiconductor device having a high breakdown voltage transistor in an output stage.

  There is a low-side driver circuit as a load driving circuit for driving a load such as a relay or a motor with a large current. For example, the low side driver circuit includes a power transistor provided between an output terminal and a ground terminal, and drives a load by controlling on / off of the power transistor. In recent years, in a communication system such as LIN (Local Interconnect Network) or K-Line for communication between in-vehicle ECUs (Electrical Control Units), a signal line (bus) connected to an output terminal of the ECU is driven. A low-side driver circuit is used as the driver circuit. For example, in the communication system of LIN, the output terminal of the low side driver in each ECU is commonly connected to one bus, and the bus is connected to a battery via a pull-up resistor. Each ECU receives signals by receiving the bus voltage at the receiving circuit, and transmits signals by turning on and off the power transistors in the output stage of the low-side driver circuit.

  The low-side driver circuit applied to a communication system such as LIN protects the low-side driver circuit from being destroyed when an ESD that generates a positive voltage exceeding the battery voltage (about 18V to 24V) occurs at the output terminal. Must. Therefore, as disclosed in Patent Documents 1 and 2, the low-side driver circuit activates the power transistor connected to the output terminal and absorbs the current when the terminal voltage becomes equal to or higher than the set clamp voltage (hereinafter, referred to as the following). , Referred to as an active clamping operation), a rise in the voltage in the positive direction of the output terminal is suppressed.

JP 2008-35067 A JP 2001-44291 A

  The low-side driver circuit needs to protect not only the application of a positive high voltage but also the application of a negative high voltage. For example, a low-side driver circuit applied to a communication system such as LIN requires protection even when an ESD that generates a negative voltage occurs or when a battery is reversely connected. In the low-side driver circuit having the circuit configuration described in Patent Document 1 or Patent Document 2, even if a negative voltage is applied to the output terminal, the output terminal is connected to the output terminal from the ground terminal via the body diode of the power transistor in the output stage. Therefore, an increase in the negative voltage at the output terminal can be suppressed. However, depending on the system to which the low-side driver circuit is applied, there is a case where a characteristic that starts to flow current when a negative voltage exceeding a predetermined magnitude is applied may be required. For example, a low-side driver circuit applied to a LIN communication system is required to have a characteristic in which a current starts to flow from about −18 V in order to prevent destruction due to reverse connection of a battery. Therefore, in a low-side driver circuit applied to such a system, backflow prevention is prevented between the drain electrode and the output terminal of the power transistor so that no current flows to the output terminal via the body diode of the power transistor when a negative voltage is applied. In addition, an ESD protection circuit that starts flowing current when a negative voltage exceeding a predetermined magnitude is applied is separately provided between the output terminal and the ground terminal. As a result, the circuit scale has been increased.

  In addition, when a low-side driver circuit is manufactured by a bulk process, desired characteristics may not be obtained due to an undesired operation of a parasitic diode formed between a circuit element and a substrate (substrate) when a negative voltage is applied. There was a problem that sufficient ESD tolerance could not be obtained. For this reason, many of the low-side driver circuits are manufactured by an SOI (Silicon On Insulator) process, resulting in an increase in chip cost.

  Therefore, the inventor of the present application considered that a new technology for reducing the cost is required in a semiconductor device that requires a high breakdown voltage.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the semiconductor device is provided on a semiconductor substrate between a power transistor provided between the first external terminal and the second external terminal, and between the first external terminal and the gate electrode of the power transistor. A clamp circuit; and a resistance circuit provided between the gate electrode of the power transistor and the second external terminal. The semiconductor device further includes an N-channel first MIS transistor having a source electrode and a back gate electrode connected to the first external terminal and a drain electrode connected to the drain electrode of the power transistor, and the gate electrode and the source of the first MIS transistor. A first resistance element provided between the electrodes and a second resistance element provided between the gate electrode and the drain electrode of the first MIS transistor.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the semiconductor device, the manufacturing cost can be reduced.

FIG. 1 is a block diagram illustrating a semiconductor device according to a representative embodiment of the present application. FIG. 2 is a block diagram illustrating a communication system according to an embodiment of the present application. FIG. 3 is a block diagram illustrating an internal configuration of ECU 1_1 according to the first embodiment. FIG. 4 is an explanatory diagram illustrating the IV characteristics of the input / output terminal LDD in the low-side driver circuit 10. FIG. 5 is a block diagram illustrating a low-side driver circuit 30 as a comparative example. FIG. 6 is a block diagram illustrating the internal configuration of the low-side driver circuit 20 according to the second embodiment.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (Low-side driver circuit that doubles as a backflow prevention diode and a transistor constituting an active clamp circuit for negative voltage)
As shown in FIG. 1, a semiconductor device (40, 1_1 to 1_n, 2_1 to 2_n) according to a representative embodiment of the present application includes a first external terminal (LDD) formed on a semiconductor substrate, Two external terminals (GND), a power transistor (MN0) provided between the first external terminal and the second external terminal, and a clamp circuit provided between the first external terminal and the gate electrode of the power transistor (14) The semiconductor device further includes a resistor circuit (15) formed between the gate electrode of the power transistor and the second external terminal formed on a semiconductor substrate, and a source electrode and a back gate electrode formed on the first external electrode. An N-channel first MIS transistor (MN1) connected to the terminal and having a drain electrode connected to the drain electrode of the power transistor. The semiconductor device further includes a first resistance element (R1) provided between a gate electrode and a source electrode of the first MIS transistor, formed on a semiconductor substrate, and a gate electrode and a drain electrode of the first MIS transistor. And a second resistance element (R2) provided between the two.

  In the semiconductor device according to item 1, when a positive voltage is applied to the first external terminal, the power transistor is turned on, whereby the body between the drain and source of the first MIS transistor is directed from the first external terminal toward the second external terminal. A current can flow through the diode. In addition, when a negative voltage is applied to the first external terminal when the power transistor is in an off state, the first MIS transistor is turned on when the applied negative voltage exceeds a predetermined magnitude. As a result, a current can flow from the second external terminal toward the first external terminal via the drain and source of the first MIS transistor. The magnitude of the negative voltage for turning on the first MIS transistor can be easily changed according to the resistance ratio between the first resistance element and the second resistance element. Therefore, according to the semiconductor device of item 1, the function of suppressing an increase in voltage when a negative voltage having a desired magnitude is applied can be realized with a smaller circuit scale, which contributes to a reduction in chip cost.

[2] (Backflow prevention by bulk process + PMOS body diode)
In the semiconductor device (1_1 to 1_n, 2_1 to 2_n) according to Item 1, the semiconductor substrate is a semiconductor substrate having a bulk structure. The clamp circuit includes a P-channel type second MIS transistor (MP5) having a drain electrode connected to the first terminal and a source electrode, a back gate electrode, and a gate electrode connected in common, and the second MIS transistor. A plurality of first diodes (ZD11 to ZD1m, D2) connected in series between the source electrode and the gate electrode of the power transistor;

  According to this, compared with the case where it manufactures by SOI process, reduction of manufacturing cost can be aimed at. Moreover, even when the semiconductor device is manufactured by a bulk process, it is possible to prevent an undesired reverse current flow to the first external terminal due to the parasitic diode between the substrate (substrate) being turned on, Desired characteristics and sufficient ESD tolerance can be realized. For example, since the body diode of the second MIS diode is used as a backflow prevention diode between the first external terminal and the first diode, the first diode is connected via the parasitic diode formed between the first clamp circuit and the substrate. It is possible to prevent current from flowing to the external terminal. Similarly, since the body diode of the first MIS diode is used as a backflow preventing diode between the first external terminal and the drain electrode of the power transistor, a parasitic diode formed between the substrate and the substrate is used. It is possible to prevent a current from flowing through the first external terminal.

[3] (Current source circuit (Embodiment 2))
In the semiconductor device (2_1 to 2_n) according to item 1 or 2, a first node (ND1) to which a gate electrode of the first MIS transistor and the first resistance element are connected in synchronization with a timing when the power transistor is turned on. And a current source circuit (21) for supplying a current.

  When a current is input from the current source circuit to the first node when the power transistor is turned on, a current flows into the first resistance element. Thereby, a voltage is generated between the gate and source of the first MIS transistor, and the first MIS transistor can be turned on. That is, when the power transistor is turned on, current can flow not only through the body diode between the drain and source of the first MIS transistor but also between the drain and source of the first MIS transistor. The resistance component between the first electrode and the drain electrode can be reduced. According to this, for example, when this semiconductor device is applied to a communication system such as a vehicle-mounted LIN, the nose margin when the signal level of the bus is set to a low level can be improved.

[4] (Connect a diode in series with resistor R2)
Any one of the semiconductor devices (1_1 to 1_n, 2_1 to 2_n) of Items 1 to 3 is provided between the gate electrode and the drain electrode of the first MIS transistor and connected in series to the second resistance element. It has a diode (D0). The second diode has an anode connected to the drain electrode side of the first MIS transistor.

  According to this, it is possible to prevent a current from flowing from the first external terminal via the first resistance element and the second resistance element when the power transistor is turned on. Thereby, the allowable current amount required for the first resistance element and the second resistance element can be suppressed. In addition, since the current output from the current source circuit can be prevented from flowing to the power transistor through the second resistance element, the first resistance element has a voltage drop sufficient to turn on the first MIS transistor. It is easy to generate.

[5] (Back-flow prevention diode to power supply terminal)
In the semiconductor device (2_1 to 2_n) according to Item 3 or 4, a third external terminal (VIN) that receives supply of power supply voltage, and a signal path that supplies the power supply voltage supplied to the third external terminal to the current source circuit And. The signal path includes a third diode (D1) having an anode connected to the third external terminal side.

  According to this, for example, when a positive ESD is applied to the first external terminal or the second external terminal, it is possible to prevent a current from flowing backward through the current source circuit toward the third external terminal. it can.

[6] (Specific example of current source circuit)
In the semiconductor device according to any one of Items 3 to 5, the current source circuit is generated based on a constant current circuit (I1) that generates a constant current and an input current that is operable by power feeding from the signal path. A current mirror circuit (210) for outputting a mirror current to the first node. The semiconductor device further includes a switch element (211) that controls supply and stop of the current generated by the constant current circuit to the current mirror circuit.

  According to this, the function of supplying current to the first node in synchronization with the timing when the power transistor is turned on can be easily realized.

[7] (Cascode current mirror)
In the semiconductor device according to Item 6, the current mirror circuit includes cascode-connected transistors (MP3 and MP4).

  According to this, the accuracy of the current supplied to the first node can be improved.

[8] (Zener diode)
In the semiconductor device according to any one of Items 2 to 7, the plurality of first diodes include zener diodes (ZD11 to ZD1m).

  According to this, a clamp voltage can be easily generated.

[9] (Pre-driver)
Any one of the semiconductor devices (1_1 to 1_n, 2_1 to 2_n) according to any one of Items 1 to 8, in response to a gate control signal (TXD) instructing on / off of the power transistor, the power to the gate electrode of the power transistor. A drive voltage generation unit (12) that outputs a drive voltage for driving the transistor is further included.

[10] (Receiving unit + controller)
The semiconductor device according to Item 9 includes a receiving unit (13) that receives a signal input to the first external terminal, and a control unit that receives the signal received by the receiving unit and generates the gate control signal ( 11).

[11] (Communication system)
A communication system (U1, U2) according to a typical embodiment of the present application includes a signal line (2) for performing communication, and a pull-up resistor provided between a power supply voltage (VBAT) and the signal line. (RL) and a plurality of semiconductor devices (1_1 to 1_n, 2_1 to 2_n) according to any one of Items 1 to 10. In each of the semiconductor devices, the first external terminal is commonly connected to the signal line.

  According to this, it becomes possible to aim at the cost reduction as the whole communication system.

2. Details of Embodiments Embodiments will be further described in detail.

<< Embodiment 1 >>
FIG. 2 is a block diagram illustrating a communication system according to an embodiment of the present application.

  The communication system U1 shown in the figure is, for example, a part of an automobile control system and constitutes a LIN (Local Interconnect Network) for performing communication between a plurality of ECUs (Electrical Control Units). The communication system U1 includes, for example, a master ECU 1_1, a plurality of slave ECUs 1_2 to 1_n (n is an integer of 2 or more), a signal line (bus) 2, and a pull-up resistor RL. . The ECUs serving as slaves include, for example, ECU 1_3 for airbag control, ECUs 1_4 and 1_5 for body control, and the like. In the communication system U1, for example, each of the ECUs 1_1 to 1_n is connected to one signal line (bus) 2 in common, and the bus 2 is connected to the battery VBAT (hereinafter referred to as reference symbol VBAT is output from the battery) via the pull-up resistor RL. Also represents the battery voltage to be used.). The ECUs 1_1 to 1_n mutually transmit and receive signals (data) via respective input / output terminals (for example, input / output terminals LDD) connected to the bus 2.

  FIG. 3 illustrates an internal configuration of the ECU 1_1. Each of the ECUs 1_1 to 1_n includes a functional unit for transmitting and receiving signals (data) between the ECUs 1_1 to 1_n via the bus 2. Although not particularly limited, the functional units in the ECUs 1_1 to 1_n have the same circuit configuration, and thus the ECU 1_1 will be typically described in detail. The ECUs 1_1 to 1_n include circuit units for realizing functions unique to each ECU as other functional units, but are not illustrated in the figure, and only functional units for transmitting and receiving signals are illustrated. .

  The ECU 1_1 is a semiconductor device configured to include, for example, a control unit (CNT) 11 and a low side driver circuit (LOW_DRV) 10. The control unit 11 and the low side driver circuit 10 are not particularly limited, but are configured by separate semiconductor chips. For example, the control unit 11 is a semiconductor integrated circuit formed on a single semiconductor substrate such as single crystal silicon by, for example, a known CMOS integrated circuit manufacturing technique. The control unit 11 is a microcontroller, for example, and controls data transmission / reception by the low-side driver circuit 10.

  The low-side driver circuit 10 is a semiconductor formed on a single semiconductor substrate such as single crystal silicon by a high-voltage technology such as a BiC-DMOS process, which is a known bulk process manufacturing technique using PN junction isolation. Integrated circuit. As a typical example of various transistors constituting the low-side driver circuit 10, a MISFET (Metal Insulator Semiconductor Transistor) that can be represented by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. In the present embodiment, each transistor is described as being a MOS transistor unless otherwise specified, and unless otherwise apparent from the context. However, the present invention is not strictly limited thereto.

  Specifically, the low-side driver circuit 10 includes a receiving unit 13 that receives data, a transmitting unit that transmits data, an input / output terminal LDD, and a ground terminal GND.

  The input / output terminal LDD is an external connection terminal connected to the bus 2 and supplied with the battery voltage VBAT via the pull-up resistor RL. Although not particularly limited, the battery voltage VBAT is a voltage of about 18 to 24 V at the maximum, for example. The ground terminal GND is an external connection terminal that receives a ground voltage.

  The receiving unit (RCVR) 13 inputs a signal (data) supplied to the input / output terminal LDD and gives it to the control unit 11. Specifically, the receiving unit 13 generates binary data according to the signal level of the input / output terminal LDD, and supplies the binary data to the control unit 11.

  The transmission unit that transmits data includes, for example, an output stage power transistor MN0, a clamp circuit 14, a pull-down circuit 15, a negative voltage control circuit 16, and a pre-driver circuit (PRE_DRV) 12.

  The power transistor MN0 in the output stage is a high breakdown voltage transistor, for example, a DMOS (Double-Diffused MOSFET) transistor. The source electrode of the power transistor MN0 is connected to the ground terminal GND, the drain electrode is connected to the negative voltage control circuit 16, and the gate electrode is connected to the output terminal of the pre-driver circuit 12. The pre-driver circuit 12 controls on / off of the power transistor MN0 by supplying a drive voltage generated based on the control signal TXD output from the control unit 11 to the gate electrode of the power transistor MN0. For example, the pre-driver circuit 12 outputs a driving voltage for turning on the power transistor MN0 when a low level control signal TXD is input, and turns off the power transistor MN0 when a high level control signal TXD is supplied. The drive voltage to be output is output. This realizes data transmission to the bus 2 via the input / output terminal LDD.

  The pull-down circuit 15 is connected between the gate and source of the power transistor MN0 and has a function of discharging the charge of the gate electrode. The pull-down circuit 15 is composed of, for example, a resistance element RG, and statically turns off the power transistor MN0 even when the power supply and the control signal TXD are not supplied to the low-side driver circuit 10.

  The clamp circuit 14 clamps the voltage between the drain and gate of the power transistor MN0. The clamp circuit 14 includes, for example, a plurality of Zener diodes ZD11 to ZD1m (m is an integer of 2 or more) connected in series, a diode D2, and a transistor MP5. The transistor MP5 is, for example, a high breakdown voltage P-channel MOS transistor, the drain electrode is connected to the input / output terminal LDD, and the gate electrode, the source electrode, and the back gate electrode are commonly connected to the cathode of the Zener diode ZD11. The As a result, the anode side of the body diode DP2 of the transistor MP5 is connected to the input / output terminal LDD. Zener diodes ZD11 to ZD1m are connected in series in the same direction. The cathode of the Zener diode ZD11 is connected to the source electrode (gate electrode, back gate electrode) of the transistor MP5, and the anode of the Zener diode ZD1m is connected to the anode of the diode D2. The Zener voltage for one Zener diode ZD11 to ZD1m is, for example, 6V. The diode D2 is a PN diode, for example, and its forward voltage is smaller than the Zener voltage for one of the Zener diodes ZD11 to ZD1m. The cathode of the diode D2 is connected to the gate electrode of the power transistor MN0 and the resistance element RG.

  The clamp circuit 14 determines a voltage (clamp voltage) that activates the power transistor MN0 and absorbs current by activating the power transistor MN0 in accordance with the positive voltage applied to the input / output terminal LDD. Specifically, the clamp voltage is determined by the total voltage of m Zener voltages of the Zener diodes ZD11 to ZD1m, the forward voltage of the diode D2, and the forward voltage of the body diode DP2. For example, the magnitude of the clamp voltage can be adjusted by changing the number of Zener diodes ZD11 to ZD1m connected in series, the number of diodes D2, and the like. Although not particularly limited, the present embodiment exemplifies a case where the clamp voltage is set to 50V. For example, when the voltage of the input / output terminal LDD exceeds 50V, current flows from the input / output terminal LDD to the resistance element RG via the body diode DP2, the Zener diodes ZD11 to ZD1m, and the diode D2, thereby causing the gate of the power transistor MN0. An active clamp operation in which the voltage rises and the power transistor MN0 is turned on is started.

  When a negative voltage exceeding a predetermined magnitude is applied to the input / output terminal LDD, the negative voltage control circuit 16 suppresses an increase in the negative voltage by performing an active clamp operation for turning on the MOS transistor. The negative voltage control circuit 16 includes, for example, a transistor MN1, resistance elements R1 and R2, and a diode D0. The transistor MN1 is, for example, a high breakdown voltage N-channel MOS transistor, and the source electrode and the back gate electrode are connected to the input / output terminal LDD, and the drain electrode is connected to the drain electrode of the power transistor MN0. As a result, the anode of the body diode DP1 of the transistor MN1 is connected to the input / output terminal LDD side, and the cathode is connected to the drain side of the power transistor MN0. The resistor element R1 has one end connected to the source electrode of the transistor MN1 and the other end connected to the gate electrode of the transistor MN1. The resistance element R2 is connected between the gate electrode and the drain electrode of the transistor MN1. Specifically, one end of the resistance element R2 is connected to the gate electrode of the transistor MN1, and the other end is connected to the cathode of the diode D0. The diode D0 has an anode connected to the drain electrode of the power transistor MN0 and the drain electrode of the transistor MN1. The diode D2 is, for example, a PN diode.

  Next, the operation of the low side driver circuit 10 will be described in detail.

  When receiving data, the low-side driver circuit 10 operates as follows. In this case, the control unit 11 outputs a high level control signal TXD. As a result, the pre-driver circuit 12 in the low-side driver circuit 10 turns off the power transistor MN0. The receiving unit 13 generates binary data based on the voltage level of the input / output terminal LDD and supplies the binary data to the control unit 11.

  When transmitting data, the low-side driver circuit 10 operates as follows. In this case, the control unit 11 switches and outputs the signal level of the control signal TXD according to the data to be transmitted. The pre-driver circuit 12 in the low-side driver circuit 10 binarizes the voltage level of the input / output terminal LDD by turning on / off the power transistor MN0 according to the signal level (high level or low level) of the control signal TXD, Data is transmitted on the bus 2. For example, when the power transistor MN0 is off, no current flows because the body diode DP0 is also reverse-biased. Thereby, the voltage level of the input / output terminal LDD becomes a high level. When the power transistor MN0 is on, a current flows from the battery VBAT to the power transistor MN0 via the pull-up resistor RL, the bus 2, the input / output terminal LDD, and the body diode DP1 of the transistor MN1. Thereby, the voltage level of the input / output terminal LDD becomes a low level. At this time, since the diode D0 is reverse-biased, no current flows through the resistance elements R1 and R2. Thereby, the allowable current amount required for the resistance elements R1 and R2 can be suppressed. The transistor MN1 is also turned off.

  When positive ESD is applied to the input / output terminal LDD, the low-side driver circuit 10 operates as follows. When the voltage at the input / output terminal LDD exceeds the clamp voltage (50V), current flows from the input / output terminal LDD to the resistance element RG via the body diode DP2, the Zener diodes ZD11 to ZD1m, and the diode D2, and the gate of the power transistor MN0. The voltage rises. When the gate voltage exceeds the threshold voltage of the power transistor MN0, the power transistor MN0 is turned on, and a current flows from the input / output terminal LDD to the ground node via the parasitic diode DP1, the power transistor MN0, and the ground terminal GND. Thereby, the voltage rise of the input / output terminal LDD is suppressed. Thereafter, as the current increases, the drain-source voltage of the power transistor MN0 increases, and the current is absorbed until the breakdown voltage is reached.

  When a negative voltage is applied to the input / output terminal LDD due to reverse battery connection or negative ESD, the operation is as follows. In this case, since the body diode DP1 of the transistor MN1 is reverse-biased, no current flows from the ground terminal GND to the input / output terminal LDD via the body diode DP1. When a negative voltage exceeding the total voltage of the forward voltage of the body diode DP0 of the power transistor MN0 and the forward voltage of the diode D0 is applied to the input / output terminal LDD, the body diode DP0, the diode D0, and the resistance element R1, from the ground terminal GND, A current flows to the input / output terminal LDD via R2. When the negative voltage at the input / output terminal LDD further increases, the current flowing through the resistance elements R1 and R2 increases, and the voltage between the gate and source of the transistor MN1 (the voltage across the resistance element R1) increases. When the voltage between the gate and source of the transistor MN1 exceeds the threshold voltage of the transistor MN1, the transistor MN1 is turned on. As a result, a current can flow from the ground terminal GND to the input / output terminal LDD through the body diode DP0 of the power transistor MN0 and the drain / source of the transistor MN1, and an increase in negative voltage can be suppressed. The magnitude of the negative voltage of the input / output terminal LDD that turns on the transistor MN1 is determined by the forward voltage of the body diode DP0 of the power transistor MN0, the forward voltage of the diode D0, and the resistance values of the resistance elements R1 and R2. In particular, the magnitude of the negative voltage at which the power transistor MN0 is turned on can be easily adjusted by adjusting the resistance ratio of the resistance elements R1 and R2. Although not particularly limited, in this embodiment, the resistance ratio of the resistance elements R1 and R2 is adjusted so that the transistor MN1 is turned on when a negative voltage of −18V is applied.

  FIG. 4 illustrates the IV characteristics of the input / output terminal LDD in the low-side driver circuit 10. In the figure, the vertical axis represents the current Iout input to the input / output terminal LDD, and the horizontal axis represents the voltage Vout of the input / output terminal LDD with respect to the ground terminal GND. The figure illustrates an Iout-Vout characteristic 500 when the control signal TXD is at a high level (the power transistor MN0 is in an off state).

  As indicated by reference numeral 500, when the voltage Vout is in the range from 0V to the clamp voltage (50V), the current Iout does not flow because the power transistor MN0 is off. When the voltage Vout exceeds the clamp voltage (50V), the current Iout starts to flow by starting the active clamp operation, and the increase in the voltage Vout is suppressed. As indicated by reference numeral 500, when a negative voltage in the range of 0V to −18V is applied to the input / output terminal LDD, the body diode DP1 of the transistor MN1 is reverse-biased, so that the current Iout does not flow. When the voltage Vout becomes −18 V, the active clamp operation by the transistor MN1 is started, so that the current Iout (negative current) flows from the ground terminal GND to the input / output terminal LDD through the body diode DP0 of the power transistor MN0 and the transistor MN1. ) Begins to flow, and the increase in negative voltage is suppressed.

  As described above, the low-side driver circuit 10 can suppress the voltage rise by the active clamp operation by the power transistor MN0 against the application of a positive high voltage to the input / output terminal LDD. Further, with respect to the application of a negative voltage to the input / output terminal LDD, the negative voltage control circuit 16 can realize a characteristic in which a current starts to flow when a negative voltage of a desired magnitude is applied by an active clamp operation. An increase in voltage can be suppressed.

  Here, as a comparative example, FIG. 5 illustrates a low-side driver circuit 30 in a case where the backflow prevention of the current through the body diode D0 when a negative voltage is applied and the ESD protection against the negative voltage are realized by separate circuits.

  As shown in the figure, the low-side driver circuit 30 includes a PN diode D1 between the input / output terminal LDD and the drain electrode of the power transistor MN0, thereby reducing the body diode DP0 of the power transistor MN0 when a negative voltage is applied. Prevents reverse current flow. Further, by connecting the ESD protection circuit 31 between the input / output terminal LDD and the ground terminal GND, ESD protection against a negative voltage is realized. As shown in FIG. 5, the circuit scale of the low-side driver circuit 30 is increased by separately configuring the backflow prevention diode D1 and the ESD protection circuit 31. On the other hand, according to the low-side driver circuit 10 according to the present embodiment, the active clamp operation by the transistor MN1 is realized using the resistance elements R1 and R2, and the body diode DP1 of the transistor MN1 is used as a diode for preventing backflow. The circuit scale can be further reduced.

  When the low-side driver circuit 30 shown in FIG. 5 is formed on a bulk substrate by a bulk process technique using PN junction isolation, each circuit element is connected to the substrate (substrate) SUB via a parasitic diode. . For example, as shown in FIG. 5, a parasitic diode DPX3 exists between the anode side of the diode D3 and the substrate, a parasitic diode DPX1 exists between the anode side of the diode D1 and the substrate, and between the anode side of the diode D4 and the substrate. There is a parasitic diode DPX4. Due to the presence of these parasitic diodes, the Iout-Vout characteristic of the low-side driver circuit 30 becomes, for example, a reference numeral 501 in FIG. Specifically, as indicated by reference numeral 501, the parasitic diode should originally have a characteristic that current does not flow until the negative voltage becomes −18 V, but before it becomes −18 V (for example, at −2 V). When DP1X, DPX3, etc. are turned on, current may flow from the substrate SUB to the input / output terminal LDD via the parasitic diodes DP1X, DPX3, etc. In order to prevent this, as described above, it is an effective method to form the low-side driver circuit 30 on the SOI substrate by the SOI process technology. However, the manufacturing cost increases as compared with the bulk process. On the other hand, according to the low-side driver circuit 10 according to the present embodiment, by using the body diode DP2 of the transistor MP5 instead of the diode D3, the current path flowing from the substrate SUB to the input / output terminal LDD via the transistor MP5. Is not formed. Further, by using the body diode DP1 of the transistor MP1 instead of the backflow preventing diode D1, a current path flowing from the substrate SUB to the input / output terminal LDD via the transistor MN1 is not formed. Therefore, even when the low-side driver circuit 10 is manufactured by a bulk process, it is possible to prevent formation of an undesired current path due to a parasitic diode between the substrate and a desired characteristic and sufficient ESD tolerance are realized. However, the manufacturing cost can be further reduced. Thereby, the cost reduction of the communication system U1 whole can be achieved.

<< Embodiment 2 >>
FIG. 6 is a block diagram illustrating an internal configuration of the communication system U2 according to the second embodiment. In addition to the function of the low-side driver circuit 10 according to the first embodiment, the low-side driver circuit 20 in the ECUs 2_1 to 2_n shown in the figure includes a connection between the input / output terminal LDD and the ground terminal GND when the power transistor MN0 is turned on. It has a function of reducing the resistance component. Specifically, the low side driver circuit 20 further includes a current source circuit 21 and a logic circuit 22 in addition to the functional units of the low side driver circuit 10. In the figure, the same components as those of the low-side driver circuit 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The current source circuit 21 supplies current to the node ND1 to which the gate electrode of the transistor MN1 and the resistance elements R1 and R2 are connected in synchronization with the timing when the power transistor MN0 is turned on. Specifically, the current source circuit 21 includes, for example, a current mirror circuit (CUM) 210, a switch circuit 211, and a constant current source circuit I1.

  The current mirror circuit 210 outputs a mirror current generated according to the input current to the node ND1. The current mirror circuit 210 includes transistors MP1 to MP4, for example. The mirror ratio of the current mirror circuit 210 (transistor size ratio of the transistors MP1 to MP4) can be appropriately changed according to the magnitude of the input current and the generated mirror current. Although not particularly limited, the present embodiment exemplifies a case where the mirror ratio is “1: 1”. The transistors MP1 and MP2 are, for example, low breakdown voltage P-channel MOS transistors. The transistors MP1 and MP2 have source electrodes connected in common and are connected to the power supply terminal VIN via the diode D5. The gate electrode and the drain electrode of the transistor MP1 are connected in common and are connected to the source electrode of the transistor MP3. The transistor MP2 has a gate electrode connected to the gate electrode of the transistor MP1, and a drain electrode connected to the source electrode of the transistor MP4. The transistors MP3 and MP4 are, for example, high breakdown voltage P-channel MOS transistors. The transistor MP3 has a gate electrode and a drain electrode connected in common and connected to the switch circuit 211, and a source electrode connected to the gate electrode and the drain electrode of the transistor MP1. Transistor MP4 has a gate electrode connected to the gate electrode of transistor MP3 and a drain electrode connected to node ND1. The power supply terminal VIN is an external connection terminal that receives power supply and is not particularly limited, but a power supply voltage higher than the battery voltage VBAT is input. The diode D5 is a PN diode, for example, and has an anode connected to the power supply terminal VIN side and a cathode connected to the current mirror circuit side. As a result, the power supply voltage can be supplied from the power supply terminal VIN to the current mirror circuit 210, and the current to the power supply terminal VIN via the current mirror circuit 21 due to the application of positive ESD to the input / output terminal LDD and the ground terminal GND. Prevent backflow.

  The constant current source circuit I1 generates and outputs a constant current. The reference symbol I1 represents not only the constant current source circuit but also the current output from the constant current source circuit.

  The switch circuit 211 controls the supply and stop of the constant current I1 to the current mirror circuit 210. The switch circuit 211 is composed of, for example, an N channel type MOS transistor MN2. The transistor MN2 has a gate terminal connected to the output terminal of the logic circuit 22, a source electrode connected to the constant current source circuit I1, and a drain electrode connected to the gate electrode and the drain electrode of the transistor MP3. The logic circuit 22 receives the control signal TXD output from the control unit 11 and drives the gate of the transistor MN2. The logic circuit 22 is, for example, an inverter circuit.

  When the high-level control signal TXD is input from the control unit 11 to the low-side driver circuit 20, the pre-driver circuit 12 turns off the power transistor MN0. The logic circuit 22 outputs a low level voltage in response to the high level control signal TXD, and turns off the transistor MN2. Thereby, the supply of the constant current I1 to the current mirror circuit 21 is stopped, and the mirror current is not supplied to the node ND1.

  When the low-level control signal TXD is input from the control unit 11 to the low-side driver circuit 20, the pre-driver circuit 12 turns on the power transistor MN0. The logic circuit 22 outputs a high level voltage in response to the low level control signal TXD, and turns on the transistor MN2. As a result, the constant current I1 is supplied to the current mirror circuit 210, and the mirror current is supplied to the node ND1. The mirror current first flows into the power transistor MN0 via the resistor element R1 and the body diode DP1 of the transistor MN1. As a result, a voltage VGS is generated between the gate and source of the transistor MN1. At this time, since the mirror current does not flow into the resistance element R2 but flows into the resistance element R1 due to the reverse-biased diode D0, the magnitude of the voltage VGS is determined by “R1 × I1”. Therefore, by setting the resistance value of the resistance element R1 and the magnitude of the constant current I1 (or mirror ratio) so that the voltage VGS is greater than or equal to the threshold voltage of the transistor MN1, the power transistor MN0 The transistor MN1 can be turned on while it is on. As a result, the on-resistance between the input / output terminal LDD and the ground terminal GND when the power transistor MN0 is on can be reduced, and the voltage when the input / output terminal LDD is set to the low level can be further reduced. be able to. Thereby, the noise margin for the receiving unit 13 in the low-side driver circuit 20 can be increased.

  For example, in the case of the low side driver circuit 10 shown in FIG. 3 or the low side driver circuit 30 shown in FIG. 5, the voltage (hereinafter referred to as the low voltage) VLO of the input / output terminal LDD when the power transistor MN0 is turned on is: Since the forward voltage of the diode DP1 or the diode D1 is added, the value is about 1V. The noise margin in this case is, for example, that the battery voltage VBAT at the time of reduced voltage is 5 V, the reception threshold by the receiver 13 is 0.45 to 0.55 VBAT (= 2.25 to 2.75 V), and the low voltage VLO is 1 V. 1.25V. On the other hand, according to the low side driver circuit 20 according to the present embodiment, as described above, the transistor MN0 is turned on while the power transistor MN0 is on, so the low voltage VLO is lower (for example, about 0.5V). The noise margin can be improved. In general, since the noise inside the automobile is relatively large, it is better that the noise margin of the receiving unit in the in-vehicle low-side driver circuit is larger. Therefore, it is particularly effective if the low-side driver circuit 20 is applied to a system having a relatively large noise such as an automobile.

  As described above, according to the low-side driver circuit 20 according to the second embodiment, similarly to the low-side driver circuit 10 according to the first embodiment, it is possible to reduce the manufacturing cost of the chip, and to reduce the cost of the entire communication system U2. Can be planned. Further, according to the low-side driver circuit 20, the low voltage VLO can be further reduced, so that the noise margin on the signal reception side can be improved.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the first and second embodiments, the case where the low-side driver circuits 10 and 20 are applied to LIN is exemplified. However, other in-vehicle communication systems such as K-Line and CAN, and drive systems such as relays and motors It is also possible to apply to.

  In the first and second embodiments, the case where the low-side driver circuits 10 and 20 are manufactured by a bulk process is illustrated, but the low-side driver circuits 10 and 20 can also be manufactured by an SOI process. According to this, as described above, the transistor MN1 can be used as both a backflow preventing diode and a negative voltage active clamp circuit, so that the circuit scale can be reduced. In this case, the transistor MP5 in the clamp circuit 14 may be removed.

  In the first and second embodiments, the circuit configuration for generating the clamp voltage in the clamp circuit 14 is exemplified by the circuit configuration in which the plurality of Zener diodes ZD11 to ZD1m and the diode D2 are connected in series. However, a desired clamp voltage can be generated. If possible, another circuit configuration may be used. For example, you may comprise only a Zener diode, without using the diode D2.

  In the first and second embodiments, the power transistor MN0 is a DMOS. However, the power transistor MN0 may be an IGBT (Insulated Gate Bipolar Transistor), a super junction structure MOS transistor, or the like. It is not limited.

  Although the cascode-type current mirror circuit 210 is exemplified in the second embodiment, the present invention is not limited to this, and there is no particular limitation as long as it is a circuit that supplies a current generated based on the constant current I1 to the node ND1. For example, a non-cascode current mirror circuit in which the transistors MP3 and MP4 are removed may be used. In this case, the transistors MP1 and MP2 are preferably constituted by high breakdown voltage MOS transistors.

  In the second embodiment, the case where the voltage supplied to the power supply terminal VIN is larger than the battery voltage VBAT is exemplified, but the present invention is not limited to this. For example, a voltage having the same magnitude as the battery voltage VBAT may be supplied to the power supply terminal VIN.

U1 communication system 1_1 to 1_n ECU
2 signal lines (bus)
RL Pull-up resistor VBAT Battery voltage LDD I / O terminal GND Ground terminal 10 Low-side driver circuit 11 Control unit 12 Pre-driver circuit 13 Reception unit 14 Clamp circuit 15 Pull-down circuit 16 Negative voltage control circuit MN0 Power transistor RG, R1, R2 Resistance element D0 , D1 diode DP0, DP1, DP2 body diode ZD11-ZD1m Zener diode MP5, MN1 transistor TXD control signal 500 Iout-Vout characteristic of low-side driver circuit 501 Iout-Vout characteristic of low-side driver circuit 30 low-side driver circuit 31 ESD protection circuit 32 Clamp circuit D3, D4 Diode R3 Resistance element DPX1, DPX3, DPX4 Parasitic diode SUB Substrate Sub-straight)
U2 communication system 2_1 to 2_n ECU
VIN power supply terminal 20 low side driver circuit 21 current source circuit 22 logic circuit 210 current mirror circuit 211 switch circuit D5 diode MP1 to MP4, MN2 transistor

Claims (11)

A first external terminal;
A second external terminal;
A power transistor provided between the first external terminal and the second external terminal;
A clamp circuit provided between the first external terminal and the gate electrode of the power transistor;
A resistance circuit provided between the gate electrode of the power transistor and the second external terminal;
An N-channel first MIS transistor having a source electrode and a back gate electrode connected to the first external terminal and a drain electrode connected to the drain electrode of the power transistor;
A first resistance element provided between a gate electrode and a source electrode of the first MIS transistor;
A semiconductor device in which a second resistance element provided between a gate electrode and a drain electrode of the first MIS transistor is formed on a semiconductor substrate. The semiconductor substrate is a bulk structure semiconductor substrate,
The clamp circuit is
A P-channel type second MIS transistor having a drain electrode connected to the first terminal and a source electrode, a back gate electrode, and a gate electrode connected in common;
The semiconductor device according to claim 1, further comprising: a plurality of first diodes connected in series between a source electrode of the second MIS transistor and a gate electrode of the power transistor.   3. The semiconductor according to claim 2, further comprising a current source circuit that supplies current to a first node to which a gate electrode of the first MIS transistor and the first resistance element are connected in synchronization with a timing at which the power transistor is turned on. apparatus. A second diode provided between a gate electrode and a drain electrode of the first MIS transistor and connected in series to the second resistance element;
The semiconductor device according to claim 3, wherein an anode of the second diode is connected to a drain electrode side of the first MIS transistor. A third external terminal for receiving power supply voltage;
A signal path for supplying the power source voltage supplied to the third external terminal to the current source circuit,
The semiconductor device according to claim 3, wherein the signal path includes a third diode having an anode connected to the third external terminal side. The current source circuit is:
A constant current circuit for generating a constant current;
A current mirror circuit that is operable by power feeding from the signal path and outputs a mirror current generated based on the input current to the first node;
The semiconductor device according to claim 5, further comprising: a switch element that controls supply and stop of the current generated by the constant current circuit to the current mirror circuit.   The semiconductor device according to claim 6, wherein the current mirror circuit includes a cascode-connected transistor.   The semiconductor device according to claim 2, wherein the plurality of first diodes include Zener diodes.   The drive voltage generation part which outputs the drive voltage for driving the power transistor to the gate electrode of the power transistor according to the gate control signal which directs on / off of the power transistor is provided. Semiconductor device. A receiving unit for receiving a signal input to the first external terminal;
The semiconductor device according to claim 9, further comprising a control unit that inputs a signal received by the receiving unit and generates the gate control signal. A signal line for communication;
A pull-up resistor provided between a power supply voltage and the signal line;
A plurality of semiconductor devices according to claim 10,
Each of the semiconductor devices is a communication system in which the first external terminal is commonly connected to the signal line.

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