JP6231793B2 - Differential signal transmission circuit - Google Patents

Description

  The present invention relates to a differential signal transmission circuit used in a CAN, FlexRay (registered trademark) network, in particular, in-vehicle, industrial equipment, medical equipment and the like.

For example, as a vehicle-mounted network, a bus system called a two-wire differential signal system or a differential transmission circuit, such as CAN (Controller Area Network) and FlexRay, is known. FlexRay was developed as the next generation standard for CAN. CAN is standardized by international standard ISO11898 or the like. Prior art documents relating to such CAN and FlexRay are disclosed in, for example, cited document 1, cited document 2, cited document 3, and cited document 4.

Cited Document 1 discloses a transceiver, a semiconductor device, and a communication system that can prevent deterioration in communication quality due to mismatch of capacitive impedance, and also discloses protection from ESD (Electro-Static Discharge). The cited document 2 alleviates the signal asymmetry in the signal transmission path driven by the differential signal transmission circuit, and reduces the radiation noise caused by the common mode current. Specifically, the slew rate of the gate potential of the P-channel transistor and the N-channel transistor is controlled to reduce the radiation noise radiated from the signal transmission path toward the periphery. Cited Document 3 discloses a differential signal transmission circuit applicable to FlexRay. Cited Document 4 provides an output driver circuit capable of increasing the communication speed. Since a relatively large capacity is added to the positive differential output node and the negative differential output node, the communication speed cannot be increased. In order to overcome such a problem, it is disclosed to provide a current circuit for supplying a charging current and a discharging current to both output nodes.

FIG. 10 shows a conceptual diagram of a well-known CAN. The CAN 900 includes a microcontroller 910, a CAN protocol controller 920, a transceiver 930, a high side output terminal CANH, a low side output terminal CANL, a first bus line SH, and a second bus line SL. A CAN signal (differential signal) is output between the first bus line SH and the second bus line SL, that is, between the high-side output terminal CANH and the low-side output terminal CANL. For example, an ECU (Electric controlled Unit) and a load resistor RL (not shown) are coupled to the first bus line SH and the second bus line SL. The load resistor RL is generally called a termination resistor, and is used to terminate both ends of the first bus line SH and the second bus line SL with a predetermined impedance. The impedance of one terminal resistor is defined as 120Ω (standard value) in ISO11898, and the load resistor RL plays a role of suppressing a reflected voltage from one terminal to the other terminal and adjusting a bus level.

A CAN protocol controller 920 incorporated in the microcontroller 910 controls the transceiver 930 and receives a reception signal from the transceiver 930. The transceiver 930 generates a bus transmission signal, that is, a signal transmitted to the first bus line SH and the second bus line SL, adjusts and secures an operating current, and protects each bus line.

When transmitting a signal to the first bus line SH and the second bus line SL, a digital signal TXD is sent from the port TX of the CAN protocol controller 920 to the transceiver 930.

JP 2011-35449 A JP 2005-260799 A JP 2007-318664 A JP 2011-166260 A

  The first object of the present invention is to increase the communication speed in CAN and FlexRay. The second purpose is to suppress the generation of electromagnetic interference (EMI). The third purpose is to improve surge resistance.

In this document, the main current path means a current path from the source to the drain and a current path from the drain to the source in the case of the PMOS transistor and the NMOS transistor, respectively. In the case of a PNP transistor and an NPN transistor, it indicates a current path from the emitter to the collector and a current path from the collector to the emitter, respectively. The control electrode refers to a gate in the case of a MIS transistor including a MOS transistor. In the case of a PNP transistor and an NPN transistor which are bipolar transistors, the control electrode indicates the base.

The differential signal transmission circuit (100) according to an embodiment of the present invention includes a power supply terminal (VCC1), a ground terminal (GND), a first main current path (Mi11), and a control electrode (N10). A high-side transistor (M11) that is coupled to the terminal (VCC1) and outputs a high level of the differential signal, and one end (N1) of the first main current path (Mi11) are coupled to transmit the high level of the differential signal. A first bus line (SH), one end of which is coupled to the high side output terminal (CANH), the high side output terminal (CANH), and one of the two bus lines (SH, SL); A load resistor (RL) whose first terminal is coupled to the other end of the bus line (SH), and one end of which is coupled to the second terminal of the load resistor (RL) and the other end of the two bus lines To the second bus line SL) and the first bus line (SH) And a second main current path (Mi21) having a low-side output terminal (CANL) to which the other end is coupled and the low level of the differential signal is transmitted, a second main current path (Mi21), and a control electrode (N20). ) Is coupled to the low-side output terminal (CANL) and the other end of the second main current path (Mi21) is coupled to the ground terminal (GND), and outputs a low-level transistor (M21) that outputs a low level differential signal. The high-side current adjusting unit (HC10) that is coupled to the control electrode (N10) of the side transistor (M11) and adjusts the current flowing through the first main current path (Mi11), and the control electrode (N20) of the low-side transistor (M21) The low-side current adjusting unit (LC20) that adjusts the current that flows through the second main current path (Mi21) is connected to one end (N1) of the first main current path (Mi11). A first constant current circuit (i3) coupled between the terminal (GND) and a second constant current coupled between one end (N2) of the second main current path (Mi21) and the power supply terminal (VCC1). And a current circuit (i6).

In the differential signal transmission circuit (100) according to another embodiment of the present invention, the high-side current adjustment unit (HC10) constitutes a high-side transistor (M11) and first current mirror circuits (M11, M21). The first transistor (M13) includes a first constant current source (i1) and a second constant current source (i2) having different current magnitudes, and the first transistor (M12) is coupled to the first transistor (M13). ), A constant current source obtained by adding one or both of the first constant current source (i1) and the second constant current source (i2) is selected and flows, and the constant current selected by the first transistor (M13) is selected. The current flowing through the first main current path (Mi11) of the high-side transistor (M11) is adjusted according to the source, and the low-side current adjustment unit (LC20) is connected to the low-side transistor (M21) and the second current. The third constant current source (i4) and the fourth constant current source (i5) have a second transistor (M23) constituting the error circuit (M21, M23). The second transistor (M23) has different current magnitudes. ), And the second transistor (M23) is selected and supplied with a constant current source obtained by adding one or both of the third constant current source (i4) and the fourth constant current source (i5). The current flowing through the main current path of the low-side transistor (M21) is adjusted according to the size of the constant current source selected by the two transistors (M23).

Furthermore, the differential signal transmission circuit (200) according to another embodiment of the present invention includes a power supply terminal (VCC), a ground terminal (GND), a first main current path (Mi31), and a first control electrode (N110). A first high side transistor (M31) coupled to a power supply terminal (VCC) and outputting a high level and a low level of a differential signal, a second main current path (Mi33), and a second control electrode (N130). A second high-side transistor (M33) coupled to the power supply terminal (VCC) and outputting a high level of the differential signal and a high level and a low level of the differential signal, a third main current path (Mi32), and a second 3 control electrodes (N120), and one end (N12) of the third current path (Mi32) is coupled between one end (N11) of the first main current path (Mi31) and the ground terminal (GND). First low side transition (M32), a fourth main current path (Mi34), and a fourth control electrode (N140), between one end (N13) of the second main current path (Mi33) and the ground terminal (GND). Common to the second low-side transistor (M34) to which the fourth current path (Mi34) is coupled, one end (N11) of the first main current path (Mi31), and one end (N12) of the third main current path (Mi32) Common connection between the first output terminal (BP) coupled to the connection point and outputting a bus signal, one end (N13) of the second main current path (Mi33), and one end (N14) of the fourth main current path (Mi34) A second output terminal (BM) coupled to a point and outputting a bus signal; a first bus line (SP) coupled to the first output terminal (BP) and the second output terminal (BM); and a second bus Between the line (SM) and the first bus line (SP) and the second bus line (SM) The load resistance (RL) combined with the first control electrode (N110), the second control electrode (N130), the third control electrode (N120), and the fourth control electrode (N140) are respectively coupled to the first high electrode. A first high-side current adjustment unit that adjusts current supplied to the side transistor (M31), the second high-side transistor (M33), the first low-side transistor (M32), and the second low-side transistor (M34) in two stages. HC10), a second high side current adjustment unit (HC10), a first low side current adjustment unit (LC20), and a second low side current adjustment unit (LC20), and a first main current path (Mi31) and a second main current A constant current circuit (i11, i13) is coupled separately between each end (N11, N13) of the path (Mi33) and the ground terminal (GND), and a third main current path ( A constant current circuit (i12, i14) is coupled between each end (N12, N14) of Mi32) and the fourth main current path (Mi34) and the power supply terminal (VCC).

According to the differential signal transmission circuit of the present invention, the communication speed can be increased and the generation of electromagnetic interference (EMI) can be suppressed. Furthermore, the surge resistance can be improved.

1 shows a differential signal transmission circuit according to a first embodiment of the present invention. 3 shows a differential signal transmission circuit according to a second embodiment of the present invention. The circuit connection and element arrangement | positioning figure by the side of the low side output terminal concerning the 2nd Embodiment of this invention are shown. The other circuit connection and element arrangement | positioning figure by the side of the low side output terminal concerning the 2nd Embodiment of this invention are shown. The differential signal transmission circuit examined in advance when implementing the first and second embodiments of the present invention is shown. The potentials of the main nodes and the CAN signal of the differential signal transmission circuit studied in advance when implementing the first and second embodiments of the present invention are shown. 3 shows potentials of main nodes and a CAN signal in the differential signal transmission circuit according to the first and second embodiments of the present invention. 4 schematically shows a slew rate at which the high-side transistor according to the first and second embodiments of the present invention transitions from on to off. 4 shows a differential signal transmission circuit according to a third embodiment of the present invention. 9 shows a differential signal transmission circuit according to a fourth embodiment of the present invention. 10 shows potentials of main nodes and a CAN signal of a differential signal transmission circuit according to a fourth embodiment of the present invention. A conceptual diagram of a well-known CAN is shown.

(First embodiment)
FIG. 1 shows a first embodiment of a differential signal transmission circuit used in a CAN compliant with ISO11898. The differential signal transmission circuit 100 includes a first power supply terminal VCC1, a second power supply terminal VCC2, and a ground terminal GND. The power supply voltage of the first power supply terminal VCC1 is 5V, and that of the second power supply terminal VCC2 is 1/2 of the first power supply terminal VCC1 and is 2.5V.

The differential signal transmission circuit 100 includes a high-side output unit 10, a low-side output unit 20, a resistance dividing circuit 30, a high-side output terminal CANH, a low-side output terminal CANL, a first bus line SH, a second bus line SL, and a resistance load RL. And an input signal TX1. One end of the first bus line SH is coupled to the high side output terminal CANH, and the other end is coupled to the first terminal of the load resistor RL. The second terminal of the load resistor RL is coupled to one end of the second bus line SL, and the other end of the second bus line SL is coupled to the low side output terminal CANL.

A differential signal (CAN signal) is output to both ends of the high-side output terminal CANH and the low-side output terminal CANL according to the low level L and high level H of the input signal TX1. Dominant and recessive are determined according to the level of the CAN signal. When the input signal TX1 is at the low level L, it is dominant and is logic "0". When the input signal TX1 is at the high level H, it is recessive and has a logic “1”.

Here is a brief description of dominant and recessive. The dominant is a logic “0” in CAN. At this time, a voltage of 3.5 V (standard value) is output to the high side output terminal CANH, and a voltage of 1.5 V (standard value) is output to the low side output terminal CANL, which are coupled to the first bus line SH and the second bus line SL. For example, all ECUs (not shown) are placed in a priority state and can communicate. Recessive is a logical “1” in CAN. At this time, a voltage of 2.5 V (standard value) is output to the high side output terminal CANH and a voltage of 2.5 V (standard value) is output to the low side output terminal CANL, which are coupled to the second bus line SH and the second bus line SL. For example, all of the ECUs (not shown) are placed in a receiving state. The relationship between dominant and recessive signal waveforms and levels will be described later.

  The differential signal transmission circuit according to the present invention is generally referred to as a two-wire differential signal system. For that reason, the first bus line coupled to the high-side output terminal CANH and the low-side output terminal CANL, respectively. This is based on the transmission system using the two lines of SH and the second bus line SL, and that these two lines take out differential signals, that is, voltages (CAN signals) whose polarities are inverted by 180 degrees.

The differential signal transmission circuit 100 is usually constituted by a semiconductor integrated circuit, but recently, a BiCDMOS process, that is, a manufacturing process in which a bipolar process, a CMOS process, and a DMOS process are integrated is often adopted. If the differential signal transmission circuit is configured by the BiCDMOS process, the high-side transistor M11 includes any one of a MOS transistor, a DMOS transistor, and a bipolar transistor, such as a transistor current capacity, on-resistance, switching response characteristics, and withstand voltage. Can be appropriately selected according to the target characteristics.

The high side output unit 10 outputs a high level signal (voltage) to the high side output terminal CANH. In CAN compliant with ISO11898, the high level signal has a minimum voltage value of 2.5V and a maximum value of 3.5V. The reason why the power supply voltage of the second power supply terminal VCC2 is set to 2.5V is to set the minimum voltage of the high side level to 2.5V. The high-side transistor M11 can be composed of, for example, a PMOS transistor, but a PNP-type bipolar transistor may be used.

In the embodiment of the present invention, for convenience of explanation, the high side transistor M11 is assumed to be a PMOS transistor. The source of the high side transistor M11 is connected to the first power supply terminal VCC1 together with its back gate. Accordingly, the source and back gate voltages of the high side transistor M11 are fixed to the power supply voltage 5V of the first power supply terminal VCC1.

The high-side current adjusting unit HC10 is coupled to the control electrode of the high-side transistor M11, that is, the gate indicated by the node N10. The high side current adjustment unit HC10 includes a transistor M13, constant current sources i1 and i2, and a switch SW11. The drain (source) current of the transistor M13 is substantially equal to the constant current source i1 when the switch SW11 is off (open), and when the switch SW11 is on (closed), the constant current source i2 is connected to the constant current source i1. It is almost equal to the added one. That is, the drain current of the transistor M13 is set in two different stages depending on whether the switch SW11 is on or off.

The transistor M13 is a PMOS type having the same conductivity type as the high-side transistor M11. The source of the transistor M13 is connected to the first power supply terminal VCC1 together with its back gate, and its gate and drain are connected in common and connected to a node N10 to which the gate of the high side transistor M11 is connected. The transistor M13 and the high side transistor M11 constitute a well-known current mirror circuit.

The magnitude of the main current (drain current) i11d flowing in the main current path Mi11 of the high-side transistor M11 constituting a part of the current mirror circuit is proportional to the magnitude of the current generated by the transistor M13. The control and adjustment of the main current i11d are performed by the high side current adjustment unit HC10.

A constant current source i1 is directly connected between the node N10 to which the high side current adjusting unit HC10 is coupled and the ground terminal GND. Of course, a switch (not shown) may be coupled between the node N10 and the constant current source i1, or between the constant current source i1 and the ground terminal GND, and the switch (not shown) may be controlled by the input signal TX1.

A constant current source i2 is coupled between the node N10 and the ground terminal GND via a switch SW11 in addition to the current path of the constant current source i1. When the switch SW11 is turned on (closed), the constant current source i2 becomes a current source in a current path from the node N10 side, that is, from the drain of the transistor M13 to the ground terminal GND. FIG. 1 shows a state where the switch SW11 is off, that is, an open state.

When the switch SW11 is off, that is, opened, a constant current source i1 that is not controlled by the switch SW11 and other switches flows as a drain (source) current of the transistor M13. The constant current source i1 is sufficient if it is enough to turn on the transistor M13 weakly. The weakly turned on transistor M13 is not sufficient to drive the high side transistor M11, but can be driven to such a degree that a relatively small current can flow through the high side transistor M11. Here, turning on strongly means that a voltage and current sufficient to drive the load are supplied. That is, the constant current source i1 is not required to have the driving capability for the high-side transistor M11 to flow the main current i11a to the high-side output terminal CANH and the load RL. That is, the constant current source i1 only needs to hold the potential V10 of the gate of the transistor M13 and the high-side transistor M11, that is, the node N10 at a predetermined level.

The potential V10H of the node N10 when only the constant current source i1 flows as the drain (source) current of the transistor M13 is V10H = (VCC1-VGS1). Here, VCC1 is a power supply voltage of the first power supply terminal VCC1, and VGS1 is a gate-source voltage necessary to flow the constant current source i1, that is, to turn on the transistor M13 weakly.

The switch SW11 responds to the input signal TX1. The combination of the low level L and high level H of the input signal TX1 and the on / off state of the switch SW11 is a design matter. For example, when the input signal TX1 is at the low level L, the switch SW11 is turned on (closed). When H, the switch SW11 can be selected to be turned off (open).

When the switch SW11 is turned on in response to the input signal TX1, a current path of the constant current source i2 is formed between the node N10 side and the ground terminal GND. At this time, a constant current source (i1 + i2) including a constant current source i1 and a constant current source i2 flows between the source and drain of the transistor M13, and the transistor M13 and the high side transistor M11 are strongly turned on. When both transistors are turned on strongly, the high side transistor M11 can output a predetermined CAN signal to both ends of the load resistor RL.

The potential V10L of the node N10 when both the transistors are strongly turned on is V10L = (VCC1-VGS2). Here, the voltage VGS2 is a gate-source voltage of the transistor M13 that is required to flow a current obtained by adding the constant current source i1 and the constant current source i2 as a drain (source) current. The gate-source voltage VGS1 is in a relationship of VGS2> VGS1.

That is, the gate-source voltage VGS2 becomes larger than the gate-source voltage VGS1 when the constant current source i1 is increased by the amount of increase of the constant current source i2. Therefore, when viewed from the ground terminal GND, the potential of the node N10 is lower when the switch SW11 is on than when it is off, so that the relationship of V10L <V10H is set. The difference between the potential V10H of the node N10 and the potential V1OL is determined according to the magnitudes of the constant current sources i1 and i2. In other words, the greater the difference between the two constant current sources, the greater the difference in gate-source voltage.

The gate potential of the high side transistor M11, that is, the potential V10 of the node N10 transitions between the potential V10L and the potential V10H when the switch SW11 is switched on and off. The difference between these potentials is much smaller than the potential difference 5V between the first power supply terminal VCC1 and the ground terminal GND, for example, in the range of 0.5V to 1V. In other words, the gate potential of the high-side transistor M11 when the input signal TX1 is switched from the high level H to the low level L or from the low level L to the high level H and the state of the CAN signal is switched from recessive to dominant or vice versa. The amount of change can be kept small. As a result, the time required for switching can be reduced, and the communication speed can be increased.

A drain which is one end of the main current path Mi11 of the high side transistor M11 is indicated by a node N1. The main current path Mi11 is a current path from the source to the drain of the high side transistor M11. Although the drain of the high-side transistor M11 is directly connected to the node N1 in FIG. 1, the circuit configuration is not limited to this. For example, one end of a resistor (not shown) may be connected to the drain of the high side transistor M11, and the other end may be connected to the node N1. The node N1 is connected to the anode of the backflow prevention diode D11, and its cathode is connected to the high side output terminal CANH. That is, the backflow prevention diode D11 is connected in series with the main current path Mi11 and in the forward direction.

Although the backflow prevention diode D11 is not an essential constituent element in the present invention, when any surge voltage arrives at the high-side output terminal CANH, the current in the direction opposite to the current path of the main current path Mi11, that is, the first from the node N1. This is useful for eliminating the problem that the current flows backward toward the power supply terminal VCC1. Therefore, the backflow prevention diode D11 is electrically coupled to the reverse path from the high side output terminal CANH toward the high side transistor M11.

The differential signal transmission circuit 100 is composed of a semiconductor integrated circuit as described above. For this reason, a parasitic capacitance (not shown) is formed between the node N1 and each electrode (not shown).

It is known that such parasitic capacitance has some influence on the response characteristics of the switching circuit, not limited to the CAN and FlexRay network. For example, parasitic capacitance reduces communication speed and delays signal transmission.

The magnitude of the current of the constant current circuit i3 coupled to the node N1 is selected to be sufficiently larger than the constant current source i1 of the high side current adjustment unit HC10. As a result, all of the main current (drain current) i11d of the high-side transistor M13 when driven by the constant current source i1 flows to the constant current circuit i3, and the main current i11a flowing to the load RL side is set to 0 and is high. The potential of the side output terminal CANH can be held at a recessive potential. The constant current source i1 is always generated regardless of whether the switch SW11 is on or off. Accordingly, the constant current circuit i3 always has the main current of the high side transistor M11 regardless of whether the input signal TX1 is at the low level L or the high level H, that is, whether the switch SW11 is on or off. (Drain current) is flowing as i11d.

The magnitude of the current of the constant current circuit i3 is set to about 1/30 of the main current i11a of the high side transistor M11. For example, the magnitude of the main current i11a is about 33 mA, and the current flowing through the constant current circuit i3 is set to about 1 mA. In addition, although the allowable range of the magnitude of the main current i11a is restricted according to the international standard of CAN, the magnitude of the current of the constant current circuit i3 is a design matter in the present invention, and is seen from the power consumption. The smaller one is preferable. However, if it is set too small, the circuit operating point and various characteristics of each transistor, each constant current source, etc. are likely to fluctuate due to manufacturing variations of the semiconductor integrated circuit. The configuration and the constant current value will be determined.

The clamp diode D12 coupled in series with the constant current circuit i3 is prepared for clamping the potential of the node N1 to a predetermined level, but is not an essential component. The minimum level of the node N1 is raised from the potential of the ground terminal GND by the forward voltage Vd of the clamp diode D12. As a result, the amount of change in the potential of the node N1 changes from VCC1 to (VCC1-Vd), and the time required for transition can be shortened. As a result, the response speed can be increased and the communication speed can be increased. In FIG. 1, the number of clamp diodes D12 is one, but more may be used. However, if the number of the clamp diodes D12 is increased too much, the minimum potential of the node N1 becomes too high, and it is necessary to consider that switching of the high side transistor M11 and the voltage setting of the high side output terminal CANH are affected. Don't be.

Note that the minimum potential of the node N1 when only the constant current circuit i3 is used without using the clamp diode D12 cannot be completely set to 0 V because of the circuit configuration of the constant current circuit i3, and the minimum level is 0. It is about 2V. Further, the maximum potential is about 4.8V which is slightly lower than the power supply voltage 5V of the first power supply terminal VCC1 for the same reason.

The main current i11a output from the drain of the high-side transistor M11, that is, the node N1, is supplied to the low-side output unit 20 via the backflow prevention diode D11, the high-side output terminal CANH, the first bus line SH, the load resistor RL, and the low-side output terminal CANL. Supplied. The voltage level of the CAN signal output between the high-side output terminal CANH and the low-side output terminal CANL is determined by the magnitude of the main current i11a supplied from the high-side transistor M11 and the load resistance RL.

The low side output unit 20 outputs a low level signal (voltage) of the CAN signal to the low side output terminal CANL. The low side output unit 20 and the high side output unit 10 are in a complementary relationship with each other. In CAN compliant with ISO11898, the standard value of the low level of the CAN signal is 1.5V for the dominant level and 2.5V for the recessive level. The low-side transistor M21 can be composed of, for example, an NMOS transistor having a conductivity opposite to that of the high-side transistor M11, but an NPN-type bipolar transistor may be used.

In the embodiment of the present invention, for convenience of explanation, the low-side transistor M21 is assumed to be an NMOS transistor. The source of the low-side transistor M21 is connected to the ground terminal GND together with its back gate. Therefore, the voltage of the source and back gate of the low side transistor M21 is fixed to approximately 0V.

The low-side current adjusting unit LC20 is coupled to the control electrode of the low-side transistor M21, that is, the gate indicated by the node N20. The low-side current adjustment unit LC20 includes a transistor M23, constant current sources i4 and i5, and a switch SW21. The transistor M23 is an NMOS type having the same conductivity type as the low-side transistor M21. The source of the transistor M23 is connected to the ground potential GND together with its back gate, its gate and drain are connected in common, and connected to the node N20 to which the gate of the low side transistor M21 is connected. The transistor M23 and the low-side transistor M21 constitute a well-known current mirror circuit.

The magnitude of the main current i21d flowing in the main current path Mi21 of the low-side transistor M21 constituting a part of the current mirror circuit is determined by the magnitude of the current generated by the transistor M23, and the control and adjustment of the main current i21d Is performed by the low-side current adjusting unit LC20.

A constant current source i4 is directly connected between the node N20 and the first power supply terminal VCC1. Of course, a switch (not shown) may be coupled between the node N20 and the constant current source i4, or between the constant current source i4 and the first power supply terminal VCC1, and the switch may be controlled by the input signal TX1.

A constant current source i5 is coupled between the node N20 and the first power supply terminal VCC1 through a switch SW21 separately from the current path of the constant current source i4. The constant current source i5 becomes a current source in a current path from the first power supply terminal VCC1 to the node N20 when the switch SW21 is turned on (closed). FIG. 1 shows a state in which the switch SW21 is off, that is, an open state. The switch SW21 is responsive to the input signal TX1. The combination of the low level L and high level H of the input signal TX1 and the on / off state of the switch SW11 is a design matter. For example, the switch SW21 can be selected to be turned on (closed) when the input signal TX1 is at the low level L, and the switch SW11 can be turned off (opened) when the input signal TX1 is at the high level H. Note that. There is a predetermined relationship between the low level and high level H of the input signal TX1 and the dominant recessive of the CAN signal.

When the switch SW21 is off, that is, opened, a constant current source i4 that is not controlled by the switch SW21 and other switches flows as a drain (source) current of the transistor M23. The magnitude of the constant current source i4 is sufficient to turn on the transistor M23 and the low-side transistor M21 weakly. Here, turning on weakly means that a small current flows through the transistor M23 and the low-side transistor M21, and that the low-side transistor M21 is not in a state sufficient to accept the current flowing through the load RL. Accordingly, the constant current source i4 is not required to have a driving capability that allows the low-side transistor M21 to flow the main current i21a to the low-side output terminal CANL and the load RL. That is, the constant current source i4 only needs to hold the potential of the gate of the low-side transistor M21, that is, the node N20 at a predetermined level.

The potential V20L viewed from the ground terminal GND of the node N20 when the constant current source i4 flows as the drain (source) current of the transistor M23 is V20L = VGS3. Here, the voltage VGS3 is a voltage between the source and the gate of the transistor M23 necessary for allowing the constant current source i4 to flow through the transistor M23.

When the switch SW21 is turned on in response to the input signal TX1, a current path of the constant current source i5 is formed between the node N20 and the first power supply terminal VCC1, and between the source and drain of the transistor M23, the constant current source i4. And a constant current source i5 are added (i4 + i5). When both transistors are strongly turned on, the low-side transistor M21 is connected to the high-side transistor via the high-side output terminal CANH, the first bus line SH, the load resistor RL, the second bus line SL, the low-side output terminal CANL, and the backflow prevention diode D21. The main current i11a supplied from M11 is drawn. As a result, a low level signal of the CAN signal is output to the low side output terminal CANL.

The potential V20H viewed from the ground terminal GND of the node N20 when both transistors are strongly turned on is V20H = VGS4. Here, the voltage VGS4 is a voltage between the gate and the source of the transistor M23 necessary for flowing a current (i4 + i5) obtained by adding the constant current source i4 and the constant current source i5. The gate-source voltage VGS3 is in a relationship of VGS4> VGS3. When the switch SW21 is turned on, both of the constant current sources i4 and i5 flow to the transistor M23. Therefore, the gate-source voltage VGS4 is higher than the gate-source voltage VGS3 necessary for flowing only the constant current source i4. growing.

A drain that is one end of the main current path Mi21 of the low-side transistor M21 is indicated by a node N2. The main current path Mi21 is a current path from the drain to the source of the low-side transistor M21. Although the drain of the low-side transistor M21 is directly connected to the node N2 in FIG. 1, the circuit configuration is not limited to this. For example, one end of a resistor (not shown) may be connected to the drain of the low side transistor M21, and the other end may be connected to the node N2. The cathode of the backflow prevention diode D21 is connected to the node N2, and the anode thereof is connected to the low side output terminal CANL. That is, the backflow prevention diode D21 is connected in series with the main current path Mi21 and in the forward direction.

The backflow prevention diode D21 is not an essential constituent element in the present invention, but when any surge voltage arrives at the low-side output terminal CANL, a current in the direction opposite to that of the main current path Mi21, that is, from the ground terminal GND toward the node N2. Useful for eliminating the problem of reverse current flow

The low-side output unit 20 is configured by a semiconductor integrated circuit as described above. For this reason, a parasitic capacitance (not shown) is formed between the node N2 and each electrode (not shown) of each circuit element.

It is known that such parasitic capacitance has some influence on the response characteristics of the switching circuit, not limited to the CAN and FlexRay network. For example, parasitic capacitance reduces communication speed and delays signal transmission.

The magnitude of the current of the constant current circuit i6 is selected to be sufficiently larger than that of the constant current source i4. Accordingly, when the transistor M23 is driven by the constant current source i4 and the low side transistor M21 is driven by the transistor M23, the main current (drain current) i21d of the low side transistor M21 is supplied only from the constant current circuit i6, and the low side transistor M21 is driven. This is because the main current i21a supplied from the output terminal CANL side can be suppressed to zero. If the main current i21a is 0, the potential of the low-side output terminal CANL can be held at a recessive level. The constant current circuit i6 has the first power supply terminal VCC1 and the second power supply terminal VCC2 regardless of whether the input signal TX1 is at the low level L or the high level H, that is, whether the switch SW21 is on or off. During the period when the power supply voltage is supplied, the main current (drain current) i21d of the low-side transistor M21 always flows.

The magnitude of the current of the constant current circuit i6 is set to about 1/30 of the main current i21a of the low-side transistor M21. For example, the main current i21a is about 33 mA, and the current magnitude of the constant current circuit i6 is about 1 mA. In addition, although the allowable range of the magnitude of the main current i21a is restricted by the international standard of CAN, the magnitude of the current of the constant current circuit i6 is a design matter in the present invention, and is seen from the power consumption. The smaller one is preferable. However, if it is set too small, the circuit operating point and various characteristics of each transistor, each constant current source, etc. are likely to fluctuate due to manufacturing variations on the semiconductor integrated circuit. The circuit configuration and the constant current value are determined.

Although the clamp diode D22 coupled in series with the constant current circuit i6 is prepared for clamping the potential of the node N2 to a predetermined level, it is not an essential component. The maximum level of the node N2 is set to be lower than the voltage of the first power supply terminal VCC1 by the forward voltage Vd of the clamp diode D22. As a result, the amount of change in the potential of the node N2 changes from VCC1 to (VCC1-Vd), and the time required for transition can be shortened. As a result, the response speed can be increased and the communication speed can be increased. In FIG. 1, the number of clamp diodes D22 is one, but more may be used. However, if the number of clamp diodes D22 is increased too much, the minimum potential of the node N2 becomes too high, and it is necessary to consider that switching of the low-side transistor M21 and the voltage setting of the low-side output terminal CANL are affected.

Note that the maximum potential of the node N2 when only the constant current circuit i6 is used without using the clamp diode D22 is about 4.8V instead of 5V due to the circuit configuration of the constant current circuit i6, and the minimum potential is the ground potential. It is about 0.2V, which is slightly higher than GND.

The main current i11a sent from the high-side output unit 10 is supplied to the drain of the low-side transistor M21, that is, the node N2, the backflow prevention diode D11, the high-side output terminal CANH, the first bus line SH, the load resistor RL, the second bus line SL, It flows in through the low-side output terminal CANL and the backflow prevention diode D21.

Note that the switch SW11 disposed in the high-side current adjustment unit HC10 and the switch SW21 disposed in the low-side current adjustment unit LC20 are selected so as to operate in the same manner. For example, when the input signal TX1 is at a low level L, both the switch SW11 and the switch SW21 are turned on, and when the input signal TX1 is at a high level, both the switch SW11 and the switch SW21 are turned off.

When the switch SW11 and SW21 are both turned on when the input signal TX1 is at the low level L, the main current i11a output from the high-side transistor M11 is the backflow prevention diode D11, the high-side output terminal CANH, the first bus line SH, The current flows into the low-side transistor M21 through the load resistor RL, the second bus line SL, the low-side output terminal CANL, and the backflow prevention diode D21.

A state in which the main current i11a output from the high side transistor M11 flows into the low side transistor M21 corresponds to a dominant of the CAN signal.

On the other hand, when the input signal TX1 is at the high level H, the switches SW11 and SW21 are both turned off, and the main current i11a supplied from the high-side transistor M11 to the low-side transistor M21 is almost zero. At this time, most of the current flowing through the high-side transistor M11 flows only through the constant current circuit i3, and most of the current flowing through the low-side transistor M21 flows only through the current circuit i6. Therefore, the high-side output terminal CANH and the low-side output terminal CANL , That is, the CAN signal output to both ends of the load resistor RL becomes 2.5 V equal to the power supply voltage of the second power supply terminal VCC2.

The resistance dividing circuit 30 includes a second power supply terminal VCC2 and resistors R11 and R12. The first terminal of the resistor R11 is connected to the second power supply terminal VCC2, and the second terminal is connected to the high side output terminal CANH. The first terminal of the resistor R12 is connected to the second power supply terminal VCC2, and the second terminal is connected to the low-side output terminal CANL. The resistors R11 and R12 are for fixing the high-side output terminal CANH and the low-side output terminal CANL to a predetermined DC potential.

For example, an ECU (not shown) is coupled between the first bus line SH and the second bus line SL to form a CAN. A load resistor RL is coupled between the first bus line SH and the second bus line SL. Here, the load resistance RL includes both terminal resistances of the first bus line SH and the second bus line SL.

(Second Embodiment)
FIG. 2 shows a second embodiment of the differential signal transmission circuit of the present invention. The difference from the first embodiment is that a protection transistor M12 is provided in the high-side output unit 10A, and a protection transistor M22 is provided in the low-side output unit 20A. The protection transistor M12 is connected between the high side output terminal CANH and the cathode of the backflow prevention diode D11, and the high side transistor M11 and the backflow prevention diode D11 are destroyed or deteriorated by an undesired surge voltage that arrives at the high side output terminal CANH. It plays a role to protect you. The breakdown voltage between the source and drain of the protection transistor M12 is secured to 50V or more.

A PMOS transistor having the same conductivity type as that of the high side transistor M11 is used as the protection transistor M12 disposed in the high side output unit 10. Preferably, a DMOS transistor capable of obtaining a high breakdown voltage is employed. The source and back gate of the protection transistor M12 are connected to the cathode of the backflow prevention diode D11, and the drain thereof is connected to the high side output terminal CANH. The gate of the protection transistor M12 is always held at the ground terminal GND. This is because the protection transistor M12 is instantly turned on when the source potential of the protection transistor M12 reaches the threshold voltage Vth so that the original circuit operation of the differential signal transmission circuit is not hindered.

The high-side output terminal CANH is required to have both positive and negative predetermined voltages, for example, a withstand voltage of −27V to 40V. In order to satisfy these requirements, a PMOS transistor having a DMOS structure with a source-drain breakdown voltage of 50 V or more is employed. As a result, it is possible to prevent a problem that an undesired surge voltage that has arrived at the high-side output terminal CANH is applied to the backflow prevention diode D11 and the high-side transistor M11.

An NMOS transistor having the same conductivity type as that of the low-side transistor M21 is used as the protective transistor M22 disposed in the low-side output unit 20A. Preferably, a DMOS transistor capable of obtaining a high breakdown voltage is employed. The source and back gate of the protection transistor M22 are connected to the node N2, the drain thereof is connected to the cathode of the backflow prevention diode D21, and the anode of the backflow prevention diode D21 is connected to the low side output terminal CANL. The gate of the protection transistor M22 is always connected to the first power supply terminal VCC1 or the second power supply terminal VCC2. This is because the drain potential of the protection transistor M22 is turned on instantaneously when it reaches the threshold voltage Vth, so that the original circuit operation of the differential signal transmission circuit 100A is not hindered.

The anode of the backflow prevention diode D21 is connected to the low side output terminal CANL. That is, the backflow prevention diode D21 is coupled directly to the low-side output terminal CANL. This is different from the circuit configuration in which the protective transistor M12 is directly coupled to the high side output terminal CANH.

The low side terminal CANL is required to have both positive and negative predetermined voltages, for example, a withstand voltage of −27V to 40V. In order to satisfy these requirements, an N-channel DMOS transistor having a source-drain breakdown voltage of, for example, 50 V or more is employed on the low-side output terminal CANL side. As a result, it is possible to prevent a problem that an undesired surge voltage that has arrived at the low-side output terminal CANL is applied to the low-side transistor.

  Since the differential signal transmission circuit 100A shown in FIG. 2 employs the protection transistors M12 and M22, the surge resistance characteristics of the high-side output terminal CANH and the low-side output terminal CANL can be improved. 2 and 1, in both cases, when the high-side current adjustment unit HC10, the low-side current adjustment unit LC20, and the constant current circuits i3 and i6 are not employed, the differential signal transmission circuit shown in FIG. Compared with the differential signal transmission circuit shown in FIG. 1, it cannot be denied that the communication speed is responsive, that is, the communication speed is increased. This is because the protection transistors M12 and M22 are employed, so that the electrical path from the node N1 to the high-side output terminal CANH and the electrical path from the node N2 to the low-side output terminal CANL become long. This is because as the electrical path becomes longer, the impedance and the distributed capacitance interposed in the electrical path increase, and it takes more time for the potentials of the nodes N1 and N2 to settle to a predetermined potential. This means a decrease in communication speed.

However, in the second embodiment of the present invention shown in FIG. 2, the protection transistors M12 and M22 are employed, and the high-side current adjustment unit HC10, the low-side current adjustment unit LC20, and the constant current circuits i3 and i6 are combined. By adopting, a differential signal transmission circuit with improved communication speed can be provided.
It is.

In the second embodiment, the same high-side current adjustment unit HC10, low-side current adjustment unit LC20, and constant current circuits i3 and i6 as those in the first embodiment shown in FIG. 1 are employed. Since these have already been explained, explanation here is omitted.

  In the low side output unit 20A, when a series connection body of the backflow prevention diode D21 and the protection transistor M22 is coupled to the low side output terminal CANL, the backflow prevention diode D21 is directly connected to the low side output terminal CANL, and the protection transistor M22 is directly connected. There are two possible cases of connection. Here, the difference between the two will be described.

  3A and 3B schematically show circuit connections and element arrangements on the low-side output terminal CANL side. In particular, the case where the backflow prevention diode D21 and the protection transistor M22 shown in FIG. 2 are formed by a BiCDMOS process is shown.

FIG. 3A shows a circuit connection in the order of the low-side output terminal CNAL, the protection transistor M22, the backflow prevention diode D21, and the node N2, and the circuit connection of the backflow prevention diode D21 and the protection transistor M22 is changed from that shown in FIG. Is. FIG. 3B shows a circuit connection as shown in FIG.

  The backflow prevention diode D21 and the protection transistor M22 shown in FIGS. 3A and 3B are formed by the BiCDMOS process as follows. That is, the buried layer B / L having the N conductivity type is selectively formed on the semiconductor substrate sub having the P conductivity type. Above the buried layer B / L, an N-type epitaxial layer N-Epi having a predetermined thickness is formed regardless of the existence of the buried layer B / L. A well layer P-Wel having a P conductivity type is formed above the buried layer B / L.

3A and 3B, a protective transistor M22 is disposed on the left side of the drawing, and a backflow prevention diode D21 is disposed on the right side thereof. The isolation between the protection transistor M22 and the backflow prevention diode D21 is performed in the lower isolation layer L / I that is in electrical contact with the semiconductor substrate sub, the well layer P-Well in the upper part, and the well layer P-Well. P-type high concentration region P ⁺ formed in (1) and a connection for connecting the high concentration region P ⁺ to the ground potential GND. The electrodes of each element are electrically separated by a selective oxide film LOCOS.

The well layer P-Well has a high-concentration region N ⁺ having a conductivity type N to form the source of the protection transistor M22 and a high-concentration region P having a conductivity type P to take the electrode of the well layer P-Well. ⁺ Is formed, and the high concentration region N ⁺ and the high concentration region P ⁺ are electrically connected in common. Here, since the well layer P-Well corresponds to the back gate of the protection transistor M22, the source of the protection transistor M22 and its back gate are connected in common.

A gate is formed on one main surface of the well layer P-Well, and the gate is connected to the first power supply terminal VCC1. Epitaxial layer N-Epi facing well layer P-Well across the gate
A well layer N-Well having an N conductivity type is formed at a predetermined location of N to form a drain of the protection transistor M22, and a N type conductivity type N ⁺ conductivity region is formed in order to take out the drain electrode therein. Form. The drain of the protection transistor M22 is connected to the low side output terminal CANL.

The backflow prevention diode D21 arranged on the right side of the protection transistor M22 when viewed in front of FIG. 3A and FIG. 3B is the entire P-Well as an anode region, and a part of the anode region has a high concentration region for taking out the electrode. In order to form P ⁺ and the cathode, a high concentration region N ⁺ having an N conductivity type is formed. The cathode of the backflow prevention diode D21 is connected to the node N2, that is, the drain of the low side transistor M21.

  The circuit connection shown in FIG. 3A shows a protection transistor M22 coupled to the low-side output terminal CANL. In such circuit connection, a parasitic diode Ds is formed between the semiconductor substrate sub and the epitaxial layer N-Epi. The parasitic diode Ds is not sufficient to prevent, for example, a −27 V to 40 V surge voltage that arrives at the low-side output terminal CANL. For example, when a surge voltage of −27 V, for example, arrives at the low-side output terminal CANL, a voltage of 27 V is applied in the forward direction of the parasitic diode Ds, and an excessive current is generated between the semiconductor substrate sub and the drain of the protection transistor M22. This is because the protective transistor M22 flows or deteriorates. For example, when a positive surge voltage of 40 V arrives at the low-side output terminal CANL, the reverse breakdown voltage of the parasitic diode Ds can be guaranteed to be 80 V, which can be sufficiently prevented.

  In FIG. 3B, the circuit connection between some elements is replaced with that in FIG. 3A. That is, the protection transistor M22 is coupled to the low-side output terminal CANL via the backflow prevention diode D21, which is equivalent to the second embodiment of the present invention shown in FIG. In the circuit connection shown in FIG. 3B, a parasitic PNP bipolar transistor Ms is formed between the well layer P-Well, the epitaxial layer N-Epi, and the semiconductor substrate sub. Since the breakdown voltage between the emitter and the collector of the parasitic transistor Ms in the present invention is −35 V to 50 V, it is sufficient to prevent, for example, a −27 V to 40 V surge voltage that arrives at the low-side output terminal CANL.

  In the second embodiment of the present invention, the surge resistance due to the protection transistor M22 can be improved by adopting the circuit connection shown in FIG. 3B rather than the circuit connection shown in FIG. 3A. The protective transistor M12 is directly connected to the high-side output terminal CANH. However, since the protective transistor M12 is a PMOS DMOS transistor, problems such as those occurring in the protective transistor M22 are sufficiently eliminated. be able to.

FIG. 4 shows a differential signal transmission circuit studied in advance for carrying out the second embodiment of the present invention. The differential signal transmission circuit 100B is different from the differential signal transmission circuit 100A in the second embodiment (FIG. 2) in the following points. First, the high-side output unit 10B includes constant current sources i7 and i8 and switches SW12 and SW13 coupled in series between the first power supply terminal VCC1 and the ground terminal GND, and a common connection point between the switch SW12 and the switch SW13. Adopts a circuit configuration coupled to the gate of the high-side transistor M11, that is, the node N10. With respect to this point, the second embodiment (FIG. 2) of the present invention is different in that the high-side current adjusting unit HC10 is adopted as the gate of the high-side transistor M11.

Second, the high-side output unit 10B does not employ the constant current circuit i3 and the clamp diode D12 shown in FIG. The constant current circuit i3 in the present invention is the main current (drain current) i11d of the high-side transistor M11, but also serves as a discharge path for discharging the charge accumulated in the node N1, thereby increasing the communication speed. This is an important circuit. However, FIG. 4 shows a circuit that does not employ such a discharge circuit.

Thirdly, in the low-side output unit 20B, constant current sources i9 and i10 and switches SW22 and SW23 are coupled in series between the first power supply terminal VCC1 and the ground terminal GND, and a common connection point between the switch SW22 and the switch SW23 is A circuit configuration coupled to the gate of the low-side transistor M21 is employed. With respect to this point, the second embodiment (FIG. 2) of the present invention is different in that the low-side current adjusting unit LC20 is adopted as the gate of the high-side transistor M21.

Fourth, the low-side output unit 20B does not employ the constant current circuit i6 and the clamp diode D22 shown in FIG.

In FIG. 4, the switches SW12 and SW13 and the switches SW22 and SW23 respond to the input signal TX1. When the input signal TX1 is at the low level L, it is assumed that the switch SW12 is off and the switch SW13 is on. The state of each switch when the input signal TX1 is high is the reverse of the previous state.

When the input signal TX1 is at the low level L, the switch SW22 is off and the switch SW23 is on. A signal obtained by inverting the input signal TX1 by the inverter INV is applied to the switches SW22 and SW23. Therefore, when the input signal TX1 is at a low level, the switch SW22 is turned on and the switch SW23 is turned off. When the input signal TX1 is at the low level L, both the high side transistor M11 and the low side transistor M21 are turned on. At this time, the logic is “0” in the dominant state of the CAN signal.

When the input signal TX1 is at the high level H, both the high side transistor M11 and the low side transistor M21 are turned off. This is a recessive state and the logic is “1”.

In the high-side output unit 10B, the potential V10B is generated at the gate of the high-side transistor M11, that is, the node N10B by turning on and off the constant current sources i7 and i8 and the switches SW12 and SW13. Although the potential V10B depends on the circuit configuration for generating the constant current sources i7 and i8, ideally, the potential V10B is a pulse voltage having a relatively large amplitude from the power supply voltage of the first power supply terminal VCC1 to the ground potential GND.

In the low-side output unit 20B, a potential 20B is generated at the gate of the low-side transistor M21, that is, the node N20B by turning on and off the constant current sources i9 and i10 and the switches SW22 and SW23. Although the potential 20B depends on the circuit configuration of the constant current sources i9 and i10, ideally, the potential 20B is a pulse voltage having a relatively large amplitude from the power supply voltage of the first power supply terminal VCC1 to the ground potential GND.

In the differential signal transmission circuit 100B shown in FIG. 4, the dominant and recessive switching of the CAN signal is performed by a relatively large amplitude transition from 0 V to 5 V applied to the gate of the high side transistor M11 and the gate of the low side transistor. Is done by. As the potential difference required for switching between dominant and recessive increases, the switching time between the two increases, which hinders the increase in communication speed.

FIG. 5A shows the potentials of the nodes N10B and N20B and the differential signals (CAN signals) output to the high-side output terminal CANH and the low-side output terminal CANL in the differential signal transmission circuit 100B shown in FIG.

In FIG. 5A, the potential V10B indicates the potential of the node N10B in FIG. The low level V10BL of the potential V10B is approximately 0V, and the high level V10BH is approximately 5V. A pulse voltage transitioning from 0V to 5V is applied to the gate of the high side transistor M11. The potential V20B is the potential of the node N20, and the polarity is different from that of the potential VB10. The low level V20BL and the high level B20BH of the potential V20B are almost the same size as the potential V10B, and a pulse voltage transitioning from 0V to 5V is applied to the gate of the low-side transistor M21.

When the gate of the high side transistor M11 is 0V and the gate of the low side transistor M21 is 5V, that is, in the period T1A, both the high side transistor M11 and the low side transistor M21 are on. At this time, the differential signal (CAN signal) becomes dominant.

When the gate of the high side transistor M11 is 5V and the gate of the low side transistor M21 is 0V, that is, in the period T2A, both the high side transistor M11 and the low side transistor M21 are off. At this time, the CAN signal becomes recessive.

Dominant means “priority”. When the dominant signal shown in FIG. 5A is transmitted to the first bus line SH and the second bus line SL via the high-side output terminal CANH and the low-side output terminal CANL, the signals are coupled to both bus lines. For example, all of the ECUs are placed in a priority state and can communicate.

Recessive means “acceptance”, and a signal (voltage) of 2.5 V determined by the second power supply terminal VCC2 is output to the high-side output terminal CANH and the low-side output terminal CANL. That is, a signal having a voltage difference of 0V between the two is output. In the recessive state all ECUs, for example, are placed in the accepting state.

FIG. 5A shows a CAN signal (differential signal) placed in a dominant and recessive state, and further shows three regions P1A, P2A, and P3A. These three areas indicate the timing at which the differential signal of the differential signal transmission circuit 100B transitions from the low level to the high level, and the rate of increase and decrease of the signal when transitioning from the high level to the low level, that is, the slew rate. .

The region P1A shows a signal waveform and a slew rate at which the voltage transitions from a signal of 3.5 V to 2.5 V at the high side output terminal CANH when the high side transistor M11 starts to transition from on to off. The region P1A shows a state where the timing at which the high-side transistor M11 starts to transition from on to off is steep and the slew rate is high. The slew rate of the region P1A can be adjusted by selecting the sizes of the constant current sources i7 and i8. Generally, in this type of differential signal transmission circuit or switching circuit, the higher the slew rate, the higher the speed communication can be performed. However, when the slew rate is increased, a problem that electromagnetic interference (EMI) occurs at the time of switching occurs. Therefore, there is a trade-off relationship between improving the communication speed and EMI resistance. Therefore, when providing a practical differential signal transmission circuit, a compromise between the two must be found.

The region P2A includes a signal waveform immediately before the signal level of the high-side output terminal CANH changes from 3.5 V to 2.5 V, and a signal immediately before the signal level of the low-side output terminal CANL changes from 1.5 V to 2.5 V. Both waveforms are shown. That is, the differential signal waveform and slew rate output to the high-side output terminal CANH and the low-side output terminal CANL immediately before both the high-side transistor M11 and the low-side transistor M21 are turned from on to off are shown.

Unlike the region P1A, the differential signal waveform and slew rate shown in the region P2A are affected by circuit elements, circuit configurations, impedances, and capacitance components coupled to the nodes N1B and N2B. In particular, the differential signal transmission circuit 100B shown in FIG. 4 employs a protective transistor M12 in order to improve surge resistance. For this reason, the electrical path from the high-side transistor M11 to the second power supply terminal VCC2 and the electrical path from the protection transistor M22 to the second power supply terminal VCC2 are increased as compared with those in FIG. Delay occurs and communication speed decreases.

The signal waveform and the slew rate shown in the region P2A indicate that the time when the voltage settles from 3.5V and 1.5V to 2.5V is moderate, and the slew rate is small.

Region P3A shows the waveform and slew rate of the differential signal at the timing when a voltage of 1.5V to 2.5V is generated at the low-side output terminal CANL when the low-side transistor M21 starts to transition from on to off. The region P3A indicates that the timing at which the low-side transistor M21 starts to transition from on to off is fast and the slew rate is relatively large. The slew rate of the region P3A can be adjusted by selecting the sizes of the constant current sources i9 and i10. In general, this type of differential signal transmission circuit or switching circuit can perform high-speed communication as the slew rate increases. However, increasing the slew rate is not preferable because electromagnetic interference (EMI) is likely to occur during switching. Therefore, there is a trade-off relationship between improving the communication speed and EMI resistance. Therefore, when providing a practical differential signal transmission circuit, a compromise between the two must be found.

The slew rate at the time of falling of the CAN signal generated by turning on / off the high side transistor M11 is the sum of the region P1A and the region P2A. Increasing the constant current sources i7 and i8 to increase the slew rate in the region P1A is not preferable because electromagnetic interference waves are easily generated. On the other hand, if the constant current sources i7 and i8 are made small in order to suppress the generation of electromagnetic interference waves, the slew rate in the region P1A becomes small, and the overall slew rate at the time of falling together with the slew rate in the region P2A becomes even smaller. As a result, the communication speed decreases. The same can be said for the low-side transistor M21.

  FIG. 5B schematically shows a waveform and a slew rate of a CAN signal (differential signal) output to the high-side output terminal CANH and the low-side output terminal CANL in the differential signal transmission circuit 100A according to the present invention shown in FIG. Shown in

In FIG. 5B, the potential V10 indicates the potential of the node N10 in FIG. 2 and the high-side output unit 10A. The potential V10 has two potentials, a potential V10H and a potential V10L. The potential V10H is a potential when the constant current source i1 is selected by the high side current adjusting unit HC10. The potential V10H is lower than the power supply voltage of the first power supply terminal VCC1 by the gate-source voltage VGS1. Here, the gate-source voltage VGS1 is a gate-source voltage of the transistor M13 when the constant current source i1 flows. The potential V10L is a potential when the constant current source (i1 + i2) is selected by the high-side current adjustment unit HC10. The potential V10L is lower than the power supply voltage of the first power supply terminal VCC1 by the gate-source voltage VGS2. Here, the gate-source voltage VGS2 is a gate-source voltage of the transistor M13 when the constant current source (i1 + i2) is selected by the high-side current adjustment unit HC10, that is, when the switch SW11 is turned on.

The potential V20 indicates the potential of the node N20 in FIG. 2 and the low-side output unit 20A. The potential V20 has two potentials, a potential V20H and a potential V20L. The potential V20H is equal to the gate-source voltage VGS4 of the transistor M23 when the constant current source (i4 + i5) is selected by the low-side current adjustment unit LC20, that is, when the switch SW21 is turned on. The potential V20L is equal to the gate-source voltage VGS3 of the transistor M23 when the constant current source i4 is selected by the low-side current adjustment unit LC20.

When the node N10 is at the potential V10L and the node N20 is at the potential V20H, that is, in the period T1B, both the high-side transistor M11 and the low-side transistor M21 are strongly turned on, and at this time, the CAN signal becomes dominant. On the other hand, when the node N10 is at the potential V10H and the node N20 is at the potential V20L, that is, in the period T2B, both the high-side transistor M11 and the low-side transistor M21 are turned on weakly, but until the predetermined current is supplied to the load resistor RL side. Absent. The CAN signal at this time is recessive.

  Region P1B is different from region P1A shown in FIG. 5A and shows a state in which the slew rate is adjusted to be slightly smaller. The slew rate is adjusted by selecting the sizes of the constant current sources i1 and i2. In order to reduce the slew rate, the constant current sources i1 and i2 may be reduced. Needless to say, the purpose of reducing the slew rate is to suppress the generation of electromagnetic interference.

The region P2B includes an output signal waveform immediately before the voltage of the high-side output terminal CANH transitions from 3.5V to 2.5V, and an output signal immediately before the voltage of the low-side output terminal CANL transitions from 1.5V to 2.5V. Waveform and slew rate are shown. That is, the waveform and slew rate of the CAN signal immediately before the transition from dominant to recessive is schematically shown.

The waveform and the slew rate of the CAN signal shown in the region P2B are in a state where the slew rate is adjusted to be larger than that in FIG. 5A and the region P2A. The differential signal waveform and the slew rate in the region P2B are obtained by adjusting the magnitude of the current flowing through the constant current circuits i3 and i6.

Region P3B shows the timing at which the low-side output terminal CANL transitions from 1.5V to 2.5V when the low-side transistor M21 starts to transition from dominant to recessive. Region P3B is different from region P3A shown in FIG. 5A and shows a state in which the slew rate is adjusted to be slightly smaller. The slew rate is adjusted by selecting the sizes of the constant current sources i1 and i2. In order to reduce the slew rate, the constant current sources i1 and i2 may be reduced. Needless to say, the purpose of reducing the slew rate is to suppress the generation of electromagnetic interference.

The slew rate when the differential signal generated by the operation of the low-side transistor M21 rises is the sum of the regions 3B and 2B. If the constant current sources i1 and i2 are reduced to reduce the slew rate in the region P3B, and if the slew rate is reduced in the region P2B by adjusting the current magnitude of the constant current circuits i3 and i6, the differential signal rises. The overall slew rate can be reduced as compared with FIG. 5A. As a result, the generation of electromagnetic interference waves can be suppressed and the communication speed can be increased.

FIG. 6 shows the inputs in the first embodiment (FIG. 1), the second embodiment (FIG. 2), and the differential signal transmission circuit 100B (FIG. 4) studied in advance for implementing these embodiments. The timing at which the signal TX1, the potential on the high side transistor M11 side, and the CAN signal (differential signal) output to the high side output terminal CANH and the low side output terminal CANL transition from recessive to dominant is shown.

First, the differential signal transmission circuit 100B shown in FIG. 4 will be described with reference to FIG. That is, this is a case where the high-side current adjustment unit HC10, the low-side current adjustment unit LC20, and the constant current circuits i3 and i6 are not employed. In this case, when the input signal TX1 is at the high level H, the gate potential of the high side transistor M11 is held at the potential V10B as shown by the characteristic S1. The potential V10B is approximately 5V. When the input signal TX1 transitions from the high level H to the low level L at time t1, the potential V10B decreases from time t2 slightly delayed from time t1 toward time t5 (0 V). At time t2, the CAN signal (differential signal) remains at the low level of 2.5V. When time t3 is reached, the potential V10B becomes (5V−Vth), which is lower than the power supply voltage of the first power supply terminal VCC1 by the threshold voltage Vt of the high-side transistor M11. After the time t3, the potential V10B drops and becomes 0V at the time t5. At time t3, the high side transistor M11 starts to turn on, and the CAN signal (differential signal) starts to rise relatively steeply as indicated by the characteristic S11. This is because the high side transistor M11 is turned on more strongly as the potential V10B of the node N10B transitions toward 0V. A time tr1 (t4-t3) from time t3 to time t4 is generally called a slew rate.

The differential signal transmission circuit 100B shown in FIG. 4 that does not include the high-side current adjustment unit HC10, the low-side current adjustment unit LC20, and the constant current circuits i3 and i6 has a large slew rate as shown in FIG. 6 and the characteristic S11. Become. However, as the slew rate is increased, electromagnetic noise is likely to be generated.

Next, the differential signal transmission circuits 100 and 100A of the present invention shown in FIGS. 1 and 2 will be described with reference to FIG. 1 and 2 each show a case where a high-side current adjustment unit HC10, a low-side current adjustment unit LC20, and constant current circuits i3 and i6 are employed. In this case, when the input signal TX1 is at the high level H, the gate potential of the high side transistor M11 is held at the potential V10H which is slightly lower than the power supply voltage of the first power supply terminal VCC1 as shown by the characteristic S2. Has been. This is because when the input signal TX1 is at the high level H, the switch SW11 of the high-side current adjustment circuit HC10 is off and the constant current source i2 is off, but the constant current source i1 flows through the transistor M13 and is weakly on. Because it is. The potential V10H at this time is lower than the power supply voltage of the first power supply terminal VCC1 by the gate-source voltage VGS1 when the constant current source i1 flows through the transistor M13. That is, V10H = (VCC1-VGS1).

When the input signal TX1 transitions from the high level H to the low level L at time t1, the potential V10H drops from time t2 slightly delayed from time t1 toward time t3, and becomes potential V10L at time t3. The potential V10L is lower than the power supply voltage of the first power supply terminal VCC1 by the gate-source voltage VGS2 when the constant current source (i1 + i2) flows through the transistor M13. That is, V10L = (VCC1-VGS2). Here, the gate-source voltage potential VGS2> VGS2. The time (t3-t2) required for the transition from the potential V10H to the potential V10L is much shorter than the time (t5-t2) of the characteristic S1 indicating the characteristics of the differential signal transmission circuit 100B illustrated in FIG. The time (t3-t2) is 1/5 to 1/10 of the time (t5-t2).

As shown by the characteristic S21, the voltage level of the CAN signal (differential signal) of the present invention gradually increased from 2.5V at time t2 and reaches 3.5V when time t4 is reached. A time tr2 (t4-t2) from time t2 to time t4 is generally called a slew rate. It can be seen that the slew rate of the present invention is greater than the previously described time tr1. That is, the slew rate is smaller than the characteristic S11 and time (t4-t3) of the differential signal transmission circuit 100B shown in FIG. In the present invention, the slew rate is intentionally reduced to suppress the generation of electromagnetic noise.

In the present invention, the slew rate is set to be small, but this can be realized by setting the circuit operating point of the high side transistor M11. In other words, this is achieved by always putting the high-side transistor M11 in the on state regardless of the recessive and dominant states. In other words, the circuit operation point of the high-side transistor M11 is set so that the high-side transistor M11 does not transition from the completely off state to the on state and does not transition from the on state to the completely off state. Yes. By setting the circuit operating point as described above, switching from recessive to dominant and from dominant to recessive can be performed not by hardware but by software, so that generation of electromagnetic waves can be suppressed.

In the present invention, the generation of electromagnetic waves is suppressed and the slew rate is slightly reduced. However, the slew rate can be adjusted by adjusting the sizes of the constant current sources i1 and i2 of the high-side current adjustment unit HC10.

FIG. 6 schematically shows the timing when the input signal TX1 transitions from the high level H to the low level in the high side transistor M11. However, in the high side transistor M11, when the input signal TX1 transits from the low level L to the high level, the potential V10L transits to the potential V10H. However, the operation of the high side transistor M11 can be switched softly between these potentials. Therefore, the generation of electromagnetic waves can be suppressed.

FIG. 6 describes the high-side transistor M11, but the same applies to the low-side transistor M21. In other words, this is achieved by always placing the low-side transistor M21 in the on state regardless of the recessive and dominant states. In other words, the high-side transistor M21 does not transition from the completely off state to the on state, and the circuit operating point of the low-side transistor M21 does not transition from the on state to the completely off state. It is set by LC20.

(Third embodiment)
FIG. 7 shows a differential signal transmission circuit according to a third embodiment of the present invention, particularly applied to a FlexRay network. The differential signal transmission circuit 200 includes a power supply terminal VCC, a ground terminal GND, a first drive circuit 210, a second drive circuit 220, a first output terminal BP, a second output terminal BM, a first bus line SP, and a second bus line. With SM. A load resistor RL is coupled between the first bus line SP and the second bus line SM. A bus signal is taken out between the first bus line SP and the second bus line SM. One end of the first bus line BP is coupled to the first output terminal BP, and one end of the second bus line SM is coupled to the second output terminal BM.

  The differential signal transmission circuit 200 is built by, for example, a BiCDMOS process. The first drive circuit 210 includes a high-side current adjustment unit HC10, a high-side transistor M31, backflow prevention diodes D31 and D32, a low-side transistor M32, and constant current sources i11 and i12. For example, a PMOS transistor is used as the high side transistor M31, but it may be a PNP type bipolar transistor. The source of the high side transistor M31 is connected to the power supply terminal VCC together with its back gate. In order to switch the operation of the high-side transistor M31, the control electrode, that is, the gate, is coupled to the high-side current adjusting unit HC10. Since the high-side current adjustment unit HC10 is the same as that employed in the first and second embodiments of the present invention, description thereof is omitted here. The transistor M13 and the high side transistor M31 that constitute a part of the high side current adjusting unit HC10 constitute a well-known current mirror circuit.

  The drain of the high side transistor M31, that is, one end of the main current path Mi31 of the transistor is indicated by a node N11. The drain (source) current of the high side transistor M31 flows from the power supply terminal VCC toward the node N11. The anode of the backflow prevention diode D31 is connected to the node N11, that is, the drain of the high side transistor M31, and the cathode is connected to the anode of the backflow diode D32. The cathode of the backflow prevention D31 and the anode of the backflow prevention diode D32 are commonly connected, and the common connection point is coupled to the first output terminal BP. The cathode of the backflow prevention diode D32 is indicated by the node N12. A low side transistor M32 is coupled to the node N12.

  For example, an NMOS transistor is used as the low-side transistor M32, but an NPN bipolar transistor may be used. The source of the low side transistor M32 is connected to the ground terminal GND together with its back gate. In order to switch the low-side transistor M32 from on to off or from off to on, the control electrode, that is, the gate, is coupled to the low-side current adjusting unit LC20. Since the low-side current adjusting unit LC20 is the same as that employed in the first and second embodiments of the present invention, description thereof is omitted here. The transistor M23 and the low side transistor M21 constituting a part of the low side current adjusting unit LC20 constitute a well-known current mirror circuit. The drain of the low side transistor M32 is indicated by a node N12. The node N12 is also one end of the main current path of the low side transistor M32. The main current path of the low-side transistor M32 is a current path that flows from the drain to the source. That is, it is a current path from the node N12 to the ground terminal GND.

  The high side transistor M31, the backflow prevention diode D31, the backflow prevention diode D32, and the low side transistor M32 are coupled in series and in the forward direction from the power supply terminal VCC to the ground terminal GND in this order.

  The first drive circuit 210 includes a high-side current adjustment unit HC10, a low-side current adjustment unit LC20, constant current sources i11 and i12, and clamp diodes D33 and D34. Such a circuit configuration is basically the same as that of the first and second embodiments already described. In other words, the high-side current adjusting unit HC10 is prepared for always turning on the high-side transistor M33, and the low-side current adjusting unit LC20 is prepared for always putting the low-side transistor M34 on. The operations and effects of the constant current circuits i11 and i12 and the clamp diodes D33 and D34 shown in FIG. 7 are the same as those of the constant current circuits i3 and i6 and the clamp diodes D12 and D22 shown in FIG.

In the first drive circuit 210, a parasitic capacitance (not shown) is added between the node N11 and the power supply terminal VCC, and a parasitic capacitance (not shown) is added between the node N11 and the ground terminal GND, and these parasitic capacitances are used for differential signal transmission. Since it has already been described in the first embodiment that it becomes an obstruction requirement for improving the communication speed of the circuit 200, description thereof is omitted here.

  The second drive circuit 220 is paired with the first drive circuit 210, and both have the same circuit configuration. That is, the high-side current adjusting unit HC10, the low-side current adjusting unit LC20, the high-side transistor M33, the backflow prevention diodes D35 and D36, the low-side transistor M34, the constant current circuits i13 and i14, and the clamp diodes D37 and D38 are provided. For example, a PMOS transistor is used as the high side transistor M33, but it may be a PNP type bipolar transistor. The source of the high side transistor M33 is connected to the power supply terminal VCC together with its back gate. A high side current adjusting unit HC10 is coupled to the gate of the high side transistor M33. The transistor M13 and the high side transistor M33 form a well-known current mirror circuit. The high-side current adjustment unit HC10 disposed in the second drive circuit 220 has the same role as that disposed in the first drive circuit 210. That is, it is prepared to always keep the high side transistor M33 on.

  The drain of the high side transistor M33, that is, one end of the main current path Mi33 is indicated by a node N13. The drain (source) current of the high side transistor M33 flows from the power supply terminal VCC toward the node N13. The anode of the backflow prevention diode D35 is connected to the node N13, that is, the drain of the high side transistor M33, and the cathode thereof is connected to the anode of the backflow prevention diode D36. A common connection point between the cathode of the backflow prevention diode D35 and the anode of the backflow prevention diode D36 is coupled to the second output terminal BM. The cathode of the backflow prevention diode D36 is indicated by the node N14. The main current path Mi34 of the low side transistor M34 is coupled to the node N14.

  For example, a MOS transistor is used as the high-side transistor M33 and the low conductivity type low-side transistor M34. Of course, an NPN type bipolar transistor may be used. The source of the low-side transistor M34 is connected to the ground terminal GND together with its back gate. A low-side current adjusting unit LC20 is coupled to a control electrode, that is, a gate (node N140) of the low-side transistor M34. That is, it is the same as that employed in the first and second embodiments (FIGS. 1 and 2), and the low-side current adjustment unit LC20 is prepared to always keep the low-side transistor M34 on.

  The high side transistor M33, the backflow prevention diodes D35 and D36, and the low side transistor M34 constituting a part of the second drive circuit 220 are coupled in series and forward from the power supply terminal VCC to the ground terminal GND in this order. Yes.

  The second drive circuit 220 includes a high-side current adjustment unit HC10, a low-side current adjustment unit LC20, constant current sources i13 and i14, and clamp diodes D37 and D38. These characteristics are basically the same as those of the first and second embodiments already described. In other words, the high-side current adjusting unit HC10 is prepared for always turning on the high-side transistor M33, and the low-side current adjusting unit LC20 is prepared for always putting the low-side transistor M34 on. The operation and effect of the constant current circuits i13 and i14 and the clamp diodes D33 and D34 shown in FIG. 7 are the same as those of the constant current circuits i3 and i6 and the clamp diodes D12 and D22 shown in FIG.

In the second drive circuit 220, a parasitic capacitance (not shown) is added between the node N13 and the power supply terminal VCC, and a parasitic capacitance (not shown) is added between the node N13 and the ground terminal GND. Since these parasitic capacitances have already been described in the first and second embodiments that the communication speed of the differential signal transmission circuit 200 is impeded, description thereof is omitted here.

(Fourth embodiment)
FIG. 8 shows a fourth embodiment according to the differential signal transmission circuit of the present invention. The difference from the third embodiment is that protective transistors M35 to M38 are provided. In the first drive circuit 210, the protection transistor M35 is connected between the first output terminal BP and the cathode of the backflow prevention diode D31, and the high side transistor M31 and backflow are generated by an undesired surge voltage that arrives at the first output terminal BP. It plays the role which protects prevention diode D31 from destruction or deterioration.

As the protection transistor M35, a PMOS transistor having the same conductivity type as that of the high side transistor M31 is used. Preferably, a DMOS transistor capable of obtaining a high breakdown voltage is employed. The source and back gate of the protection transistor M35 are connected to the cathode of the backflow prevention diode D31, and the drain of the protection transistor M35 is connected to the first output terminal BP. The gate of the protection transistor M35 is always held at the ground terminal GND. This is because the protection transistor M35 is instantly turned on when the source potential of the protection transistor M35 reaches the threshold voltage Vth so that the original circuit operation of the differential signal transmission circuit is not hindered.

The first output terminal BP is required to have both positive and negative predetermined voltages, for example, a withstand voltage of −27V to 40V. In order to satisfy such requirements, a PMOS transistor having a source-drain breakdown voltage of 50 V or more is employed as the protection transistor M35. Accordingly, it is possible to prevent a problem that an undesired surge voltage that has arrived at the first output terminal BP is applied to the backflow prevention diode D31 and the high-side transistor M31.

As the protection transistor M36, an NMOS transistor having the same conductivity type as that of the low-side transistor M32 is used. Preferably, a DMOS transistor capable of obtaining a high breakdown voltage is employed. The source and back gate of the protection transistor M36 are connected to the drain of the low side transistor M32 indicated by the node N12. The drain of the protection transistor M36 is connected to the cathode of the backflow prevention diode D32, and the gate thereof is connected to the power supply terminal VCC and is always kept at a high potential. The anode of the backflow prevention diode D32 is connected to the first output terminal BP.

FIG. 8 shows a structure in which a backflow prevention diode D32 is coupled to the first output terminal BP, and a protection transistor M36 is coupled to the subsequent stage. If a circuit configuration in which the protection transistor M36 is coupled to the first output terminal BP and the backflow prevention diode D32 is coupled to the first output terminal BP is employed, the problem described in FIG. 3A occurs, which is not preferable.

The first output BP is required to have both positive and negative predetermined voltages, for example, a withstand voltage of −27V to 40V. In order to satisfy these requirements, an N-channel DMOS transistor having a source-drain breakdown voltage of, for example, 50 V or more is also used on the low-side transistor M32 side of the first output terminal BP. As a result, it is possible to prevent a problem that an undesired surge voltage that has arrived at the first output terminal BP is applied to the low-side transistor M32.

In the second drive circuit 220, the protection transistor M37 is connected between the second output terminal BM and the cathode of the backflow prevention diode D35, and the high-side transistor M33 and the protection transistor M37 are connected by an undesired surge voltage arriving at the third output terminal BM. It plays a role of protecting the backflow prevention diode D35 from destruction or deterioration.

As the protection transistor M37, a PMOS transistor having the same conductivity type as that of the high side transistor M33 is used. Preferably, a DMOS transistor capable of obtaining a high breakdown voltage is employed. The source and back gate of the protection transistor M37 are connected to the cathode of the backflow prevention diode D35, and the drain thereof is connected to the second output terminal BM. The gate of the protection transistor M37 is always held at the ground terminal GND. This is because the protection transistor M37 is turned on instantaneously when the source potential of the protection transistor M37 reaches the threshold voltage Vth, so that the original circuit operation of the differential signal transmission circuit is not hindered.

The second output terminal BM is required to have both positive and negative predetermined voltages, for example, a withstand voltage of −27V to 40V. In order to satisfy such requirements, a PMOS transistor having a source-drain breakdown voltage of 50 V or more is employed as the protection transistor M37. As a result, it is possible to prevent a problem that an undesired surge voltage that has arrived at the second output terminal BM is applied to the backflow prevention diode D35 and the high-side transistor M33.

As the protection transistor M38, an NMOS transistor having the same conductivity type as that of the low-side transistor M34 is used. Preferably, a DMOS transistor capable of obtaining a high breakdown voltage is employed. The source and back gate of the protection transistor M38 are connected to the drain of the low side transistor M34 indicated by the node N14. The drain of the protection transistor M38 is connected to the cathode of the backflow prevention diode D36, and the gate of the protection transistor M38 is connected to the power supply terminal VCC and is always kept at a high potential. The anode of the backflow prevention diode D36 is connected to the second output terminal BM. That is, the backflow prevention diode D36 is coupled to the second output terminal BM without coupling the protection transistor M38.

The second output terminal BM is required to have both positive and negative predetermined voltages, for example, a withstand voltage of −27V to 40V. In order to satisfy these requirements, a protective transistor M38 made of an N-channel DMOS transistor having a source-drain breakdown voltage of, for example, 50 V or more is also used on the low-side transistor M34 side of the second output terminal BM. As a result, it is possible to prevent a problem that an undesired surge voltage that has arrived at the second output terminal BM is applied to the low-side transistor M34.

  FIG. 9 shows potentials generated by the high-side current adjustment unit HC10 and the low-side current adjustment unit LC20 in FIGS. 7 and 8, and output signals output to the first output terminal BP and the second output terminal BM. The high side current adjustment unit HC10 and the low side current adjustment unit LC20 are controlled by control signals CTRL31 to CTRL34 output from the control circuit 300.

A potential V110 indicates a potential generated in the first drive circuit 210 and the node N110. The potential V110 is generated by the high side current adjusting unit HC10. The potential V110 includes a high level V110H and a low level V110L. The high level V110H is the potential of the node N110 when the switch SW11 is in the off state, that is, the constant current source i1 is selected in the high-side current adjustment unit HC10. On the other hand, the low level V110L is the potential of the node N110 when the switch SW is on, that is, when the constant current source (i1 + i2) is selected. In order to pass a constant current source (i1 + i2) through the transistor M13, a gate-source voltage VGS corresponding to the constant current source (i1 + i2) is required. For this reason, the potential V110L viewed from the ground terminal GND is smaller (lower) than that of the constant current source i1 alone. The setting of the potential V110H and the potential V110L and the setting of the difference between them are design matters and are determined according to the absolute values of the constant current source i1 and the constant current source i2 and the difference between them.

  A potential V120 indicates a potential generated in the first drive circuit 210 and the node N120. The potential V120 is generated by the low-side current adjustment unit LC20. The potential V120 includes a high level V120H and a low level V120L. The high level V120H is the potential of the node N120 when the switch SW21 is in the high state, that is, the constant current source (i4 + i5) is selected in the low-side current adjustment unit LC20. On the other hand, the low level V120L is the potential of the node N120 when the switch SW21 is in an off state, that is, only the constant current source i4 is selected. In order to pass the constant current source (i4 + i5) through the transistor M23, a gate-source voltage VGS corresponding to the constant current source (i4 + i5) is required. For this reason, the potential V120L viewed from the ground terminal GND is larger (higher) than when only the constant current source i4 is used. The setting of the potential V120H and the potential V120L and the setting of the difference between them are design matters and are determined according to the absolute values of the constant current source i4 and the constant current source i5 and the difference between them.

  A potential V130 indicates a potential generated in the second drive circuit 220 and the node N130. The potential V130 is generated by the high side current adjusting unit HC10. The potential V130 includes a high level V130H and a low level V130L. The high level V130H is the potential of the node N130 when the switch SW11 is in the off state, that is, the constant current source i1 is selected in the high-side current adjusting unit HC10. On the other hand, the low level V130L is the potential of the node N130 when the switch SW11 is on, that is, when the constant current source (i1 + i2) is selected. In order to pass a constant current source (i1 + i2) through the transistor M13, a gate-source voltage VGS corresponding to the constant current source (i1 + i2) is required. For this reason, the potential V130L viewed from the ground terminal GND is smaller (lower) than when only the constant current source i1 is used. The setting of the potential V130H and the potential V130L and the setting of the difference between them are design matters and are determined according to the absolute values of the constant current source i1 and the constant current source i2 and the difference between them.

A potential V140 indicates a potential generated in the second drive circuit 220 and the node N140. The potential V140 is generated by the low-side current adjustment unit LC20. The potential V140 includes a high level V140H and a low level V140L. The high level V140H is the potential of the node N140 when the switch SW21 is in the high state, that is, the constant current source (i4 + i5) is selected in the low-side current adjustment unit LC20. On the other hand, the low level V140L is the potential of the node N140 when the switch SW21 is in the off state, that is, only the constant current source i4 is selected. In order to pass the constant current source (i4 + i5) through the transistor M23, a gate-source voltage VGS corresponding to the constant current source (i4 + i5) is required. For this reason, the potential V120L viewed from the ground terminal GND is larger (higher) than when only the constant current source i4 is used. The setting of the potential V140H and the potential V140L and the setting of the difference between them are design matters and are determined according to the absolute values of the constant current source i4 and the constant current source i5 and the difference between them.

The bus signal Out is output to the first output terminal BP and the second output terminal BM. The bus signal Out output to these output terminals is determined according to the following operation. During the period of time T1 to T2, the high side transistor M31 disposed in the first drive circuit 210 is driven by the constant current source i1 of the high side current adjustment unit HC10, and the low side transistor M34 of the second drive circuit 220 is driven by the low side current adjustment. It is driven by the constant current source i4 of the part LC20. In addition, during the period from time T1 to T2, the high-side transistor M33 of the second drive circuit 220 is driven by the constant current source (i1 + i2) of the high-side current adjustment unit HC10, and the low-side transistor M32 disposed in the first drive circuit 210 is It is driven by the constant current source (i4 + i5) of the low-side current adjusting unit LC20. Due to the operation of each of these transistors, the level of the bus signal output to the second output terminal BM is higher than that of the bus signal output to the first output terminal BP during the period of time T1 to T2.

During the period from time T2 to T3, the high-side transistor M31 disposed in the first drive circuit 210 is driven by the constant current source (i1 + i2) of the high-side current adjustment unit HC10, and the low-side transistor M34 of the second drive circuit 220 is low-side It is driven by the constant current source (i4 + i5) of the current adjusting unit LC20. Further, during the period from time T1 to time T2, the high-side transistor M33 of the second drive circuit 220 is driven by the constant current source i1 of the high-side current adjustment unit HC10, and the low-side transistor M32 disposed in the first drive circuit 210 is low-side current. It is driven only by the constant current source i4 of the adjustment unit LC20. Due to the operation of each of these transistors, the level of the bus signal output to the first output terminal BP is higher than that of the bus signal output to the second output terminal BM during the period from time T2 to T3.

In the FlexRay network, when it is larger (higher) than one of the bus signals of the first output terminal BP and the second output terminal BM, it is a period called a dominant. On the other hand, the period from time T3 to T4 and the period after time T4 are referred to as recessive. When the high side transistors M31 and M33 are driven by the constant current source (i1 + i2) and the low side transistors M32 and M34 are driven by the constant current source (i4 + i5) in a relatively short period of time T3 to T4, the first output terminal BP and The bus signal output to the second output terminal BM is held at a level approximately in the middle of the dominant period. This intermediate level is the same level when the high side transistors M31 and M33 are driven only by the constant current source i1 and the low side transistors M32 and M34 are driven only by the constant current source i4 at time T4.

As described above, the differential signal transmission circuit including the high-side current adjustment circuit HC10, the low-side current adjustment circuit LC20, and the constant current sources i11, i12, i13, i14 according to the present invention can be applied to the FlexRay network, The speed can be increased.

The differential signal transmission circuit according to the present invention is useful for both CAN and FlexRay networks, but is not limited to this, and can be applied to all switching circuits for high-speed communication, and its industrial applicability is extremely high. large.

10, 10A, 10B High side output unit 20, 20A, 20B Low side output unit 30 Resistance divider circuit 100, 100A, 100B, 200, 200A Differential signal transmission circuit 210 High side output unit 220 Low side output unit 300 Control circuit BP First Output terminal BM Second output terminal CANH High side output terminal CANL Low side output terminals D11, D21, D31, D32, D35, D36 Backflow prevention diodes D12, D22, D33, D34, D37, D38 Clamp diode GND Ground terminal HC10 High side current Adjustment unit i1, i2, i4, i5, i7 to i10 Constant current source i3, i6, i11 to i14 Constant current circuit LC20 Low side current adjustment unit M11, M31, M33 High side transistors M12, M22, M35 to M38 Protective transistor Star M21, M32, M34 low side transistor Mi11, Mi21, Mi31~Mi34 main current path N1, N2, N11~N14 node (one end of the main current path)
Out Bus signal RL Load resistance SH, SP First bus line SL, SM Second bus line VCC Power supply terminal VCC1 First power supply terminal VCC2 Second power supply terminal

Claims (15)

A differential signal transmission circuit for outputting a differential signal to two bus lines,
A power terminal;
A grounding terminal;
A high side transistor having a first main current path and a control electrode and coupled to the power supply terminal;
A high side output terminal coupled to one end of the first main current path;
A first bus line having one end coupled to the high-side output terminal and being one of the two bus lines;
A load resistor having a first terminal coupled to the other end of the first bus line;
A second bus line, one end of which is coupled to the second terminal of the load resistor and being the other of the two bus lines;
A low-side output terminal having the other end coupled to the second bus line;
A low side transistor having a second main current path and a control electrode, wherein one end of the second main current path is coupled to the low side output terminal and the other end of the second main current path is coupled to the ground terminal;
A high-side current adjusting unit that is coupled to the control electrode of the high-side transistor and adjusts a current flowing through the first main current path;
A low-side current adjusting unit that is coupled to the control electrode of the low-side transistor and adjusts a current flowing through the second main current path;
A first constant current circuit coupled between the one end of the first main current path and the ground terminal;
A second constant current circuit coupled between the one end of the second main current path and the power supply terminal ;
Equipped with a,
When the differential signal is set to the first state, the high-side current adjustment unit makes the current flowing through the first main current path larger than the current flowing through the first constant current circuit, and the differential signal is When two states are set, the current flowing through the first main current path is made smaller than the current flowing through the first constant current circuit,
When the differential signal is set to the first state, the low-side current adjustment unit makes a current flowing through the second main current path larger than a current flowing through the second constant current circuit, and the differential signal is When the second state is set, the current flowing through the second main current path is made smaller than the current flowing through the second constant current circuit.
A differential signal transmission circuit. The high-side current adjustment unit includes a first transistor that forms a first current mirror circuit with the high-side transistor, and the first transistor includes a first constant current source and a second constant current having different current magnitudes. A source is coupled, and a constant current source obtained by adding one or both of the first constant current source and the second constant current source is selected and flows to the first transistor, and the constant current source selected by the first transistor is selected. The current flowing in the main current path of the high-side transistor is adjusted in proportion to the current source, and the low-side current adjusting unit includes a second transistor that forms a second current mirror circuit with the low-side transistor, and A third constant current source and a fourth constant current source having different current magnitudes are coupled to the two transistors, and the third constant current source and the fourth constant current source are coupled to the second transistor. A constant current source obtained by adding one or both of the current sources is selected and supplied, and a current flowing through the main current path of the low-side transistor depends on the size of the constant current source selected by the second transistor. The differential signal transmission circuit according to claim 1, wherein the differential signal transmission circuit is adjusted.   First switch means is coupled to at least one of the first constant current source and the second constant current source, and the first switch means is generated according to the high level or the low level of the differential signal. On the basis of an input signal having a logical value, and a second switch means is coupled to at least one of the third constant current source and the fourth constant current source, and the second switch means The differential signal transmission circuit according to claim 2, wherein the differential signal transmission circuit is turned on / off based on an input signal in accordance with a logical value generated according to the high level or the low level of the differential signal. A first backflow prevention diode is coupled in series and forward between one end of the first main current path and the high side output terminal, and in series between one end of the second main current path and the low side output terminal. 4. The differential signal transmission circuit according to claim 3, wherein a second backflow prevention diode is coupled in the forward direction. The first constant current circuit includes a constant current source and a first clamp diode coupled in series with the constant current source in a forward direction, and the second constant current circuit includes another constant current source and the constant current source. 5. The differential signal transmission circuit according to claim 4, further comprising a second clamp diode coupled in series and in a forward direction. A series connection of the first backflow prevention diode and the first protection transistor is coupled in series and forward between one end of the first main current path and the high side output terminal, and the low side output terminal and the second side differential signal transmission circuit according to claim 2, series connection of the second blocking diode and the second protection transistor in series and forward direction, characterized in that it is coupled between the main current path.   The first backflow prevention diode and the first protection transistor are coupled in this order from one end of the first main current path to the high side output terminal, and from the low side output terminal to the second main current path, The differential signal transmission circuit according to claim 6, wherein the second backflow prevention diode and the second protection transistor are coupled in this order.   The differential signal transmission circuit according to claim 7, wherein the differential signal transmission circuit is built by a BiCDMOS process.   9. The differential signal transmission circuit according to claim 8, wherein the first protection transistor and the second protection transistor are formed of DMOS transistors. A power terminal;
A grounding terminal;
A first high-side transistor coupled to said power supply terminal having a first main current path and the first control electrode,
A second high-side transistor coupled to the power supply terminal and a second main current path and the second control electrode,
A first low-side transistor having a third main current path and a third control electrode, the third main current path being coupled between one end of the first main current path and the ground terminal;
A second low-side transistor having a fourth main current path and a fourth control electrode, the fourth main current path being coupled between one end of the second main current path and the ground terminal;
A first output terminal coupled to a common connection point between one end of the first main current path and one end of the third main current path; and outputting the differential signal;
A second output terminal coupled to a common connection point between one end of the second main current path and one end of the fourth main current path; and outputting the differential signal;
A first bus line and a second bus line respectively coupled to the first output terminal and the second output terminal;
A load resistor coupled between the first bus line and the second bus line;
The first high side transistor, the second high side transistor, the first low side transistor, and the second low side coupled to the first control electrode, the second control electrode, the third control electrode, and the fourth control electrode, respectively. the first high-side current adjusting unit that adjusts the current supplied to each separate transistor, and the second high-side current adjustment unit, the first low-side current adjusting unit, and the second low-side current adjustment unit,
A first constant current circuit and a second constant current circuit coupled separately between one end of each of the first main current path and the second main current path and the ground terminal;
A third constant current circuit and a fourth constant current circuit respectively coupled between one end of the third main current path and the fourth main current path and the power supply terminal ;
With
The first high-side current adjustment unit makes the current that flows through the first main current path smaller than the current that flows through the first constant current circuit when the differential signal is in the first state, Is set to the second state, the current flowing through the first main current path is made larger than the current flowing through the first constant current circuit, and when the differential signal is set to the third state, the first main current path Is equal to the current flowing through the second main current circuit,
The second high-side current adjustment unit makes the current flowing through the second main current path larger than the current flowing through the second constant current circuit when the differential signal is set to the first state, When the signal is in the second state, the current flowing in the second main current path is made smaller than the current flowing in the second constant current circuit, and when the differential signal is in the third state, the second state The current flowing in the main current path is equal to the current flowing in the first main current circuit;
The first low-side current adjustment unit makes the current that flows in the third main current path larger than the current that flows in the third constant current circuit when the differential signal is in the first state, Is set to the second state, the current flowing through the third main current path is made smaller than the current flowing through the third constant current circuit, and when the differential signal is set to the third state, the third main current path is The current flowing in the current path is equal to the current flowing in the fourth main current circuit;
The second low-side current adjustment unit makes the current that flows through the fourth main current path smaller than the current that flows through the fourth constant current circuit when the differential signal is in the first state, Is set to the second state, the current flowing through the fourth main current path is made larger than the current flowing through the fourth constant current circuit, and when the differential signal is set to the third state, the fourth main current path is set. Making the current flowing in the current path equal to the current flowing in the third main current circuit;
A differential signal transmission circuit . The first high-side current adjustment unit includes a first transistor that forms a first current mirror circuit with the first high-side transistor, and the first transistor has a first constant current source having a different current magnitude and A second constant current source is coupled, and the first transistor is selectively supplied with a constant current source obtained by adding one or both of the first constant current source and the second constant current source, and the first transistor The current flowing through the first main current path of the first high-side transistor is adjusted in proportion to the constant current source selected in step (i), and the second high-side current adjustment unit includes the second high-side transistor and the second high-side transistor. A second transistor constituting a two-current mirror circuit, and a first constant current source and a second constant current source having different current magnitudes are coupled to the second transistor, and the first transistor A constant current source obtained by adding one or both of the first constant current source and the second constant current source is selected and supplied to the data, and proportional to the constant current source selected by the second transistor, A current flowing through the first main current path of the second high-side transistor is adjusted, and the first low-side current adjustment unit includes a third transistor that forms a third current mirror circuit with the first low-side transistor; A third constant current source and a fourth constant current source having different current magnitudes are coupled to the third transistor, and the third transistor is either one of the third constant current source or the fourth constant current source or A constant current source obtained by adding both is selected and supplied, and the current flowing through the main current path of the first low-side transistor is adjusted in proportion to the constant current source selected by the third transistor. Differential signal transmission circuit according to claim 10, wherein the door. A series connection of a first backflow prevention diode and a first protection transistor is coupled in series and forward between one end of the first main current path and the first output terminal, and one end of the second main current path A series connection body of a second backflow prevention diode and a second protection transistor is coupled in series and in the forward direction between the second output terminal and between the first output terminal and one end of the third main current path. A series connection of a third backflow prevention diode and a third protection transistor is coupled in series and in the forward direction, and a fourth backflow prevention in series and in the forward direction is performed between the second output terminal and one end of the fourth main current path. The differential signal transmission circuit according to claim 11, wherein a series connection body of a diode and a fourth protection transistor is coupled.   The first backflow prevention diode and the first protection transistor are coupled in this order from one end of the first main current path to the first output terminal, and from the first output terminal to one end of the third main current path. The third backflow prevention diode and the third protection transistor are coupled in this order, and the second backflow prevention diode and the second protection transistor are connected from one end of the second main current path toward the second output terminal. 13. The fourth backflow prevention diode and the fourth protection transistor are coupled in this order, and are coupled in this order from the second output terminal toward one end of the fourth main current path. Differential signal transmission circuit.   14. The differential signal transmission circuit according to claim 13, wherein the differential signal transmission circuit is built by a BiCDMOS process.   The differential signal transmission circuit according to claim 14, wherein the first protection transistor, the second protection transistor, the third protection transistor, and the fourth protection transistor are formed of DMOS transistors.

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