JP7112873B2 - 配線基板、半導体パッケージ及び配線基板の製造方法 - Google Patents

配線基板、半導体パッケージ及び配線基板の製造方法 Download PDF

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Publication number
JP7112873B2
JP7112873B2 JP2018073456A JP2018073456A JP7112873B2 JP 7112873 B2 JP7112873 B2 JP 7112873B2 JP 2018073456 A JP2018073456 A JP 2018073456A JP 2018073456 A JP2018073456 A JP 2018073456A JP 7112873 B2 JP7112873 B2 JP 7112873B2
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Japan
Prior art keywords
layer
metal layer
pad
opening
wiring board
Prior art date
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Active
Application number
JP2018073456A
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English (en)
Japanese (ja)
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JP2019186330A5 (https=
JP2019186330A (ja
Inventor
康之 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2018073456A priority Critical patent/JP7112873B2/ja
Priority to US16/373,951 priority patent/US10886211B2/en
Publication of JP2019186330A publication Critical patent/JP2019186330A/ja
Publication of JP2019186330A5 publication Critical patent/JP2019186330A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2018073456A 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法 Active JP7112873B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018073456A JP7112873B2 (ja) 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法
US16/373,951 US10886211B2 (en) 2018-04-05 2019-04-03 Wiring board and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018073456A JP7112873B2 (ja) 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2019186330A JP2019186330A (ja) 2019-10-24
JP2019186330A5 JP2019186330A5 (https=) 2021-02-12
JP7112873B2 true JP7112873B2 (ja) 2022-08-04

Family

ID=68097357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018073456A Active JP7112873B2 (ja) 2018-04-05 2018-04-05 配線基板、半導体パッケージ及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US10886211B2 (https=)
JP (1) JP7112873B2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7459492B2 (ja) * 2019-11-29 2024-04-02 大日本印刷株式会社 配線基板
US11903145B2 (en) * 2020-12-31 2024-02-13 Samsung Electronics Co., Ltd. Wiring board and semiconductor module including the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014103295A (ja) 2012-11-21 2014-06-05 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2015233085A (ja) 2014-06-10 2015-12-24 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2017112318A (ja) 2015-12-18 2017-06-22 新光電気工業株式会社 端子構造、端子構造の製造方法、及び配線基板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350386B1 (en) * 2000-09-20 2002-02-26 Charles W. C. Lin Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
US8338287B2 (en) * 2010-03-24 2012-12-25 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US8389397B2 (en) * 2010-09-14 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing UBM undercut in metal bump structures
JP2013093405A (ja) 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
JP2016035969A (ja) 2014-08-01 2016-03-17 味の素株式会社 回路基板及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014103295A (ja) 2012-11-21 2014-06-05 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP2015233085A (ja) 2014-06-10 2015-12-24 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2017112318A (ja) 2015-12-18 2017-06-22 新光電気工業株式会社 端子構造、端子構造の製造方法、及び配線基板

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US20190311982A1 (en) 2019-10-10
JP2019186330A (ja) 2019-10-24
US10886211B2 (en) 2021-01-05

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