JP7111892B2 - Information processing device and work machine - Google Patents

Description

The present disclosure relates to an information processing device that writes to a memory in which a program is stored, and a working machine that includes the information processing device.

2. Description of the Related Art Conventionally, there is an information processing apparatus including a plurality of CPUs and a memory into which data is written from the plurality of CPUs (for example, Japanese Unexamined Patent Application Publication No. 2002-200013). The information processing apparatus of Patent Document 1 stops the operation of CPUs other than the CPU that writes to the memory among the plurality of CPUs.

International Publication No. WO2008/078564

By the way, a processing unit such as a CPU may cause an error in processing due to heat, for example, when the temperature of the operating environment is high. In this case, there is a possibility that unauthorized writing is performed from the processing unit to the memory.

The present disclosure has been made in view of the above problems, and aims to provide an information processing device and a working machine that can restrict unauthorized writing from a processing unit to a memory.

In order to solve the above problems, the present specification provides a program which is connected between a processing unit, a memory storing a program, and the processing unit and the memory, and controls writing from the processing unit to the memory. and a memory controller that outputs a reset signal to the memory controller to restrict writing from the processing unit to the memory, and cancels the restriction by the reset signal in response to obtaining a permission signal from the processing unit . a reset circuit , wherein the memory has a write restriction function that restricts writing, the write restriction function can be canceled from the processing unit via the memory controller, and the processing unit receives an input from the outside When the program stored in the memory is updated according to the information received, the permission signal is output to release the restriction by the reset circuit, and the write restriction function is released via the memory controller. and when the update is completed, the memory is placed in a write-restricted state via the memory controller, the output of the permission signal is stopped, and the restriction is performed by the reset circuit. Disclose the device.

Further, the content of the present disclosure is not limited to the information processing device, and it is beneficial to implement it as a work machine provided with the information processing device.

According to the information processing device and the like of the present disclosure, the reset circuit restricts writing to the memory in the processing unit. Therefore, even if a processing error or the like occurs and the processing unit tries to execute unauthorized writing to the memory, the reset circuit can restrict unauthorized writing.

It is a top view showing a schematic structure of a component mounting system of this embodiment. It is a perspective view which shows schematic structure of a component mounting machine and a loader. 1 is a block diagram of a multiplex communication system; FIG. 2 is a block diagram showing the configuration of a first multiprocessing device; FIG. 10A and 10B are timing charts of a write operation to the memory of the comparative example and the memory of the present embodiment;

An embodiment of the present disclosure will be described below with reference to the drawings. FIG. 1 is a plan view showing a schematic configuration of a component mounting system 10 of this embodiment. FIG. 2 is a perspective view showing a schematic configuration of the component mounting machine 20 and the loader 13. As shown in FIG. In the following description, the left-right direction in FIG. 1 is called the X direction, the front-rear direction is called the Y direction, and the direction perpendicular to the X and Y directions is called the Z direction (vertical direction).

As shown in FIG. 1, the component mounting system 10 includes a production line 11, a loader 13, and a management computer 15. The production line 11 has a plurality of component mounters 20 arranged in the X direction, and mounts electronic components on the substrate 17 and the like. The board 17 is, for example, transported from the component mounting machine 20 on the left side shown in FIG.

As shown in FIG. 2, the component mounting machine 20 has a base 21 and a module 22 . The base 21 has a substantially rectangular box shape elongated in the Y direction, and is placed on the floor of a factory where the component mounting machine 20 is installed. For example, the base 21 is vertically positioned so as to align the board transfer devices 23 of adjacent modules 22, and is fixed to the base 21 of the adjacent component mounter 20. As shown in FIG. The module 22 is a device for mounting electronic components on the substrate 17 and is placed on the base 21 . The module 22 can be pulled out to the front side in the front-rear direction with respect to the base 21 and can be replaced with another module 22 .

The module 22 includes a substrate transfer device 23 , a feeder table 24 , a head section 25 and a head moving mechanism 27 . The substrate transfer device 23 is provided inside the module 22 and transfers the substrate 17 in the X direction. The feeder table 24 is provided on the front surface of the module 22 and is an L-shaped table when viewed from the side. The feeder table 24 has a plurality of slots (not shown) arranged in the X direction. A feeder 29 for supplying electronic components is attached to each slot of the feeder table 24 . The feeder 29 is, for example, a tape feeder that supplies electronic components from a tape containing electronic components at a predetermined pitch. Note that, as shown in FIG. 1, a touch panel 26 is provided on the upper cover of the module 22 for inputting operations to the component mounting machine 20 . FIG. 2 shows a state in which the upper cover and the touch panel 26 are removed.

The head unit 25 includes a suction nozzle (not shown) that sucks an electronic component supplied from a feeder 29 , and mounts the electronic component sucked by the suction nozzle onto the substrate 17 . The head unit 25 has, for example, an electromagnetic motor (not shown) as a drive source for changing the positions of a plurality of suction nozzles and the positions of individual suction nozzles. The head moving mechanism 27 moves the head section 25 to any position in the X and Y directions in the upper portion of the module 22 . Specifically, the head moving mechanism 27 includes an X-axis slide mechanism 27A that moves the head section 25 in the X direction, and a Y-axis slide mechanism 27B that moves the head section 25 in the Y direction. The X-axis slide mechanism 27A is attached to the Y-axis slide mechanism 27B. The X-axis slide mechanism 27A also includes a third slave 65 (see FIG. 3) connected to an industrial network, which will be described later. Various elements such as a relay 81 and a sensor 83 (see FIG. 3) provided in the X-axis slide mechanism 27A are connected to the third slave 65. Input/output signals of various elements are processed based on the CD.

The Y-axis slide mechanism 27B has a linear motor (not shown) as a drive source. The X-axis slide mechanism 27A moves to any position in the Y direction based on the drive of the linear motor of the Y-axis slide mechanism 27B. Also, the X-axis slide mechanism 27A has a linear motor (not shown) as a drive source. The head unit 25 is attached to the X-axis slide mechanism 27A and moves to any position in the X direction based on the drive of the linear motor of the X-axis slide mechanism 27A. Accordingly, the head section 25 moves to an arbitrary position on the upper portion of the module 22 as the X-axis slide mechanism 27A and the Y-axis slide mechanism 27B are driven.

Further, the head portion 25 is attached to the X-axis slide mechanism 27A via a connector, and can be attached and detached with one touch, and can be changed to a different type of head portion 25, for example, a dispenser head. Therefore, the head portion 25 of this embodiment can be attached to and detached from the component mounting machine 20 (an example of a work machine). A mark camera 69 (see FIG. 3) for photographing the substrate 17 is fixed to the head portion 25 while facing downward. The mark camera 69 can pick up an image of an arbitrary position on the substrate 17 from above as the head section 25 moves. The image data GD picked up by the mark camera 69 is image-processed in the body control device 51 (see FIG. 3) of the module 22 . The main body control device 51 acquires information about the substrate 17, an error in the mounting position, and the like by image processing.

The head unit 25 also includes a second slave 61 (see FIG. 3) connected to the industrial network. The second slave 61 is connected to various elements such as the relay 75 and the sensor 77 provided in the head section 25, and controls the various elements based on the control data CD received from the master 53 (see FIG. 3) of the device main body section 41. process the input and output signals of The head unit 25 is also provided with a parts camera 71 that captures an image of the electronic component sucked and held by the suction nozzle. The image data GD captured by the parts camera 71 is image-processed in the body control device 51 (see FIG. 3) of the module 22 . The main body control device 51 acquires the error of the holding position of the electronic component in the suction nozzle and the like by image processing.

Further, as shown in FIG. 2 , an upper guide rail 31 , a lower guide rail 33 , a rack gear 35 and a non-contact feeding coil 37 are provided on the front surface of the base 21 . The upper guide rail 31 is a rail with a U-shaped cross section extending in the X direction, and the opening faces downward. The lower guide rail 33 is a rail extending in the X direction and having an L-shaped cross section, and has a vertical surface attached to the front surface of the base 21 and a horizontal surface extending forward. The rack gear 35 is provided at the lower portion of the lower guide rail 33, extends in the X direction, and has a front surface with a plurality of vertical grooves. The upper guide rail 31 , lower guide rail 33 and rack gear 35 of the base 21 can be detachably connected to the upper guide rail 31 , lower guide rail 33 and rack gear 35 of the adjacent base 21 . Therefore, the component mounting machines 20 can increase or decrease the number of component mounting machines 20 arranged in the production line 11 . The contactless power feeding coil 37 is a coil provided on the upper portion of the upper guide rail 31 and arranged along the X direction, and supplies power to the loader 13 .

The loader 13 is a device that automatically replenishes and collects the feeder 29 for the component mounting machine 20 , and has a gripper (not shown) that clamps the feeder 29 . The loader 13 is provided with upper rollers (not shown) inserted into the upper guide rails 31 and lower rollers (not shown) inserted into the lower guide rails 33 . Moreover, the loader 13 is provided with a motor as a drive source. A gear meshing with the rack gear 35 is attached to the output shaft of the motor. The loader 13 includes a power receiving coil that receives power from the contactless power feeding coil 37 of the component mounter 20 . The loader 13 supplies the electric power received from the contactless power feeding coil 37 to the motor. Thus, the loader 13 can move in the X direction (horizontal direction) by rotating the gear with the motor. Moreover, the loader 13 can rotate the rollers in the upper guide rail 31 and the lower guide rail 33 and move in the X direction while maintaining the position in the vertical direction and the front-rear direction.

The management computer 15 shown in FIG. 1 is a device for centrally managing the component mounting system 10 . For example, the component mounting machine 20 of the production line 11 starts the electronic component mounting work based on the management of the management computer 15 . The component mounting machine 20 mounts electronic components using the head section 25 while conveying the board 17 . Management computer 15 also monitors the number of electronic components remaining in feeder 29 . For example, when the management computer 15 determines that the feeder 29 needs to be replenished, it displays on the screen an instruction to set the feeder 29 containing the part type requiring replenishment to the loader 13 . The user confirms the screen and sets the feeder 29 to the loader 13 . When the management computer 15 detects that the desired feeder 29 has been set in the loader 13, it instructs the loader 13 to start replenishment work. The loader 13 moves to the front of the component mounter 20 that has received the instruction, and mounts the feeder 29 set by the user in the slot of the feeder table 24 by gripping the feeder 29 with the grip portion. Thereby, a new feeder 29 is supplied to the component mounting machine 20 . In addition, the loader 13 holds the feeder 29 that has run out of components with the gripping portions, pulls it out from the feeder table 24, and collects it. In this way, the loader 13 can automatically supply a new feeder 29 and recover a feeder 29 that has run out of parts.

Next, a multiplex communication system provided in the component mounting machine 20 will be described. FIG. 3 is a block diagram showing the configuration of the multiplex communication system of the component mounting machine 20. As shown in FIG. As shown in FIG. 2, the component mounting machine 20 includes an apparatus main unit 41, a branch slave 43, and a fixed multiplexer 45 in the module 22. As shown in FIG. The device main unit 41 , branch slave 43 , and fixed multiplexer 45 are provided in the module 22 below the substrate transfer device 23 .

As shown in FIG. 3, in the multiplex communication system of the present embodiment, an apparatus main unit 41, a branch slave 43 and a fixed multiplexer 45 fixed within the module 22, and a movable unit (X-axis slide Data transmission between the mechanism 27A and the head unit 25) is performed by multiplex communication. The device main unit 41 has a main control device 51 and a master 53 . Also, the branch slave 43 is connected to the master 53 . The fixed multiplexer 45 includes a first multiplexer 55 . A first slave 57 of the first multiprocessing unit 55 is connected to the branch slave 43 . The head unit 25 is provided with a second multiprocessing device 63 having a second slave 61 . A third multiprocessing unit 67 having a third slave 65 is provided in the X-axis slide mechanism 27A.

Branch slave 43 , first slave 57 , second slave 61 and third slave 65 are controlled by master 53 . The master 53 centrally controls transmission of control data CD for controlling the branch slave 43, first slave 57, second slave 61, and third slave 65 connected to the industrial network. Industrial networks are, for example, EtherCAT®. The industrial network of the present disclosure is not limited to EtherCAT (registered trademark), and other networks (communication standards) such as MECHATROLINK (registered trademark)-III and Profinet (registered trademark) can be employed.

The main body control device 51 is, for example, a processing circuit mainly composed of a CPU. Determine the content (type of electronic component to be mounted, mounting position, etc.). Further, the main body control device 51 causes the master 53 to transmit the control data CD corresponding to the determined control contents. The master 53 transmits control data CD to the branch slave 43, the first slave 57, the second slave 61 and the third slave 65 via the industrial network.

The head section 25 has the above-described second multiprocessing device 63, mark camera 69, parts camera 71, and the like. The second slave 61 processes signals input and output by various elements (relay 75, sensor 77, etc.) based on the control data CD received from the master 53 of the apparatus main body 41. FIG. For example, in the control data CD, write areas and read areas are set for each of a plurality of slaves (second slave 61, etc.). The second slave 61 drives the relay 75 and the sensor 77 based on the data read from the read area for the second slave 61 in the control data CD received from the master 53 . In addition, the second slave 61 writes data corresponding to the drive result signal of the relay 75 and the detection signal of the sensor 77 into the write area for the second slave 61 in the control data CD. The second slave 61 transmits the written control data CD to the master 53 and other slaves (third slave 65, etc.). The control data CD is transmitted by multiple high-speed serial communication, which will be described later. Similarly to the second slave 61, the first slave 57 of the first multiprocessing unit 55 selects various elements provided in the fixed multiplexer 45 based on the control data CD received from the master 53 via the branch slave 43. Control.

Further, the third slave 65 of the X-axis slide mechanism 27A, like the second slave 61 of the head unit 25 described above, controls the relay 81, the sensor 83, etc. attached to the X-axis slide mechanism 27A based on the control data CD. to control. The control data CD is, for example, the master 53, the branch slave 43, the first slave 57, the second slave 61, the first slave 57, the third slave 65, the first slave 57, the branch slave 43, and the master 53 in this order. It is circulated and transmitted. The third slave 65 controls the relay 81 and the like based on the data in the read area of the control data CD received from the master 53 via the first slave 57 . Also, the third slave 65 writes data detected by the sensor 83 and the like in the write area of the control data CD and transmits the data to the master 53 via the first slave 57 .

Various elements (elements controlled by the control data CD) included in the head section 25, the X-axis slide mechanism 27A, and the like are not particularly limited. For example, the relay 81 of the X-axis slide mechanism 27A is a limit switch that outputs a drive signal for driving the brake of the linear motor of the X-axis slide mechanism 27A. The relay 81 outputs a drive signal to drive the brake, thereby suppressing overrun of the X-axis slide mechanism 27A, for example. Also, the sensor 83 of the X-axis slide mechanism 27A is a substrate height sensor that measures the height of the upper surface of the substrate 17 based on the reference height position set in the component mounting machine 20, for example.

Next, the multiplex communication for transmitting the control data CD of the industrial network and the image data GD of the parts camera 71 will be described. The component mounting machine 20 of this embodiment performs data transmission among the fixed multiplexer 45, the X-axis slide mechanism 27A and the head 25 by multiplexed high-speed serial communication. As shown in FIG. 3, the fixed multiplexer 45 has optical conversion modules 85 and 87 in addition to the first multiplexer 55 described above. The optical conversion module 85 is connected to an optical conversion module 89 of the head section 25 via an optical fiber cable 91 . Similarly, the optical conversion module 87 of the fixed multiplexer 45 is connected via an optical fiber cable 95 to the optical conversion module 93 of the X-axis slide mechanism 27A. The optical fiber cables 91 and 95 have improved bending resistance by adjusting the arrangement and thickness of the optical fiber lines in the cables, for example. As a result, even when the optical fiber cables 91 and 95 are bent due to the movement of the head section 25 and the X-axis slide mechanism 27A, data can be transmitted stably without damaging the optical fiber lines. The communication connecting the fixed multiplexing unit 45, the head unit 25, and the X-axis slide mechanism 27A is not limited to optical communication. good. Further, the communication system provided in the component mounting machine 20 is not limited to a wired communication system, and may be a wireless communication system.

Next, the configuration of the first multiprocessing device 55 will be described. The configurations of the second multiprocessing device 63 and the third multiprocessing device 67, which are multiprocessing devices other than the first multiprocessing device 55, are similar to that of the first multiprocessing device 55. FIG. Therefore, in the following description, the configuration of the first multiprocessing device 55 will be mainly described, and the configuration of the second multiprocessing device 63 and the third multiprocessing device 67 will be omitted.

FIG. 4 shows the configuration of the first multiprocessing unit 55. As shown in FIG. As shown in FIG. 4, the first multiprocessing device 55 comprises an FPGA 101 and a memory 105. FIG. The FPGA 101 is a Field Programmable Gate Array and a programmable logic device capable of constructing a logic circuit based on configuration information. The FPGA 101 includes a multiprocessing unit 121, a CPU 123, a memory controller 124, and a reset circuit 125 in addition to the first slave 57 described above. The first slave 57 is, for example, an IP core used for building logic circuits of programmable logic devices. Note that the programmable logic device of the present disclosure is not limited to FPGA, and may be programmable logic device (PLD) or composite programmable logic device (CPLD).

The multiplex processing unit 121 is a logic circuit built in the FPGA 101 based on configuration information 142 stored in the memory 105, which will be described later, and executes multiplex processing. For example, the multiplex processing unit 121 inputs and multiplexes the control data CD of the industrial network, the imaging start signal to be transmitted from the main body control device 51 to the mark camera 69 or the like, and the like. The multiplexing unit 121 performs multiplexing by, for example, a time division multiplexing method (TDM: Time Division Multiplexing). The multiplex processing unit 121, for example, multiplexes various types of input data according to a certain time (time slot) assigned to the input port, and outputs the multiplexed data to the optical conversion module 85 (see FIG. 3). to the head unit 25 via. Further, the multiplex processing unit 121 separates the multiplexed data received from the head unit 25 and the X-axis slide mechanism 27A. The configuration of the multiplex communication system shown in FIGS. 3 and 4 is an example and can be changed as appropriate. For example, the encoder signal of the encoder of the electromagnetic motor that is the driving source of the suction nozzle of the head unit 25 and the control command for the encoder may be multiplexed. Also, in the multiplex communication system of this embodiment shown in FIG. 3, the Y-axis slide mechanism 27B is not connected. However, for example, the encoder signal of the linear scale attached to the linear motor of the Y-axis slide mechanism 27B may be transmitted by a multiplex communication system.

The CPU 123 is a processing circuit mounted on the FPGA 101, and is NIOS (registered trademark)-II manufactured by Altera Corporation, for example. The CPU 123 is connected to the memory controller 124 via the bus 131, for example. Memory controller 124 is coupled to memory 105 via bus 132, for example. The memory 105 is, for example, an EPCQ (Quad Serial Configuration Device, registered trademark), and includes a flash memory that stores a control program 141 and configuration information 142 . The CPU 123 transmits and receives various signals to and from the memory 105 via the bus 131 , memory controller 124 and bus 132 . The various signals referred to here are the clock signal clk and the data signal data. Note that the configuration described above is an example. For example, the storage device for storing the control program 141 and configuration information 142 is not limited to EPCQ (flash memory), but may be EEPROM or the like.

For example, when power is supplied to the FPGA 101 when the component mounting machine 20 is activated, the CPU 123 reads the control program 141 from the memory 105 and executes it. The CPU 123 performs various controls by executing the control program 141 . In the following description, the CPU 123 that executes the control program 141 may be simply referred to as the CPU 123. For example, the description "the CPU 123" may mean "the CPU 123 that executes the control program 141".

For example, the CPU 123 processes control data CD transmitted and received by the first slave 57 via the industrial network as various controls. The CPU 123 outputs, for example, signals from relays and sensors (not shown) provided in the fixed multiplexer 45 to the first slave 57 . The first slave 57 writes the data according to the signals of the relays and sensors in the write area for the first slave 57 in the control data CD. Also, the first slave 57 outputs to the CPU 123 the data read from the read area for the first slave 57 among the control data CD received from the master 53 . The CPU 123 drives relays and sensors based on data input from the first slave 57 . Therefore, the control program 141 of this embodiment is a program used for controlling various operations of the component mounting machine 20 . In addition, the content of control by the control program 141 described above is an example. For example, the CPU of the second multiprocessing device 63 may execute encoder signal processing, control signal processing of the parts camera 71, and the like.

Further, for example, when power is supplied to the FPGA 101 when the component mounting machine 20 is activated, the CPU 123 reads out the configuration information 142 from the memory 105 and builds the logic circuit of the FPGA 101 . The CPU 123 constructs logic circuits such as the multiprocessing unit 121 based on the configuration information 142 read from the memory 105 .

In addition, the memory 105 of this embodiment has a write restriction function that restricts writing from the outside. Specifically, the memory controller 124 has a status register 124A. The memory controller 124 controls writing to the memory 105 according to the bit values of the status register 124A. Also, the memory 105, like the memory controller 124, has a status register 105A. The memory 105 takes in the data signal data via the bus 132 in synchronization with the clock signal clk, for example, when the bit value of the status register 105A is set to a value that permits writing. The memory 105 writes the fetched data to the specified address in the storage area. In addition, the memory 105 prohibits fetching of the data signal data and writing to the storage area when a value prohibiting writing is set as the bit value.

Also, the memory controller 124 synchronizes the bit values of the status register 124A and the bit values of the status register 105A of the memory 105, for example. For example, when executing writing to the memory 105, the CPU 123 rewrites the bit value of the status register 124A via the bus 131 to a value that permits writing. The memory controller 124 rewrites the bit value of the status register 105A of the memory 105 to a value that permits writing in response to the rewriting of the status register 124A. As a result, the memory 105 becomes writable.

After completing the writing to the memory 105, the CPU 123 changes the bit value of the status register 124A to a value that prohibits writing. The memory controller 124 rewrites the bit value of the status register 105A of the memory 105 to a value that prohibits writing in response to the rewriting of the status register 124A. As a result, the memory 105 enters a write-prohibited state. Therefore, the memory 105 of this embodiment can release the write restriction function from the CPU 123 via the memory controller 124 . Note that the method of realizing the write restriction function of the memory 105 is not limited to the method using the status registers 124A and 105A described above. For example, memory 105 may allow or inhibit writing depending on the signal level of a particular signal line included in bus 132 . For example, the memory 105 may permit writing when the signal level of any signal line included in the bus 132 is high, and prohibit writing when it is low. Also, the memory controller 124 may change the signal level of this signal line according to the bit value of the status register 124A.

The FPGA 101 also includes a reset circuit 125, as shown in FIG. The reset circuit 125 is, for example, a logic circuit constructed based on the configuration information 142 . The CPU 123 constructs the logic circuit of the reset circuit 125 based on the configuration information 142 read from the memory 105 when the FPGA 101 is activated, for example. Note that the reset circuit 125 is not limited to a logic circuit, and may be dedicated hardware such as an ASIC.

The reset circuit 125 outputs a reset signal rest to the memory controller 124 to restrict writing from the CPU 123 to the memory 105 . Therefore, the first multiprocessing unit 55 of the present embodiment has a configuration in which writing is restricted by the reset circuit 125 in addition to the write prohibiting function of the memory 105, and double writing is restricted.

The reset circuit 125 is connected to the CPU 123 via the bus 133, for example. The reset circuit 125 transmits/receives the clock signal clk1 and the enable signal EN via the bus 133 . The reset circuit 125 also outputs a reset signal rest to the memory controller 124 . The memory controller 124, for example, stops operating while receiving a high-level reset signal rest. In this state, the CPU 123 and the memory 105 are disconnected. Therefore, the CPU 123 is prohibited from writing to the memory 105 while the high-level reset signal rest is being output from the reset circuit 125 to the memory controller 124 .

Also, the memory controller 124 enters an operating state, for example, when a low-level reset signal rest is input. The CPU 123 enables writing to the memory 105 by rewriting the status register 124A of the memory controller 124 which is operating by inputting the low-level reset signal rest.

Also, the reset circuit 125 changes the signal level of the reset signal rest according to the signal level of the enable signal EN input from the CPU 123 via the bus 133, for example. For example, the reset circuit 125 sets the signal level of the reset signal rest to high level while receiving the high level enable signal EN from the CPU 123 . This makes it possible to stop the operation of the memory controller 124 and prohibit writing to the memory 105 .

For example, the CPU 123 sets the signal level of the enable signal EN to a high level while not executing writing to the memory 105 . Accordingly, in a normal state in which writing is not executed, the reset circuit 125 outputs a high-level reset signal rest to the memory controller 124 to stop the memory controller 124 . The signal levels of the reset signal rest and the enable signal EN described above are examples. For example, the memory controller 124 may be configured to stop operating while a low-level reset signal is being input.

The CPU 123 updates the control program 141 and configuration information 142 stored in the memory 105 based on information input from the outside. The CPU 123 may, for example, input configuration information 142 for updating from the device main body 41 or the management computer 15 . Further, the CPU (not shown) of the second multiprocessing device 63 of the head unit 25 and the CPU (not shown) of the third multiprocessing device 67 of the X-axis slide mechanism 27A communicate with the first multiprocessing device 55 via multiplex communication. configuration information, etc. may be received from the Also, the first multiprocessing device 55 may have an external interface for inputting the configuration information 142 . The external interface referred to here is, for example, a JTAG connector that executes communication conforming to the standard proposed by JTAG (Joint Test Action Group) defined by IEEE1149.1. The CPU 123 may update the configuration information 142 stored in the memory 105 with the configuration information 142 input via the JTAG connector.

The CPU 123 executes writing to the memory 105 when updating such configuration information 142 and the control program 141 . For example, when a low-level enable signal EN is input from the CPU 123, the reset circuit 125 changes the signal level of the reset signal rest to low level. This allows the memory controller 124 to operate and write to the memory 105 . By changing the signal level of the enable signal EN, the CPU 123 can change the operating state of the memory controller 124 and prohibit or permit writing to the memory 105 . It should be noted that the content of processing by the reset circuit 125 described above is an example. For example, the reset circuit 125 may change whether or not to output the reset signal rest depending on whether or not the enable signal EN is input. The reset circuit 125 may be configured to output the reset signal rest upon detecting the input of the enable signal EN. Thereby, the CPU 123 can control writing to the memory 105 by controlling the input of the enable signal EN.

Therefore, the reset circuit 125 of this embodiment cancels the restriction of the memory controller 124 by the reset signal rest in response to obtaining the low-level enable signal EN from the CPU 123 (an example of the processing unit). According to this, when the CPU 123 wants to execute writing to the memory 105 , the CPU 123 can output a low-level enable signal EN to the reset circuit 125 to cancel the restriction by the reset circuit 125 so that writing can be performed. Accordingly, the CPU 123 can execute writing to the memory 105 at appropriate timing by controlling the enable signal EN.

Further, when the reset circuit 125 of the present embodiment cannot acquire the low-level enable signal EN from the CPU 123, it outputs the high-level reset signal rest and maintains the restriction by the reset signal rest. According to this, the reset circuit 125 always sets the reset signal rest to high level and restricts writing while the low level enable signal EN cannot be obtained from the CPU 123 . This makes it possible to restrict unauthorized writing more reliably.

Note that the method of acquiring the enable signal EN is not limited to the above method. For example, the reset circuit 125 may monitor the state of the CPU 123 and acquire a response signal from the CPU 123 as the enable signal EN. When the reset circuit 125 cannot normally acquire the enable signal EN from the CPU 123 (for example, when the enable signal EN cannot be acquired for a certain period of time), the reset circuit 125 may set the reset signal rest to high level to prohibit writing. Alternatively, the reset circuit 125 may monitor an error occurring in the CPU 123 and set the reset signal rest to a high level to prohibit writing when an error is detected.

Further, the CPU 123 of this embodiment outputs a low-level enable signal EN to release the restriction by the reset circuit 125, rewrites the status register 124A of the memory controller 124, and releases the write restriction function of the memory 105. 105 is written. In such a configuration, writing to the memory 105 is restricted by two things: the write restriction function of the memory 105 itself and the restriction by the reset circuit 125 . In other words, unauthorized writing to memory 105 can be restricted twice.

Also, as described above, the control program 141 and the configuration information 142 stored in the memory 105 are executed when the FPGA 101 is activated. Therefore, the control program 141 and the configuration information 142 (an example of the program) of the present embodiment are startup programs executed by the CPU 123 (an example of the processing unit) when the first multiprocessing device 55 (an example of the information processing device) is started. . Therefore, according to the present embodiment, it is possible to restrict unauthorized writing that rewrites the startup program executed by the CPU 123 at the time of startup. As a result, the first multiprocessing device 55 and, in turn, the component mounting machine 20 can be started more stably.

Also, the first multiprocessing unit 55 has an FPGA 101 (an example of a programmable logic device) that constructs a logic circuit based on the configuration information 142 . The memory 105 stores configuration information 142 (an example of a program). According to this, unauthorized writing that rewrites the configuration information 142 necessary for constructing the logic circuit of the FPGA 101 can be restricted. As a result, the first multiprocessing unit 55 can be activated more stably.

Next, a write operation to the memory 105 will be described. As an example, an operation of rewriting the configuration information 142 stored in the memory 105 after starting the component mounting machine 20 will be described. FIG. 5 shows a comparative example and a timing chart of the write operation to the memory 105 of this embodiment.

The POWER ON signal shown in FIG. 5 indicates the timing at which power supply to the FPGA 101 is started. The status register signal indicates the state of the status registers 124A and 105A, and rises in the write-disabled state and falls in the write-enabled state. The FPGA and CPU operation signals indicate the operation states of the FPGA 101 and CPU 123, and rise when the FPGA 101 and CPU 123 are operating, and fall when the operations are stopped. A reset signal indicates the signal level of the reset signal rest. The memory write inhibit signal indicates the write inhibit state of the memory 105, rising in the write inhibit state and falling in the write enable state. The write to memory signal indicates the state of writing to the memory 105, and rises while the memory 105 is being written.

First, the timing chart of the comparative example shown in the upper diagram of FIG. 5 will be described. The configuration of the comparative example is, for example, a configuration without the reset circuit 125 . First, power is supplied to the FPGA 101 at time T1 shown in FIG. The status registers 124A and 105A are set with bit values that prohibit writing as initial values. As a result, the signal in the status register becomes write-inhibited (high level). Writing to the memory 105 is prohibited until power supply to the FPGA 101 stabilizes.

At time T2, the FPGA 101 and CPU 123 start activation processing. At this point, writing to the memory 105 is prohibited, but reading is enabled. The CPU 123 reads the control program 141 from the memory 105 and executes it. Also, the CPU 123 reads the configuration information 142 and executes construction of the multiprocessing unit 121 and the like.

Next, at time T5, the CPU 123 changes the bit values of the status registers 124A and 105A to writable values in order to rewrite the configuration information 142. FIG. After changing the status registers 124A and 105A, the CPU 123 executes the write processing of the memory 105 (time T6 to time T7). As a result, the configuration information 142 is rewritten with new data. After completing the writing, the CPU 123 resets the bit values of the status registers 124A and 105A to values indicating write prohibition (time T8).

Here, in the configuration of such a comparative example, writing to the memory 105 can be restricted by the status registers 124A and 105A. However, the processing of the CPU 123 is subject to errors. For example, the CPU 123 may cause an error in the processing content due to heat in the usage environment, erroneously change the values of the status registers 124A and 105A, and rewrite the configuration information 142 . Alternatively, the CPU 123 may cause an error due to an error in referring to an address in the memory space within the CPU 123 and rewrite the configuration information 142 . In contrast, in this embodiment, the reset circuit 125 can restrict such unauthorized writing.

As shown in the lower diagram of FIG. 5, for example, the FPGA 101 and the CPU 123 start activation processing at time T2 and complete the activation processing at time T3. The CPU 123 has not completed its startup from when the power of the component mounting machine 20 is turned on until time T3. During this time, the CPU 123 outputs a low-level enable signal EN.

After being activated, the reset circuit 125 changes the signal level of the reset signal rest to a low level when a low-level enable signal EN is input from the CPU 123 . Moreover, the reset signal rest is at a low level when the reset circuit 125 is not activated. This allows the memory controller 124 to operate and the CPU 123 to read the control program 141 and configuration information 142 from the memory 105 .

At time T3, when the execution of the control program 141 and the construction of the logic circuit based on the configuration information 142 are completed, the CPU 123 changes the enable signal EN to high level and the reset signal rest to high level. Thereby, writing to the memory 105 can be prohibited by the reset circuit 125 in addition to the status registers 124A and 105A. As a result, even if an error occurs in the processing of the CPU 123 as described above and an attempt is made to rewrite the bit values of the status registers 124A and 105A, the reset circuit 125 outputs a high-level reset signal rest to stop the operation of the memory controller 124. By stopping, writing to the memory 105 can be prohibited.

Next, at time T4, the CPU 123 sets the enable signal EN to low level and the reset signal rest to low level in order to execute writing to the memory 105 . As a result, the memory controller 124 becomes operational.

At time T5, the CPU 123 changes the bit values of the status registers 124A and 105A to writable values in order to rewrite the configuration information 142, as in the comparative example. After changing the status registers 124A and 105A, the CPU 123 executes the write processing of the memory 105 (time T6 to time T7).

After completing the writing, the CPU 123 restores the bit values of the status registers 124A and 105A to values that prohibit writing (time T8). At this point, writing to memory 105 is prohibited. Then, the CPU 123 sets the enable signal EN to high level and the reset signal rest to high level (time T9). As a result, writing to the memory 105 is doubly prohibited. In this manner, the reset circuit 125 of the first multiprocessing device 55 of this embodiment can restrict unauthorized writing to the memory 105 .

Incidentally, the component mounting machine 20 is an example of a work machine. The CPU 123 is an example of a processing unit. The first multiprocessing device 55 is an example of an information processing device. The control program 141 and configuration information 142 are examples of programs.

As described above, the present embodiment described above has the following effects.
In one aspect of this embodiment, memory controller 124 controls writes from CPU 123 to memory 105 via status register 124A. The reset circuit 125 outputs a reset signal rest to the memory controller 124 to restrict writing to the memory 105 . According to this, even if the CPU 123 tries to execute unauthorized writing to the memory 105 due to a processing error or the like, the reset circuit 125 can restrict unauthorized writing.

It goes without saying that the present disclosure is not limited to the above embodiments, and that various improvements and modifications are possible without departing from the scope of the present disclosure.
For example, although the first multiprocessing device 55 of the above embodiment includes one CPU 123, one memory controller 124, one reset circuit 125, and one memory 105, it may have more than one. For example, writing to a plurality of memories 105 may be restricted individually by a plurality of reset circuits 125 .
Also, in the above embodiment, three slaves (first to third slaves 57, 61, 65) are connected to one master 53, but the present invention is not limited to this. The number of masters 53 may be two or more. Also, the number of slaves may be two or more than four.
Further, the multiplex communication may be, for example, a frequency multiplexing method other than the time division multiplexing method.
Further, in the above-described embodiment, an example in which the component mounting machine 20 that mounts electronic components on the substrate 17 is employed as the work machine in the present disclosure has been described. However, the working machine in the present disclosure is not limited to the component mounting machine 20, and other board-to-board working machine such as a solder printing device can be adopted. Also, the work machine may be, for example, a machine tool or a robot that performs assembly work.

20 component mounting machine (working machine), 55 first multiprocessing device (information processing device), 105 memory, 123 CPU (processing unit), 124 memory controller, 125 reset circuit, 141 control program (program), 142 configuration information ( program), rest Reset signal.

Claims (6)

a processing unit;
a memory in which the program is stored;
a memory controller connected between the processing unit and the memory and controlling writing from the processing unit to the memory;
a reset circuit that outputs a reset signal to the memory controller, restricts writing from the processing unit to the memory, and cancels the restriction by the reset signal in response to obtaining a permission signal from the processing unit ;
with
The memory is
having a write restriction function that restricts writing, and can release the write restriction function from the processing unit via the memory controller;
The processing unit is
When the program stored in the memory is updated according to the information input from the outside, after the permission signal is output to release the restriction by the reset circuit and the write restriction function is released via the memory controller. , updating said program in said memory;
The information processing apparatus , wherein when the update is finished, the memory is placed in a write-restricted state via the memory controller, the output of the permission signal is stopped, and restriction is performed by the reset circuit . Said program
including a program for processing control data sent and received on an industrial network;
The processing unit is
2. The information processing apparatus according to claim 1, wherein said program for processing said control data is updated. 3. The information processing apparatus according to claim 1 , further comprising the reset circuit that maintains the restriction by the reset signal when the permission signal cannot be acquired from the processing unit. Said program
4. The information processing apparatus according to any one of claims 1 to 3, comprising a boot program executed by said processing unit when said information processing apparatus is booted. Equipped with a programmable logic device that builds a logic circuit based on configuration information,
The programmable logic device is
constructing a multiplex processing unit for generating multiplexed data to be transmitted in multiplex communication by the logic circuit based on the configuration information;
Said program
including the configuration information;
The processing unit is
5. The information processing apparatus according to claim 1 , wherein said configuration information stored in said memory is updated based on said configuration information received via said multiplex communication . A work machine comprising the information processing device according to any one of claims 1 to 5, wherein data relating to work is processed by the information processing device.

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