WO2020136705A1

WO2020136705A1 - Multiplex communication device and working machine

Info

Publication number: WO2020136705A1
Application number: PCT/JP2018/047491
Authority: WO
Inventors: 伸夫長坂; 憲司渡邉
Original assignee: 株式会社Ｆｕｊｉ
Priority date: 2018-12-25
Filing date: 2018-12-25
Publication date: 2020-07-02
Also published as: JPWO2020136705A1; JP7209014B2

Abstract

The present invention provides a multiplex communication device which can be easily checked for processing details of the multiplex communication device, and a working machine.　The multiplex communication device is configured to be communicable with a communication unit. The multiplex communication device is provided with: a logic analyzer unit for outputting a processing signal subjected to processing by the multiplex communication device as a JTAG signal; and a multiplexing unit for transmitting, to the communication unit, multiplexed data in which a plurality of signals including the JTAG signal are multiplexed.

Description

Multiplex communication device and work machine

The present disclosure relates to a technique for confirming the processing content of a device that performs multiplex communication.

Conventionally, there is an electronic component mounting machine that performs optical wireless multiplex communication between the control device and the mounting head (for example, Patent Document 1). In the electronic component mounting machine described in Patent Document 1, the mounting work is performed while performing multiplex communication between the optical wireless device connected to the control device and the optical wireless device connected to the mounting head.

Japanese Patent Laid-Open No. 2005-53594

For example, the mounting head described above is equipped with various sensors, cameras, servo motors, etc., and processes signals that control these devices. When confirming the processing signal for debugging the processing in the mounting head or investigating a defect, it is necessary to connect a terminal for investigation to the mounting head. For example, it may be necessary to disassemble the mounting head in order to connect a surveying cable. In addition, for example, movement of the mounting head may cause disconnection or disconnection of the investigation cable. Therefore, there is a problem in that the confirmation work becomes complicated when it is attempted to confirm the processing contents of a device that performs multiplex communication, such as a mounting head.

The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a multiplex communication device and a work machine that can easily confirm the processing content.

In order to solve the above problems, the present specification describes a multiplex communication apparatus configured to be communicable with a communication unit, and a logic analyzer section that outputs a processing signal processed by the multiplex communication apparatus as a JTAG signal, A multiplex communication device is disclosed, comprising: a multiplexing unit that transmits multiplexed data obtained by multiplexing a plurality of signals including the JTAG signal to the communication unit.

Further, the content of the present disclosure is not limited to the implementation of the multiplex communication device, and is also useful when implemented as a work machine including the multiplex communication device.

According to the multiplex communication device and the like of the present disclosure, the JTAG signal output from the logic analyzer unit can be multiplexed and transmitted to the communication unit. On the communication unit side, by separating the JTAG signal from the multiplexed data, the processed signal processed by the multiplex communication device can be confirmed. Thereby, the processing content of the multiplex communication device can be easily confirmed on the communication unit side.

It is a top view which shows schematic structure of the component mounting system of this embodiment. It is a perspective view showing a schematic structure of a component mounting machine and a loader. It is a block diagram of a multiplex communication system. It is a figure which shows the content of the multiplexed data transmitted from a fixed part board|substrate to a mounting head in the multiplex communication of an optical fiber cable. It is a figure which shows the content of the multiplexed data transmitted from a mounting head to a fixed part board|substrate in the multiplex communication of an optical fiber cable. It is a flow chart which shows a processing procedure for controlling a TAP controller. It is a figure which shows an example of the observation screen of PC for FPGA development.

Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is a plan view showing a schematic configuration of a component mounting system 10 of this embodiment. FIG. 2 is a perspective view showing a schematic configuration of the component mounting machine 20 and the loader 13. In the following description, the horizontal direction of FIG. 1 is referred to as the X direction, the vertical direction of FIG. 1 is referred to as the front-back direction (Y direction), and the direction perpendicular to the X and Y directions is referred to as the Z direction (vertical direction). Will be described.

As shown in FIG. 1, the component mounting system 10 includes a production line 11, a loader 13, and a host computer 15. The production line 11 has a plurality of component mounting machines 20 arranged in the X direction, and mounts electronic components (not shown) on the board 17. The board 17 is, for example, carried out from the left component mounting machine 20 shown in FIG. 1 to the right component mounting machine 20, and electronic components are mounted during transportation.

As shown in FIG. 2, the component mounting machine 20 includes a base 21 and a module 22. The base 21 has a substantially rectangular parallelepiped shape in the Y direction and is placed on the floor or the like of the factory where the component mounting machine 20 is installed. The position of the base 21 in the vertical direction is adjusted so that, for example, the positions of the substrate transfer devices 23 of the adjacent modules 22 are aligned. The base 21 is fixed to the base 21 of the adjacent component mounting machine 20. The module 22 is a device that mounts electronic components on the board 17, and is mounted on the base 21. The module 22 can be pulled out to the front side in the front-rear direction with respect to the base 21, and can be replaced with another module 22.

The module 22 includes a substrate transfer device 23, a feeder base 24, a mounting head 25, and a head moving mechanism 27. The substrate transfer device 23 is provided in the module 22 and transfers the substrate 17 in the X direction. The feeder base 24 is provided on the front surface of the module 22 and is an L-shaped base in a side view. The feeder table 24 includes slots (not shown) arranged in the X direction. A feeder 29 for supplying electronic components is attached to each slot of the feeder base 24. The feeder 29 is, for example, a tape feeder that supplies electronic components from a tape containing the electronic components at a predetermined pitch. As shown in FIG. 1, on the upper cover of the module 22, a touch panel 26 for performing operation input to the component mounting machine 20 is provided. FIG. 2 shows a state in which the upper cover and the touch panel 26 are removed.

The mounting head 25 has a holding member (not shown) that holds the electronic components supplied from the feeder 29. As the holding member, for example, a suction nozzle that is supplied with a negative pressure to hold an electronic component, a chuck that grips and holds an electronic component, or the like can be adopted. The mounting head 25 has, for example, a plurality of servo motors 75 (see FIG. 3) as a drive source for changing the overall positions of the plurality of holding members and the positions of the individual holding members. The holding member rotates, for example, based on the driving of the servo motor 75, about an axis along the Z direction. The mounting head 25 mounts the electronic component held by the holding member on the board 17.

Further, the head moving mechanism 27 moves the mounting head 25 to an arbitrary position in the X direction and the Y direction in the upper portion of the module 22. More specifically, the head moving mechanism 27 includes an X-axis slide mechanism 27A that moves the mounting head 25 in the X direction and a Y-axis slide mechanism 27B that moves the mounting head 25 in the Y direction. The X-axis slide mechanism 27A is attached to the Y-axis slide mechanism 27B.

Also, the X-axis slide mechanism 27A includes, for example, a slave 61 (see FIG. 3) connected to an industrial network. The industrial network here is, for example, EtherCAT (registered trademark). Note that the industrial network of the present disclosure is not limited to EtherCAT (registered trademark), and other networks (communication standards) such as MECHATROLINK (registered trademark)-III and Profinet (registered trademark) can be adopted. The slave 61 is connected to various elements such as a relay and a sensor provided in the X-axis slide mechanism 27A, and outputs signals to and from the various elements based on control data received from the apparatus main body 41 (see FIG. 3). To process.

The Y-axis slide mechanism 27B has a linear motor (not shown) as a drive source. The X-axis slide mechanism 27A moves to an arbitrary position in the Y direction based on the drive of the linear motor of the Y-axis slide mechanism 27B. Further, the X-axis slide mechanism 27A has a linear motor 77 (see FIG. 3) as a drive source. The mounting head 25 is attached to the X-axis slide mechanism 27A, and moves to an arbitrary position in the X direction based on the driving of the linear motor 77 of the X-axis slide mechanism 27A. Therefore, the mounting head 25 moves to an arbitrary position in the X direction and the Y direction within the module 22 in accordance with the driving of the X-axis slide mechanism 27A and the Y-axis slide mechanism 27B.

The mounting head 25 is attached to the X-axis slide mechanism 27A via a connector and can be attached and detached with one touch, and can be changed to a different type of mounting head 25, for example, a dispenser head or the like. Therefore, the mounting head 25 of the present embodiment is attachable to and detachable from the component mounting machine 20 (an example of a working machine). Further, a mark camera 69 (see FIG. 3) for photographing the substrate 17 is fixed to the X-axis slide mechanism 27A in a state of facing downward. The mark camera 69 can image an arbitrary position of the substrate 17 from above as the head moving mechanism 27 moves. The image data captured by the mark camera 69 is transmitted from the X-axis slide mechanism 27A to the apparatus main body 41 by multiplex communication described later, and is image-processed by the image processing board 87 (see FIG. 3) of the apparatus main body 41. The image processing board 87 acquires information (marks and the like) about the board 17 and error of the mounting position by image processing.

The mounting head 25 also includes a slave 62 (see FIG. 3) connected to the industrial network described above. Various elements such as a relay and a sensor provided on the mounting head 25 are connected to the slave 62. The slave 62 processes signals input to and output from various elements based on the control data received from the apparatus main body 41 (see FIG. 3). Further, the mounting head 25 is provided with a parts camera 71 that images the electronic components held by the holding member. The image data captured by the parts camera 71 is transmitted from the mounting head 25 to the apparatus body 41 by multiplex communication, and is image-processed by the image processing board 87 (see FIG. 3) of the apparatus body 41. The image processing board 87 acquires an error or the like of the holding position of the electronic component on the holding member by image processing.

Further, as shown in FIG. 2, an upper guide rail 31, a lower guide rail 33, a rack gear 35, and a non-contact power feeding coil 37 are provided on the front surface of the base 21. The upper guide rail 31 is a rail having a U-shaped cross section that extends in the X direction, and the opening thereof faces downward. The lower guide rail 33 is a rail having an L-shaped cross section that extends in the X direction, has a vertical surface attached to the front surface of the base 21, and a horizontal surface extending forward. The rack gear 35 is a gear that is provided below the lower guide rail 33, extends in the X direction, and has a plurality of vertical grooves formed on the front surface. The upper guide rail 31, the lower guide rail 33, and the rack gear 35 of the base 21 can be detachably connected to the upper guide rail 31, the lower guide rail 33, and the rack gear 35 of the adjacent base 21. Therefore, the component mounting system 10 can increase or decrease the number of component mounting machines 20 lined up in the production line 11. The non-contact power feeding coil 37 is a coil provided in the upper portion of the upper guide rail 31 and arranged along the X direction, and supplies electric power to the loader 13.

The loader 13 is a device that automatically replenishes and collects the feeder 29 with respect to the component mounting machine 20, and includes a grip portion (not shown) that clamps the feeder 29. The loader 13 is provided with an upper roller (not shown) inserted into the upper guide rail 31 and a lower roller (not shown) inserted into the lower guide rail 33. Further, the loader 13 is provided with a motor as a drive source. A gear that meshes with the rack gear 35 is attached to the output shaft of the motor. The loader 13 includes a power receiving coil that receives power from the non-contact power feeding coil 37 of the component mounting machine 20. The loader 13 supplies the electric power received from the non-contact power feeding coil 37 to the motor. Accordingly, the loader 13 can move in the X direction (left and right direction) by rotating the gear by the motor. Further, the loader 13 can rotate in the upper guide rail 31 and the lower guide rail 33 and move in the X direction while maintaining the position in the up-down direction and the front-rear direction.

The host computer 15 shown in FIG. 1 is a device that comprehensively manages the component mounting system 10. For example, the component mounting machine 20 of the production line 11 starts the mounting work of electronic components based on the management of the host computer 15. The component mounting machine 20 performs the mounting work of the electronic component by the mounting head 25 while conveying the board 17. The host computer 15 also monitors the number of remaining electronic components of the feeder 29. For example, when the host computer 15 determines that the feeder 29 needs to be replenished, the host computer 15 displays on the screen an instruction to set the feeder 29 accommodating the component type that needs the replenishment in the loader 13. The user confirms the screen and sets the feeder 29 on the loader 13. When the host computer 15 detects that the desired feeder 29 is set in the loader 13, the host computer 15 instructs the loader 13 to start the supply operation. The loader 13 moves to the front of the component mounting machine 20 that has received the instruction, clamps the feeder 29 set by the user with the gripping portion, and mounts the feeder 29 in the slot of the feeder base 24. As a result, a new feeder 29 is supplied to the component mounting machine 20. Further, the loader 13 holds the feeder 29, which has run out of parts, by the gripping portion, pulls it out from the feeder base 24, and collects it. In this way, the new feeder 29 can be replenished and the feeder 29 that has run out of parts can be automatically collected by the loader 13.

Next, the multiple communication system provided in the component mounting machine 20 will be described. FIG. 3 is a block diagram showing a configuration of a multiplex communication system applied to the component mounting machine 20. As shown in FIG. 2, the component mounting machine 20 includes a device main body 41 and a fixed substrate 45 in a module 22. The apparatus main body portion 41 and the fixed portion substrate 45 are provided in the module 22 below the substrate transfer device 23. As shown in FIG. 3, in the component mounting machine 20 of the present embodiment, a fixed portion substrate 45 fixed inside the module 22, a movable portion (X-axis slide mechanism 27A and mounting head 25) that moves within the module 22. Data transmission between the two is performed by optical communication (multiplex communication) via the optical fiber cables 81 and 82.

The device body 41 includes a servo amplifier 83, a device control main board 85, and an image processing board 87. Further, the fixed part substrate 45 has an FPGA (Field Programmable Gate Array) 91, a JTAG connector 92, transmission side

photoelectric converters

93A and 94A, reception side

photoelectric converters

93B and 94B, and a multiple JTAG connector 96. .. Further, the X-axis slide mechanism 27A has an X-axis substrate 95, a mark camera 69, a linear motor 77, and a linear scale 78. The mounting head 25 has a head substrate 97, a parts camera 71, a servomotor 75, and an encoder 76.

In the component mounting machine 20 of this embodiment, various data of the mounting head 25 and the devices of the X-axis slide mechanism 27A are transmitted and received by multiplexed optical communication. The various data mentioned here are, for example, a linear scale signal of the linear scale 78 of the X-axis slide mechanism 27A and an encoder signal of the encoder 76 of the mounting head 25. The various data are image data of the mark camera 69 and the parts camera 71, for example. The various data are control data of the slave 61 of the X-axis slide mechanism 27A and the slave 62 of the mounting head 25. An example of the data to be multiplexed will be described later with reference to FIGS. 4 and 5, but the present invention is not limited to this.

The FPGA 91 of the fixed unit board 45 multiplexes the data input from the servo amplifier 83 of the apparatus body 41, the apparatus control main board 85, and the image processing board 87. For example, the FPGA 91 constructs a logic circuit that reads configuration information from a non-volatile memory (not shown) at the time of startup and performs a multiplexing process. The FPGA 91 multiplexes input data by, for example, a time division multiplexing method (TDM: Time Division Multiplexing). The FPGA 91 multiplexes, for example, various data input from the servo amplifier 83 or the like according to a fixed time (time slot) assigned to the input port, and the multiplexed multiplexed data is transmitted side

photoelectric converters

93A and 94A. Via the X-axis slide mechanism 27A and the mounting head 25.

The JTAG connector 92 is connected to the FPGA 91. The JTAG connector 92 is, for example, a connector that executes communication in accordance with the standard proposed by JTAG (Joint Test Action Group) defined by IEEE1149.1. The JTAG connector 92 has pins for inputting and outputting a JTAG signal. The JTAG signal is a signal in a format conforming to JTAG. The JTAG connector 92 has pins for inputting/outputting JTAG signals such as TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data In), and TDO (Test Data Out), which will be described later. .. Further, the JTAG connector 92 has pins for ground and VCC in addition to the signals described above.

The FPGA 91 can input config information via the JTAG connector 92 and can build a logic circuit based on the input config information. Further, the fixed part substrate 45 can update the configuration information of the non-volatile memory based on the configuration information input via the JTAG connector 92, read it into the FPGA 91 at the next activation, and can activate it. .. As a result, the fixed part substrate 45 can perform initial setting of the config information based on the information input via the JTAG connector 92, for example. For example, the worker of the manufacturer of the component mounting machine 20 connects the setting PC to the JTAG connector 92. The operator operates the setting PC and outputs the configuration information to the FPGA 91 and the nonvolatile memory of the fixed part substrate 45 via the JTAG connector 92. As a result, it is possible to set the configuration information at the time of factory shipment.

Further, the component mounting machine 20 of the present embodiment transmits a JTAG signal for executing the debug function of the FPGA 103 of the X-axis slide mechanism 27A and the FPGA 113 of the mounting head 25, which will be described later, in multiplex communication. The multiplex JTAG connector 96 is a connector used for inputting and outputting multiplexed JATG signals. Details will be described later.

Further, the X-axis substrate 95 of the X-axis slide mechanism 27A has a transmission side photoelectric converter 101A, a reception side photoelectric converter 101B, an FPGA 103, and a JTAG connector 105. As shown in FIG. 3, the X-axis substrate 95 of the X-axis slide mechanism 27A and the head substrate 97 of the mounting head 25 have the same configuration as the fixed portion substrate 45. Therefore, in the description of the X-axis substrate 95 and the head substrate 97, the description of the same configuration as the fixed part substrate 45 will be appropriately omitted. The transmission side photoelectric converter 93A and the reception side photoelectric converter 93B of the fixed part substrate 45 are connected to the transmission side photoelectric converter 101A and the reception side photoelectric converter 101B of the X-axis slide mechanism 27A via the optical fiber cable 81. There is. The FPGA 103 multiplexes the image data of the mark camera 69, the linear scale signal of the linear scale 78, the control data of the slave 61, and the like. The X-axis board 95 is capable of inputting configuration information and the like via the JTAG connector 105, similarly to the fixed section board 45 described above.

Similarly, the head substrate 97 of the mounting head 25 has a transmission side photoelectric converter 111A, a reception side photoelectric converter 111B, an FPGA 113, and a JTAG connector 115. The transmission side photoelectric converter 94A and the reception side photoelectric converter 94B of the fixed part substrate 45 are connected to the transmission side photoelectric converter 111A and the reception side photoelectric converter 111B of the mounting head 25 via the optical fiber cable 82. The FPGA 113 multiplexes the image data of the parts camera 71 of the mounting head 25, the encoder signal of the encoder 76, the control data of the slave 62, and the like. The circuits (

FPGAs

91, 103, 113) that perform the multiplexing process are not limited to FPGAs, and may be programmable logic devices (PLDs) or composite programmable logic devices (CPLDs). Further, the multiplexing process may be realized by a process by an application specific integrated circuit (ASIC), a software process by a CPU, or the like.

The optical fiber cables 81 and 82 are, for example, those in which the bending resistance is enhanced by adjusting the arrangement and thickness of the optical fiber lines in the cables. As a result, even if the optical fiber cables 81 and 82 are bent due to the movement of the mounting head 25 and the X-axis slide mechanism 27A, data can be stably transmitted without damaging the optical fiber lines. The communication for connecting the fixed part substrate 45, the mounting head 25, and the X-axis slide mechanism 27A is not limited to wired communication, but may be optical wireless communication using a laser or the like.

The transmission side photoelectric converter 93A of the fixed part substrate 45 converts the multiplexed data multiplexed by the FPGA 91 into an optical signal and transmits it to the reception side photoelectric converter 101B of the X-axis substrate 95 via the optical fiber cable 81. .. The reception side photoelectric converter 101B converts the optical signal received from the transmission side photoelectric converter 93A into a photocurrent of an electric signal and outputs the photoelectric current to the FPGA 103. The FPGA 103 of this embodiment has an AD conversion circuit and the like, and converts an analog photocurrent into a digital signal for processing.

Further, the FPGA 103 executes demultiplexing of the converted digital signal, that is, multiplexed data, and separates the multiplexed data into the multiplexed data. The FPGA 103 outputs the separated various data to the corresponding device. As a result, multiplex communication (optical communication) in which various data are multiplexed is executed between the fixed part substrate 45 and the X-axis slide mechanism 27A. Similarly, the FPGA 103 multiplexes the image data of the mark camera 69 and transmits the multiplexed data to the reception side photoelectric converter 93B of the fixed part substrate 45 via the transmission side photoelectric converter 101A. The FPGA 91 demultiplexes the multiplexed data and outputs the separated various data to the image processing board 87 of the apparatus main body 41 or the like.

Also, the fixed part substrate 45 performs multiple optical communication with the mounting head 25 as well as the X-axis slide mechanism 27A. The transmission side photoelectric converter 94A and the reception side photoelectric converter 94B of the fixed part substrate 45 are connected to the transmission side photoelectric converter 111A and the reception side photoelectric converter 111B of the head substrate 97 via the optical fiber cable 82. The FPGA 91 of the fixed part substrate 45 performs multiplex communication with the FPGA 113 of the head substrate 97 via the optical fiber cable 82. The multiplex communication line of the optical fiber cables 81 and 82 is, for example, full duplex communication of 5 Gbps.

The device main body 41 of the present embodiment executes control of the X-axis slide mechanism 27A and the mounting head 25 by the above-described multiplex optical communication. The servo amplifier 83 of the apparatus body 41 executes initialization processing for the linear scale 78 of the X-axis slide mechanism 27A, acquisition processing of a linear scale signal, and the like. The linear scale 78 transmits a linear scale signal indicating the slide position of the X-axis slide mechanism 27A to the servo amplifier 83 via multiplex communication. The servo amplifier 83 is connected to the linear motor 77 of the X-axis slide mechanism 27A via a power supply line (not shown), and changes the power supplied to the linear motor 77 based on the linear scale signal of the linear scale 78. Then, the feedback control for the linear motor 77 is executed. The device control main board 85 controls the servo amplifier 83 based on the production program received from the host computer 15. As a result, the X-axis slide mechanism 27A moves to the position in the X direction based on the production program.

Similarly, the servo amplifier 83 executes initialization processing for the encoder 76 of the mounting head 25, encoder signal acquisition processing, and the like. The encoder 76 transmits an encoder signal indicating the rotational position of the servo motor 75 to the servo amplifier 83 via multiplex communication. As described above, the servo motor 75 functions as a drive source that drives the holding member of the mounting head 25. The servo amplifier 83 is connected to the encoder 76 of the mounting head 25 via a power line (not shown), and performs feedback control for the servo motor 75 based on the encoder signal of the encoder 76. As a result, the mounting head 25 rotates or vertically moves the holding member based on the production program.

The device control main board 85 of the device body 41 can control the X-axis slide mechanism 27A and the relays and sensors of the mounting head 25 via the above-mentioned industrial network. The device control main board 85 functions as a master in the industrial network, and transmits control data to the slave 61 of the X-axis slide mechanism 27A and the slave 62 of the mounting head 25 via multiplex communication. The

slaves

61 and 62 drive relays and sensors based on the control data received from the device control main board 85. In addition, the

slaves

61 and 62 write the value of the signal acquired from the relay or the sensor in the control data and transmit the control data to the device control main board 85 via the multiplex communication. As a result, the device control main board 85 can control the relay and the like of each device.

The configuration of the multiplex communication system shown in FIG. 3 is an example and can be changed as appropriate. For example, a linear scale signal attached to a linear motor (not shown) of the Y-axis slide mechanism 27B (see FIG. 2) may be transmitted by multiplex communication. Further, the signal of the relay or the like of the Y-axis slide mechanism 27B may be transmitted by multiplex communication. Further, the fixed part substrate 45 may include a slave controlled by the device control main substrate 85. The slave 61 may be a circuit block of the FPGA 103 (IP core or the like), that is, a part of the FPGA 103. Further, the component mounting machine 20 does not have to include devices related to the industrial network (circuits functioning as masters of the device control main board 85,

slaves

61, 62, etc.).

With the above configuration, the device control main board 85 controls the component mounting machine 20 based on the production program received from the host computer 15. The apparatus control main board 85 is, for example, a processing circuit mainly composed of a CPU, and executes processing based on a production program. The device control main board 85 receives the data collected by the industrial network, the linear scale signal of the linear scale 78, the encoder signal of the encoder 76, and the like via multiplex communication. Further, the apparatus control main board 85 inputs the result (error of the holding position, etc.) obtained by processing the image data picked up by the mark camera 69 or the parts camera 71 by the image processing board 87. The device control main board 85 determines the next control content (type of electronic component to be mounted, mounting position, etc.) based on these data and the like. The device control main board 85 controls various devices according to the determined control content.

(Structure of multiplexed data)
Next, the contents of the multiplexed data transmitted by the above-mentioned multiplex communication will be described. FIG. 4 shows the contents of multiplexed data transmitted from the fixed part substrate 45 to the mounting head 25 in the multiplex communication of the optical fiber cable 82. FIG. 5 shows the content of the multiplexed data transmitted from the mounting head 25 to the fixed part substrate 45 in the optical fiber cable 82. Note that the data arrays and data contents in FIGS. 4 and 5 are examples. Further, regarding the multiplexed data transmitted by the optical fiber cable 81 that connects the fixed part substrate 45 and the X-axis slide mechanism 27A, the same configuration as the multiplexed data of the optical fiber cable 82 can be adopted, and therefore the description thereof will be made. Omit it.

Each of FIG. 4 and FIG. 5 shows 32-bit (8-bit blocks A to D) multiplexed data. For example, the multiplexed data is converted into 8B/10B every 8 bits (each block) in order to maintain the DC balance of the transmission data, and has a total of 40 bits. Therefore, in the multiplexed data, for example, one frame is composed of 40 bits. For example, when the cycle per frame is set to 8 nsec (frequency is 125 MHz), the

FPGAs

91 and 113 construct a multiplexed communication line of 5 Gbps (40 bits×125 MHz).

4 and 5 show multiplexed data for each clock (for example, 8 nsec). Further, FIGS. 4 and 5 show data of 10 clocks of 0-9. The first block A (BIT (bit) 0 to BIT 7) of the multiplexed data transmitted from the fixed substrate 45 shown in FIG. 4 is used for transmitting a control command or the like to the mounting head 25, for example. This command is, for example, a symbol for controlling a K code (K code) in 8B/10B conversion. Further, the same data as the block A is set in the block B of the multiplexed data shown in FIG. As the error correction method for blocks A and B, for example, Reed-Solomon code can be used. A 1-bit value indicating the presence or absence of data is set in blocks A and B. The bit value indicating the presence or absence of the data is effective for the blocks A and B when the communication speed between the devices that input/output the data to be transmitted in the blocks A and B is slow with respect to the communication speed of the multiplex communication (5 Gbps). It is a value indicating whether or not various data are set. As a result, the receiving-side device that receives the data of blocks A and B can detect whether or not valid data is set based on the bit value indicating the presence or absence of this data, and process the data or discard the data. Can be done quickly.

The pixel values (image data) of the parts camera 71 are set in blocks A and B of the multiplexed data transmitted from the mounting head 25 shown in FIG. As an error correction method, for example, Reed-Solomon code can be used. When the mounting head 25 includes a plurality of cameras, the blocks A and B may be used separately for transmitting the image data of each camera.

Further, in the multiplexed data block C (BIT1 to BIT5) shown in FIG. 4, control signals for controlling the parts camera 71 are set. The control signals here are, for example, control signals CC1 to CC4 in the case of the camera link standard. Alternatively, the control signal is, for example, a trigger signal (CAM-TRG in the drawing) for instructing the parts camera 71 to capture an image. Further, in BIT0 of the block C, a bit value indicating the presence or absence of the data of the block C is set.

Also, in the BIT6 of the block C, a parity bit (K code flag in the figure) for detecting whether or not a burst error exceeding the correction capability has occurred in the encoding of the block B by the Reed-Solomon code. It is set. Specifically, for example, in the setting of encoding by the Reed-Solomon code, the setting is such that consecutive errors of two blocks can be continuously corrected. In this case, if continuous errors of 3 blocks or more occur in multiplex communication, the receiving side (mounting head 25) cannot correct the data. Therefore, for example, even parity corresponding to 8 bits of the block B is set in the BIT6 of the block C, and when a continuous error of three or more blocks is detected on the receiving side, abnormal stop or correction of the image data ( The case where the fixed part substrate 45 of FIG. 5 is on the receiving side) is executed. Further, the parity bit corresponding to the block A is set in the BIT7 of the block C, similarly to the BIT6. In the block C of the multiplexed data shown in FIG. 5, parity bits (K code flag in the figure) are set in BIT6 and BIT7, as in FIG. The blank portion shown in FIG. 5 indicates an empty bit for which data is not set.

Further, the encoder signal of the encoder 76 of the mounting head 25 is set in BIT0 to BIT3 of the block D in FIGS. 4 and 5. In the case of FIG. 4, the encoder signal mentioned here is an initial setting signal transmitted from the servo amplifier 83 to the encoder 76, a signal for inquiring about the state, a signal for acquiring position information, and the like. Further, in the case of FIG. 5, the encoder signal is a signal indicating position information or the like transmitted from the encoder 76 to the servo amplifier 83. For example, the mounting head 25 includes four sets of servo motors 75 and encoders 76. In this case, the mounting head 25 can move the holding member in the movement directions of the four axes. In FIGS. 4 and 5, four BITs 0 to 3 are set corresponding to each of such four-axis encoders 76. A Hamming code, for example, can be used as an error correction method for the data of BIT0 to BIT6 of the block D.

In BIT0 of block D, encoder signal data is set in the first 4 clocks (clocks 0 to 4 in FIGS. 4 and 5) of 10 clocks (E1 in FIGS. 4 and 5). An encoder signal is assigned to each bit position in

clocks

0 and 2. Further, at each bit position in the

clocks

1 and 3, information indicating the presence/absence of data of the encoder signal (“presence/absence of E1” in FIGS. 4 and 5) is allocated in bits. As described above, the information indicating the presence/absence of data indicates that, for example, when the data transfer rate of the encoder signal is lower than the data transfer rate of the multiplexed data, the low-speed encoder signal indicates each bit position (BIT0 This is information for indicating whether or not the clock is set to 0, 1). The encoder signal and the information indicating the presence/absence of the encoder signal are set alternately every cycle.

Further, in the clock 4 of BIT0, timeout information indicating whether or not a timeout error has occurred in the communication between the servo amplifier 83 and the encoder 76 is set. In addition, a bit value for cyclic redundancy check (CRC) is set to the clock 5 of BIT0 by the transmitting side (“CRC abnormality” in FIGS. 4 and 5). A 4-bit code bit, which is a Hamming code of the forward error correction code, is set in clocks 6 to 9 of BIT0. The error correction code is, for example, a shortened form of the Hamming code (15, 11). Further, as in the case of BIT0, 4-bit code bits are set in the clocks 6 to 9 of BIT1 to BIT6. Upon receiving the multiplexed data, the

FPGAs

91 and 103 perform error detection and correction on the data of the demultiplexed encoder signal and the like based on the error correction code. Note that the data related to the encoder signal is set in BIT1 to BIT3 as in BIT0.

The control signal of the parts camera 71 is set in BIT4 of the block D shown in FIGS. 4 and 5. The control signal mentioned here is, for example, a control signal for UART communication for controlling lighting of the parts camera 71 when the parts camera 71 is a camera of the camera link standard. Information relating to data values of clocks 0 to 3 is set in

clocks

4 and 5 of BIT4.

Data related to an industrial network, for example, MECHATROLINK (registered trademark)-III is set in

BITs

5 and 6 of the block D shown in FIGS. 4 and 5 (“MIII” in FIGS. 4 and 5). Such). This data is control data for the slave 62. Control data of MECHATROLINK (registered trademark)-III is set in 4 bits of clocks 0 to 3 of

BITs

5 and 6. Information indicating the presence or absence of data is set in the clock 4 of the

BITs

5 and 6. Further, a bit value for cyclic redundancy check (CRC) is set on the clock 5 of

BITs

5 and 6 by the transmitting side.

Also, in the BIT 7 of the block D shown in FIGS. 4 and 5, data of the JTAG signal for executing the debug function of the FPGA 113 of the mounting head 25 is set. No error correction method is set for the data of the JTAG signal. It should be noted that an error correction code may be added to the JATG signal data as in the case of other data.

BIT7 TCK (Test Clock) is a clock signal (Test Clock) in the JTAG standard, and is used, for example, as a system clock of a serial data bus connecting a JTAG connector. As shown in FIG. 3, the FPGA 113 of this embodiment includes a TAP controller 121 (an example of a logic analyzer unit) and a multiplexing unit 123. The FPGA 91 of the fixed unit substrate 45 and the FPGA 103 of the X-axis slide mechanism 27A include a TAP controller and a multiplexing unit, like the FPGA 113. Since the drawings are complicated, the TAP controllers of the

FPGAs

91 and 103 are not shown.

TAP controller 121 is, for example, Altera (registered trademark) Inc. Signal TAP (registered trademark) and Xilinx (registered trademark) Inc. This is a logic circuit used in a logic analyzer such as ChipScope. The TAP controller 121 is constructed as a logic circuit of the FPGA 113. The TAP controller 121 is, for example, a 16-state state machine. The 16 states here are, for example, the Test-Logic-Rest state that resets the test logic and the Run-Test/Idle state that maintains the idle state. The TAP controller 121 takes in signals other than TCK (TMS, TDI, TDO) at the rising edge of TCK, for example. The TAP controller 121 executes acquisition of an observation target signal set by the logic analyzer software described later. Further, the TAP controller 121 outputs the captured signal as a JTAG signal (BIT7 of block D in FIG. 5) to the multiplexing unit 123 based on a trigger condition or the like.

The multiplexing unit 123 is constructed as a logic circuit of the FPGA 113. The multiplexing unit 123 performs the multiplexing process in the FPGA 113, that is, the demultiplexing of the multiplexed data shown in FIG. 4 and the multiplexing process of the multiplexed data shown in FIG.

BIT7 TMS (Test Mode Select) in block D of FIG. 4 is data for controlling the state transition of the TAP controller 121. The TAP controller 121 transits between the 16 states according to the TMS signal received from the logic analyzer software of the FPGA development PC 127 (see FIG. 3) described later, for example. As a result, the FPGA development PC 127 can execute control on the TAP controller 121. TDI (Test Data In) of BIT7 in FIG. 4 is input data to the TAP controller 121 such as instruction data, test data, and circuit data. The TAP controller 121 inputs the TDI signal to its own registers and the like. TDO (Test Data Out) of BIT7 in FIG. 5 is output data from the TAP controller 121 such as instruction data, test data, and circuit data. As shown in FIGS. 4 and 5, TCK, TMS, and TDO(TDI) are sequentially transmitted every clock (every 8 nsec). The configuration of the multiplexed data shown in FIGS. 4 and 5 is an example, and may be changed as appropriate according to the required communication speed, the type and number of devices attached to the component mounting machine 20, and the like. For example, a reset signal (TRST) may be multiplexed and transmitted as a JTAG signal.

As shown in FIG. 3, the fixed part substrate 45 of the present embodiment includes a multiple JTAG connector 96. Three multiple JTAG connectors 96 are provided corresponding to the TAP controllers 121 of the

FPGAs

91, 103, and 113. For example, each of the three multiple JTAG connectors 96 is connected to the FPGA development PC 127 via the JTAG device 125, as shown in FIG. The JTAG device 125 is connected to the FPGA development PC 127 via a cable 126. The cable 126 is, for example, a USB cable that performs communication conforming to the USB standard. In this case, the JTAG device 125 is a converter that converts the serial cable connected to the multiple JTAG connector 96 into a USB standard cable.

The FPGA development PC 127 is a personal computer mainly composed of a CPU. The FPGA development PC 127 is connected to the component mounter 20 when setting, changing, or adding a circuit of the TAP controller 121. The FPGA development PC 127 executes the logic analyzer software stored in the hard disk by the CPU to set the TAP controller 121 of the

FPGAs

91, 103, 113 and control the TAP controller 121. The logic analyzer software referred to here is, for example, Altera (registered trademark) Inc. Signal TAP (registered trademark) and Xilinx (registered trademark) Inc. It is software that provides a user interface for setting the logic analyzer function such as ChipScope. Therefore, in the component mounting machine 20 of the present embodiment, the logic analyzer software of the FPGA development PC 127 connected to the fixed board 45 can set the TAP controller of the FPGA 91 of the fixed board 45. Moreover, the logic analyzer software of the FPGA development PC 127 can set the TAP controller 121 of the

FPGA

91, 113 of the movable part (X-axis slide mechanism 27A and mounting head 25) via the multiplex communication system of the component mounting machine 20. It is possible.

(About logic analyzer software)
Next, the control of the TAP controller 121 by the logic analyzer software of the FPGA development PC 127 will be described. FIG. 6 is a flowchart showing a processing procedure for controlling the TAP controller 121. In the following description, the TAP controller 121 of the FPGA 113 of the mounting head 25 will be described as an example. As with the FPGA 113, the FPGA 103 can also be set to a TAP controller (not shown).

First, in step 11 of FIG. 6 (hereinafter, simply referred to as S) 11, the user operates the FPGA development PC 127 to activate the logic analyzer software. The user creates a design file (Signal TAP file in the case of Signal TAP (registered trademark)) for mounting the TAP controller 121 on the FPGA 113.

At S13, the user operates the logic analyzer software to set the clock signal and the observed signal. The TAP controller 121 samples the signal to be observed, for example, in synchronization with the rising edge of the clock signal set in S13. Therefore, the clock signal is, for example, a signal for setting a trigger condition for starting observation of the processed signal. The logic analyzer software can acquire information on various processed signals processed by the FPGA 113 based on the configuration information of the FPGA 113, for example. Alternatively, the logic analyzer software may execute communication with the FPGA 113 and acquire information on the processing signal of the FPGA 113.

Logic analyzer software displays the acquired processing signal information on the monitor of FPGA development PC 127. The user confirms the display on the monitor and selects a clock signal or a signal to be observed from the processed signals of the FPGA 113. As the signal to be observed, for example, a processed signal processed by the multiplexing unit 123 can be adopted. As the processing signal of the multiplexing unit 123, in addition to image data, control data of an industrial network, an encoder signal, etc., a signal indicating the establishment of a link for multiplex communication of the optical fiber cable 82, a signal indicating an abnormality such as a link disconnection, etc. Can be adopted. Note that other signals processed by the FPGA 113 (such as signals from various sensors) can also be used as the signals to be observed.

When the processing signal of the multiplexing unit 123 is selected as the signal to be observed, the TAP controller 121, as described later, the processing signal of the multiplexing unit 123 in the multiplexing unit 123 in the JTAG signal format (TDO signal or the like). Output to. The multiplexing unit 123 multiplexes the JTAG signal input from the TAP controller 121 into multiplexed data and transmits the multiplexed data. Therefore, the TAP controller 121 of this embodiment outputs the processed signal processed by the multiplexing unit 123 as a JTAG signal. As a result, a signal indicating the establishment of a link for multiplex communication can be transmitted by multiplex communication, and the content of the signal can be confirmed on the fixed part substrate 45 side.

Further, for example, as the logic circuit of the FPGA 113, a logic circuit that changes a specific signal level when a data error of an encoder signal or the like occurs may be built in the TAP controller 121. Then, this specific signal may be set as an observation target signal. Thereby, the abnormality of the encoder signal can be observed.

Next, the user operates the logic analyzer software to compile the design file and generate a post-compiled file (SOF file in the case of Signal TAP (registered trademark)) (S15). Next, the file after compilation is executed from the FPGA development PC 127 to the FPGA 113 (S17). For example, the user operates the logic analyzer software and selects the cable 126 corresponding to the FPGA 113 from the cables 126 connected to each of the three multiplexed JTAG connectors 96. As a result, the download destination of the compiled file can be selected.

When the user executes the download, the compiled file is input from the FPGA development PC 127 to the multiplexing unit (not shown) of the FPGA 91 via the multiple JTAG connector 96. The multiplexing unit of the FPGA 91 multiplexes the data of the compiled file into the BIT 7 of the block D of the multiplexed data shown in FIG. 4, for example. In this case, the BIT7 of the block D of the multiplexed data is used for the transmission of the compiled file in the initial processing, and is used for the transmission of the JTAG signal when the observation is started. It should be noted that transmission of the compiled file may be executed using bits other than BIT7 of the block D of the multiplexed data.

The FPGA 113 changes the circuit configuration of the TAP controller 121 by, for example, receiving the file after compilation and changing a part of the logic circuit. As a result, the signal to be observed by the TAP controller 121 can be changed, and the contents of the JTAG signal output from the TAP controller 121 and the trigger condition for starting the capture can be changed. The TAP controller 121 starts up with the changed circuit configuration and starts observing the processed signal (S19). Further, the user starts the mounting work of the component mounting machine 20 and executes the test operation and the like.

This will start the analysis via multiplex communication (S21). Specifically, for example, the logic analyzer software of the FPGA development PC 127 appropriately changes the state of the TAP controller 121 using the TMS signal. Further, the logic analyzer software uses the TDI signal to execute an instruction or the like to the TAP controller 121. The TAP controller 121 samples the observation target signal set by the user and outputs it as a JTAG signal (TDO signal or the like) to the multiplexing unit 123. The multiplexing unit 123 transmits the JTAG signal input from the TAP controller 121 to the FPGA 91 of the fixed unit substrate 45 via multiplex communication. The multiplexing unit of the FPGA 91 separates the BIT7 of the block D shown in FIG. 5 from the multiplexed data, and outputs the JTAG signal to the FPGA development PC 127 via the multiplex JTAG connector 96. The logic analyzer software transmits the JTAG signal of the response or the instruction again to the FPGA 113. The JTAG signal transmitted between the logic analyzer software of the FPGA development PC 127 and the FPGA 113 is transmitted by BIT7 of block D shown in FIGS.

If the processing signal of the FPGA 113 is analyzed using the JTAG connector 115 of the mounting head 25, it may be necessary to disassemble the mounting head 25 or the like. Further, the cable connected to the movable mounting head 25 may be dropped or broken. On the other hand, in the present embodiment, by operating the FPGA development PC 127, various controls can be performed on the TAP controller 121 of the FPGA 113 connected by multiplex communication. This eliminates the need to disassemble the mounting head 25 or the like in order to analyze the processing signal of the FPGA 113.

FIG. 7 shows an example of the observation screen displayed on the FPGA development PC 127 by the logic analyzer software. As shown in FIG. 7, on the observation screen, a waveform display unit 131 that displays the waveform of the signal to be observed set in S13 of FIG. 6 is displayed. The waveform of each observation target signal is displayed on the waveform display unit 131. The user can confirm the state of the processing signal of the FPGA 113 by confirming this waveform. For example, when an error occurs in the mounting work of the component mounting machine 20, the cause of the error can be analyzed from the state of the processing signal at the time of occurrence.

The waveform display unit 131 displays the waveform of a signal with the horizontal axis representing time, for example. Zero (0) of the time indicates, for example, the time when the sampling of the processed signal is started, that is, the rising timing of the clock signal set in S13 (the time when the trigger condition is satisfied).

Various setting buttons 133 are displayed on the waveform display unit 131. For example, when the save button of the setting button 133 is pressed, the FPGA development PC 127 performs a process of saving the observation target signal data displayed on the waveform display unit 131. Further, in response to the execution button being pressed, the FPGA development PC 127 starts the output (sampling) of a signal to the TAP controller 121. In addition, in response to pressing the stop button, the FPGA development PC 127 causes the TAP controller 121 to stop outputting signals. The setting button is a button for displaying a screen for changing various conditions such as changing the signal to be observed.

Also, on the right side of the waveform display unit 131, a USB cable selection display screen 135 that displays the selected cable 126 is displayed. By operating the pull-down menu of the USB cable selection display screen 135, the user can select the cable 126, that is, the

target FPGA

91, 103, 113 (TAP controller 121). For example,

USB cable numbers

1, 2, and 3 in the pull-down menu correspond to the

FPGAs

91, 103, and 113 in that order. By performing the observation using such an observation screen, it becomes possible to observe the processed signals of the

FPGAs

91, 103, 113 through the multiplex communication.

Here, the FPGA 113 of the present embodiment is provided on the mounting head 25 that is movable with respect to the fixed fixing portion substrate 45. As described above, the FPGA 113 of the mounting head 25 transmits the JTAG signal to the fixed part substrate 45 by multiplex communication. As a result, it is not necessary to connect a surveying cable or the like to the mounting head 25 to directly obtain the processing signal from the mounting head 25. As a result, when confirming the processing contents of the device such as the mounting head 25 that performs multiplex communication, the confirmation work becomes easy.

The TAP controller 121 is a logic circuit composed of FPGA. According to this, after confirming the processing signal on the fixed unit substrate 45 side, it is possible to change the logic circuit of the TAP controller 121, change the processing signal to be acquired, and the like as necessary.

The FPGA 113 is also provided in the mounting head 25 that mounts electronic components on the board 17. In the component mounting machine 20 that mounts electronic components on the board 17 by the mounting head 25, work is performed while moving the mounting head 25 at high speed. For this reason, if the mounting work is performed while the surveying cable is connected to the mounting head 25, the cable may drop or break, making debugging more difficult. Therefore, in the component mounting machine 20 including the mounting head 25, it is extremely effective to transmit the processing signal from the mounting head 25 as a JTAG signal by multiplex communication.

Incidentally, the component mounting machine 20 is an example of a working machine. The FPGA 113 of the mounting head 25 is an example of a multiplex communication device. The fixed part substrate 45 is an example of a communication part. The TAP controller 121 is an example of a logic analyzer unit. The FPGA development PC 127 is an example of a display device.

As described above, according to this embodiment described above, the following effects can be obtained.
In one aspect of this embodiment, the FPGA 113 transmits to the fixed unit substrate 45 the TAP controller 121 that outputs a processing signal processed by the FPGA 113 as a JTAG signal, and the multiplexed data obtained by multiplexing a plurality of signals including the JTAG signal. And a multiplexing unit 123 for

According to this, the JTAG signal output from the TAP controller 121 can be multiplexed and transmitted to the fixed part substrate 45. On the fixed unit substrate 45 side, by separating the JTAG signal from the multiplexed data, the processing signal processed by the FPGA 113 (on the mounting head 25 side) can be confirmed. As a result, the processed signal can be obtained by multiplex communication, and it is not necessary to connect a surveying cable to the mounting head 25, and it is not necessary to disassemble the mounting head 25. Further, since the survey cable is not connected, there is no possibility that the survey cable may be dropped or disconnected due to the movement of the mounting head 25. Therefore, the processing content of the mounting head 25 can be easily confirmed. Further, since necessary processing signals can be transmitted to the fixed part substrate 45 side by multiplex communication, it is not necessary to provide a large-capacity storage part for accumulating the processing signals on the head substrate 97 or the like.

Needless to say, the present disclosure is not limited to the above-described embodiments, and various improvements and changes can be made without departing from the spirit of the present disclosure.
For example, the multiplex communication device that transmits the JTAG signal by multiplex communication is not limited to a movable device, but may be a fixed device.
In addition, the TAP controller 121 does not have to output the processing signal processed by the multiplexing unit 123 (such as a signal indicating the establishment of a link) as a JTAG signal.
Further, the TAP controller 121 and the multiplexing unit 123 do not have to be programmable logic devices such as FPGA. For example, the processing by the TAP controller 121 and the multiplexing unit 123 may be realized by hardware processing such as ASCI, or may be realized by software processing by executing a program by the CPU.

Further, in the above-described embodiment, the component mounting machine 20 that mounts electronic components on the board 17 is adopted as the working machine of the present disclosure, but the working machine is not limited to this. For example, as the working machine, various working machines such as a solder coating device for coating the substrate 17 with solder, a machine tool, and a nursing robot can be adopted.
Further, the component mounting machine 20 may be configured without the FPGA development PC 127.

17 boards, 25 mounting heads, 20 component mounting machines (working machines), 45 fixed part boards (communication parts), 113 FPGAs (multiplex communication devices), 121 TAP controllers (logic analyzer parts), 123 multiplex parts, 127 FPGA development PC (display device).

Claims

A multiplex communication device configured to communicate with a communication unit,
A logic analyzer unit for outputting a processing signal processed by the multiplex communication device as a JTAG signal;
A multiplexing unit that transmits multiplexed data obtained by multiplexing a plurality of signals including the JTAG signal to the communication unit;
A multiplex communication device comprising:
The communication unit is
It is a fixed part,
The multiplex communication device,
The multiplex communication device according to claim 1, wherein the multiplex communication device is configured to be movable with respect to the fixed portion.
The logic analyzer unit,
The multiplex communication device according to claim 1 or 2, which outputs the processed signal processed by the multiplexing unit as the JTAG signal.
The logic analyzer unit,
4. The multiplex communication device according to claim 1, wherein the multiplex communication device comprises a programmable logic device that constructs a logic circuit based on configuration information.
A working machine equipped with the multiplex communication device according to any one of claims 1 to 4.
Equipped with a mounting head that mounts electronic components on the board,
The multiplex communication device,
The work machine according to claim 5, which is provided in the mounting head.
The working machine according to claim 5 or 6, further comprising a display device that is connected to the communication unit and displays a waveform of the processing signal based on the JTAG signal received by the multiplexed data.