JP7209014B2 - work machine - Google Patents

Description

TECHNICAL FIELD The present disclosure relates to technology for confirming processing details of a device that performs multiplex communication.

Conventionally, there is an electronic component mounting machine that performs optical wireless multiplex communication for communication between a control device and a mounting head (for example, Patent Document 1, etc.). In the electronic component mounting machine described in Patent Document 1, mounting work is performed while performing multiplex communication between an optical wireless device connected to a control device and an optical wireless device connected to a mounting head.

JP 2015-53594 A

For example, the mounting head described above includes various sensors, cameras, servo motors, etc., and processes signals for controlling these devices. When checking processed signals for debugging processing in the mounting head or investigating defects, it becomes necessary to connect a terminal for investigation to the mounting head. For example, it becomes necessary to disassemble the mounting head in order to connect cables for investigation. Further, for example, there is a possibility that the cable for investigation may come off or break due to the movement of the mounting head. For this reason, when trying to confirm the processing contents of a device that performs multiplex communication, such as the mounting head, there is a problem that the confirmation work becomes complicated.

The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a work machine that allows easy confirmation of processing details.

In order to solve the above problems, the present specification provides a fixed part substrate , a multiplex communication device configured to enable wired multiplex communication between the fixed part substrate , and an operation provided with the multiplex communication device. and a main unit for controlling the operation of the working unit, wherein the multiplex communication device includes a logic analyzer unit for outputting a JTAG signal as a processed signal processed by the multiplex communication device. and a multiplexing unit for transmitting multiplexed data obtained by multiplexing a plurality of signals including the JTAG signal to the fixed unit board , wherein the apparatus main unit transmits control information transmitted via the wired multiplex communication. The fixed part board has a connection part that can be connected to an information processing device that processes the JTAG signal, and the control information and the JTAG signal are multiplexed. transmitting the multiplexed data to and from the multiplex communication device, separating the control information from the multiplexed data received from the multiplex communication device and outputting the control information to the device main unit, and separating the JTAG signal from the multiplexed data is separated and output to the information processing device, the working section is a mounting head that mounts an electronic component on a board, and the apparatus main body section transfers the mounting head to the control information via the fixing section board. The logic analyzer unit outputs the processed signal processed by the multiplex communication device as the JTAG signal in response to the control of the mounting head by the control information, and the device main body unit output the JTAG signal regardless of the control instruction based on the control information from to the mounting head; The processing unit can create a compile file using logic analyzer software, and the logic analyzer unit changes the logic circuit based on the compile file received from the information processing unit via the fixed unit board, and performs the multiplexing. A work machine is disclosed in which a data area used by the apparatus main body for transmitting the control information and a data area used by the information processing apparatus for transmitting the compile file are separately set in the compilation data .

According to the multiplex communication device and the like of the present disclosure, the JTAG signal output from the logic analyzer section can be multiplexed and transmitted to the communication section. By separating the JTAG signal from the multiplexed data on the communication unit side, it is possible to confirm the processed signal processed by the multiplex communication device. As a result, the processing contents of the multiplex communication device can be easily confirmed on the communication unit side.

It is a top view showing a schematic structure of a component mounting system of this embodiment. It is a perspective view which shows schematic structure of a component mounting machine and a loader. 1 is a block diagram of a multiplex communication system; FIG. FIG. 4 is a diagram showing the contents of multiplexed data transmitted from the fixed part substrate to the mounting head in multiplex communication of the optical fiber cable; FIG. 10 is a diagram showing the contents of multiplexed data transmitted from the mounting head to the fixed part substrate in multiplex communication of the optical fiber cable; 4 is a flow chart showing a processing procedure for controlling a TAP controller; It is a figure which shows an example of the observation screen of PC for FPGA development.

An embodiment of the present disclosure will be described below with reference to the drawings. FIG. 1 is a plan view showing a schematic configuration of a component mounting system 10 of this embodiment. FIG. 2 is a perspective view showing a schematic configuration of the component mounting machine 20 and the loader 13. As shown in FIG. In the following description, the left-right direction in FIG. 1 is called the X direction, the up-down direction in FIG. will be named and explained.

As shown in FIG. 1, the component mounting system 10 includes a production line 11, a loader 13, and a host computer 15. The production line 11 has a plurality of component mounters 20 arranged in the X direction, and mounts electronic components (not shown) on the substrate 17 . The board 17 is, for example, transported from the component mounting machine 20 on the left side shown in FIG.

As shown in FIG. 2, the component mounting machine 20 has a base 21 and a module 22 . The base 21 has a substantially rectangular parallelepiped shape in the Y direction and is placed on the floor of a factory where the component mounting machine 20 is installed. The vertical position of the base 21 is adjusted, for example, so that the positions of the board transfer devices 23 of the adjacent modules 22 are aligned. The base 21 and the base 21 of the adjacent component mounting machine 20 are fixed to each other. The module 22 is a device for mounting electronic components on the substrate 17 and is placed on the base 21 . The module 22 can be pulled forward in the front-rear direction with respect to the base 21 and can be replaced with another module 22 .

The module 22 includes a substrate transfer device 23 , a feeder table 24 , a mounting head 25 and a head moving mechanism 27 . The substrate transfer device 23 is provided inside the module 22 and transfers the substrate 17 in the X direction. The feeder table 24 is provided on the front surface of the module 22 and is an L-shaped table when viewed from the side. The feeder table 24 has a plurality of slots (not shown) arranged in the X direction. A feeder 29 for supplying electronic components is attached to each slot of the feeder table 24 . The feeder 29 is, for example, a tape feeder that supplies electronic components from a tape containing electronic components at a predetermined pitch. Note that, as shown in FIG. 1, a touch panel 26 is provided on the upper cover of the module 22 for inputting operations to the component mounting machine 20 . FIG. 2 shows a state in which the upper cover and the touch panel 26 are removed.

The mounting head 25 has a holding member (not shown) that holds electronic components supplied from the feeder 29 . As the holding member, for example, a suction nozzle that receives negative pressure to hold the electronic component, a chuck that grips and holds the electronic component, or the like can be employed. The mounting head 25 has, for example, a plurality of servomotors 75 (see FIG. 3) as drive sources for changing the overall position of the plurality of holding members and the positions of individual holding members. The holding member rotates around an axis extending in the Z direction, for example, when driven by a servomotor 75 . The mounting head 25 mounts the electronic component held by the holding member on the board 17 .

Also, the head moving mechanism 27 moves the mounting head 25 to any position in the X direction and the Y direction in the upper portion of the module 22 . Specifically, the head moving mechanism 27 includes an X-axis slide mechanism 27A that moves the mounting head 25 in the X direction, and a Y-axis slide mechanism 27B that moves the mounting head 25 in the Y direction. The X-axis slide mechanism 27A is attached to the Y-axis slide mechanism 27B.

The X-axis slide mechanism 27A also includes, for example, a slave 61 (see FIG. 3) connected to an industrial network. The industrial network here is, for example, EtherCAT (registered trademark). The industrial network of the present disclosure is not limited to EtherCAT (registered trademark), and other networks (communication standards) such as MECHATROLINK (registered trademark)-III and Profinet (registered trademark) can be employed. The slave 61 is connected to various elements such as relays and sensors provided in the X-axis slide mechanism 27A, and receives signals input/output from the various elements based on control data received from the apparatus main body 41 (see FIG. 3). process.

The Y-axis slide mechanism 27B has a linear motor (not shown) as a drive source. The X-axis slide mechanism 27A moves to any position in the Y direction based on the drive of the linear motor of the Y-axis slide mechanism 27B. The X-axis slide mechanism 27A also has a linear motor 77 (see FIG. 3) as a drive source. The mounting head 25 is attached to the X-axis slide mechanism 27A and moves to any position in the X direction based on the drive of the linear motor 77 of the X-axis slide mechanism 27A. Accordingly, the mounting head 25 moves to any position in the X and Y directions within the module 22 as the X-axis slide mechanism 27A and the Y-axis slide mechanism 27B are driven.

Moreover, the mounting head 25 is attached to the X-axis slide mechanism 27A via a connector, and can be attached and detached with one touch, and can be changed to a different type of mounting head 25, for example, a dispenser head. Therefore, the mounting head 25 of this embodiment can be attached to and detached from the component mounting machine 20 (an example of a work machine). A mark camera 69 (see FIG. 3) for photographing the substrate 17 is fixed to the X-axis slide mechanism 27A while facing downward. The mark camera 69 can take an image of an arbitrary position on the substrate 17 from above as the head moving mechanism 27 moves. The image data captured by the mark camera 69 is transmitted from the X-axis slide mechanism 27A to the device main body 41 by multiplex communication, which will be described later, and image-processed in the image processing board 87 (see FIG. 3) of the device main body 41. FIG. The image processing board 87 acquires information (marks, etc.) on the board 17, mounting position errors, etc. by image processing.

The mounting head 25 also includes a slave 62 (see FIG. 3) connected to the industrial network described above. Various elements such as relays and sensors provided in the mounting head 25 are connected to the slave 62 . The slave 62 processes signals input and output from various elements based on control data received from the device main body 41 (see FIG. 3). Also, the mounting head 25 is provided with a parts camera 71 that captures an image of the electronic component held by the holding member. Image data captured by the parts camera 71 is transmitted from the mounting head 25 to the device main body 41 by multiplex communication, and image-processed in the image processing board 87 (see FIG. 3) of the device main body 41 . The image processing board 87 acquires the error of the holding position of the electronic component in the holding member by image processing.

Further, as shown in FIG. 2 , an upper guide rail 31 , a lower guide rail 33 , a rack gear 35 and a non-contact feeding coil 37 are provided on the front surface of the base 21 . The upper guide rail 31 is a rail with a U-shaped cross section extending in the X direction, and the opening faces downward. The lower guide rail 33 is a rail extending in the X direction and having an L-shaped cross section, and has a vertical surface attached to the front surface of the base 21 and a horizontal surface extending forward. The rack gear 35 is provided at the lower portion of the lower guide rail 33, extends in the X direction, and has a front surface with a plurality of vertical grooves. The upper guide rail 31 , lower guide rail 33 and rack gear 35 of the base 21 can be detachably connected to the upper guide rail 31 , lower guide rail 33 and rack gear 35 of the adjacent base 21 . Therefore, the component mounting system 10 can increase or decrease the number of component mounting machines 20 arranged in the production line 11 . The contactless power feeding coil 37 is a coil provided on the upper portion of the upper guide rail 31 and arranged along the X direction, and supplies power to the loader 13 .

The loader 13 is a device that automatically replenishes and collects the feeder 29 for the component mounting machine 20 , and has a gripper (not shown) that clamps the feeder 29 . The loader 13 is provided with upper rollers (not shown) inserted into the upper guide rails 31 and lower rollers (not shown) inserted into the lower guide rails 33 . Moreover, the loader 13 is provided with a motor as a drive source. A gear meshing with the rack gear 35 is attached to the output shaft of the motor. The loader 13 includes a power receiving coil that receives power from the contactless power feeding coil 37 of the component mounter 20 . The loader 13 supplies the electric power received from the contactless power feeding coil 37 to the motor. Thus, the loader 13 can move in the X direction (horizontal direction) by rotating the gear with the motor. Moreover, the loader 13 can rotate the rollers in the upper guide rail 31 and the lower guide rail 33 and move in the X direction while maintaining the position in the vertical direction and the front-rear direction.

The host computer 15 shown in FIG. 1 is a device for centrally managing the component mounting system 10 . For example, the component mounting machine 20 of the production line 11 starts the electronic component mounting operation based on the management of the host computer 15 . The component mounting machine 20 mounts electronic components using a mounting head 25 while conveying the board 17 . Host computer 15 also monitors the number of electronic components remaining in feeder 29 . For example, when the host computer 15 determines that the feeder 29 needs to be replenished, it displays on the screen an instruction to set the feeder 29 containing the part type requiring replenishment to the loader 13 . The user confirms the screen and sets the feeder 29 to the loader 13 . When the host computer 15 detects that the desired feeder 29 has been set in the loader 13, it instructs the loader 13 to start replenishment work. The loader 13 moves to the front of the component mounter 20 that has received the instruction, and mounts the feeder 29 set by the user in the slot of the feeder table 24 by gripping the feeder 29 with the grip portion. Thereby, a new feeder 29 is supplied to the component mounting machine 20 . In addition, the loader 13 holds the feeder 29 that has run out of components with the gripping portions, pulls it out from the feeder table 24, and collects it. In this way, the loader 13 can automatically supply a new feeder 29 and recover a feeder 29 that has run out of parts.

Next, a multiplex communication system provided in the component mounting machine 20 will be described. FIG. 3 is a block diagram showing the configuration of a multiplex communication system applied to the component mounting machine 20. As shown in FIG. As shown in FIG. 2, the component mounting machine 20 includes an apparatus main body 41 and a fixing board 45 inside the module 22 . The device main body 41 and the fixed substrate 45 are provided inside the module 22 below the substrate transfer device 23 . As shown in FIG. 3, in the component mounting machine 20 of the present embodiment, a fixed part substrate 45 fixed inside the module 22 and a movable part (the X-axis slide mechanism 27A and the mounting head 25) that moves inside the module 22 are arranged. Data transmission between is performed by optical communication (multiplex communication) via optical fiber cables 81 and 82 .

The device main body 41 has a servo amplifier 83 , a device control main board 85 and an image processing board 87 . Further, the fixed part board 45 has an FPGA (Field Programmable Gate Array) 91, a JTAG connector 92, transmission-side photoelectric converters 93A and 94A, reception-side photoelectric converters 93B and 94B, and a multiplex JTAG connector 96. . The X-axis slide mechanism 27A also has an X-axis substrate 95, a mark camera 69, a linear motor 77, and a linear scale 78. As shown in FIG. The mounting head 25 also has a head substrate 97 , a parts camera 71 , a servo motor 75 and an encoder 76 .

In the component mounting machine 20 of the present embodiment, various data of devices possessed by the mounting head 25 and the X-axis slide mechanism 27A are transmitted and received by multiplex optical communication. The various data referred to here are, for example, linear scale signals of the linear scale 78 of the X-axis slide mechanism 27A and encoder signals of the encoder 76 of the mounting head 25 . Various data are image data of the mark camera 69 and the parts camera 71, for example. The various data are control data for the slave 61 of the X-axis slide mechanism 27A and the slave 62 of the mounting head 25. FIG. An example of data to be multiplexed will be described later with reference to FIGS. 4 and 5, but the data is not limited to this.

The FPGA 91 of the fixed part board 45 multiplexes the data input from the servo amplifier 83 of the device body part 41, the device control main board 85, and the image processing board 87. FIG. The FPGA 91 constructs a logic circuit that reads configuration information from a non-volatile memory (not shown) and performs multiplexing processing, for example, at startup. The FPGA 91 multiplexes input data by, for example, time division multiplexing (TDM). The FPGA 91, for example, multiplexes various data input from the servo amplifier 83 or the like according to a certain time (time slot) assigned to the input port, and transmits the multiplexed data to the transmission side photoelectric converters 93A and 94A. to the X-axis slide mechanism 27A and the mounting head 25 via.

The JTAG connector 92 is connected to the FPGA 91 . The JTAG connector 92 is, for example, a connector that performs communication conforming to the standard proposed by JTAG (Joint Test Action Group) defined by IEEE1149.1. The JTAG connector 92 has pins for inputting and outputting JTAG signals. A JTAG signal is a signal in a format conforming to JTAG. The JTAG connector 92 has pins for inputting and outputting JTAG signals such as TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data In), and TDO (Test Data Out), which will be described later. . In addition to the signals described above, the JTAG connector 92 has pins for ground and VCC.

The FPGA 91 is capable of inputting configuration information via the JTAG connector 92 and constructing a logic circuit based on the input configuration information. In addition, the fixed part board 45 can update the configuration information in the non-volatile memory based on the configuration information input via the JTAG connector 92, and can be read into the FPGA 91 at the next startup and started. . As a result, the fixed part board 45 can perform initial setting of configuration information based on information input via the JTAG connector 92, for example. For example, an operator at the manufacturer of the component mounting machine 20 connects the setting PC to the JTAG connector 92 . The operator operates the setting PC to output the configuration information to the FPGA 91 and the non-volatile memory of the fixed part board 45 via the JTAG connector 92 . This allows you to set factory configuration information.

Further, in the component mounting machine 20 of the present embodiment, in multiplex communication, a JTAG signal for executing a debugging function of the FPGA 103 of the X-axis slide mechanism 27A and the FPGA 113 of the mounting head 25, which will be described later, is transmitted. A multiplex JTAG connector 96 is a connector for inputting/outputting multiplexed JTAG signals. Details will be described later.

Also, the X-axis substrate 95 of the X-axis slide mechanism 27A has a transmission-side photoelectric converter 101A, a reception-side photoelectric converter 101B, an FPGA 103, and a JTAG connector 105. FIG. As shown in FIG. 3, the X-axis substrate 95 of the X-axis slide mechanism 27A and the head substrate 97 of the mounting head 25 have the same configuration as the fixing portion substrate 45. As shown in FIG. Therefore, in the description of the X-axis substrate 95 and the head substrate 97, the description of the same configuration as that of the fixed portion substrate 45 will be omitted as appropriate. The transmission-side photoelectric converter 93A and the reception-side photoelectric converter 93B of the fixed part substrate 45 are connected to the transmission-side photoelectric converter 101A and the reception-side photoelectric converter 101B of the X-axis slide mechanism 27A via an optical fiber cable 81. there is The FPGA 103 multiplexes image data from the mark camera 69, linear scale signals from the linear scale 78, control data from the slave 61, and the like. The X-axis board 95 is capable of inputting configuration information and the like through the JTAG connector 105 in the same manner as the fixed part board 45 described above.

Similarly, the head substrate 97 of the mounting head 25 has a transmission-side photoelectric converter 111A, a reception-side photoelectric converter 111B, an FPGA 113, and a JTAG connector 115. FIG. The transmitting side photoelectric converter 94A and the receiving side photoelectric converter 94B of the fixed part board 45 are connected to the transmitting side photoelectric converter 111A and the receiving side photoelectric converter 111B of the mounting head 25 via the optical fiber cable 82 . The FPGA 113 multiplexes image data from the parts camera 71 of the mounting head 25, encoder signals from the encoder 76, control data from the slave 62, and the like. Note that the circuits (FPGAs 91, 103, 113) that perform multiplexing processing are not limited to FPGAs, and may be programmable logic devices (PLDs) or composite programmable logic devices (CPLDs). Further, the multiplexing process may be realized by processing by an application specific integrated circuit (ASIC), software processing by a CPU, or the like.

The optical fiber cables 81 and 82 have enhanced flexibility by adjusting the arrangement and thickness of the optical fiber lines in the cables, for example. As a result, even when the optical fiber cables 81 and 82 are bent due to the movement of the mounting head 25 and the X-axis slide mechanism 27A, data can be transmitted stably without damaging the optical fiber lines. Note that the communication connecting the fixed part substrate 45, the mounting head 25, and the X-axis slide mechanism 27A is not limited to wired communication, and may be optical wireless communication using a laser or the like.

The transmission-side photoelectric converter 93A of the fixed part board 45 converts the multiplexed data multiplexed by the FPGA 91 into an optical signal, and transmits the optical signal to the reception-side photoelectric converter 101B of the X-axis board 95 via the optical fiber cable 81. . The reception-side photoelectric converter 101B converts the optical signal received from the transmission-side photoelectric converter 93A into a photocurrent of an electric signal, and outputs the electric signal to the FPGA 103 . The FPGA 103 of this embodiment has an AD conversion circuit and the like, and converts analog photocurrent into a digital signal for processing.

The FPGA 103 also performs demultiplexing of the converted digital signal, ie, multiplexed data, and separates the data multiplexed into the multiplexed data. The FPGA 103 outputs various separated data to corresponding devices. As a result, multiplex communication (optical communication) in which various data are multiplexed is performed between the fixed part substrate 45 and the X-axis slide mechanism 27A. Similarly, the FPGA 103 multiplexes the image data of the mark camera 69 and the like, and transmits the multiplexed data to the reception side photoelectric converter 93B of the fixed part substrate 45 via the transmission side photoelectric converter 101A. The FPGA 91 demultiplexes the multiplexed data and outputs the separated various data to the image processing board 87 of the apparatus main body 41 or the like.

Further, the fixed part substrate 45 performs multiplex optical communication with the mounting head 25 in the same manner as the X-axis slide mechanism 27A. The transmitting side photoelectric converter 94A and the receiving side photoelectric converter 94B of the fixed part board 45 are connected to the transmitting side photoelectric converter 111A and the receiving side photoelectric converter 111B of the head board 97 via the optical fiber cable 82 . The FPGA 91 of the fixed part board 45 performs multiplex communication with the FPGA 113 of the head board 97 via the optical fiber cable 82 . The multiplex communication lines of the optical fiber cables 81 and 82 are, for example, 5 Gbps full-duplex communication.

The device main body 41 of this embodiment controls the X-axis slide mechanism 27A and the mounting head 25 by the multiple optical communication described above. The servo amplifier 83 of the apparatus main body 41 executes initialization processing for the linear scale 78 of the X-axis slide mechanism 27A, linear scale signal acquisition processing, and the like. The linear scale 78 transmits a linear scale signal indicating the slide position of the X-axis slide mechanism 27A to the servo amplifier 83 via multiplex communication. The servo amplifier 83 is connected to the linear motor 77 of the X-axis slide mechanism 27A via a power line (not shown), and changes the power supplied to the linear motor 77 based on the linear scale signal of the linear scale 78. , the feedback control for the linear motor 77 is executed. The device control main board 85 controls the servo amplifier 83 based on the production program and the like received from the host computer 15 . As a result, the X-axis slide mechanism 27A moves to the X-direction position based on the production program.

Similarly, the servo amplifier 83 performs initialization processing for the encoder 76 of the mounting head 25, acquisition processing of encoder signals, and the like. The encoder 76 transmits an encoder signal indicating the rotational position of the servo motor 75 to the servo amplifier 83 via multiplex communication. The servomotor 75 functions as a drive source or the like for driving the holding member of the mounting head 25, as described above. The servo amplifier 83 is connected to the encoder 76 of the mounting head 25 via a power line (not shown), and performs feedback control of the servo motor 75 based on the encoder signal of the encoder 76 . Thereby, the mounting head 25 rotates and moves the holding member up and down based on the production program.

Further, the device control main board 85 of the device main body 41 can control the X-axis slide mechanism 27A and the relays, sensors, etc. provided in the mounting head 25 via the industrial network described above. The device control main board 85 functions as a master in the industrial network, and transmits control data to the slave 61 of the X-axis slide mechanism 27A and the slave 62 of the mounting head 25 via multiplex communication. The slaves 61 and 62 drive relays and sensors based on control data received from the device control main board 85 . Further, the slaves 61 and 62 write the values of signals obtained from relays and sensors in control data, and transmit the data to the device control main substrate 85 via multiplex communication. As a result, the device control main board 85 can control the relays and the like of each device.

Note that the configuration of the multiplex communication system shown in FIG. 3 is an example and can be changed as appropriate. For example, a linear scale signal attached to a linear motor (not shown) of the Y-axis slide mechanism 27B (see FIG. 2) may be transmitted by multiplex communication. Also, signals from the relays of the Y-axis slide mechanism 27B may be transmitted by multiplex communication. Also, the fixed part board 45 may include slaves controlled by the device control main board 85 . Also, the slave 61 may be a circuit block (IP core, etc.) of the FPGA 103 , that is, a part of the FPGA 103 . Further, the component mounting machine 20 does not have to be equipped with devices related to the industrial network (circuits functioning as masters of the device control main board 85, slaves 61 and 62, etc.).

With the configuration described above, the device control main board 85 controls the component mounting machine 20 based on the production program received from the host computer 15 . The device control main board 85 is, for example, a processing circuit mainly composed of a CPU, and executes processing based on a production program. The device control main board 85 receives the data collected by the industrial network, the linear scale signal of the linear scale 78, the encoder signal of the encoder 76, etc. via multiplex communication. Further, the device control main board 85 inputs the result (error of holding position, etc.) of processing the image data captured by the mark camera 69 or the parts camera 71 by the image processing board 87 . The device control main board 85 determines the next control contents (the type of electronic component to be mounted, the mounting position, etc.) based on these data. The device control main board 85 controls various devices according to the determined control contents.

(Structure of multiplexed data)
Next, the contents of the multiplexed data transmitted by the above multiplex communication will be described. FIG. 4 shows the contents of multiplexed data transmitted from the fixed part board 45 to the mounting head 25 in the multiplex communication of the optical fiber cable 82 . FIG. 5 shows the contents of multiplexed data transmitted from the mounting head 25 to the fixed part board 45 via the optical fiber cable 82 . Note that the data arrays and data contents in FIGS. 4 and 5 are examples. In addition, since the same configuration as the multiplexed data of the optical fiber cable 82 can be adopted for the multiplexed data transmitted by the optical fiber cable 81 connecting the fixed part substrate 45 and the X-axis slide mechanism 27A, the explanation thereof will be omitted. omitted.

Each of FIGS. 4 and 5 shows 32-bit multiplexed data (blocks A to D of 8 bits each). For example, the multiplexed data is 8B/10B converted every 8 bits (each block) to maintain the DC balance of the transmission data, resulting in a total of 40 bits. Therefore, one frame of the multiplexed data is composed of 40 bits, for example. For example, when the period per frame is set to 8 nsec (frequency is 125 MHz), FPGAs 91 and 113 construct multiple communication lines of 5 Gbps (40 bits×125 MHz).

4 and 5 show multiplexed data for each clock (for example, 8 nsec). 4 and 5 show data of 10 clocks 0-9. The head block A (BIT (bit) 0 to BIT7) of the multiplexed data transmitted from the fixed part board 45 shown in FIG. This command is, for example, a symbol for controlling K code (K code) in 8B/10B conversion. The same data as block A is set in block B of the multiplexed data shown in FIG. As a method of error correction for blocks A and B, for example, Reed-Solomon code can be used. Also, in blocks A and B, a 1-bit value indicating the presence or absence of data is set. This bit value indicating the presence or absence of data is effective for blocks A and B when the communication speed between devices for inputting and outputting data transmitted in blocks A and B is slow with respect to the communication speed (5 Gbps) of multiplex communication. This value indicates whether or not any data is set. As a result, the device on the receiving side that receives the data of blocks A and B can detect whether or not valid data is set based on the bit value indicating the presence or absence of this data, and process or discard the data. can be done quickly.

Pixel values (image data) of the parts camera 71 are set in blocks A and B of the multiplexed data transmitted from the mounting head 25 shown in FIG. As an error correction method, for example, a Reed-Solomon code can be used. When the mounting head 25 has a plurality of cameras, blocks A and B may be used separately for transmitting image data of the respective cameras.

A control signal for controlling the parts camera 71 and the like are set in block C (BIT1 to BIT5) of the multiplexed data shown in FIG. The control signals referred to here are, for example, the control signals CC1 to CC4 in the case of the camera link standard. Alternatively, the control signal is a trigger signal (CAM-TRG in the drawing) that instructs the parts camera 71 to pick up an image. Also, in BIT0 of block C, a bit value indicating presence/absence of block C data is set.

In BIT 6 of block C, there is a parity bit (K code flag in the figure) for detecting whether or not a burst error or the like exceeding the correction capability has occurred in encoding by Reed-Solomon code for block B. is set. Specifically, for example, in the setting of encoding by Reed-Solomon code, the setting is such that consecutive errors in two blocks can be corrected. In this case, if three or more blocks of consecutive errors occur in multiplex communication, the receiving side (mounting head 25) cannot correct the data. Therefore, for example, an even parity corresponding to 8 bits of block B is set in BIT 6 of block C, and when a continuous error of 3 blocks or more is detected on the receiving side, abnormal stop or image data correction ( 5 is on the receiving side), etc. are executed. A parity bit corresponding to block A is set in BIT7 of block C, similarly to BIT6. Also, in block C of the multiplexed data shown in FIG. 5, parity bits (K code flags in the figure) are set in BITs 6 and 7, as in FIG. Note that blank portions shown in FIG. 5 indicate empty bits in which no data is set.

BIT0 to BIT3 of block D in FIGS. 4 and 5 are set with encoder signals of the encoder 76 of the mounting head 25. FIG. In the case of FIG. 4, the term "encoder signal" means a signal for initial setting transmitted from the servo amplifier 83 to the encoder 76, a signal for inquiring about the state, a signal for acquiring position information, and the like. Further, in the case of FIG. 5, the encoder signal is a signal indicating position information and the like transmitted from the encoder 76 to the servo amplifier 83 . For example, the mounting head 25 comprises four sets of servo motors 75 and encoders 76 . In this case, the mounting head 25 can move the holding member in the movement directions of the four axes. 4 and 5, four bits 0 to 3 are set corresponding to each of such four-axis encoders 76. FIG. Further, as a method of error correction for the data of BIT0 to BIT6 of block D, for example, Hamming code can be used.

In BIT0 of block D, encoder signal data (E1 in FIGS. 4 and 5) is set in the first four clocks (clocks 0 to 4 in FIGS. 4 and 5) out of 10 clocks. Each bit position in clocks 0 and 2 is assigned a bit of the encoder signal. Information indicating the presence/absence of encoder signal data (“E1 presence/absence” in FIGS. 4 and 5) is assigned to each bit position in clocks 1 and 3. FIG. For example, when the data transfer rate of the encoder signal is lower than the data transfer rate of the multiplexed data, the information indicating the presence/absence of this data is stored at each bit position (BIT0). This is information for indicating whether or not clocks 0, 1) are set. The encoder signal and the information indicating the presence/absence of the encoder signal are set alternately for each cycle.

Timeout information indicating whether or not a timeout error has occurred in communication between the servo amplifier 83 and the encoder 76 is set in clock 4 of BIT0. In addition, a bit value for a cyclic redundancy check (CRC) is set in clock 5 of BIT0 by the transmitting side (“CRC abnormality” in FIGS. 4 and 5). Clocks 6 to 9 of BIT0 are set with 4-bit code bits, which are Hamming codes of forward error correction codes. Error correction codes are, for example, shorthand for Hamming codes (15,11). In clocks 6 to 9 of BIT1 to 6, 4 sign bits are set as in BIT0. When receiving the multiplexed data, the FPGAs 91 and 103 execute error detection and correction on data such as demultiplexed encoder signals based on the error correction code. BIT1 to BIT3 are set with data related to the encoder signal in the same manner as BIT0.

A control signal for the parts camera 71 is set in BIT4 of block D shown in FIGS. The control signal referred to here is, for example, a control signal of UART communication for controlling lighting of the parts camera 71 when the parts camera 71 is a Camera Link standard camera. Information related to the data values of clocks 0 to 3 is set in clocks 4 and 5 of BIT4.

BITs 5 and 6 of block D shown in FIGS. 4 and 5 are set with data related to an industrial network, for example, MECHATROLINK (registered trademark)-III (“MIII” in FIGS. 4 and 5). Such). This data is control data for the slave 62 . Control data of MECHATROLINK (registered trademark)-III is set in 4 bits of clocks 0 to 3 of BIT5 and BIT6. Information indicating the presence or absence of data is set in clock 4 of BITs 5 and 6 . In clock 5 of BITs 5 and 6, a bit value for a cyclic redundancy check (CRC) is set by the transmitting side.

BIT 7 of block D shown in FIGS. 4 and 5 is set with JTAG signal data for executing the debugging function of the FPGA 113 of the mounting head 25 . No error correction method is set for JTAG signal data. Note that an error correction code may be added to the data of the JATG signal as well as other data.

TCK (Test Clock) of BIT7 is a clock signal (Test Clock) in the JTAG standard, and is used, for example, as a system clock of a serial data bus connecting JTAG connectors. The FPGA 113 of this embodiment includes a TAP controller 121 (an example of a logic analyzer section) and a multiplexing section 123, as shown in FIG. The FPGA 91 of the fixed part substrate 45 and the FPGA 103 of the X-axis slide mechanism 27A are provided with a TAP controller and a multiplexing part, like the FPGA 113 . Since the drawing is complicated, illustration of the TAP controllers of the FPGAs 91 and 103 is omitted.

The TAP controller 121 is manufactured by Altera (registered trademark) Inc., for example. signal TAP (registered trademark) and Xilinx (registered trademark) Inc. It is a logic circuit used in a logic analyzer such as the ChipScope of the company. The TAP controller 121 is constructed as a logic circuit of the FPGA113. The TAP controller 121 is, for example, a 16-state state machine. Here, the 16 states are, for example, a Test-Logic-Rest state for resetting the test logic and a Run-Test/Idle state for maintaining an idle state. The TAP controller 121, for example, captures other signals (TMS, TDI, TDO) other than TCK at the rising edge of TCK. The TAP controller 121 acquires a signal to be observed set by logic analyzer software, which will be described later. The TAP controller 121 also outputs the captured signal to the multiplexer 123 as a JTAG signal (BIT 7 in block D in FIG. 5) based on trigger conditions and the like.

The multiplexer 123 is constructed as a logic circuit of the FPGA 113 . The multiplexing unit 123 performs the multiplexing processing in the FPGA 113 described above, that is, the non-multiplexing of the multiplexed data shown in FIG. 4 and the multiplexing processing of the multiplexed data shown in FIG.

TMS (Test Mode Select) of BIT 7 in block D of FIG. 4 is data for controlling the state transition of the TAP controller 121 . The TAP controller 121 transitions between each of 16 states according to, for example, a TMS signal received from the logic analyzer software of the later-described FPGA development PC 127 (see FIG. 3). This allows the FPGA development PC 127 to control the TAP controller 121 . TDI (Test Data In) of BIT 7 in FIG. 4 is input data to the TAP controller 121 such as instruction data, test data, and circuit data. The TAP controller 121 inputs the TDI signal to its own registers and the like. TDO (Test Data Out) of BIT7 in FIG. 5 is output data from the TAP controller 121 such as instruction data, test data, and circuit data. As shown in FIGS. 4 and 5, TCK, TMS, and TDO (TDI) are transmitted in sequence every clock (every 8 nsec). The configuration of the multiplexed data shown in FIGS. 4 and 5 is an example, and may be changed as appropriate according to the required communication speed, the type and number of devices attached to the component mounting machine 20, and the like. For example, a reset signal (TRST) may be multiplexed and transmitted/received as a JTAG signal.

As shown in FIG. 3, the fixed part board 45 of this embodiment has a multiplex JTAG connector 96 . Three multiple JTAG connectors 96 are provided corresponding to the TAP controllers 121 of the FPGAs 91 , 103 , and 113 . For example, each of the three multiplexed JTAG connectors 96 are connected to FPGA development PC 127 via JTAG equipment 125 as shown in FIG. The JTAG equipment 125 is connected to an FPGA development PC 127 via a cable 126 . The cable 126 is, for example, a USB cable that performs communication conforming to the USB standard. In this case, the JTAG device 125 is a converter that converts a serial cable connected to the multiplex JTAG connector 96 into a USB standard cable.

The FPGA development PC 127 is a personal computer mainly including a CPU. The FPGA development PC 127 is connected to the component mounting machine 20 when setting, changing, or adding circuits of the TAP controller 121 . The FPGA development PC 127 sets the TAP controllers 121 of the FPGAs 91, 103, and 113 and controls the TAP controllers 121 by executing the logic analyzer software stored in the hard disk. The logic analyzer software referred to here is, for example, Altera (registered trademark) Inc. software. Signal TAP® from Xilinx® Inc. This software provides a user interface for setting logic analyzer functions such as ChipScope. Therefore, in the component mounting machine 20 of this embodiment, the logic analyzer software of the FPGA development PC 127 connected to the fixed board 45 can set the TAP controller of the FPGA 91 of the fixed board 45 . Also, the logic analyzer software of the FPGA development PC 127 can set the TAP controller 121 of the FPGAs 91 and 113 of the moving parts (the X-axis slide mechanism 27A and the mounting head 25) via the multiplex communication system of the component mounter 20. It is possible.

(About logic analyzer software)
Next, control of the TAP controller 121 by logic analyzer software of the PC 127 for FPGA development will be described. FIG. 6 is a flow chart showing a processing procedure for controlling the TAP controller 121. As shown in FIG. In the following description, the TAP controller 121 of the FPGA 113 of the mounting head 25 will be described as an example. It should be noted that the FPGA 103 can also be set to a TAP controller (not shown) in the same manner as the FPGA 113 .

First, in step 11 (hereinafter simply referred to as S) in FIG. 6, the user operates the FPGA development PC 127 to activate the logic analyzer software. The user creates a design file (Signal TAP file for Signal TAP (registered trademark)) for mounting the TAP controller 121 on the FPGA 113 .

In S13, the user operates the logic analyzer software to set the clock signal and the signal to be observed. The TAP controller 121 samples the signal to be observed, for example, in synchronization with the rising edge of the clock signal set in S13. Therefore, the clock signal is, for example, a signal for setting a trigger condition for starting observation of the processed signal. The logic analyzer software can acquire information on various processed signals processed by the FPGA 113 based on the configuration information of the FPGA 113, for example. Alternatively, the logic analyzer software may communicate with the FPGA 113 and acquire information on the signal processed by the FPGA 113 .

The logic analyzer software displays the acquired processed signal information on the monitor of the FPGA development PC 127 . The user confirms the display on the monitor and selects the clock signal or the signal to be observed from among the signals processed by the FPGA 113 . For example, a processed signal processed by the multiplexer 123 can be used as the signal to be observed. Signals processed by the multiplexing unit 123 include image data, industrial network control data, encoder signals, signals indicating the establishment of multiplex communication links in the optical fiber cable 82, signals indicating abnormalities such as link disconnection, and the like. can be adopted. Note that other signals processed by the FPGA 113 (such as signals from various sensors) can also be used as signals to be observed.

When the signal processed by the multiplexing unit 123 is selected as the signal to be observed, as will be described later, the TAP controller 121 sends the signal processed by the multiplexing unit 123 to the multiplexing unit 123 in the form of a JTAG signal (such as a TDO signal). Output to The multiplexing unit 123 multiplexes the JTAG signal input from the TAP controller 121 into multiplexed data and transmits the multiplexed data. Therefore, the TAP controller 121 of this embodiment outputs the processed signal processed by the multiplexer 123 as a JTAG signal. As a result, a signal indicating the establishment of a multiplex communication link can be transmitted by multiplex communication, and the content of the signal can be confirmed on the fixed part substrate 45 side.

Further, for example, as a logic circuit of the FPGA 113 , a logic circuit that changes a specific signal level when a data error or the like occurs in the encoder signal may be constructed in the TAP controller 121 . Then, this specific signal may be set as the signal to be observed. This makes it possible to observe an abnormality in the encoder signal.

Next, the user operates the logic analyzer software to compile the design file and generate a compiled file (SOF file for Signal TAP (registered trademark)) (S15). Next, the compiled file is downloaded from the FPGA development PC 127 to the FPGA 113 (S17). For example, the user operates the logic analyzer software to select the cable 126 corresponding to the FPGA 113 among the cables 126 connected to each of the three multiplex JTAG connectors 96 . This allows you to choose where to download the compiled files.

When the download is executed by the user, the compiled file is input from the FPGA development PC 127 to the multiplexer (not shown) of the FPGA 91 via the multiplex JTAG connector 96 . The multiplexing unit of the FPGA 91 multiplexes the data of the file after compilation to BIT7 of block D of multiplexed data shown in FIG. 4, for example. In this case, BIT7 of block D of the multiplexed data is used for transmission of the compiled file in initial processing, and is used for transmission of JTAG signals when observation is started. It should be noted that transmission of the file after compilation may be executed using bits other than BIT7 of block D of the multiplexed data.

The FPGA 113 changes the circuit configuration of the TAP controller 121 by, for example, receiving the compiled file and changing part of the logic circuit. As a result, the signal to be observed by the TAP controller 121 can be changed, and the contents of the JTAG signal output from the TAP controller 121, the trigger condition for starting acquisition, and the like can be changed. The TAP controller 121 starts up with the changed circuit configuration and starts observing the processed signal (S19). Also, the user starts the mounting work of the component mounting machine 20 and executes test operations and the like.

As a result, analysis via multiplex communication is started (S21). Specifically, for example, the logic analyzer software of the FPGA development PC 127 appropriately changes the state of the TAP controller 121 using the TMS signal. Also, the logic analyzer software uses the TDI signal to execute commands and the like for the TAP controller 121 . The TAP controller 121 samples a signal to be observed set by the user and outputs it to the multiplexer 123 as a JTAG signal (such as a TDO signal). The multiplexing unit 123 transmits the JTAG signal input from the TAP controller 121 to the FPGA 91 of the fixed unit substrate 45 via multiplex communication. The multiplexing unit of the FPGA 91 separates BIT 7 of block D shown in FIG. The logic analyzer software retransmits JTAG signals of responses and commands to the FPGA 113 . A JTAG signal transmitted between the logic analyzer software of the FPGA development PC 127 and the FPGA 113 is transmitted at BIT 7 of block D shown in FIGS.

If the JTAG connector 115 of the mounting head 25 is used to analyze the processed signal of the FPGA 113, the mounting head 25 may need to be disassembled. Moreover, there is a possibility that the cable connected to the movable mounting head 25 may come off or break. On the other hand, in this embodiment, by operating the PC 127 for FPGA development, various controls can be performed on the TAP controller 121 of the FPGA 113 connected by multiplex communication. This eliminates the need to disassemble the mounting head 25 in order to analyze the processed signal of the FPGA 113 .

FIG. 7 shows an example of an observation screen displayed on the FPGA development PC 127 by the logic analyzer software. As shown in FIG. 7, the observation screen displays a waveform display section 131 that displays the waveform of the signal to be observed set in S13 of FIG. The waveform display section 131 displays the waveform of each signal to be observed. The user can confirm the state of the processed signal of the FPGA 113 by confirming this waveform. For example, when an error occurs in the mounting work of the component mounting machine 20, the cause of the error can be analyzed from the state of the processing signal at the time of occurrence.

The waveform display unit 131 displays the waveform of the signal, for example, with the horizontal axis representing time. The time zero (0) indicates, for example, the time when sampling of the processed signal is started, that is, the rising timing of the clock signal set in S13 (the time when the trigger condition is satisfied).

Various setting buttons 133 are displayed above the waveform display section 131 . For example, when the save button of the setting button 133 is pressed, the FPGA development PC 127 performs a process of saving the data of the observation target signal displayed on the waveform display section 131 . Also, in response to pressing the execution button, the FPGA development PC 127 starts outputting (sampling) signals to the TAP controller 121 . Also, in response to pressing the stop button, the FPGA development PC 127 causes the TAP controller 121 to stop outputting signals. The setting button is a button for displaying a screen for changing various conditions such as changing the signal to be observed.

A USB cable selection display screen 135 displaying the cable 126 being selected is displayed on the right side of the waveform display section 131 . By operating the pull-down menu of the USB cable selection display screen 135, the user can select the cable 126, that is, select the target FPGAs 91, 103, 113 (TAP controller 121). For example, the USB cable numbers 1, 2, and 3 in the pull-down menu correspond to the order of the FPGAs 91, 103, and 113. By performing observation using such an observation screen, it becomes possible to observe the processed signals of the FPGAs 91, 103, and 113 via multiplex communication.

Here, the FPGA 113 of the present embodiment is provided on the mounting head 25 that is movable with respect to the fixed part substrate 45 . As described above, the FPGA 113 of the mounting head 25 transmits JTAG signals to the fixed part board 45 by multiplex communication. This eliminates the need to directly acquire the processing signal from the mounting head 25 by connecting an investigation cable or the like to the mounting head 25 . As a result, when trying to confirm the processing contents of a device such as the mounting head 25 that performs multiplex communication, the confirmation work is facilitated.

Also, the TAP controller 121 is a logic circuit configured by an FPGA. According to this, after confirming the processing signal on the fixed part substrate 45 side, it is possible to change the logic circuit of the TAP controller 121, change the processing signal to be acquired, etc. as necessary.

Also, the FPGA 113 is provided in a mounting head 25 that mounts electronic components on the substrate 17 . In the component mounting machine 20 that mounts the electronic component on the substrate 17 by the mounting head 25, the mounting head 25 is moved at high speed during the work. For this reason, if the mounting work is performed while the cable for investigation is connected to the mounting head 25, the cable may come off or break, making debugging more difficult. Therefore, in the component mounting machine 20 having the mounting head 25, it is extremely effective to transmit processing signals from the mounting head 25 in the form of JTAG signals through multiplex communication.

Incidentally, the component mounting machine 20 is an example of a work machine. FPGA 113 of mounting head 25 is an example of a multiplex communication device. The fixed part board 45 is an example of a communication part. The TAP controller 121 is an example of a logic analyzer section. The FPGA development PC 127 is an example of a display device.

As described above, the present embodiment described above has the following effects.
In one aspect of the present embodiment, the FPGA 113 transmits multiplexed data obtained by multiplexing a plurality of signals including the JTAG signal to the TAP controller 121 that outputs the processing signal processed by the FPGA 113 as a JTAG signal to the fixed part board 45. and a multiplexing unit 123 for processing.

According to this, the JTAG signal output from the TAP controller 121 can be multiplexed and transmitted to the fixed part substrate 45 . By separating the JTAG signal from the multiplexed data on the fixed part board 45 side, it is possible to confirm the processing signal processed by the FPGA 113 (on the mounting head 25 side). This eliminates the need to connect a cable for investigation to the mounting head 25 and disassemble the mounting head 25 because the processed signal can be obtained by multiplex communication. In addition, since the cable for investigation is not connected, there is no possibility that the cable for investigation will fall off or break due to the movement of the mounting head 25 . Therefore, it is possible to easily confirm the processing contents of the mounting head 25 . Further, since the necessary processing signals can be transmitted to the fixed part substrate 45 by multiplex communication, it is not necessary to provide a large-capacity storage unit for storing the processing signals in the head substrate 97 or the like.

It goes without saying that the present disclosure is not limited to the above embodiments, and that various improvements and modifications are possible without departing from the scope of the present disclosure.
For example, a multiplex communication device that transmits JTAG signals by multiplex communication is not limited to a movable device, and may be a fixed device.
Also, the TAP controller 121 does not have to output the processed signal (such as the signal indicating the establishment of the link) processed by the multiplexer 123 as the JTAG signal.
Also, the TAP controller 121 and the multiplexer 123 may not be programmable logic devices such as FPGAs. For example, the processing by the TAP controller 121 and the multiplexing unit 123 may be realized by hardware processing such as ASCII, or may be realized by software processing such as executing a program on the CPU.

Further, in the above-described embodiment, the component mounting machine 20 that mounts electronic components on the substrate 17 is used as the working machine of the present disclosure, but the present invention is not limited to this. For example, as the work machine, various work machines such as a solder application device that applies solder to the substrate 17, a machine tool, and a care robot can be employed.
Further, the component mounting machine 20 may be configured without the FPGA development PC 127 .

17 substrate, 25 mounting head, 20 component mounting machine (working machine), 45 fixed part substrate (communication part), 113 FPGA (multiplex communication device), 121 TAP controller (logic analyzer part), 123 multiplexing part, 127 FPGA development PC (display device).

Claims (3)

a fixed part substrate ;
a multiplex communication device capable of performing wired multiplex communication with the fixed part substrate ;
a working unit provided with the multiplex communication device;
an apparatus main body section for controlling the operation of the working section;
A working machine comprising
The multiplex communication device
a logic analyzer unit that outputs a processed signal processed by the multiplex communication device as a JTAG signal;
a multiplexing unit that transmits multiplexed data obtained by multiplexing a plurality of signals including the JTAG signal to the fixed unit substrate ;
with
The device main body is
controlling the operation of the working unit by means of control information transmitted via the wired multiplex communication;
The fixed part substrate is
a connection unit that can be connected to an information processing device that processes the JTAG signal, and transmits the multiplexed data obtained by multiplexing the control information and the JTAG signal to and from the multiplex communication device; separating the control information from the multiplexed data received from the multiplex communication device and outputting it to the device main unit, separating the JTAG signal from the multiplexed data and outputting it to the information processing device;
The working unit
A mounting head for mounting electronic components on a substrate,
The device main body is
controlling the mounting head by the control information via the fixed part substrate;
The logic analyzer section
outputting the processed signal processed by the multiplex communication device as the JTAG signal in response to the control of the mounting head by the control information, and providing the control information from the device main body to the mounting head; outputting the JTAG signal regardless of the control instruction based on;
The logic analyzer section
It consists of programmable logic devices that build logic circuits based on configuration information,
The information processing device is
A compilation file can be created by logic analyzer software,
The logic analyzer section
changing a logic circuit based on the compile file received from the information processing device via the fixed part board;
The multiplexed data includes
A work machine , wherein a data area used by the apparatus body for transmitting the control information and a data area used by the information processing apparatus for transmitting the compile file are set separately . The logic analyzer section
2. The working machine according to claim 1, wherein a signal to be observed to be transmitted to said information processing device among said processed signals is changed based on said compile file. The information processing device is
3. The working machine according to claim 1 , wherein the waveform of said processed signal is displayed based on said JTAG signal received by said multiplexed data.

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