JP7097840B2 - Protection control device - Google Patents

Description

The present disclosure relates to a protective control device.

There is known a protection control device that collects electric energy such as current and voltage from an electric power system at a plurality of places and controls and protects electric power equipment by using the electric energy. Conventionally, a parallel bus such as PCI (Peripheral Component Interconnect) has been used as a bus for transmitting the amount of electricity sampled by each node provided in the protection control device to the CPU (Central Processing Unit).

However, the parallel bus has a limit in increasing the data transmission speed, and the number of signal wirings is large, which is not suitable for miniaturization of the device. Therefore, the parallel bus is a high-speed serial that can achieve both high transmission speed and low wiring. The transition to buses is in progress. In this case, in order to synchronize the sampling timing of the electric energy in each node provided in the protection control device, a timing signal for notifying the sampling timing is transmitted to each node via the serial bus.

For example, Japanese Patent Application Laid-Open No. 2013-143748 (Patent Document 1) discloses a time synchronization system. In this system, by assigning different IP addresses to the main processing unit and the time synchronization processing unit provided in the master, the variation in network delay is reduced, and the time synchronization packet is not affected by the variation in network delay. I am considering communicating.

Japanese Unexamined Patent Publication No. 2013-143748

In the serial bus, data is transmitted by packet communication, so the timing signal is embedded in the communication packet and transmitted. In a configuration in which a master including a CPU and a plurality of slaves for sampling electric energy are connected by a serial bus, if the number of slaves is large, the distortion of the signal waveform becomes large and correct data cannot be communicated. Therefore, it is conceivable to provide a repeater that electrically separates the serial bus to reduce the number of slaves on the same bus. However, in this case, since the processing delay when the communication packet passes through the repeater is added, the arrival time difference of the timing signal in each slave becomes large, and the synchronization accuracy of the desired sampling timing cannot be obtained.

An object of an aspect of the present disclosure is to improve the synchronization accuracy of the sampling timing of electric energy in each slave in a protection control device including a master and a plurality of slaves.

A protection control device according to an embodiment is a protection control device for a communication packet between a master, a first plurality of slaves connected to the master via the first serial bus, and the first serial bus and the second serial bus. A bus repeater that performs transfer and a second plurality of slaves connected to the bus repeater via a second serial bus are provided. The bus repeater synchronizes the communication packet with the sampling timing of the electric quantity in each of the first and second plurality of slaves based on the information contained in the communication packet received via the first serial bus. The first determination circuit that determines whether or not the packet is a packet, and when the communication packet is a synchronization packet, the synchronization packet stored in advance in the internal memory is sent to the second plurality of slaves via the second serial bus. Includes a transmit circuit to transmit.

According to the present disclosure, in a protection control device including a master board and a plurality of slave boards, it is possible to improve the synchronization accuracy of the sampling timing of the electric energy in each slave board.

It is a figure which shows an example of the whole structure of the protection control device according to Embodiment 1. FIG. It is a figure which shows an example of the hardware composition of the protection control device which follows Embodiment 1. FIG. It is a figure which shows an example of the structure of the bus repeater according to Embodiment 1. FIG. It is a figure which shows typically the structure of the synchronization packet and the data packet according to Embodiment 1. FIG. It is a figure for demonstrating the advantage of Embodiment 1. FIG. It is a figure which shows an example of the structure of the bus repeater according to Embodiment 2. FIG. It is a figure which shows typically the structure of the synchronization packet and the data packet according to Embodiment 2. FIG. It is a figure which shows an example of the configuration of the slave according to Embodiment 3. It is a figure for demonstrating the advantage of Embodiment 3. FIG. It is a figure which shows an example of the whole structure of the protection control device according to other embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are designated by the same reference numerals. Their names and functions are the same. Therefore, the detailed description of them will not be repeated.

Embodiment 1.
<Overall configuration>
FIG. 1 is a diagram showing an example of the overall configuration of the protection control device 100 according to the first embodiment. With reference to FIG. 1, the protection control device 100 includes a master 10, a plurality of slaves 11, serial buses 13A and 13B, and a bus repeater 15. Typically, the master 10 and the plurality of slaves 11 are each composed of different boards.

In the present embodiment, the protection control device 100 includes n slaves (for example, n = 20), and the n slaves 11 are assigned numbers # 1 to # n for convenience. To distinguish. The n slaves 11 are also referred to as slaves # 1 to # n, respectively. The slaves # 1 to # m are connected to the master 10 and the bus repeater 15 via the serial bus 13A. Further, the slaves # m + 1 to # n are connected to the bus repeater 15 via the serial bus 13B.

The serial buses 13A and 13B (hereinafter, also collectively referred to as "serial bus 13") are multipoint type high-speed serial buses, and are composed of, for example, an M-LVDS (Multipoint Low Voltage Differential Signaling) bus. The master 10 sends and receives communication packets to and from each slave 11 via the serial bus 13 and the bus repeater 15.

FIG. 2 is a diagram showing an example of the hardware configuration of the protection control device 100 according to the first embodiment. The slaves 11a and 11b in FIG. 2 correspond to the slaves # 1 and # 2 in FIG. 1, respectively, and the slave 11c in FIG. 2 corresponds to the slave # m + 1 in FIG.

With reference to FIG. 2, the master 10 is connected to the slaves 11a and 11b via the serial bus 13A. Further, the master 10 is connected to the slave 11c via the serial bus 13A, the bus repeater 15 and the serial bus 13B.

The master 10 transmits a communication packet in which various command information is embedded to each slave 11. For example, the master 10 transmits a synchronization packet for synchronizing the sampling timing of the electric energy in each slave 11. Further, the master 10 transmits a data packet including command information for transmitting the amount of electricity sampled by each slave 11 to the master 10. The master 10 receives the amount of electricity transmitted from each slave 11 according to the command information.

The master 10 includes a CPU 22, a bus interface (I / F) 21, a RAM (Random Access Memory) 23, and a ROM (Read Only Memory) 24 as main hardware configurations.

The CPU 22 controls the operation of the protection control device 100 by reading and executing a program stored in advance in the ROM 24. The ROM 24 stores various information used by the CPU 22. The CPU 22 is, for example, a microprocessor. The hardware may be an FPGA (Field Programmable Gate Array) other than the CPU, an ASIC (Application Specific Integrated Circuit), or a circuit having other arithmetic functions.

The CPU 22 takes in digital data from each slave 11 via the serial bus 13. The CPU 22 executes a control operation using the captured digital data according to the program stored in the ROM 24.

For example, when the CPU 22 detects an accident of a monitoring target (for example, a transmission line) based on the control calculation result (for example, when the calculated value exceeds the set value), the DO provided in the slave 11 is provided. (Digital output) A control signal is output via a circuit. Further, the CPU 22 receives various signals from an external device via a DI (digital input) circuit provided in the slave 11.

The bus interface 21 is connected to the serial bus 13A, and is, for example, an interface corresponding to the M-LVDS standard. The CPU 22 communicates with each slave 11 via the bus interface 21. Typically, the bus interface 21 is composed of a circuit such as FPGA.

The slaves 11a to 11c are also referred to as a bus interface 31a to 31c (hereinafter, also collectively referred to as "bus interface 31") and an AD (analog-to-digital) conversion circuit 32a to 32c (hereinafter, "AD conversion circuit 32", respectively). Collectively) and. The slave 11a further includes a DI circuit 33a and a DO circuit 34a. The bus interface 31 is, for example, an interface corresponding to the M-LVDS standard.

The bus interfaces 31a and 31b are connected to the serial bus 13A, and the bus interface 31c is connected to the serial bus 13B. The bus interface 31a is connected to the AD conversion circuit 32a, the DI circuit 33a and the DO circuit 34a, the bus interface 31b is connected to the AD conversion circuit 32b, and the bus interface 31c is connected to the AD conversion circuit 32c.

The bus interface 31 receives the communication packet transmitted from the master 10, and if it is the reception target, transmits the control signal to the corresponding circuit. Here, when the received communication packet is a broadcast notification packet or a packet whose destination address matches its own address, the bus interface 31 determines that it is the reception target. For example, when the bus interface 31 receives the synchronization packet sent to the slave 11 by the broadcast notification in order to synchronize the sampling timing of the electric energy, the bus interface 31 outputs the sampling timing signal to the AD conversion circuit 32.

The AD conversion circuit 32 is connected to an auxiliary transformer (not shown). The auxiliary transformer takes in the input current from the current transformer or the input voltage from the voltage transformer, converts it into a voltage signal suitable for signal processing in the internal circuit of the protection control device 100, and outputs it. The AD conversion circuit 32 takes in an analog signal (that is, a voltage signal) output from the auxiliary transformer and converts it into a digital signal. Specifically, the AD conversion circuit 32 includes an analog filter, a sample hold circuit, a multiplexer, and a signal converter.

The analog filter removes high frequency noise components from the voltage signal output from the auxiliary transformer. The sample hold circuit samples the signal output from the analog filter at a predetermined sampling period. Based on the timing signal input from the CPU 22, the multiplexer sequentially switches the waveform signal input from the sample hold circuit in chronological order and inputs it to the signal converter. The signal converter converts the waveform signal input from the multiplexer from analog data to digital data. The AD conversion circuit 32 outputs the digitally converted signal (that is, digital data) to the master 10 via the bus interface 31.

The DI circuit 33a captures, for example, a status signal of a system device provided in the power system. The DO circuit 34a outputs a control signal to the system equipment.

The bus repeater 15 transfers a communication packet between the serial bus 13A and the serial bus 13B. Typically, the bus repeater 15 shapes the electric signal corresponding to the communication packet input from one serial bus 13 and outputs it to the other serial bus 13.

<Composition of bus repeater>
In the protection control device 100, the master 10 and the plurality of slaves 11 are connected by a serial bus 13, and a bus repeater 15 is provided so that data can be correctly communicated even if the number of slaves is large.

The master 10 transmits a synchronization packet for synchronizing the sampling timing of the electric energy in each slave 11 to each slave 11 via the serial bus 13 and the bus repeater 15. The bus repeater 15 has the following configuration in order to minimize the synchronization deviation of the sampling timing due to the processing delay of the bus repeater 15.

FIG. 3 is a diagram showing an example of the configuration of the bus repeater 15 according to the first embodiment. With reference to FIG. 3, the bus repeater 15 has a receiving circuit 110 and an error detecting circuit 120 as a configuration for transmitting a communication packet from the upstream side (that is, the serial bus 13A) to the downstream side (that is, the serial bus 13B side). The buffer memory circuit 130, the synchronous packet output circuit 140, and the transmission circuit 150 are included.

The receiving circuit 110 receives the communication packet from the master 10 via the serial bus 13A. Specifically, the receiving circuit 110 includes a serial-parallel conversion circuit 111 and a decoder circuit 113.

The serial-parallel conversion circuit 111 converts the communication packet received from the serial bus 13A from serial data to parallel data and outputs the communication packet to the decoder circuit 113.

The decoder circuit 113 is a circuit that decodes the input signal, and has a decoder corresponding to the coding method. In this embodiment, the decoder circuit 113 is composed of an 8B / 10B decoder. The decoder circuit 113 converts the communication packet from 10-bit data to 8-bit data and outputs the communication packet to the error detection circuit 120. The coding method is not limited to the 8B / 10B coding method, and may be a 4B / 5B coding method.

The communication packet received in the receiving circuit 110 is typically a synchronization packet or a data packet.

FIG. 4 is a diagram schematically showing the configuration of a synchronization packet and a data packet according to the first embodiment. Specifically, FIG. 4A shows an example of a synchronous packet configuration, and FIG. 4B shows an example of a data packet configuration.

With reference to FIG. 4A, the synchronization packet includes a head flag area 51, a synchronization flag area 52, and an FCS (Frame Check Sequence) area 53 in which error detection information is stored. Further, the synchronous packet is a packet that is broadcast to all slaves and does not have an address that specifies a communication partner. With reference to FIG. 4B, the data packet includes a head flag area 61, a header area 62, a payload area 63 in which the data body is stored, and an FCS area 64. Information such as a communication command, an address for designating a communication partner, a sequence number, and a data length is stored in the header area 62.

As shown in FIG. 4A, the synchronization packet does not have a header area and a payload area. In the synchronization flag area 52, a control code Sx indicating that the communication packet received from the master 10 is a synchronization packet is stored. This control code Sx is, for example, a K code such as K28.5 indicating a comma code.

As described above, the synchronization packet does not have a variable element, and is composed only of the flag stored in the head flag area 51 and the synchronization flag area 52 and the error detection information stored in the FCS. Therefore, the packet length of the synchronization packet is shorter than the packet length of the data packet. On the other hand, since various command information which is a variable element is stored in the payload area in the data packet, the packet length is relatively long.

Again, referring to FIG. 3, when the control code Sx is detected in the communication packet, the decoder circuit 113 outputs a detection result (for example, a detection flag signal) indicating that the control code Sx is detected in the synchronous packet output circuit. Output to 140. Further, the detection flag signal of the control code Sx is output to the error detection circuit 120.

The error detection circuit 120 detects an error based on the FCS included in the communication packet, and outputs the error detection result to the synchronous packet output circuit 140.

The synchronous packet output circuit 140 functions as a bypass circuit for synchronous packets. Specifically, when the synchronous packet output circuit 140 receives the input of the detection flag signal of the control code Sx from the decoder circuit 113 (that is, when the communication packet includes the control code Sx), the synchronous packet output circuit 140 is received by the reception circuit 110. It is determined that the communication packet is a synchronization packet. Then, when the error is not detected in the error detection circuit 120 (that is, when the error detection result is "no error"), the synchronization packet output circuit 140 determines that there is no error in this synchronization packet. In this case, the synchronization packet output circuit 140 outputs the synchronization packet (that is, the synchronization packet shown in FIG. 4A) stored in advance in the internal memory to the transmission circuit 150.

On the other hand, even when the synchronous packet output circuit 140 receives the input of the detection flag signal of the control code Sx from the decoder circuit 113, when an error is detected in the error detection circuit 120 (that is, the error detection result is ". If there is an error), the synchronization packet is not output to the transmission circuit 150. Further, the synchronous packet output circuit 140 does not output the synchronous packet to the transmission circuit 150 when the input of the detection flag signal of the control code Sx is not received from the decoder circuit 113 (that is, when the control code Sx is not detected). ..

When the error detection circuit 120 receives the input of the detection flag signal of the control code Sx from the decoder circuit 113, the error detection circuit 120 determines that the communication packet received from the decoder circuit 113 is a synchronization packet, and determines that the communication packet (that is, the synchronization packet). ) Is discarded.

On the other hand, when the error detection circuit 120 does not accept the input of the detection flag signal of the control code Sx, the error detection circuit 120 determines that the communication packet is a data packet. If no error is detected in the data packet, the error detection circuit 120 outputs the data packet to the buffer memory circuit 130. When an error is detected in the data packet, the error detection circuit 120 discards the data packet or sets an error flag indicating that the error has been detected in the data packet and sets the data packet. Is output to the buffer memory circuit 130. When the error flag is set in the data packet, the buffer memory circuit 130 generates an FCS and replaces the FCS in the communication packet with the generated FCS.

The buffer memory circuit 130 temporarily stores the received data packet and outputs the stored data packet to the transmission circuit 150. For example, the buffer memory circuit 130 is composed of a FIFO (First In First Out) memory. Specifically, the buffer memory circuit 130 replaces the data packet processed by the operating clock of the receiving circuit 110 with the operating clock of the transmitting circuit 150, and outputs the data packet to the transmitting circuit 150.

The transmission circuit 150 outputs the communication packet to the serial bus 13B. Specifically, the transmission circuit 150 includes an encoder circuit 151 and a parallel serial conversion circuit 153.

The encoder circuit 151 is a circuit that encodes an input signal, and has an encoder according to the coding method. In this embodiment, the encoder circuit 151 is composed of an 8B / 10B encoder. The encoder circuit 151 converts the communication packet from 8-bit data to 10-bit data and outputs the communication packet to the parallel serial conversion circuit 153. Specifically, the encoder circuit 151 converts the synchronization packet received from the synchronization packet output circuit 140 or the data packet received from the buffer memory circuit 130 into 10-bit data and outputs the data packet to the parallel serial conversion circuit 153.

The parallel serial conversion circuit 153 converts the communication packet (that is, the synchronization packet or the data packet) received from the encoder circuit 151 from the parallel data to the serial data and outputs the communication packet to the serial bus 13B.

Further, the bus repeater 15 includes a reception circuit 160, an error detection circuit 170, a buffer memory circuit 180, and a transmission circuit 190 as a configuration for transmitting communication packets from the downstream side to the upstream side.

The receiving circuit 160 receives the data packets transmitted from the slaves # m + 1 to # n via the serial bus 13B. Specifically, the receiving circuit 160 includes a serial-parallel conversion circuit 161 and a decoder circuit 163.

The serial-parallel conversion circuit 161 converts the data packet received from the serial bus 13B from the serial data to the parallel data and outputs the data packet to the decoder circuit 163. The decoder circuit 163 is composed of an 8B / 10B decoder, converts a data packet from 10-bit data to 8-bit data, and outputs the data packet to the error detection circuit 170.

If no error is detected in the data packet, the error detection circuit 170 outputs the data packet to the buffer memory circuit 180. When an error is detected in the data packet, the error detection circuit 170 discards the data packet or outputs the data packet in which the error flag is set to the buffer memory circuit 180. The buffer memory circuit 180 temporarily stores the input data packet and outputs it to the transmission circuit 190.

The transmission circuit 190 outputs a data packet to the serial bus 13A. Specifically, the transmission circuit 190 includes an encoder circuit 191 and a parallel serial conversion circuit 193.

The encoder circuit 191 is composed of an 8B / 10B encoder, converts 8-bit data into 10-bit data, and outputs the data to the parallel serial conversion circuit 193. Specifically, the encoder circuit 191 converts the data packet received from the buffer memory circuit 130 into 10-bit data and outputs the data packet to the parallel serial conversion circuit 193.

The parallel-serial conversion circuit 193 converts the data packet received from the encoder circuit 191 from the parallel data to the serial data and outputs the data packet to the serial bus 13A.

As described above, the bus repeater 15 is a circuit that determines whether or not the communication packet is a synchronization packet based on the information (for example, control code Sx) included in the communication packet received via the serial bus 13A. (For example, synchronous packet output circuit 140) is included. Further, when the communication packet is a synchronization packet, the bus repeater 15 transmits a synchronization packet stored in advance in the internal memory of the bus repeater 15 to each slave # m + 1 to # n via the serial bus 13B. Includes circuit 150.

Further, the bus repeater 15 includes a buffer memory circuit 130 that accumulates the communication packet and outputs the accumulated communication packet to the transmission circuit 150 when the communication packet is not a synchronization packet. The transmission circuit 150 transmits the communication packet received from the buffer memory circuit 130 to each slave # m + 1 to # n via the serial bus 13B.

The bus repeater 15 includes an error detection circuit 120 that detects an error in a communication packet received via the serial bus 13A. Even if it is determined that the communication packet is a synchronous packet, if an error is detected by the error detection circuit 120, the synchronous packet is not output from the synchronous packet output circuit 140, so that the transmission circuit 150 is a bus. The synchronization packet stored in the internal memory of the repeater 15 is not transmitted.

When the communication packet received via the serial bus 13A includes the control code Sx, the synchronization packet output circuit 140 determines that the communication packet is a synchronization packet, and transmits a synchronization packet stored in advance in the internal memory. Output to circuit 150.

According to the configuration of the bus repeater 15 as described above, when it is determined that the communication packet is a synchronization packet, the synchronization packet prepared in advance is immediately transmitted to each slave # m + 1 to # n on the downstream side. Ru. Therefore, the process of temporarily accumulating the communication packet and outputting it to the transmission circuit 150 becomes unnecessary, and the time for the synchronized packet to pass through the bus repeater 15 can be shortened.

A control code Sx indicating that the communication packet is a synchronization packet is stored in the synchronization flag area 52, which can be detected by the decoder circuit 113. Therefore, the detection processing time of the synchronization packet can be shortened, and as a result, the time for determining that the communication packet is the synchronization packet can be shortened. Further, since the packet length of the synchronization packet is shorter than the packet length of the data packet, the synchronization packet can pass through the bus repeater 15 in a short time. As a result, the time for the synchronous packet to pass through the bus repeater 15 can be further shortened.

<Advantage>
FIG. 5 is a diagram for explaining the advantages of the first embodiment. With reference to FIG. 5, the arrival time difference T1 of the synchronization packet when the synchronization packet is transmitted from the master 10 to each of the slaves # 1 to # n is shown. Specifically, the arrival time difference T1 is the time from the transmission time of the synchronization packet by the master 10 to the reception time of the synchronization packet by the slave #n.

Further, the arrival time difference T2 of the data packet when the data packet is transmitted from the master 10 to the slaves # 1 to # n is shown. Specifically, the arrival time difference T2 is the time from the transmission time of the data packet by the master 10 to the reception time of the data packet by the slave #n.

As shown in FIG. 5, the arrival time difference T1 is shorter than the arrival time difference T2. This is because the transit time Td1 in which the synchronous packet passes through the bus repeater 15 is shorter than the transit time Td2 in which the data packet passes through the bus repeater 15. As described above, by configuring and processing the bus repeater 15 described above, it is possible to improve the synchronization accuracy of the sampling timing of the amount of electricity in each slave 11 by shortening the passing time of the synchronization packet in the bus repeater 15.

Embodiment 2.
In the first embodiment, a configuration for storing the control code Sx in the synchronization flag area 52 of the synchronization packet has been described in order to identify that the communication packet is a synchronization packet. In the second embodiment, a configuration for storing the synchronization command in the header area of the synchronization packet will be described. The overall configuration of the protection control device 100 according to the second embodiment is the same as the <overall configuration> of the first embodiment.

FIG. 6 is a diagram showing an example of the configuration of the bus repeater 15A according to the second embodiment. With reference to FIG. 6, the bus repeater 15A includes the decoder circuit 113, the error detection circuit 120 and the synchronous packet output circuit 140 in the bus repeater 15 shown in FIG. 3, the decoder circuit 113A, the detection circuit 120A and the synchronous packet output circuit 140A, respectively. Corresponds to the configuration replaced with. Therefore, the detailed description of the configuration similar to that of the bus repeater 15 will not be repeated.

The receiving circuit 110A receives the communication packet from the master 10 via the serial bus 13A. Here, the configuration of the synchronization packet and the data packet received in the reception circuit 110A will be described.

FIG. 7 is a diagram schematically showing the configuration of a synchronization packet and a data packet according to the second embodiment. Specifically, FIG. 7A shows an example of a synchronous packet configuration, and FIG. 7B shows an example of a data packet configuration. Since the configuration of the data packet shown in FIG. 7 (b) is the same as the configuration of the data packet shown in FIG. 4 (b), a detailed description thereof will not be given.

With reference to FIG. 7A, the synchronization packet includes a head flag area 51, a header area 54, and an FCS area 53. As shown in FIG. 7A, the synchronization packet according to the second embodiment has the header area 54 and does not have the synchronization flag area 52 shown in FIG. 4A. This point is different from the configuration of the synchronous packet according to the first embodiment. The header area 54 contains a synchronization command. The point that the variable element does not exist in the synchronous packet is the same as that of the synchronous packet shown in FIG. 4 (a).

Again, with reference to FIG. 6, the receiving circuit 110A includes a serial-parallel conversion circuit 111 and a decoder circuit 113A. The decoder circuit 113A is composed of an 8B / 10B decoder, converts 10-bit data into 8-bit data, and outputs the data to the detection circuit 120A.

In the first embodiment, the decoder circuit 113 has detected the control code Sx stored in the synchronization flag area 52 of the synchronization packet. However, in the second embodiment, since the control code Sx is not included in the synchronization packet as shown in FIG. 7B, the decoder circuit 113A does not detect the control code Sx.

When the detection circuit 120A detects that the header area of the communication packet received from the decoder circuit 113A contains a synchronization command, the detection circuit 120A outputs a detection result (for example, a detection flag signal) indicating that the synchronization command is detected. Output to circuit 140A. Further, the detection circuit 120A detects an error based on the FCS included in the communication packet, and outputs the error detection result to the synchronous packet output circuit 140A.

When the synchronization packet output circuit 140A receives the input of the detection flag signal of the synchronization command from the detection circuit 120A (that is, when the communication packet includes the synchronization command), the communication packet received in the reception circuit 110A is synchronized. Judge as a packet. Then, when the error is not detected in the detection circuit 120A, the synchronization packet output circuit 140A determines that there is no error in this synchronization packet. In this case, the synchronization packet output circuit 140A outputs the synchronization packet stored in advance in the internal memory to the transmission circuit 150.

On the other hand, the synchronous packet output circuit 140A transmits a synchronous packet to the transmission circuit 150 when an error is detected in the detection circuit 120A even when the detection circuit 120A receives the input of the detection flag signal of the synchronization command. Do not output. Further, when the synchronization packet output circuit 140A does not accept the input of the detection flag signal of the synchronization command from the detection circuit 120A (that is, when the synchronization command is not detected), the synchronization packet output circuit 140A does not output the synchronization packet to the transmission circuit 150.

When the synchronization command is detected in the communication packet, the detection circuit 120A determines that the communication packet received in the reception circuit 110A is a synchronization packet, and discards this communication packet (that is, the synchronization packet).

On the other hand, if the synchronization command is not detected in the communication packet, the detection circuit 120A determines that the communication packet is a data packet. If no error is detected in the data packet, the detection circuit 120A outputs the data packet to the buffer memory circuit 130. When an error is detected in the data packet, the detection circuit 120A discards the data packet or outputs the data packet in which the error flag is set to the buffer memory circuit 130. When the error flag is set in the data packet, the buffer memory circuit 130 generates an FCS and replaces the FCS in the communication packet with the generated FCS.

As described above, the bus repeater 15A is a circuit (for example) that determines whether or not the communication packet is a synchronization packet based on the information (for example, a synchronization command) included in the communication packet received via the serial bus 13A. For example, a synchronous packet output circuit 140A) is included. Further, when the communication packet is a synchronization packet, the bus repeater 15A transmits the synchronization packet stored in the internal memory of the bus repeater 15A to each slave # m + 1 to # n via the serial bus 13B. including.

When the communication packet received via the serial bus 13A includes a synchronization command, the synchronization packet output circuit 140A determines that the communication packet is a synchronization packet, and transmits a synchronization packet stored in advance in the internal memory. Output to 150.

In the second embodiment, the header area 54 stores a synchronization command indicating that the communication packet is a synchronization packet, which can be detected by the detection circuit 120A. Even in this case, the detection processing time of the synchronization packet can be shortened, and as a result, the time for determining that the communication packet is the synchronization packet can be shortened.

<Advantage>
According to the second embodiment, it has the same advantages as the first embodiment.

Embodiment 3.
In the first and second embodiments described above, the configuration for shortening the time for the synchronization packet to pass through the bus repeater has been described. However, in the third embodiment, after the bus interface 31 of each slave 11 receives the synchronization packet, A configuration for shortening the time until the sampling timing signal of the electric quantity is output to the AD conversion circuit 32 will be described. The overall configuration of the protection control device 100 according to the third embodiment is the same as the <overall configuration> of the first embodiment.

FIG. 8 is a diagram showing an example of the configuration of the slave 11P according to the third embodiment. With reference to FIG. 8, the slave 11P includes a bus interface 31P and an AD conversion circuit 32. Here, the slave 11P corresponds to the slave 11 in FIG. 1, but the reference numeral “P” is added for convenience of distinction. This also applies to the bus interface 31P.

In the following, for the sake of facilitation of description, the slave 11P is assumed to be one of the slaves # 1 to # m connected to the serial bus 13A in FIG. Further, it is assumed that each configuration of the synchronization packet and the data packet is the configuration shown in FIG. 4 described in the first embodiment. The slaves # m + 1 to # n also have the same configuration as the slave 11P described below.

The bus interface 31P includes a reception circuit 210, an error detection circuit 220, a timing signal output circuit 230, a command generation circuit 240, a communication packet generation circuit 250, and a transmission circuit 260.

The receiving circuit 210 receives the communication packet from the master 10 via the serial bus 13A. Specifically, the receiving circuit 210 includes a serial-parallel conversion circuit 211 and a decoder circuit 213. The configuration of the receiving circuit 210 is the same as the configuration of the receiving circuit 110 of the bus repeater 15.

The serial-parallel conversion circuit 211 converts the communication packet received from the serial bus 13A from serial data to parallel data and outputs the communication packet to the decoder circuit 213. The decoder circuit 213 is composed of an 8B / 10B decoder, converts a communication packet from 10-bit data to 8-bit data, and outputs the communication packet to the error detection circuit 220.

When the control code Sx is detected in the communication packet, the decoder circuit 213 outputs a detection result (for example, a detection flag signal) indicating that the control code Sx is detected to the timing signal output circuit 230. Further, this control code Sx is output to the error detection circuit 220. The error detection circuit 220 detects an error based on the FCS included in the communication packet, and outputs the error detection result to the timing signal output circuit 230.

When the timing signal output circuit 230 receives the input of the detection flag signal of the control code Sx from the decoder circuit 213 (that is, when the communication packet includes the control code Sx), the timing signal output circuit 230 determines that the communication packet is a synchronization packet. do. Then, when the error is not detected in the error detection circuit 220, the timing signal output circuit 230 determines that there is no error in this synchronization packet. In this case, the timing signal output circuit 230 outputs a sampling timing signal (for example, a pulse signal) of the amount of electricity to the AD conversion circuit 32.

On the other hand, the timing signal output circuit 230 ADs the sampling timing signal when an error is detected in the error detection circuit 220 even when the input of the detection flag signal of the control code Sx is received from the decoder circuit 213. No output to the conversion circuit 32. Further, the timing signal output circuit 230 does not output the sampling timing signal to the AD conversion circuit 32 when the input of the detection flag signal of the control code Sx is not received from the decoder circuit 213.

When the error detection circuit 220 receives the input of the detection flag signal of the control code Sx from the decoder circuit 213, the error detection circuit 220 determines that the communication packet received from the decoder circuit 213 is a synchronization packet, and determines that the communication packet (that is, the synchronization packet). ) Is discarded.

On the other hand, when the error detection circuit 220 does not accept the input of the detection flag signal of the control code Sx, the error detection circuit 220 determines that the communication packet is a data packet. If no error is detected in the data packet, the error detection circuit 220 outputs the data packet to the command generation circuit 240. When an error is detected in the data packet, the error detection circuit 220 discards the data packet or sets an error flag in the data packet and sends the data packet to the command generation circuit 240. Output.

The command generation circuit 240 analyzes the data packet, and if it is a data packet addressed to itself, generates a command signal corresponding to this data packet and outputs it to the AD conversion circuit 32. For example, the command signal commands a signal to transmit the amount of electricity sampled by the AD conversion circuit 32 to the master 10, and an operation mode (for example, ON, OFF, etc. of the filter circuit) in the AD conversion circuit 32. Including signals and the like.

The AD conversion circuit 32 outputs the sampled electric energy to the communication packet generation circuit 250 according to the command signal. Further, the AD conversion circuit 32 outputs a state signal indicating its current state to the communication packet generation circuit 250. The state signal includes a signal indicating whether or not the state of the AD conversion circuit 32 is normal, a signal indicating that sampling of electric energy has been completed, and the like.

The communication packet generation circuit 250 generates a data packet containing the amount of electricity, a state signal, etc. received from the AD conversion circuit 32, and outputs the data packet to the transmission circuit 260.

The transmission circuit 260 outputs a data packet to the serial bus 13A. Specifically, the transmission circuit 260 includes an encoder circuit 261 and a parallel serial conversion circuit 263.

The encoder circuit 261 is composed of an 8B / 10B encoder. The encoder circuit 261 converts an 8-bit data into a 10-bit data and outputs the data packet to the parallel serial conversion circuit 263.

As described above, when the bus interface 31P determines that the communication packet is a synchronization packet based on the information (for example, control code Sx) included in the communication packet received via the serial bus 13A, the amount of electricity is increased. A timing signal output circuit 230 that outputs a sampling timing signal to the AD conversion circuit 32 is included.

Further, the bus interface 31P includes an error detection circuit 220 that detects an error in a communication packet received via the serial bus 13A. Even if the communication packet is a synchronous packet, if an error is detected by the error detection circuit 220, the timing signal output circuit 230 does not output the sampling timing signal of the amount of electricity to the AD conversion circuit 32.

In the above, the case where each configuration of the synchronization packet and the data packet has the configuration shown in FIG. 4 has been described, but the configuration is not limited to the configuration, and the configuration shown in FIG. 7 in the second embodiment may be used. In this case, the error detection circuit 220 in FIG. 8 is replaced with a detection circuit having the same function as the detection circuit 120A.

Specifically, when the detection circuit detects that the header area of the communication packet received from the decoder circuit 213 includes a synchronization command, the detection circuit outputs the synchronization command to the timing signal output circuit 230. Further, the detection circuit detects an error based on the FCS included in the communication packet, and outputs the error detection result to the timing signal output circuit 230. The timing signal output circuit 230 receives an input of a synchronization command from the detection circuit, and outputs a sampling timing signal when an error is not detected in the detection circuit.

<Advantage>
FIG. 9 is a diagram for explaining the advantages of the third embodiment. Here, it is assumed that the data packet and the synchronization packet are transmitted from the master 10 to the slaves # 1 to # m.

With reference to FIG. 9, when the master 10 transmits a data packet, the slave # 1 receives the data packet. The bus interface 31P of slave # 1 analyzes the received data packet and outputs a command signal corresponding to the data packet to the AD conversion circuit 32. Specifically, the time from the time when the master 10 transmits the data packet to the time when the command signal is output to the AD conversion circuit 32 of the slave # 1 is shown as the output delay time Tdx1 of the command signal.

The time Ts1 is the time from the time when the command signal is output in the slave # 1 to the time when the command signal is output in the slave # m, and indicates the output time difference of the command signal between the slave # 1 and the slave # m. ing.

Further, when the master 10 transmits a synchronization packet, the synchronization packet is received by the slave # 1. When the bus interface 31P of the slave # 1 receives the synchronization packet, it outputs the sampling timing signal of the electric energy to the AD conversion circuit 32. Specifically, the time from the transmission time of the synchronization packet by the master 10 to the output time of the sampling timing signal by the bus interface 31P of the slave # 1 is shown as the output delay time Tdx2 of the sampling timing signal.

The time Ts2 is the time from the output time of the sampling timing signal in the slave # 1 to the output time of the sampling timing signal in the slave # m, and indicates the output time difference of the sampling timing signal between the slave # 1 and the slave # m. There is. Typically, time Ts1 and time Ts2 are the same.

As shown in FIG. 9, the output delay time Tdx2 of the sampling timing signal is shorter than the output delay time Tdx1 of the command signal. This is because the bus interface 31P immediately outputs a sampling timing signal when it determines that the received communication packet is a synchronous packet. On the other hand, it takes time because the command signal corresponding to the data packet is output after the data packet is analyzed by the command generation circuit 240. In FIG. 9, since the packet length of the synchronization packet is shorter than the packet length of the data packet, the difference between the output delay time Tdx1 and the output delay time Tdx2 is larger.

In this way, by shortening the time from when the bus interface 31P receives the synchronization packet to when the sampling timing signal is output to the AD conversion circuit 32, the synchronization accuracy of the sampling timing of the amount of electricity in each slave 11 is further improved. Can be improved.

For example, when the master 10 outputs a synchronized packet in synchronization with the system frequency of the transmission line, each slave 11 can sample the electric energy at a timing close to the output timing of the synchronized packet by the master 10, and the synchronization accuracy with the system frequency. Can be improved.

Other embodiments.
(1) In the above-described embodiment, a configuration in which the master 10 is connected to a plurality of slaves # 1 to # n using one bus repeater 15 as shown in FIG. 1 has been described, but the configuration is limited to this configuration. I can't. For example, as shown in FIG. 10, the master 10 may be connected to a plurality of slaves # 1 to # n by using two bus repeaters 15.

FIG. 10 is a diagram showing an example of the overall configuration of the protection control device 100A according to other embodiments. With reference to FIG. 10, the protection control device 100A includes a master 10, a plurality of slaves # 1 to # n, serial buses 13A and 13B, bus repeaters 15_1 and 15_2, and an optical cable 18.

The master 10 is connected to the slaves # 1 to # m and the bus repeater 15_1 via the serial bus 13A. The bus repeater 15_1 and the bus repeater 15_2 are connected via an optical cable 18.

The bus repeater 15_2 is connected to the slaves # m + 1 to # n via the serial bus 13B. Therefore, the master 10 is connected to the slaves # m + 1 to # n via the serial bus 13A, the bus repeaters 15_1, 15_2, and the serial bus 13B.

The bus repeater 15_1 and 15_2 have the same configuration and function as the bus repeater 15 described above. However, the bus repeaters 15_1 and 15_2 have a circuit for converting an electric signal into an optical signal.

For example, the communication packet received by the bus repeater 15_1 is converted from an electric signal into an optical signal after being processed by the bus repeater 15 described above, and transmitted to the bus repeater 15_2. The communication packet received by the bus repeater 15_2 is converted from an optical signal into an electric signal, then processed by the bus repeater 15 described above, and transmitted to the serial bus 13B.

(2) In the above-described embodiment, when each slave 11 includes a DI circuit, a synchronization packet for synchronizing the timing at which each DI circuit captures a signal is transmitted from the master 10 to each slave 11. It may be configured as such.

(3) The configuration exemplified as the above-described embodiment is an example of the configuration of the present invention, can be combined with another known technique, and a part thereof is not deviated from the gist of the present invention. It is also possible to change and configure it, such as by omitting it. Further, in the above-described embodiment, the processing and configuration described in the other embodiments may be appropriately adopted and carried out.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims, not the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

10 master, 11,11P slave, 13A, 13B serial bus, 15,15A bus repeater, 18 optical cable, 21,31a to 31c, 31P bus interface, 22 CPU, 24 ROM, 32a to 32c AD conversion circuit, 33a DI circuit, 34a DO circuit, 100,100A protection control device, 110,110A, 160,210 reception circuit, 111,161,211 serial parallel conversion circuit, 113,113A,163,213 decoder circuit, 120,170,220 error detection circuit, 120A detection circuit, 130,180 buffer memory circuit, 140,140A synchronous packet output circuit, 150,190,260 transmission circuit, 151,191,261 encoder circuit, 153,193,263 parallel serial conversion circuit, 230 timing signal output circuit , 240 command generation circuit, 250 communication packet generation circuit.

Claims (8)

With the master
With the first plurality of slaves connected to the master via the first serial bus,
A bus repeater that transfers communication packets between the first serial bus and the second serial bus,
A second plurality of slaves connected to the bus repeater via the second serial bus are provided.
The bus repeater is
A synchronization packet for synchronizing the sampling timing of the amount of electricity in each of the first and second plurality of slaves based on the information contained in the communication packet received via the first serial bus. The first judgment circuit that judges whether or not it is
When the communication packet is the synchronization packet, a protection control device including a transmission circuit for transmitting a synchronization packet stored in advance in the internal memory to the second plurality of slaves via the second serial bus. .. The bus repeater further includes a buffer memory circuit that accumulates the communication packet and outputs the accumulated communication packet to the transmission circuit when the communication packet is not the synchronization packet.
The protection control device according to claim 1, wherein the transmission circuit transmits the communication packet received from the buffer memory circuit to the second plurality of slaves via the second serial bus. Further including a first error detection circuit for detecting an error in a communication packet received via the first serial bus.
Even when the communication packet is determined to be the synchronization packet by the first determination circuit, when the error is detected by the first error detection circuit, the transmission circuit is the internal memory. The protection control device according to claim 1 or 2, wherein the synchronization packet stored in the device is not transmitted. The synchronization packet contains a predetermined control code.
Claims 1 to claim that when the communication packet received via the first serial bus includes the predetermined control code, the first determination circuit determines that the communication packet is the synchronization packet. 3. The protection control device according to any one of 3. The synchronization packet contains a synchronization command in the header area.
Any one of claims 1 to 3, wherein when the communication packet received via the first serial bus includes the synchronization command, the first determination circuit determines that the communication packet is the synchronization packet. The protection control device according to item 1. Each of the first plurality of slaves
The bus interface connected to the first serial bus and
It includes an AD (analog-to-digital) conversion circuit connected to the bus interface.
The bus interface includes a signal output circuit that outputs a sampling timing signal of electricity to the AD conversion circuit.
When the signal output circuit determines that the communication packet is the synchronization packet based on the information contained in the communication packet received via the first serial bus, the signal output circuit transmits the sampling timing signal to the AD conversion circuit. The protection control device according to any one of claims 1 to 5, which is output. The bus interface further includes a second error detection circuit that detects an error in a communication packet received via the first serial bus.
Even if the communication packet is the synchronization packet, if the error is detected by the second error detection circuit, the signal output circuit does not output the sampling timing signal to the AD conversion circuit. , The protection control device according to claim 6. The protection control device according to any one of claims 1 to 7, wherein each of the first serial bus and the second serial bus is an M-LVDS (multipoint low voltage differential signaling) bus.

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