JP7095331B2 - Power storage device and power storage system - Google Patents

Description

The present invention relates to a power storage device and a power storage system.

With the progress of IoT technology, efforts are underway to make the power supply to edge devices battery-less by using energy harvesting technology. For example, an application has been realized in which an LED is turned on by electric power generated by electrostatic induction by a piezoelectric element, peel charge and triboelectric charge in a power generation rubber, an electret, or the like.

However, since the generated voltage is high and the generated current is small in piezoelectric elements, triboelectric charging, and power generation by electrostatic induction, it is suitable for applications such as connecting LEDs in series to make them illuminate instantaneously, but the CPU operation required for IoT edge devices The voltage and current required for sensor drive and wireless transmission cannot be satisfied. Therefore, even if the generated voltage is high and the current is small, there is a need for technological development that efficiently utilizes the generated power.

Generally, in the case of a minute amount of generated power, the generated power is stored in a capacitor and converted into a drive voltage required for an edge device by a DC / DC converter. However, since the output impedance of the piezoelectric element or the power generation device by electrostatic induction is high, if the capacitor is directly stored in a capacitor with low impedance, it will be stored in the low voltage state at the time of storage, and there is a problem that the energy storage efficiency is low. ..

Therefore, Patent Document 1 proposes a power supply circuit that generates operating power by using minute power generated by a power generation element having a high output impedance and outputting a low current. In this power supply circuit, an electret element is assumed as a power generation element that outputs a minute amount of power, has a high output impedance of 15 MΩ, and has a maximum output of 92.5 Vp-p and 3.1 μA.

However, assuming that the power supply circuit of Patent Document 1 is applied to a power generation rubber having a maximum output of 400 V and 1 μA, the output voltage of the power generation rubber is larger than that of the electlet element, so that the power consumed by the internal resistance of the power generation rubber is high. It was inefficient because it became large.

Therefore, in view of the above circumstances, an object of the present invention is to provide a power storage device capable of improving energy storage efficiency and usage efficiency by using the power output by a power generation element that outputs high voltage and low current. ..

In order to solve the above problems, the present invention has the following means.
According to one aspect
A power storage device connected to a power generation element and a load circuit.
A power storage unit with multiple power storage devices and
A timing control unit that controls the series-parallel switching of the plurality of power storage devices, and
It has a series-to-parallel switching switch unit that is controlled by the timing control unit and switches the series-parallel switching of the plurality of storage devices.
The timing control unit provides hysteresis by including a hysteresis generation circuit to control the switching timing.
The hysteresis generation circuit includes a transistor, a resistor, and an inverter.
A power storage device, characterized by the above, is provided.

According to one aspect, in the power storage device, the energy storage efficiency and the usage efficiency can be improved by using the electric power output by the power generation element that outputs high voltage and low current.

The schematic diagram of the power storage system which concerns on embodiment of this invention. The schematic diagram of the power storage system which concerns on the comparative example. Conceptual diagram of a power generation element mounted on a power storage system. The figure which explains the equivalent circuit diagram at the time of electricity storage using a power generation element, and the storage energy rate by the condition which stores electricity in a capacitor. The figure explaining the equivalent circuit diagram at the time of power generation consumption by a resistance load using a power generation element, and the ratio of the power supply amount by the condition of supplying power to a resistance load. The figure explaining the state of the switch which connects two capacitors in series. The figure explaining the state of the switch which connects two capacitors in parallel. Explanatory drawing of the configuration example 1 of the series-parallel switching timing control unit. Explanatory drawing of the configuration example 2 of the series-parallel switching timing control unit. A specific circuit diagram of a power storage device according to an embodiment of the present invention. It is a figure which shows the flow of the electric current at the time of electricity storage and at the time of electric power supply in the electricity storage device of FIG. The circuit diagram of the power storage system of FIG. It is a figure explaining the Example in the case of adding the function linked with the communication module mounted on the microcomputer to the IC function of FIG. The timing chart of the series-parallel switching operation in the power storage device of FIG. (A) A circuit diagram in which the capacity of the capacitor is fixed, and a diagram showing the transition of the stored current and the stored voltage in the state of (b) and (a), and the voltage between the capacitor terminals at the time of discharging. The figure which shows the transition of the current at the time. (A) A circuit diagram for switching the series-parallel of the capacitor, and (b) a diagram showing the transition of the storage current and the storage voltage in the state of (a) and the voltage between the capacitor terminals at the time of discharge. The figure explaining the embodiment of the circuit which connects four capacitors in series. The figure explaining the embodiment of the capacitor multi-stage connection circuit.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following drawings, the same components may be designated by the same reference numerals and duplicate explanations may be omitted.

<Power storage system>
First, the power storage system of the present invention will be described with reference to FIG. FIG. 1 is a schematic diagram of a power storage system (energy power storage system) according to an embodiment of the present invention.

The power storage system 100 includes a power generation element 2, a rectifier circuit 4, a power storage device 1, and a load circuit 3.

The power storage device 1 includes a series-parallel switching timing control unit 5, a series-parallel switching switch unit 6, and a power storage unit 7. The power storage unit 7 is composed of capacitors C1 and C2, which are a plurality of power storage devices that can switch between a series connection state and a parallel connection state.

The power generation element 2 is generated by a power generation rubber, a piezoelectric element, or electrostatic induction. The generated power is a high voltage and a low current, and the power generation will be described later together with FIG.

The load circuit 3 is, for example, an LED (light emitting diode), an IC (Integrated Circuit) having a CPU (Central Processing Unit) function, a sensor, a wireless transmission IC, or the like.

In the power storage system 1, after the energy generated by the power generation element 2 is rectified by the rectifier circuit 4, the energy is stored at a high voltage in a plurality of series-connected capacitors C1 and C2 (see FIG. 12), and the plurality of capacitors C1 are stored. , C2 are connected in parallel to supply energy to the load circuit 3.

More specifically, the AC energy generated by the power generation element 2 is rectified by the rectifier circuit (rectifier unit) 4. At this time, the series-parallel switching timing control unit 5 controls the series-parallel switching switch unit 6 to store energy (storage voltage) in a plurality of capacitors C1 and C2 connected in series by the storage unit 7. Then, when the stored voltage reaches a constant voltage, the series-parallel switching timing control unit 5 controls the series-parallel switching switch unit 6, and a plurality of capacitors C1 and C2 are connected in parallel to supply power to the load circuit 3. ..

Then, when the output potential of the power storage unit 7 becomes equal to or lower than a certain voltage, the series-parallel switching timing control unit 5 controls the series-parallel switching switch unit 6 to restore the plurality of capacitors C1 and C2 to the series connection to generate a power generation element. The energy generated from 2 is stored.

<Comparison example>
FIG. 2 shows, for comparison, a schematic diagram of a system that stores energy generated by an energy harvesting element and supplies it to a load circuit.

FIG. 2 shows an example of a typical energy harvest system. Also in this example, the energy generated by the energy harvesting element is supplied to the load circuit through the rectifier circuit 4 and the power storage device 1X.

The power storage device 1X of FIG. 2 includes a first power storage unit 101, which is a power storage side storage unit, a power conversion circuit 102, and a second power storage unit 103, which is a supply side power storage unit. That is, in the general energy storage system 100X, the power storage unit is separately provided with the first power storage unit 101 for power storage and the second power storage unit 103 on the supply side.

In the configuration of FIG. 2, the voltage stored in the first storage unit 101 is converted into the operating voltage of the load circuit 3 by the power conversion circuit 102 such as a DC / DC converter, and the voltage is stored in the second storage unit 103 to load the load. Power the circuit. At this time, this power storage device has the following problems.
(A): Generation of loss due to current consumption in the power conversion circuit 102 (B): Generation of loss due to conversion efficiency (C): Addition of components such as an inductor

Specifically, it is necessary to perform step-up conversion or step-down conversion of the voltage in relation to the voltage stored in the first storage unit 101 and the voltage stored in the second storage unit 103.

When the storage voltage of the first storage unit 101 <the storage voltage of the second storage unit 103, it is necessary to perform boost conversion. Electric power is stored at a low voltage, and it is necessary to increase the power storage device 1X by the following (Equation 1).

Further, since the stored energy is proportional to the square of the stored voltage, the storage by the power generation element 2 that outputs a low current at a high voltage such as a power generation rubber causes a loss due to the current consumption in the power conversion circuit 102, so that the stored energy is stored. The voltage rise efficiency is poor, and the storage efficiency is low (A).

Next, when the storage voltage of the first storage unit 101> the storage voltage of the second storage unit 103, it is necessary to perform step-down conversion. In this case, since energy can be stored in the first storage unit 101 at a high voltage by (Equation 1), the energy storage device can be made smaller and energy can be stored at a high voltage. However, since a difference between the storage voltage of the first storage unit 101 and the storage voltage of the second storage unit 103 occurs, that amount becomes a loss and the energy conversion efficiency decreases (B).

As described above, in the configuration of FIG. 2, the loss in which the current consumption in the power conversion circuit 102 becomes large and the loss due to the voltage change become large, and the power storage device becomes large due to the increase in the number of components. ..

In comparison with this, in the power storage system of the embodiment of the present invention shown in FIG. 1, a power storage unit having a plurality of capacitors is commonly used at the time of power storage and at the time of power supply, and for driving the power storage unit. Energy efficiency is good because the current is small and there is no voltage conversion loss.

<Power generation element>
FIG. 3 is a conceptual diagram of the power generation element 2 mounted on the power storage system of the present invention.

The power generation element 2 is made of, for example, a power generation rubber, and generates electric charges by applying a peeling force, a frictional force, a vibration force, or a deformation force to generate electric charge.

The amount of power generated by the power generation element 2 is a voltage of 10 to 1000 V (for example, 40 V) and a current of 50 nA to 100 μA (for example, 6 μA).

Further, since the power generation element composed of the power generation rubber or the piezoelectric element has a high resistance and outputs a current due to a predetermined charge, it can be approximated by the current source 21 and the internal resistance 22. The resistance value of the internal resistance 22 is 1 to 100 MΩ (megaohm) (for example, 10 MΩ).

Here, the capacitor and the resistance load connected to the power generation element 2 will be described with reference to FIGS. 4 and 5.

FIG. 4 (a) is an equivalent circuit diagram at the time of electricity storage using a power generation element, and FIG. 4 (b) is a diagram illustrating a storage energy rate under a condition of storing electricity in a capacitor.

FIG. 4B is a graph showing the energy generated by the power generation element as a ratio (%) calculated by changing the capacity value of the capacitor and assuming that the stored energy at the maximum is 100%. Is.

When the capacity of the capacitor is set to the part indicated by the arrow in FIG. 4 (b), impedance matching is achieved between the capacitor and the power generation element 2 (output side) consisting of a constant current source and an internal resistance, and energy can be stored most efficiently. ..

FIG. 5A is an equivalent circuit diagram at the time of power generation consumption by a resistance load using the power generation element 2, and FIG. 5B describes the ratio of the power supply amount under the condition of supplying power to the resistance load. It is a figure to do.

In FIG. 5 (b), the energy generated by the power generation element is expressed by the ratio (%) calculated by changing the resistance value of the load resistance and assuming that the energy consumed at the maximum is 100%. It is a graph.

When the resistance value of the load resistance is set to the part indicated by the arrow in FIG. 5 (b), the load resistance and the internal resistance of the power generation element 2 are in the same state, and when the internal resistance = the load resistance, the load circuit 3 (output side). ) And impedance matching, energy can be used most efficiently.

<Clock-parallel switching>
FIG. 6 is a schematic diagram showing a state of a switch connecting two capacitors in series. FIG. 7 is a schematic diagram showing a state of a switch connecting two capacitors in parallel.

The series-parallel changeover switch unit 6 includes three switches Sw1, Sw2, and Sw3. The power storage unit 7 includes two capacitors C1 and C2. The capacitor is an example of a power storage device, and may be an electric double layer capacitor, a lithium ion capacitor, a lithium ion battery, a lead storage battery, or various power storage devices.

As shown in FIG. 6, when the switch Sw2 of the series-parallel switching switch unit 6 is ON and the switches Sw1 and Sw3 are OFF, the capacitors C1 and C2 of the storage unit 7 are connected in series.

Further, as shown in FIG. 7, when the switches Sw1 and Sw3 of the series-parallel switching switch unit 6 are ON and the switch Sw2 is OFF, the capacitors C1 and C2 of the storage unit 7 are in the parallel connection state.

<Sequential / parallel switching timing control unit>
FIG. 8 is a diagram illustrating a first configuration example of the parallel / parallel switching timing control unit.
The series-parallel switching timing control unit 5 (timing control unit) shown in FIG. 8 includes a series-parallel switching switch control unit 50, two resistors R1 and R2, and two switches Sw4 and Sw5.

The series-parallel changeover switch control unit 50 monitors the input voltage Vin that is the reference for the series-parallel switching, and functions as a voltage monitor circuit that outputs the control signal S1. Then, the series-parallel changeover switch control unit 50 generates a control signal S1 according to the detection result of the input voltage Vin to the terminal 11, and the generated control signal S1 controls the switch Sw4 and the switch Sw5.

Further, in the series-parallel switching timing control unit 5, the resistance R1 and the switch Sw4 form a high impedance drive inverter 51, and the resistance R2 and the switch Sw5 form a high impedance drive inverter 52. The switch Sw4 and the switch Sw5 are composed of, for example, Nch transistors.

The parallel / parallel switching timing control unit 5 generates control signals φ1 and φ2 for controlling the parallel / parallel switching switch unit 6, and outputs them from terminals 53 and 54.

In the series-parallel switching timing control unit 5, the series-parallel switching switch control unit 50 and the inverter 51 function as the hysteresis generation circuit H. The hysteresis generation circuit H quickly detects a change in the input voltage Vin, and has a hysteresis at the switching threshold so that the signal once switched from L level to H level (or H level to L level) is prevented from being unstablely switched. (Difference) is provided. In this example, the hysteresis generation circuit H switches the control signal φ1 from the H level to the L level when the input voltage Vin rises and reaches a predetermined first voltage, and the input voltage Vin drops from the first voltage. When the predetermined second voltage is reached, the control signal φ1 is switched from the L level to the H level. Details will be described later together with FIG.

In this configuration, by using the high impedance resistors R1 and R2 for the inverters 51 and 52, the power storage device is also a piezoelectric element or a high impedance output power generation element 2 having a high voltage and a low current generated by electrostatic induction. 1 circuit can be driven. For example, the resistance values of the resistors R1 and R2 are 1 MΩ to 500 MΩ.

FIG. 9 is a diagram illustrating a second configuration example of the parallel / parallel switching timing control unit.
The series-parallel switching timing control unit 5A shown in FIG. 9 includes a series-parallel switching switch control unit 50, two constant current sources IC1 and IC2, and two switches Sw4 and Sw5.

Further, in the series-parallel switching timing control unit 5A, the constant current source IC1 and the switch Sw4 form a high impedance drive inverter 51A, and the constant current source IC2 and the switch Sw5 form a high impedance drive inverter 52A. The switch Sw4 and the switch Sw5 are composed of, for example, Nch transistors.

The control signal S1 generated by the series-parallel changeover switch control unit 50 controls the switches Sw4 and Sw5, and the control signals φ1 and φ2 for controlling the series-parallel changeover switch unit 6 are generated and output from the terminals 53 and 54. .. In the parallel / parallel switching timing control unit 5A, the switch control unit 50 and the inverter 51A function as the hysteresis generation circuit H.

In this configuration, by using high impedance constant current sources IC1 and IC2 for the inverters 51A and 52A, even a high impedance output power generation element 2 that has a high voltage and a low current generated by a piezoelectric element or electrostatic induction can be used. , The circuit of the power storage device 1 can be driven. For example, the current values generated by the constant current sources IC1 and IC2 included in the inverters 51A and 52A are 10 nA to 100 μA.

FIG. 10 is a specific circuit diagram of the power storage device 1 according to the embodiment of the present invention.

The power storage device 1 includes a series-parallel switching timing control unit 5B, a series-parallel switching switch unit 6, a power storage unit 7, and an output switch unit 8 (output unit). The power storage device 1 may be combined into one IC as a power storage IC.

The parallel / parallel switching timing control unit 5B includes a changeover switch control unit 50B, two dip region transistors Tr1 and Tr3, and two Nch transistors (FET: Field effect transistors) Tr2 and Tr4.

In this configuration, the changeover switch control unit 50B is composed of an Nch transistor Tr5 and three resistances R3, R4, and R5. The three resistors R3, R4, and R5 are high resistances having a high resistance value (high impedance). The transistor Tr5 is a hysteresis generation switch, and a signal indicating the state of the load circuit 3 may be input.

The series-parallel changeover switch control unit 50B monitors the input voltage Vin, which is the series-parallel changeover voltage, and outputs the control signal S1.

The series-parallel switching timing control unit 5B includes two inverters 51B and 52B controlled by the control signal (S1) generated by the series-parallel switching switch control unit 50B.

The inverter 51B is composed of a depth region transistor Tr1 and an Nch transistor Tr2. The control signal φ1 from the inverter 51B is taken out at the terminal 53.

The series-parallel changeover switch control unit 50B and the inverter 51B constitute a hysteresis generation circuit H.

The inverter 52B is composed of a depth region transistor Tr3 and an Nch transistor Tr4. The control signal φ2 from the inverter 52B is taken out at the terminal 54.

The depth region transistors Tr1 and Tr3 function as the constant current sources IC1 and IC2 in FIG. The Nch transistors Tr2 and Tr4 function as switches Sw4 and Sw5 in FIG.

The parallel / parallel switching timing control unit 5B outputs an H level control signal φ1 and an L level control signal φ2 so that a plurality of capacitors C1 and C2 are connected in series during the storage period.

Then, when the input voltage Vin reaches a predetermined first voltage, the L level control signal φ1 and the H level control signal φ2 are output so that the plurality of capacitors C1 and C2 are connected in parallel.

After that, when the voltage Vin drops due to the use of electric power by the load circuit and becomes smaller than the predetermined second voltage, the H level control signals φ1 and the L level are controlled so that a plurality of capacitors C1 and C2 are connected in series. The signal φ2 is output.

Further, the parallel / parallel changeover switch unit 6 is formed of a Pch transistor Tr6, an Nch transistor Tr7, and analog switches Tr8 and Tr9.

In the parallel / parallel changeover switch unit 6, the Pch transistor Tr6 corresponds to the switch Sw1 of FIGS. 6 and 7, the Nch transistor Tr7 corresponds to the switch Sw3, and the switch Sw2 is an analog switch composed of two transistors Tr8 and Tr9. It is configured.

By configuring the parallel / parallel changeover switch unit 6 and the output switch unit 8 with a transistor which is an analog switch, voltage loss (potential difference) does not occur. For comparison, configuring a switch with diodes causes voltage loss. Therefore, in the present invention, it is possible to operate the switch without a potential difference.

Although not shown in FIG. 1, the power storage device 1 may include an output switch unit 8 that supplies electric power to the load circuit when connected in parallel. The output switch unit 8 is formed of an analog switch of two transistors Tr10 and Tr11.

In the power storage device 1 of the present invention, since a high resistance or constant current transistor having a high resistance is used, the series-parallel switching timing control unit 5B has a high impedance (high impedance).

Therefore, the power storage device 1 can be driven with a current (for example, 60 nA) lower than the high voltage and low current (for example, 400 V, 6 μA) generated power generated from the power generation element.

Further, in the configuration of FIG. 10, the total impedance of the elements constituting the timing control unit 5B, the parallel / parallel changeover switch unit 6, and the output switch unit 8 can be made higher than the internal impedance of the power generation element 2. As a result, the drive power consumption required for direct / parallel switching of the power generation device can be suppressed, and the energy storage efficiency can be improved.

Since the elements constituting the parallel / parallel changeover switch unit 6 and the output switch unit 8 are composed of MOS transistors, the series / parallel changeover switch unit 6 and the output switch unit 8 are controlled by the series / parallel changeover timing control unit 5B. The power consumed is only the MOS transistor gate drive power when the switch unit is on and off, and the energy storage efficiency can be improved.

Further, the impedance of the power storage device 1 at the time of storage is higher than the impedance of the power storage device 1 at the time of use. Therefore, the power storage device 1 can store power at a high voltage and a low current, and can improve the energy storage efficiency. Further, the output voltage of the power storage device 1 is, for example, 3V at the time of use, and it is possible to drive an electronic device such as a CPU that requires power consumption of several mA.

In addition, although the inverters 51B and 52B composed of the depth region transistor and the Nch transistor have a two-stage configuration in FIG. 10, the number of stages of the same inverter may be increased if gain is required.

In that case, the timing of the signal changes of the control signals φ1 and φ2 of the inverters 51B and 52B is matched with the switch switching timing of the parallel / parallel switching switch unit 6.

Here, FIG. 11 shows the flow of current in the power storage device 1 of FIG. In FIG. 11, (a) shows a state in which capacitors are connected in series and is stored, and (b) shows a state in which capacitors are connected in parallel and is in use of electric power.

Since the control signal φ1 is input to the gate of the Pch transistor Tr6 constituting the switch Sw1, the control signal φ1 is L, that is, turned on at the time of discharging.

Since the control signal φ2 is input to the gate of the Nch transistor Tr7 constituting the switch Sw3, the control signal φ2 is turned on when H, that is, when discharged.

A control signal φ2 is input to the gate of the Pch transistor Tr8 constituting the switch Sw2, and a control signal φ2 is input to the gate of the Nch transistor Tr9. Therefore, the switch Sw2 is turned on when the control signal φ2 is L and the control signal φ1 is H, that is, when electricity is stored.

Further, in the switch Sw4 of the output switch unit 8, the control signal φ1 is input to the gate of the Pch transistor Tr10, and the control signal φ2 is input to the gate of the Nch transistor Tr11. Therefore, the switch Sw4 is turned on when the control signal φ1 is L and the control signal φ2 is H, that is, when discharging and supplying an output voltage to the load circuit 3.

A current flows through the switches Sw1, Sw2, Sw3 included in the series-parallel changeover switch unit 6 and the switch Sw4 of the output switch unit 8 to change the state of the switch only when the series-parallel changeover is performed. Therefore, it is possible to reduce the current consumption during storage and use (discharge).

FIG. 12 is a diagram illustrating an embodiment based on a specific circuit diagram of the power storage system 100 of FIG.

The rectifier circuit 4 is composed of a diode bridge composed of four diodes D1, D2, D3, and D4. The rectifier circuit 4 full-wave rectifies the AC power output from the power generation element 2.

The rectified power is stored in a plurality of series-connected capacitors C1 and C2 in the power storage device 1, and when a constant voltage is reached, power is supplied to the load circuit 3 with the plurality of capacitors C1 and C2 connected in parallel. ..

<IC conversion>
FIG. 13 is a schematic diagram showing a configuration example in which a function linked to a communication module mounted on a microcomputer is added in a power storage system.

In this embodiment, the load circuit 3 includes a communication module 31 and a sensor 32.

Further, in the power storage device 1C of FIG. 13, the functions of the series-parallel switching timing control unit 5, the series-parallel switching switch unit 6, and the output switch unit 8 are integrated as the series-parallel switching IC 9.

In the present embodiment, a function of controlling the parallel / parallel switching timing by linking with the communication module 31 mounted on the microcomputer is added to the linear / parallel switching IC 9.

In this power storage system 100C, electric power is supplied to the communication module 31 and the sensor 32 by the output voltage Vout of the parallel / parallel switching IC 9.

When the connections of the capacitors C1 and C2 are in the parallel state, the series-parallel switching IC9 of the power storage device 1C outputs a signal _RST indicating that the communication module 31 is in the parallel state to the microcomputer mounted on the communication module 31 to output the communication module 31. Tell that power can be supplied to.

After the system operation of the communication module 31 is completed, the communication module 31 instructs the series-parallel switching IC 9 to output a signal _SEND indicating that the voltage is no longer required to the microcomputer and shift to charging at a predetermined timing. Then, in the power storage device 1, the capacitors C1 and C2 are switched to the series connection state to start charging. The signal _SEND is a signal that changes the connection of the capacitors C1 and C2 from parallel to series by controlling the voltage at the gate of the transistor Tr5 of the parallel / parallel switching timing control unit 5B in FIG.

In the power storage system 100C having this configuration, the power storage device 1C can improve the power storage efficiency by cooperating with the CPU on the load side.

In addition, this system can also utilize the result of signal processing of the signal from the sensor 32 by the microcomputer mounted on the communication module 31 as an IoT edge terminal through a communication means such as wireless.

<Timing chart>
Next, the connection switching operation in the power storage device will be described with reference to FIG. FIG. 14 is a timing chart of the series-parallel switching operation in the power storage device 1.

As shown in FIG. 12, the electric power generated by the power generation element 2 is rectified by the rectifier circuit 4, and the electric power is supplied to the power storage device 1.

At time T0, the capacitors C1 and C2 are not stored.

When the power rectified from time T1 starts to be supplied to the power storage device 1, since the series-parallel switching timing control unit 5B has a high impedance configuration, the circuit is started by the power output from the power generation element 2 with high impedance. Control signals φ1 and φ2 are generated.

When the storage is started, the control signal φ1 becomes HIGH, the control signal φ2 becomes LOW level, the series-parallel switching switch unit 6 operates, the switches Sw1 and Sw3 are OFF, the switch Sw2 is ON, and the capacitor C1 of the storage unit 7 is turned on. , C2 are connected in series.

When the capacitors C1 and C2 are in series and the input voltage Vin, which is the power from the power generation element 2, reaches 10V (first voltage), the series-parallel changeover switch control unit 50 operates at the timing of T2, and the control signal φ1 Is switched to LOW, and the control signal φ2 is switched to HIGH. In response to this, the series-parallel switching switch unit 6 operates, the switch Sw2 is turned off, the switches Sw1 and Sw3 are turned on, and the capacitors C1 and C2 of the storage unit 7 are connected in parallel. When the capacitors _C1 and _C2 of the storage unit 7 are switched from the series connection to the parallel connection, the voltage changes from the state of (Vin = VC1 + VC2) to the state of (Vin = _VC1 = _VC2 ), so that the storage voltage ( Input voltage Vin) is reduced by half (10V⇒5V).

When the load circuit 3 is driven at the timing of T3, electric power (output voltage Vout) is supplied to the load circuit 3 and the input voltage Vin also decreases.

Here, it is assumed that there is no power supply from the power generation element 2 from time T2 to T4.

When the input voltage Vin drops and reaches 2V (second voltage), the control signal φ1 becomes HIGH, the control signal φ2 becomes LOW, the switches Sw1 and Sw3 turn OFF, and the switch Sw2 turns ON at the timing of T4. , Capacitors C1 and C2 of the power storage unit 7 are connected in series to store electric power from the power generation element 2.

After that, when the input voltage Vin rises and reaches 10V (first voltage), the capacitors C1 and C2 are connected in parallel.

The above operation is continued.

Here, the timing of T2 is 10V and the timing of T4 is 2V, but an arbitrary voltage can be set by changing the resistance values of the resistors R3, R4, and R5 of the series-parallel changeover switch control unit 50.

It is also possible to continue the power supply from the power generation element 2 in the parallel state. In that case, the voltage decrease of the input voltage Vin from T3 to T4 may be gradual or may increase.

Next, the operation in the power storage system 100C linked with the communication module of FIG. 13 will be described using the right side of FIG. Even in the configuration of FIG. 13, the operations from T0 to T5 are the same.

At the timing of time T6, the series-parallel switching IC 9 outputs a signal S _ST indicating that the communication module 31 is in a parallel state to the microcomputer mounted on the communication module 31 to inform the communication module 31 that power can be supplied. In FIG. 14, during the periods T3 to T4 and T6 to T7, the load circuit operating period (discharge period, system operating period) in which the power storage device 1 supplies power to the communication module 31 in synchronization with the communication module 31. ).

After the system operation of the communication module 31 is completed at time T7, when the signal _SEND is output from the communication module 31 to the series-parallel switching IC9 at the timing of T8, the capacitors C1 and C2 are switched to the series connection state for charging. Let's get started.

When the power storage device 1 operates in cooperation with the communication module 31, the power supply is stopped during the discharge period when the voltage drops to 2 V or the signal _SEND is output, whichever comes first. In FIG. 14, since the signal _SEND was output before the voltage dropped to 2V, the power supply was stopped at that point, the connection states of the capacitors C1 and C2 were switched in series, and the operation was shifted to the storage operation. ..

<Stored energy>
Here, the energy stored in the capacitor will be described.

The energy W (J) that can be stored in the capacitor can be expressed by the following equation.

また、コンデンサをｎ個、直列接続すると、容量(Csn)は、

Also, if n capacitors are connected in series, the capacitance (Csn) will be

コンデンサをｎ個、並列接続すると、容量(Cpn)は、

When n capacitors are connected in parallel, the capacitance (Cpn) will be

コンデンサｎ個直列接続で蓄電できるエネルギー（Ws）は、

The energy (Ws) that can be stored by connecting n capacitors in series is

コンデンサｎ個並列接続で蓄電できるエネルギー（Wp）は、

The energy (Wp) that can be stored by connecting n capacitors in parallel is

例えば具体的に、n=2、C=1(μF)、V=5（V）とすると
コンデンサ２個直列接続で蓄電できるエネルギー（Ws）は、

For example, specifically, if n = 2, C = 1 (μF), and V = 5 (V), the energy (Ws) that can be stored by connecting two capacitors in series is

コンデンサ２個並列接続で蓄電できるエネルギー（Wp）は、

The energy (Wp) that can be stored by connecting two capacitors in parallel is

As described above, Ws = Wp, and the same amount of energy can be stored in the capacitor regardless of whether n capacitors of the same capacity are stored in series or in parallel.
In order to store n in series, it is necessary to store in a high voltage n × V (V) state. On the other hand, stored energy is required to be supplied to electronic devices that drive CPUs and connect sensors and the like in systems such as the IoT (Internet of Things). These devices are required to be driven by about 1 to 3 lithium batteries, that is, a voltage of about 3 to 10 V and a current of about several μA to several mA.

Here, by connecting n capacitors of the same capacity C in series and storing them in a high impedance state and switching those capacitors from series connection to parallel connection, the energy stored in the capacitors is maintained at a low voltage. It can drive IoT systems etc. in a low impedance state.

Assuming that the resistance attached to the circuit is R, the impedance (Z) is defined by the following equation.

コンデンサをｎ個直列にした場合の回路のインピーダンス（Zsn）は、（式２）で示したようにCsn＝C/nとなるので、下記（式９）のように示される。

The impedance (Zsn) of the circuit when n capacitors are connected in series is Csn = C / n as shown in (Equation 2), and is therefore shown as shown in (Equation 9) below.

コンデンサをｎ個並列にした場合の回路のインピーダンス（Zpn）は、（式３）で示したようにCpn＝n×Cとなるので、下記（式１０）のように示される。

The impedance (Zpn) of the circuit when n capacitors are connected in parallel is Cpn = n × C as shown in (Equation 3), and is therefore shown as shown in (Equation 10) below.

となる。ここで、回路上に付く抵抗Rを小さくすると、直列時のインピーダンスZsn（式９）が高く、並列時のインピーダンスZpn（式１０）が低いことがわかる。

Will be. Here, it can be seen that when the resistance R attached to the circuit is reduced, the impedance Zsn (Equation 9) in series is high and the impedance Zpn (Equation 10) in parallel is low.

As described above, by performing the series-parallel switching of the capacitor, energy is stored from (Equation 4) and (Equation 9) with high voltage at high voltage n × V (V) at the time of energy storage, and (Equation) at the time of energy supply. From 5) and (Equation 10), it can be seen that power can be efficiently supplied to the system equipment at a low voltage V (V).

High voltage of several tens of volts to several hundreds of volts is generated in power generation by electrostatic induction of a piezoelectric element or power generation rubber. Further, the output current is a low current in units of nA to μA, and can be regarded as a low current power supply having a high output impedance. Therefore, a circuit that efficiently converts the energy stored in the capacitor at a high voltage by a piezoelectric element or electrostatic induction into the energy supplied to a system driven by a current of several μA to several mA at a voltage of about 3 to 10 V. Is required.

Here, as a comparative example, FIG. 15 shows a diagram in which the capacitance of the capacitor is fixed, and FIG. 16 shows a diagram in which the capacitance of the capacitor is switched in series and in parallel as in the present invention.

Specifically, FIG. 15 (a) shows a circuit diagram in which the capacity of the capacitor is fixed, and FIG. 15 (b) shows the storage current and the storage voltage in the state of FIG. 15 (a), and between the capacitor terminals at the time of discharge. It is a figure which shows the transition of a voltage.

FIG. 15 shows an example in which one capacitor having a capacity of 0.25 μF (microfarad) is used and operated with a capacity of 0.25 μF both during charging and discharging.

Generally, the drive voltage of the CPU operation, the sensor drive, and the wireless transmission IC is about 2 to 5 V. As shown in FIG. 15B, in this configuration example, since the capacity stored in the capacitor at the time of discharge is small, the voltage value drops sharply, and the time during which the voltage value is in the range of 2 to 4.5V is It is 20 ms. Therefore, power can be used only for 20 ms.

On the other hand, FIG. 16 (a) shows a circuit diagram for switching the series-parallel of the capacitor, and FIG. 16 (b) shows the storage current and the storage voltage in the state of FIG. 16 (a), and the capacitor terminal at the time of discharge. The figure which shows the transition of the inter-voltage is shown.

FIG. 16 shows an example in which two capacitors having a capacity of 0.5 μF are used in a series state during charging and operated at a capacity of 0.25 μF, and in a parallel state during discharging and operated at a capacity of 1.0 μF. There is.

As shown in FIG. 16B, in this configuration example, the voltage value is halved at the time of switching by switching the capacitor from the series connection to the parallel connection at the time of discharging, but after that, discharging using a capacitor having a large capacity is performed. Therefore, the voltage value gradually drops, so that the time during which the voltage value is in the range of 2 to 4.5 V is 84 ms. Compared with FIG. 15B, the capacity of the capacitor at the time of charging is the same, but the switching of FIG. 16 increases the time during which the electric power can be used at the time of discharging more than four times.

As shown in FIG. 16, in the power storage system of the present invention, by switching between series connection and parallel connection of capacitors, energy is stored by impedance matching with high voltage and high impedance at the time of power storage. On the other hand, at the time of discharge, energy can be supplied by impedance matching with low impedance at a voltage required for an IoT system or the like.

<Example of installing a large number of capacitors in a power storage device>
The above has described the configuration in which the power storage device 1 includes two capacitors, but the number of the plurality of capacitors is not limited to two. FIG. 17 is a diagram illustrating an embodiment of a circuit in which four capacitors are connected in series.

FIG. 17 is an internal block diagram of the 4 series / parallel switching IC 90.

The parallel / parallel changeover switch unit 60 corresponds to the series / parallel changeover switch unit 6 in FIG. 10, and is composed of switch groups 61, 62, and 63. The switch groups 61 and 63 are turned on when the capacitors C1, C2, C3 and C4 are connected in parallel, and turned off when the capacitors C1, C2, C3 and C4 are connected in series. The switch group 62 is turned on when the capacitors C1, C2, C3, and C4 are connected in series, and turned off when the capacitors C1, C2, C3, and C4 are connected in parallel.

The switch 80 corresponds to the output switch unit 8.

The series-parallel switching timing control unit 5D is the same as the series-parallel switching timing control unit 5B for switching the two capacitors in FIG. 10, but when the capacitors are connected in series in multiple stages by cascode connection as shown in FIG. A switching circuit 55 for switching between the master side and the slave side is mounted.

FIG. 18 is a diagram illustrating an embodiment of a capacitor multi-stage connection circuit.

In FIG. 18, the capacitor multi-stage connection circuit 90E is composed of a 4 series / parallel switching master IC 91 and a 4 series / parallel switching slave ICs 92, 93, 94, 95.

By mounting the master / slave switching circuit 55 of FIG. 17 on the master IC 91, the four ICs 92, 93, 94, and 95 are configured to be cascode-connected as slave ICs, and each output voltage Vout output is switched by 4 series-parallel switching. It can be connected to the master IC 91 and multi-stage connection is possible.

In this way, when connecting in multiple stages, the cascode connection is controlled in multiple stages by the master-slave method. By connecting in this way, it is possible to connect more multi-stage capacitors, which makes it possible to further improve efficiency.

In the above embodiment, the power storage device of the present invention can detect the switching voltage at high voltage and low current, operate at high voltage and low current to switch the parallel connection, and can store power with high efficiency. Is.

In the above embodiment, the series-parallel switching timing control unit 5 is provided with the hysteresis generation circuit H internally to provide history for the control signal φ1, but the series-parallel switching timing control unit 5 provides hysteresis. If it can be provided, the hysteresis generation circuit may exist in addition to the series-parallel switching timing control unit 5.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and is within the scope of the gist of the embodiment of the present invention described in the claims. Various modifications and changes are possible.

1,1C Power storage device 2 Power generation element 3 Load circuit 4 Rectifier circuit (rectifier)
5,5D parallel / parallel switching timing control unit (timing control unit)
6,60 Parallel / parallel changeover switch unit 7 Power storage unit 8 Output switch unit (output unit)
9,90,90E series / parallel switching IC
31 Communication module 32 Sensor 50 Series-parallel switching control unit (voltage monitor circuit)
51, 52 Inverter 61, 62, 63 Switch group 91 Master IC
92,93,94,95 Slave IC
100 Power storage system C1, C2, C3, C4 Capacitor (power storage device)
H Hysteresis generation circuit Tr1, Tr3 Diplomat transistor Tr2, Tr4 Nch transistor

Japanese Unexamined Patent Publication No. 2013-236506

Claims (15)

A power storage device connected to a power generation element and a load circuit.
A power storage unit with multiple power storage devices and
A timing control unit that controls the series-parallel switching of the plurality of power storage devices, and
It has a series-to-parallel switching switch unit that is controlled by the timing control unit and switches the series-parallel switching of the plurality of storage devices.
The timing control unit provides hysteresis by including a hysteresis generation circuit to control the switching timing.
The hysteresis generation circuit includes a transistor, a resistor, and an inverter.
A power storage device characterized by this. The power storage device according to claim 1 , wherein the inverter includes a resistor and a series circuit of N-channel transistors. The power storage device according to claim 1 , wherein the inverter includes a series circuit of a depth region transistor and an N channel transistor. The power storage device according to any one of claims 1 to 3 , wherein the parallel / parallel changeover switch unit has an analog switch. The power storage device has an output unit that outputs an output voltage to the load circuit.
The power storage according to any one of claims 1 to 4 , wherein the total impedance of the timing control unit, the parallel / parallel changeover switch unit, and the output unit is equal to or higher than the internal impedance of the power generation element. Device. The timing control unit has a voltage monitor circuit that monitors the input voltage to the power storage device.
When the timing control unit controls the parallel / parallel changeover switch unit, the plurality of power storage devices are connected in series during the power storage operation, and the monitored input voltage reaches the first voltage. Connect in parallel
During the discharge operation, when the monitored input voltage reaches a second voltage lower than the first voltage, the plurality of power storage devices are connected in series.
The power storage device according to any one of claims 1 to 5 , wherein the power storage device is characterized by the above. The series-to-parallel changeover switch unit is a plurality of series-to-parallel changeover slave ICs having a series-to-parallel changeover switch function.
The timing control unit is a series-parallel switching master IC to which the output voltages of the plurality of series-parallel switching slave ICs are connected.
The plurality of series-parallel switching slave ICs are cascode-connected.
The series-parallel switching master IC controls the plurality of series-parallel switching slave ICs in multiple stages by a master-slave method.
The power storage device according to any one of claims 1 to 6. Power generation elements that generate electric power and
The rectifying unit connected to the power generation element and
The power storage device according to any one of claims 1 to 7, which is connected to the subsequent stage of the rectifying unit.
A power storage system characterized by having a load circuit. The power storage system according to claim 8 , wherein a signal is sent from the load circuit to the power storage device. The power storage system according to claim 9 , wherein the signal is a signal that changes a voltage with respect to the input of the hysteresis of the timing control unit. The power storage system according to any one of claims 8 to 10 , wherein the amount of power generated by the power generation element is a power generation voltage of 10 V to 1000 V, and the power generation current is 50 nA to 100 μA. The power generation element is a power generation element that generates power by friction due to deformation and vibration.
The power storage system according to any one of claims 8 to 11 . The power generation element is a power generation rubber that generates power by deformation and vibration.
The power storage system according to any one of claims 8 to 11 . The power storage system according to any one of claims 8 to 11 , wherein the power generation element is a power generation element that generates power by pressure due to deformation and vibration. The power storage system according to any one of claims 8 to 11 , wherein the power generation element is a power generation element that generates power by electrostatic induction due to deformation and vibration.

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