JP2015154627A - Voltage step-down circuit and voltage step-down and charge circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage step-down and charge circuit that can minimize the number of capacitors of a voltage step-down circuit without simply preparing two systems of circuits that perform charging by switching connection of capacitors in series or in parallel in order to constantly feed currents from high voltage power supply to low voltage power storage means.SOLUTION: A voltage step-down and charge circuit comprises power generating means 40, power storing means 10 and voltage step-down means 10 that lowers output of the power generating means by multiple levels to charge the power storing means 20. The voltage step-down means is constituted by connecting a plurality of voltage step-down stages vertically, and each voltage step-down stage is constituted of two capacitor pairs comprising capacitors whose step-down magnification is lesser by one than the step-down magnification of each step-down stage. Further in each stepping-down stage capacitors in either one of the capacitor pairs are connected in series and capacitors in the other capacitor pair are connected in parallel, and connection states of both capacitor pairs are switched alternately at timing with equal time width.

Description

  The present invention relates to a structure for charging power obtained from a high-voltage power source, and more particularly to its circuit configuration.

  Conventionally, in the field of electronic watches and energy harvesting, a step-down charging circuit that can charge a storage means such as a secondary battery of about several volts or an electric double layer capacitor from a power source that generates a relatively high voltage Has been proposed.

  An example of a conventional step-down charging circuit is shown in FIG. This is an example in which a primary battery is used as a power source and the output voltage is stepped down to drive a load.

  The step-down circuit 92 in this example is a voltage dividing circuit as shown in FIG. 6, and the connection state of the two step-down capacitors 92A and 92B is shown in the series state (state a) in FIG. 6 (a) and FIG. 6 (b). By alternately switching to the parallel state (state b), a voltage half the input voltage is generated (double step-down), and the load circuit 91 is driven with the obtained low voltage. The load circuit 91 is obtained by connecting a low power consumption integrated circuit 91A and a stabilization capacitor 91B in parallel. By the operation of the step-down circuit 92, it is possible to generate a voltage ½ of the battery voltage with low loss and supply power to the load circuit 91. Note that such a step-down circuit 92 is generally operated with a clock having a duty cycle of 50% so that the time ratio between the state a and the state b is 1: 1.

JP 59-141089 (2-3 pages, FIGS. 3-4)

  The conventional step-down circuit shown in FIG. 6 is sufficient for use in applying a low voltage to such a relatively light load, but the purpose is to extract power from a power source such as a generator instead of a power source such as a battery. The problem of poor efficiency arises. This is because, in the state of FIG. 6B, an appropriate load is not connected to the power generation means 40, and an invalid time during which the power generated by the power generation means 40 cannot be extracted occurs. This invalid time is half of the operation cycle, and the power extraction efficiency from the power generation means 40 is only 50% at the maximum.

  In the prior art, there is no disclosure that suggests a method for extracting the generated power with maximum efficiency while reducing the voltage from the power generation means 40 that generates a high voltage. However, in order to eliminate the time during which the generated power cannot be extracted, another step-down circuit 92 is provided. A configuration in which a system is prepared and operated in a complementary manner can be easily considered. In other words, when one of the two step-down circuits is in state a, the other is set to state b, and when one step-down circuit is in state b, the other is set to operate in state a. In this way, the reduction in efficiency due to the invalid time is eliminated.

  However, if two systems of the step-down circuit 92 are simply prepared, the number of capacitors used in the step-down circuit 92 is simply doubled. Since the capacitor of the step-down circuit 92 has a capacity that cannot be built in the integrated circuit, it is necessary to externally attach a chip component capacitor. If the number of capacitors increases, problems such as an increase in cost and mounting area of the chip component itself occur.

  The step-down charging circuit according to the present invention employs the following configuration.

  That is, a plurality of step-down stages each having a plurality of capacitors and a switch circuit that switches a connection state of the plurality of capacitors are provided, and the plurality of step-down stages are connected in cascade. The capacitor set includes two capacitor sets each having a smaller number of capacitors, and the capacitor set connected to the input side of the step-down stage is equal to the capacitor set connected to the output side. It is characterized by being switched alternately by width.

  In the present application, it is possible to realize a step-down circuit that can extract power with maximum efficiency to a connected load as viewed from the power generation means with a minimum number of capacitors.

  Therefore, according to the present application, it is possible to realize a function of taking out electric power from a high-voltage power source with high efficiency and charging the power storage means with low loss in a small space. In particular, even when using an electrostatic induction generator using an electret element that has a high generator voltage but high output impedance and high generated power, power can be extracted from the generator with high efficiency and at a high magnification. Therefore, it is possible to provide a step-down charging circuit that can be reduced in size even when a step-down voltage is required.

1 is a circuit diagram showing a step-down charging circuit configuration including step-down means according to a first embodiment of the present invention. It is a circuit diagram showing a circuit state at the time of step-down operation of the step-down means. 1 is a circuit diagram showing an overall configuration of a step-down charging circuit of the present invention. FIG. 6 is a waveform diagram showing timing signal waveforms for driving a step-down circuit. It is the circuit diagram which showed the structure of the pressure | voltage fall means of the 2nd Embodiment of this invention. It is a circuit diagram showing a circuit state at the time of step-down operation of a conventional step-down circuit. It is the graph which showed the number of capacitors required by the pressure | voltage fall means of this invention.

  Hereinafter, an embodiment for realizing such a step-down charging circuit will be described in detail with reference to the drawings. First, the configuration and operation of the first embodiment of the present invention will be described with reference to FIGS. Thereafter, the configuration and operation of the second embodiment of the present invention will be described with reference to FIG.

[Overview of First Embodiment: FIG. 3]
The first embodiment will be described with reference to FIG.

  The step-down charging circuit according to the first embodiment is a suitable example in the case of a generator in which the power generation voltage waveform of the power generation means does not change in the voltage direction. As an example, an electrostatic induction generator that rotates at a constant speed and has a relatively high output resistance corresponds to this.

  In this example, the output of the power generation means is full-wave rectified by the rectification means, and the step-down magnification is set so that the power can be extracted most with respect to the voltage amplitude of the rectification output. As will be described in detail later, when the step-down circuit performs a step-down operation, the power generation means can regard the portion after the step-down circuit as a high-voltage constant voltage load, thereby realizing high power extraction efficiency.

[Description of Configuration of First Embodiment: FIGS. 1-2]
The configuration of the first embodiment will be described.

  The step-down charging circuit of the present invention includes a power generation unit 40, a rectification unit 50, a step-down unit 100, and a power storage unit 20.

  The step-down unit 100 includes a step-down circuit 10 and a timing generation circuit 13. The output of the step-down unit 100 is connected to a power storage unit 20 which is a secondary battery having a terminal voltage of 2V. When the step-down circuit 10 performs a step-down operation, the step-down unit 100 can be regarded as a high voltage constant voltage load.

  The power generation means 40 is an AC generator that outputs a high voltage alternating voltage. The rectifier 50, which is a so-called diode bridge, is configured to be capable of full-wave rectifying the output of the power generator 40 and applying the rectified output to the step-down device 100. The step-down means 100 can be stored in the power storage means 20 that is a secondary battery via the step-down circuit 10 that converts the voltage of the rectified output. The power generation means 40 is assumed to be an AC generator that can be expressed as a simple model in which a voltage source 41 having a generated voltage amplitude (single amplitude) V0 of 30 V and an internal resistance 42 having an output resistance value R are connected in series.

  The step-down circuit 10 is a circuit block that can convert an input voltage to a substantially lower voltage by switching the connection state of the capacitor between series and parallel. The configuration of the step-down circuit 10 will be described in detail next.

[Configuration Description of Step-Down Circuit: FIGS. 1 to 4]
The configuration of the step-down circuit 10 will be described with reference to FIG. Here, the step-down circuit 10 is configured to perform a 6-fold step-down operation. Note that the timing necessary for the operation of the step-down circuit 10 is obtained from the timing generation circuit 13.

  The step-down circuit 10 has a configuration in which a first step-down stage 11 and a second step-down stage 12 are connected in cascade as shown in FIG. In other words, the first step-down stage 11 that doubles the output of the rectifying unit 50 and the second step-down stage 12 that triples the output of the first step-down stage 11 and outputs it to the power storage unit 20 are configured. . Each step-down stage includes a plurality of capacitors, and a connection state between the capacitors is switched by a so-called analog switch configured by combining MOS transistors.

  The first step-down stage 11 includes two capacitors, a capacitor 101 and a capacitor 102, in order to perform a step-down operation equivalent to twice in this portion. The first step-down stage 11 operates to serialize the capacitor 101 and the capacitor 102 by alternately changing the order viewed from the rectifying means 50.

  In order to enable this switching operation, the switches 102 to 105 are connected to both ends of the capacitor 101, and the switches 106 to 109 are connected to both ends of the capacitor 102 and the ground potential.

  In the first step-down stage 11, the rectifying means 50 side is the input side, and the subsequent second step-down stage 12 side is the output side.

  The second step-down stage 12 includes a capacitor 201A and a capacitor 201B as the capacitor set 201 in order to perform a step-down operation equivalent to three times in this portion. The capacitor set 202 includes a capacitor 202A and a capacitor 202B.

The second step-down stage 12 operates to serialize the capacitor set 201 and the capacitor set 202 by alternately changing the order viewed from the first step-down stage 11.
At the same time, an operation is performed in which the positive electrode of the capacitor set on the side close to the ground potential among the capacitor set of the second step-down stage 12 is connected to the positive electrode of the power storage means 20.
Then, all the capacitors of the capacitor set 201 are set in series or parallel, and all the capacitors of the capacitor set 202 are set in the opposite parallel state or series.

  To enable this switching operation, the switches 203 to 208 are connected to both ends of the capacitors 201A and 201B and the ground potential, and the switches 213 to 218 are connected to both ends of the capacitors 202A and 202B and the ground potential.

  In addition, the negative terminal of the capacitor set on the side far from the ground potential in the capacitor set of the second step-down stage 12 also operates to connect to the positive electrode of the power storage means 20.

  The switch 209 and the switch 219 are connected between the second step-down stage 12 and the power storage means 20 so that this connection operation is possible.

  In the second step-down stage 12, the first step-down stage 11 side is the input side, and the subsequent power storage means 20 side is the output side.

These switches are controlled by a first timing signal S31 and a second timing signal S32 described later. That is, the conduction of the switches 102, 104, 107, 109, 204, 207, 209, 213, 215, 216, and 218 is controlled by the first timing signal S31,
The switches 103, 105, 106, 108, 203, 205, 206, 208, 214, 217, and 219 are conductively controlled by the second timing signal S32.

  Note that the number of capacitors in the capacitor set 101 and the capacitor set 102 is 1 which is obtained by subtracting 1 from 2 which is the step-down magnification of the first step-down stage 11.

  The number of capacitors in the capacitor set 201 and the capacitor set 202 is 2 which is obtained by subtracting 1 from 3 which is the step-down magnification of the second step-down stage 12.

  In the first step-down stage 11, each of the capacitor 101 and the capacitor 102 corresponds to a capacitor set, but the number of capacitors is one.

  In addition, the value of the step-down magnification at each step-down stage corresponds to an element obtained by prime factorization of the value of the step-down magnification of the entire step-down circuit 10.

  The step-down magnification in this example is 6 times. The factoring of this value 6 is 6 = 2 × 3, which is decomposed into two elements 2 and 3. Corresponding to this, the step-down circuit 10 is composed of two step-down stages having step-down magnifications of 2 times and 3 times.

  Here, the element of 2 corresponds to the value of the step-down magnification of the first step-down stage 11, and the element of 3 corresponds to the value of the step-down magnification of the second step-down stage 12.

  FIG. 3 shows a state when the step-down circuit 10 performs the above-described 6-fold step-down operation.

  In the step-down circuit 10, as shown in FIG. 3, the first step-down stage 11 performs a double step-down operation, and the second step-down stage 12 performs a triple step-down operation. By the operation of these two step-down stages, the step-down circuit 10 performs a step-down operation equivalent to 6 times the multiplication of these values.

In the state a shown in FIG.
In the first step-down stage 11, the capacitor 101 is connected in series in the order of the higher potential side and the capacitor 102 in the order of the ground potential side. The point where the negative electrode of the capacitor 101 and the positive electrode of the capacitor 102 are connected becomes the output of the first step-down stage 11, and charges are sent to the second step-down stage 12.

  In the second step-down stage 12, the capacitor 201 </ b> A, the capacitor 201 </ b> B, and the power storage unit 20 are connected in series with respect to the output of the first step-down stage 11. Further, the capacitor 202A and the capacitor 202B are connected to the power storage means 20 in parallel.

  That is, in this state a, the capacitor 101 is connected to the input side of the first step-down stage 11, and 102 is connected to the output side. In the second step-down stage 12, capacitors 201A and 201B (capacitor set 201) connected in series are connected to the input side, and capacitors 202A and 202B (capacitor set 202) connected in parallel are connected to the output side. ).

In the state b shown in FIG.
In the first step-down stage 11, the capacitor 102 is connected in series in the order of the higher potential side and the capacitor 101 in the order of the ground potential side. The point where the negative electrode of the capacitor 102 and the positive electrode of the capacitor 101 are connected is the output of the first step-down stage 11, and charges are sent to the second step-down stage 12.

  In the second step-down stage 12, the capacitor 202A, the capacitor 202B, and the power storage means 20 are connected in series with respect to the output of the first step-down stage 11. Furthermore, the capacitor 201 </ b> A and the capacitor 201 </ b> B are connected to the power storage means 20 in parallel.

  That is, in this state b, the capacitor 102 is connected to the input side of the first step-down stage 11, and the capacitor 101 is connected to the output side. In the second step-down stage 12, capacitors 202A and 202B (capacitor set 202) connected in series are connected to the input side, and capacitors 201A and 201B (capacitor set 201) connected in parallel are connected to the output side. ).

  The operation clock for switching between the state a and the state b is a two-phase clock signal as shown in FIG. The state a and the state b in FIG. 3 are switched alternately according to the first timing signal S31 and the second timing signal S32.

  In the period A in FIG. 4, that is, in the period in which the first timing signal S31 is at a high level, the state a in FIG. 3 is set. Further, during the period B, that is, the period when the second timing signal S32 is at the high level, the switching control is performed so as to be in the state b of FIG. Period A and period B are 50 milliseconds.

  The first timing signal S31, which is one of the clocks, and the second timing signal S32, which is the other, have a relationship that can be regarded as an inverted signal, but at the instant of switching, the switches that constitute each step-down stage are turned on simultaneously. Thus, a switching delay period D is provided so as not to short-circuit each capacitor. The period D can be set to a necessary minimum time width of about several nanometers to several tens of nanoseconds by a known delay time generation method.

[Description of operation of step-down circuit: FIG. 3]
When the step-down circuit 10 performs a step-down operation according to the first timing signal S31 and the second timing signal S32, the capacitor that is charged from the output of the rectifying means 50 has a terminal voltage slightly increased by storing electric charge. When the capacitor is discharged, the electric charge stored in the capacitor is instantaneously sucked into the power storage means 20 and becomes equal to the terminal voltage of the power storage means 20. This is because the impedance of the power storage means 20 is low.

  Specifically, in the state a shown in FIG. 3A, the capacitor 101, the capacitor 201A, and the capacitor 201B are in a state of charging electric charge obtained from the power generation means 10, and the capacitor 102, the capacitor 202A, and the capacitor 202B are charged. Becomes a state in which the electric charge stored in the immediately preceding state (state b) is discharged to the power storage means 20 side.

In the state b shown in FIG. 3B, the capacitor 102, the capacitor 202A, and the capacitor 202B are charged with the electric charge obtained from the power generation means 10, and the capacitor 101, the capacitor 201A, and the capacitor 201B are immediately before. The electric charge stored in the state (state a) is discharged to the power storage means 20 side.
Therefore, the power storage means 20 is always in a charged state in both the state a and the state b.

  When the step-down circuit 10 operates in this way, the voltage between the terminals of each capacitor of the second step-down stage 12 is always substantially equal to the storage voltage VBT, and the voltage between the terminals of each capacitor of the first step-down stage 110A is the storage voltage VBT. As a result, the load voltage VL that is the input side voltage of the step-down circuit 10 is almost six times the storage voltage VBT.

  As described above, a voltage value obtained by multiplying the storage voltage VBT by the step-down magnification n appears on the input side of the step-down circuit 10. Since the voltage at the input side terminal of the step-down circuit 10 hardly changes even when the generated current flows, the step-down circuit 10 is excluded except for a very short period (period D in FIG. 4) in which the connection state of the step-down circuit 10 is switched. Always behaves as if it is a voltage source of n · VBT. The voltage value of the load that looks like this voltage source corresponds to the load voltage VL.

  In particular, by operating the two capacitor sets in the step-down stage in a complementary manner, the other capacitor set can be charged while the other capacitor set is in the discharged state. Therefore, a constant voltage load is always connected to the power generation means 40. In this state, the power generated by the power generation means 40 can be always taken out.

  Further, in this step-down operation, since all the capacitors in the step-down circuit 10 have only a slight voltage change in the terminal voltage even through the operation of transferring charges, loss due to charge transfer is suppressed, and as a result, In the step-down circuit 10, it is possible to transfer charges with little loss to the power storage means 20 in which the terminal voltage is lower than the input voltage.

  Therefore, by configuring the step-down circuit 10 in this way, it is possible to connect a load that can always be regarded as a constant voltage source without time when the power generation means 40 is unloaded, and step down the power generation output with low loss. As a result, the power storage means 20 can be charged with high efficiency.

[Description of Configuration of Second Embodiment: FIG. 5]
Next, the second embodiment will be briefly described. This is an example in which the step-down circuit 10 is stepped down eight times with respect to the power generation means 10 whose power generation voltage is 40 V higher than that of the above-described embodiment.

  A circuit diagram in which the step-down circuit portion is simplified is shown in FIG. The overall configuration of the step-down charging circuit in the second embodiment is the same as that of the first embodiment shown in FIG. 1, and the step-down circuit 10 in FIG. 1 may be replaced with the step-down circuit shown in FIG.

Although the step-down magnification is 8 times, the prime factorization of the value of 8 is 8 = 2 × 2 × 2, which is decomposed into the same three elements of 2. Corresponding to this, the step-down circuit 10 is composed of three step-down stages having the same double step-down magnification.

  That is, the step-down circuit 10 includes step-down stages 111, 112, and 113, which are connected in cascade. Each step-down stage has a double step-down function, and the same step-down stage as the first step-down stage 11 in the first embodiment is used for these step-down stages. As for the connection of the operation clock, the switching control of the capacitor of each step-down stage is performed by the first timing signal S31 and the second timing signal S32 similar to those of the first embodiment.

[Description of Operation of Second Embodiment]
The operation of the second embodiment will be briefly described.

  When the step-down circuit 10 performs a step-down operation according to the first timing signal S31 and the second timing signal S32, the voltage across the terminals of each capacitor of the third step-down stage 113 is always substantially equal to the stored voltage VBT, and the second step-down stage The voltage between terminals of each capacitor of 112 is always almost equal to twice the storage voltage VBT, and the voltage between terminals of each capacitor of the first step-down stage 111 is always substantially equal to four times the storage voltage VBT. The load voltage VL that is the input side voltage of the circuit 10 is approximately eight times the storage voltage VBT.

  Therefore, by controlling the step-down circuit 10 in this manner, it is possible to charge the power storage unit 20 with high efficiency while converting the output of the rectifying unit 50 into a voltage, as in the first embodiment.

  FIG. 7 shows a graph comparing the number of capacitors required in the step-down charging circuit according to the present invention with the number of capacitors conventionally required. As described above, the step-down magnification of the step-down stage corresponds to each factor obtained by factoring the entire step-down magnification value. Therefore, when the step-down magnification itself is a prime number (for example, 11 times step-down), Although the difference in the number of capacitors is small, it can be seen that when the value of the step-down magnification is an integer with a large divisor, a smaller number of capacitors is required compared to the conventional case, and thus the high effect of the present invention can be obtained. For example, in the case of 16 times step-down, in this application, the number of capacitors is half that of the conventional one.

  In the above-described embodiments, the step-down magnification that can be selected by the step-down circuit 10 is fixed, but this is not restrictive. By increasing the number of capacitors in the step-down circuit 10 or changing the connection state of the capacitors in a more complicated manner, the step-down magnification can be varied to increase the selection range, or to obtain an intermediate value. It is also possible to do. For example, the voltage is stepped down three times at the first stage of the step-down circuit 10, stepped down three times at the second stage, and then stepped down 9/2 times (4.5 times) by adding the third stage and boosting it twice. It is also possible.

  The number of step-down stages of the step-down circuit 10 is three, which is the number of elements obtained by factoring the step-down magnification, but is not limited to this. It is also possible to set the second step of the step-down stage in the first embodiment to a step-down magnification equivalent to four times. Specifically, by increasing the number of capacitors of the two capacitor sets of the second step-down stage 12 in the first embodiment to 3, the step-down ratio at this step-down stage can be increased to 4, thereby reducing the step-down circuit. The step-down magnification of 10 can be set to 8 times as in the second embodiment.

  In this case, the total number of required capacitors is not minimized, but an effect that the step-down magnification such as 6 times or 4 times as well as 8 times can be selected by inserting a switch as appropriate.

Further, in the above embodiments, the power generation means 40 is premised on that the power generation does not stop even if the power generation amount changes, but the extra step-down operation is stopped by detecting that the power generation has stopped. Alternatively, a function of preventing the power storage means 20 from being discharged reversely by providing a rectifying function between the step-down circuit 10 and the power storage means 20 may be provided.

DESCRIPTION OF SYMBOLS 10 Step-down circuit 11 1st step-down stage 12 2nd step-down stage 13 Timing generation circuit 20 Power storage means 40 Power generation means 50 Rectification means 101, 102, 201, 202 Capacitor set

Claims (4)

A plurality of step-down stages (11, 12) having a plurality of capacitors and a switch circuit for switching a connection state of the plurality of capacitors;
The plurality of step-down stages (11, 12) are connected in cascade,
Each step-down stage has two capacitor sets (101, 102, 201, 202) with a number of capacitors one less than the step-down ratio of each step-down stage,
The capacitor set is a step-down circuit in which the capacitor set connected to the input side of the step-down stage and the capacitor set connected to the output side are alternately switched with an equal time width. The step-down magnification is an integer,
The step-down stage has the same number of stages as the number of elements when the step-down magnification is factorized, and
2. The step-down circuit according to claim 1, wherein step-down ratios at the respective step-down stages respectively correspond to the values of the elements. When the number of capacitors in the capacitor set (201, 202) is 2 or more,
Capacitors in the capacitor set on the input side are connected in series,
3. The step-down circuit according to claim 1, wherein capacitors in the capacitor set on the output side are connected in parallel. A step-down circuit according to any one of claims 1 to 3,
Power generation means (40) for inputting a generated voltage to the step-down circuit;
Power storage means (20) for inputting and charging a step-down voltage from the step-down circuit;
A step-down charging circuit comprising:

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