JP7092592B2 - Semiconductor devices, semiconductor wafers, and electronic devices - Google Patents

Description

One aspect of the invention relates to semiconductor devices, semiconductor wafers, and electronic devices.

It should be noted that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.

In recent years, a transistor (OS transistor) using an oxide semiconductor (Oxide Semiconductor) in a channel forming region has been attracting attention. The leakage current (off current) of the OS transistor is extremely small when the transistor is in a non-conducting state. Therefore, application to semiconductor devices capable of retaining data is being studied.

The OS transistor is required to maintain a state in which the off current is extremely small for a long period of time. Therefore, in addition to the gate electrode for controlling the conduction state, a configuration in which a back gate electrode is provided and a voltage is applied to the back gate electrode to control the threshold voltage has been studied (see, for example, Patent Document 1).

US Patent Application Publication No. 2011/01773737

In Patent Document 1, the back gate is adjusted to the voltage fluctuation at the gate electrode by utilizing the capacitive coupling between the wiring on the gate electrode side (ward line) and the wiring on the back gate electrode side (back gate potential line). The configuration that fluctuates the voltage at the electrode is disclosed. However, in a configuration in which the voltage at the back gate electrode is changed according to the voltage change at the gate electrode by using capacitive coupling, the capacitance (also referred to as capacitance) between the word line and the back gate line is changed. Needs to be large. In this case, the load on the word line may increase, and the operating speed such as turning on or off the transistor may decrease.

Further, in the configuration in which the voltage at the back gate electrode is fluctuated according to the fluctuation of the ward line signal by using capacitive coupling, the control width of the potential of the back gate potential line is equal to or less than the amplitude voltage of the ward line signal. Therefore, it is difficult to increase the amplitude voltage of the back gate potential line.

One of the problems of the present invention is to provide a novel semiconductor device or the like capable of varying the amplitude voltage of the backgate potential line without increasing the capacitance of the word line. Another object of the present invention is to provide a novel semiconductor device or the like capable of increasing the amplitude voltage of the back gate potential line without depending on the amplitude voltage of the signal applied to the word line. .. Alternatively, one aspect of the present invention is to provide a new semiconductor device or the like.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. Is.

One aspect of the present invention includes a memory cell, a drive circuit, a voltage holding circuit, a buffer circuit, and a capacitive element, the memory cell has a first transistor, and the first transistor has a first transistor. It has a first semiconductor layer, a first gate electrode, and a first backgate electrode, the first gate electrode is electrically connected to the first wiring, and the first backgate electrode is , Electrically connected to the second wiring, the drive circuit has the function of giving a signal to control the continuity state of the first transistor to the first wiring, and the voltage holding circuit is the same as that of the first transistor. It has a function of applying a voltage for controlling the threshold voltage to the second wiring, and the voltage holding circuit provides the second wiring during the period in which the signal for controlling the conduction state of the first transistor is given to the first wiring. It has the function of electrically floating, the input terminal of the buffer circuit is electrically connected to the first wiring, and the output terminal of the buffer circuit is electrically connected to one electrode of the capacitive element. The other electrode of the capacitive element is a semiconductor device that is electrically connected to the second wiring.

One aspect of the present invention includes a memory cell, a drive circuit, a voltage holding circuit, a buffer circuit, and a capacitive element, the memory cell has a first transistor, and the first transistor has a first transistor. It has a first semiconductor layer, a first gate electrode, and a first backgate electrode, the first gate electrode is electrically connected to the first wiring, and the first backgate electrode is , Electrically connected to the second wiring, the drive circuit has the function of giving a signal to control the continuity state of the first transistor to the first wiring, and the voltage holding circuit is the same as that of the first transistor. It has a function of applying a voltage for controlling a threshold voltage to a second wiring, a voltage holding circuit has a second transistor, and the second transistor has a second semiconductor layer and a second gate electrode. The second gate electrode is electrically connected to one of the source or drain of the second transistor, and the input terminal of the buffer circuit is electrically connected to the first wiring of the buffer circuit. The output terminal is a semiconductor device that is electrically connected to one electrode of the capacitive element and the other electrode of the capacitive element is electrically connected to the second wiring.

In one aspect of the present invention, the second semiconductor layer is preferably a semiconductor device having an oxide semiconductor.

In one aspect of the present invention, the first transistor and the second transistor are n-channel type transistors, and the threshold voltage of the second transistor is the same for the first gate electrode and the first backgate electrode. A semiconductor device having a value larger than the threshold voltage of the first transistor when the potential is used is preferable.

In one aspect of the present invention, the buffer circuit is preferably a semiconductor device having a function of boosting the voltage of the input terminal and outputting the voltage to the output terminal.

One aspect of the present invention is an electronic device comprising the semiconductor device described above and at least one of an antenna, a battery, an operation switch, a microphone, or a speaker.

One aspect of the present invention is a semiconductor wafer having a plurality of the above-mentioned semiconductor devices and having a separation region.

Further, another aspect of the present invention is described in the description and drawings of the embodiments described below.

According to one aspect of the present invention, it is possible to provide a semiconductor device or the like having a novel configuration capable of varying the amplitude voltage of the back gate line without increasing the capacitance of the word line. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device or the like having a novel configuration capable of increasing the amplitude voltage of the back gate potential line without depending on the amplitude voltage of the signal applied to the word line. Alternatively, according to one aspect of the present invention, a novel semiconductor device or the like can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

The figure explaining the structure and operation of the semiconductor device. The figure explaining the structure of the semiconductor device. The figure explaining the operation of a semiconductor device. The figure explaining the operation of a semiconductor device. The figure explaining the operation of a semiconductor device. The figure explaining the operation of a semiconductor device. The figure explaining the structure of the semiconductor device. The figure explaining the structure of the semiconductor device. The figure explaining the structure of the semiconductor device. The figure explaining the structure of the semiconductor device. The figure explaining the structure of the semiconductor device. The cross-sectional view which shows the structural example of the semiconductor device. The cross-sectional view which shows the structural example of the semiconductor device. Top view and sectional view showing a structural example of a transistor. The figure explaining the structure of the semiconductor wafer and the electronic component. The figure which shows the structural example of the electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that embodiments can be implemented in many different embodiments and that the embodiments and details can be varied in various ways without departing from the spirit and scope thereof. .. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

In the present specification and the like, the ordinal numbers "first", "second", and "third" are added to avoid confusion of the constituent elements. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. Further, for example, the component referred to in "first" in one of the embodiments of the present specification and the like is regarded as another embodiment or the component referred to in "second" in the scope of claims. It is possible. Further, for example, the component referred to in "first" in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the scope of claims.

In the drawings, the same elements or elements having the same function, elements of the same material, elements formed at the same time, and the like may be designated by the same reference numerals, and the repeated description thereof may be omitted.

(Embodiment 1)
The configuration and operation of the semiconductor device according to one aspect of the present invention will be described with reference to FIGS. 1 to 11. The semiconductor device of one aspect of the present invention has a function as a storage device capable of holding data for a certain period of time.

The semiconductor device 10 shown in FIG. 1A includes a memory cell array 11, a peripheral circuit 12, a voltage holding circuit 13, a buffer circuit 17, and a capacitive element 18.

As an example, the memory cell array 11 has four memory cells MC (MC1_1, MC1_2, MC2_1, MC2_2) having 2 rows and 2 columns. The number of memory cells MC is not limited to four, and may be more than four.

When it is necessary to specify one of the memory cell MCs, the reference code of the memory cell MC is used, and when referring to an arbitrary memory cell MC, the reference numerals such as memory cells MC1_1, MC1_2, MC2_1, and MC2_2 are used. I will explain. The same applies to the other elements, and a reference numeral such as "_2" or [1] is used to distinguish a plurality of elements.

The memory cell MC1_1 has a transistor M1_1. The memory cell MC1_1 holds a voltage (data voltage) corresponding to the data. The data voltage is, for example, a high-level voltage if the data is "1" and a low-level voltage if the data is "0". The memory cell _{MC1_1} has a capacitive element CS for holding the data voltage. The data voltage is held in the node SN1-1 between the transistor _{M1_1} and the capacitive element CS.

Similarly, the memory cells MC1_2, MC2_1 and MC2_2 have transistors M1-2, M2_1, and M2_2, respectively. The memory cells MC1_2, MC2_1, and _{MC2_1} each have a capacitive element CS for holding a data voltage. The data voltage is held in the nodes SN1_2, SN2_1, and SN2_2 of the memory cells MC1_2, MC2_1, and MC2_2.

The transistors M1_1, M1_2, M2_1, and M2_1 have a gate electrode and a back gate electrode, respectively. For the transistors M1_1, M1-2, M2_1, and M2_1, it is preferable to use an oxide semiconductor (OS) for the semiconductor layer in which the channel is formed. A transistor in which an OS is used in a semiconductor layer on which a channel is formed is also referred to as an OS transistor. In the following description, the transistors M1_1, M1-2, M2_1, and M2_1 will be described as n-channel type transistors, but may be p-channel type transistors.

The leak current (off current) that flows in the OS transistor when it is not conducting is extremely small. Therefore, by setting the transistors M1_1, M1_2, M2_1, and M2_1 in a non-conducting state, it is possible to continue to hold the charge corresponding to the data voltage written in the nodes SN1_1, SN1_1, SN2_1, and SN2_2.

As an example, in the memory cell MC having 2 rows and 2 columns, the writing of the data voltage to the nodes SN1_1, SN1_1, SN2_1, and SN2_2 is controlled by the word signal given to the word line WL (WL_1, WL_2).

The word line WL_1 is connected to the gate electrodes of the transistors M1_1 and M1-2. The word line WL_2 is connected to the gate electrodes of the transistors M2_1 and M2_2. The word signal makes the transistors M1_1 and M1-2, or the transistors M2_1 and M2_1 conductive by setting a high level voltage ( _{VH_WL} ). The word signal makes the transistors M1_1 and M1-2, or the transistors M2_1 and M2_1 non-conducting by setting a low level voltage ( _{VL_WL} ).

The memory cell MC having 2 rows and 2 columns applies a data voltage to the bit lines BL (BL_1, BL_1) as an example. The data voltage is written to the nodes SN1_1, SN1_2, SN2_1, and SN2_2 via the transistors M1_1, M1-2, M2_1, and M2_2 by controlling the word signal given to the word line WL of each row.

The bit line BL_1 is connected to one of the source or drain of the transistors M1_1 and M2_1. The bit line BL_2 is connected to one of the source or drain of the transistors M1-2 and M2_2.

In the two-row, two-column memory cell MC, for example, the threshold voltages of the transistors M1_1, M1-2, M2_1, and M2_1 are controlled by the backgate voltage ( _VBG ) applied to the backgate potential lines BGL (BGL_1, BGL_1).

The backgate voltage is a voltage capable of positively or negatively shifting the threshold voltage of the transistors M1_1, M1_2, M2_1, and M2_1. For example, when the threshold voltage is positively shifted, the back gate voltage is a voltage smaller than the reference voltage (0V). With this configuration, the transistors M1_1, M1-2, M2_1, and M2_1 can be put into a non-conducting state without reducing the low-level voltage of the word signal to a smaller voltage. Therefore, the amplitude voltage of the word signal can be reduced.

The backgate potential line BGL_1 is connected to the backgate electrodes of the transistors M1_1 and M1_2. The backgate potential line BGL_2 is connected to the backgate electrodes of the transistors M2_1 and M2_2.

The peripheral circuit 12 has a function of giving a word signal to the word lines WL_1 and WL_1. The peripheral circuit 12 has a function of applying a data voltage to the bit lines BL_1 and BL_1. The peripheral circuit 12 is composed of a plurality of circuits such as a word line drive circuit and a bit line drive circuit. The peripheral circuit 12 outputs the word signal and the data voltage during the period of writing and reading the data voltage to and from the memory cell MC, and during the other period, the word signal is used as a low-level voltage, and the transistor M1-1. Make sure that M1-2, M2_1, and M2_1 are in a non-conducting state.

The voltage holding circuit 13 has a function of applying a back gate voltage to the back gate potential lines BGL_1 and BGL_1. The voltage holding circuit 13 has a function of electrically floating the back gate potential lines BGL_1 and BGL_2 during the period in which the peripheral circuit 12 writes and reads the data voltage to and from the memory cell MC.

In the buffer circuit 17_1, the input terminal is connected to the word line WL_1. In the buffer circuit 17_1, the output terminal is connected to one electrode of the capacitive element 18_1. The other electrode of the capacitive element 18_1 is connected to the backgate potential line BGL_1. Similarly, in the buffer circuit 17_2, the input terminal is connected to the word line WL_1. In the buffer circuit 17_2, the output terminal is connected to one electrode of the capacitive element 15_2. The other electrode of the capacitive element 18_2 is connected to the back gate potential line BGL_2.

In FIG. 1A, the node between the buffer circuit 17_1 and the capacitive element 18_1 is illustrated as a node BN_1. In FIG. 1A, the node between the buffer circuit 17_2 and the capacitive element 18_2 is illustrated as a node BN_2.

The buffer circuit 17_1 has a function of amplifying the amplitude voltage of the input terminal and outputting it from the output terminal. For example, the buffer circuit 17_1 has a function of outputting the voltage V _{H_WL} of the word signal as the voltage V _{H_BUF} . Further, the buffer circuit 17_1 has a function of outputting the voltage _{VL_WL} of the word signal as a voltage _{VL_BUF} . The buffer circuit 17_1 outputs the voltages V _{H_BUF} and _{VL_BUF} with increased charge supply capacity. Further, the voltages V _{H_BUF} and _{VL_BUF} may have different potentials from the voltage V _{H_WL} and the voltage V _{L_WL} , and the voltage V _{H_BUF} is preferably a potential larger than the voltage V _{H_WL} . Since the buffer circuit 17_1 can amplify the word signal and output it to the capacitive element 18_1, it is possible to increase the fluctuation of the potential due to the capacitive coupling with respect to the backgate potential line BGL_1. In addition, the capacitance parasitic on the word line WL_1 can be reduced.

Similarly, the buffer circuit 17_2 has a function of amplifying the amplitude voltage of the input terminal and outputting it from the output terminal. For example, the buffer circuit 17_2 has a function of outputting the voltage V _{H_WL} of the word signal as the voltage V _{H_BUF} . Further, the buffer circuit 17_2 has a function of outputting the voltage _{VL_WL} of the word signal as a voltage _{VL_BUF} . The buffer circuit 17_2 outputs the voltages V _{H_BUF} and _{VL_BUF} with increased charge supply capacity. Since the buffer circuit 17_2 can amplify the word signal and output it to the capacitive element 18_2, it is possible to increase the fluctuation of the potential due to the capacitive coupling with respect to the back gate potential line BGL_2. In addition, the capacitance parasitic on the word line WL_2 can be reduced.

The capacitive element 18_1 has a function of being able to change the potential of the other electrode, which is electrically suspended, according to the fluctuation of the potential of one electrode. Capacitive element 18_1 can boost the voltage of the other by using capacitive coupling by electrically suspending the other electrode. The capacitance element 18_1 can increase the fluctuation of the potential due to the capacitive coupling by making the capacitance larger than the capacitance of the backgate potential line BGL_1.

Similarly, the capacitive element 18_2 has a function of being able to change the potential of the other electrode, which is electrically suspended, according to the fluctuation of the potential of one electrode. Capacitive element 18_2 can boost the voltage of the other by using capacitive coupling by electrically suspending the other electrode. The capacitance element 18_2 can increase the fluctuation of the potential due to the capacitive coupling by making the capacitance larger than the capacitance of the backgate potential line BGL_2.

With the above configuration, during the period when the access transistor of the memory cell is turned off, the back gate voltage can be continuously applied to the back gate potential line to positively shift the threshold voltage of the access transistor of the memory cell. At the same time, the voltage of the backgate potential line can be increased by using capacitive coupling without affecting the operating speed of the word line. In addition, by generating a signal in which the amplitude voltage of the word line is increased in the buffer circuit, the voltage fluctuation of the back gate potential line can be increased without affecting the operating speed of the word line, so that the memory cell can be used. The on-current of the access transistor can be increased and the off-current can be reduced.

In addition, in one aspect of the present invention, different backgate potential lines, such as the backgate potential line BGL_1 and the backgate potential line BGL_1, are electrically suspended separately. That is, the back gate potential line BGL_1 and the back gate potential line BGL_1 are both electrically suspended, but the backgate potential line BGL_1 is set to the high level of the word signal of the word line WL_1 via the buffer circuit 17_1 and the capacitive element 18_1. When raising the voltage, the word signal of the word line WL_2 is set to a low level to reduce the voltage rise due to the capacitive coupling of the backgate potential line BGL_1 via the buffer circuit 17_1 and the capacitive element 18_1, and the voltage increase of the backgate voltage initially applied is reduced. Fluctuations can be suppressed. With this configuration, it is possible to achieve both an increase in the on-current of the transistor whose ward signal is a high-level voltage and a maintenance of the off-current of the transistor whose ward signal is a low-level voltage in an extremely small state. be able to.

Next, in FIG. 1B, the operation of the semiconductor device 10 shown in FIG. 1A will be described. In FIG. 1B, the word signal of the word line WL_1 in the period P1 and the period P2, the word signal of the word line WL_1, the voltage of the node BN_1 corresponding to the output signal of the buffer circuit 17_1, and the voltage of the node BN_1 corresponding to the output signal of the buffer circuit 17_1 , The voltage of the back gate potential line BGL_1 and the voltage of the back gate potential line BGL_1 are illustrated. In FIG. 1B, the times T1 to T7 are illustrated for the sake of explanation.

The period P1 corresponds to a period for setting the backgate voltage of the backgate potential line. The period P2 corresponds to a period in which a word signal is applied to the word line in order to write or read the data voltage.

In FIG. 1B, the high-level voltage of the word signals of the word lines WL_1 and _{WL_1} is shown as VH_WL. V _{H_WL} is preferably a voltage larger than the reference voltage 0V, and is a voltage that makes the transistors M1_1, M1-2, M2_1, and M2_2 conductive. In FIG. 1B, the low-level voltage of the word signal of the word lines WL_1 and _{WL_1} is illustrated as VL_WL. _{VL_WL} is preferably a voltage of 0 V or less as a reference voltage, and is a voltage that causes the transistors M1_1, M1-2, M2_1, and M2_1 to be in a non-conducting state.

Further, in FIG. 1B, the high-level voltage of the output signals of the buffer circuits 17_1 and _{17_2} is shown as VH_BUF. It is preferable that V _{H_BUF} has a voltage larger than V _{H_WL} . In FIG. 1B, the low-level voltage of the output signals of the buffer circuits 17_1 and _{17_2} is shown as VL_BUF. It is preferable that _{VL_BUF} has the same voltage as _{VL_WL} or a reference voltage of 0 V or less.

In FIG. 1 (B), the back gate voltages of the back gate potential lines BGL_1 and BGL_1 are shown as _VBG . The _VBG is preferably smaller than the reference voltage 0V and preferably smaller than _VL or _{VL_BUF} . By setting _VBG smaller than _VL or _{VL_BUF} , it is possible to reliably prevent a negative shift of the threshold voltage of the transistor and maintain a state in which the off-current is extremely small.

In the period P1 of FIG. 1B, the voltages of the back gate potential lines BGL_1 and BGL_1 are set from the reference voltage 0V to _VBG at the time T1. In the period P1, the word lines WL_1 and WL_1 are set to low-level voltages.

In the period P1 of FIG. 1 (B), the voltages of the back gate potential lines BGL_1 and BGL_1 are maintained at _VBG at the time T2. In each of the transistors M1_1, M1-2, M2_1, and M2_1, the voltage of the back gate electrode is _VBG . Therefore, the threshold voltage of each transistor is positively shifted, and the off-current becomes extremely small.

In the period P2 of FIG. 1 (B), at time T3, the voltage of the back gate potential lines BGL_1 and BGL_1 is set to _VBG and the state is electrically suspended. In the period P2, the word lines WL_1 and WL_1 are set to _{VF_WL} or _{VL_WL} in order to write or read the data voltage. At time T3, the word lines WL_1 and WL_1 are both _{VL_WL} , and the transistors M1_1, M1_2, M2_1, and M2_2 are in a non-conducting state. Further, at time T3, both the nodes BN_1 and BN_2 are _{VL_BUF} .

The transistors M1_1, M1-2, M2_1, and M2_1 are electrically suspended in a state where the voltage of the back gate electrode is _VBG . Since the electric charge corresponding to the _VBG applied to the back gate electrode is retained, the threshold voltage is positively shifted and the off current is maintained in an extremely small state.

In the period P2 of FIG. 1B, the word line WL_1 is set to V _{H_WL} in order to write or read the data voltage to the memory cells MC1_1 and MC1_2 connected to the word line WL_1 of the first line at time T4. Let the word line WL_2 be _{VL_WL} . The transistors M1_1 and M1-2 are in a conductive state, and the transistors M2_1 and M2_1 are in a non-conducting state. Further, at time T4, the node BN_1 becomes _{VH_BUF} and the node BN_1 becomes _{VL_BUF} .

As described above, in the period P2 of FIG. 1 (B), the back gate potential lines BGL_1 and BGL_1 are electrically suspended in a state of being set to _VBG . Therefore, at time T4, the transistors M1_1 and M1-2 are brought into a conductive state, that is, the word line WL_1 is boosted from _{VL_WL} to _{VH_WL} , so that the node BN_1 is boosted from _{VL_BUF} to _{VH_BUF} , and the capacitive coupling of the capacitive element 18_1 is performed. The voltage of the back gate potential line BGL_1 can be increased by.

With this configuration, even if the V _{H_WL} of the word line WL_1 is set to a smaller voltage, the voltage applied to one electrode of the capacitive element 18_1 can be set to V _{H_BUF} . By setting one electrode of the capacitive element 18_1 to _{VH_BUF} , the fluctuation range of the voltage at the node BN_1 can be increased without affecting the operating speed of the word line WL_1, so that the backgate potential line BGL_1 using capacitive coupling can be increased. The fluctuation range of the voltage can be increased. Therefore, the on-current can be increased when the transistors M1_1 and M1_2 are in a conductive state.

In addition, in the period P2 of FIG. 1 (B), the voltage of the back gate potential lines BGL_1 and BGL_1 is set to _VBG and the state is electrically suspended. Therefore, at time T4, the fluctuation of the voltage of the back gate potential line BGL_2 is suppressed by making the transistors M2_1 and M2_2 non-conducting, that is, by maintaining the word line WL_2 at _{VL_WL} and the node BN_2 at _{VL_BUF} . can do.

This configuration can be realized by separately electrically suspending the back gate potential line BGL_1 and the back gate potential line BGL_1. That is, the back gate potential line BGL_1 and the backgate potential line BGL_1 can be individually electrically connected to each other via a switch, a transistor, or the like to realize an electrically floating state. With this configuration, the on-current of the transistor is increased by boosting the backgate potential line BGL_1 with the node _{BN_1} as VH_BUF, and the transistor with the node _{BN_1} as VL_BUF and the backgate potential line BGL_1 as _VBG . It is possible to achieve both the maintenance of the off-current in an extremely small state.

In the period P2 of FIG. 1 (B), the time T5 is the same as the time T3. That is, both the word lines WL_1 and WL_1 are _{VL_WL} , and the transistors M1_1, M1_1, M2_1, and M2_2 are in a non-conducting state. The voltage of the back gate potential line BGL_1 at the time T4 described above is stepped down as the node BN_1 steps down from _{VH_BUF} to _{VL_BUF} at time T5. This step-down is due to the step-down using the capacitive coupling in the capacitive element 18_1. As a result of step-down, the voltage of the back gate potential line BGL_1 is the original _VBG . Therefore, the transistors M1_1, M1-2, M2_1, and M2_1 are electrically suspended in a state where the voltage of the back gate electrode is _VBG . The voltage of the back gate potential line BGL_1 may fluctuate due to fluctuations in the voltage of the bit line BL or the node SN other than the word line WL_1.

In the period P2 of FIG. 1B, the word line WL_1 is set to VL_WL in order to write or read the data voltage to the memory cells MC2_1 and MC2_2 connected to the word line WL_2 in the second line at time T6 _. Let the word line WL_2 be V _{H_WL} . The transistors M1_1 and M1-2 are in a non-conducting state, and the transistors M2_1 and M2_1 are in a conducting state. Further, at time T6, the node BN_1 becomes _{VL_BUF} , and the node _{BN_1} becomes VH_BUF.

As described above, in the period P2 of FIG. 1 (B), the back gate potential lines BGL_1 and BGL_1 are electrically suspended in a state of being set to _VBG . Therefore, at time T6, the transistors M2_1 and M2_2 are brought into a conductive state, that is, the word line WL_1 is boosted from _{VL_WL} to _{VEH_WL} , so that the node BN_1 is boosted from _{VL_BUF} to _{VH_BUF} , and the capacitive coupling of the capacitive element 18_2 is performed. The voltage of the back gate potential line BGL_2 can be increased by.

With this configuration, even if the V _{H_WL} of the word line WL_2 is set to a smaller voltage, the voltage applied to one electrode of the capacitive element 18_2 can be set to V _{H_BUF} . By setting one electrode of the capacitive element 18_2 to _{VH_BUF} , the fluctuation range of the voltage at the node BN_2 can be increased without affecting the operating speed of the word line WL_2, so that the back gate potential line BGL_2 using capacitive coupling can be increased. The fluctuation range of the voltage can be increased. Therefore, the on-current can be increased when the transistors M2_1 and M2_1 are brought into a conductive state.

In addition, in the period P2 of FIG. 1 (B), the voltage of the back gate potential lines BGL_1 and BGL_1 is set to _VBG and the state is electrically suspended. Therefore, at time T6, the fluctuation of the voltage of the back gate potential line BGL_1 is suppressed by making the transistors M1_1 and M1-2 in a non-conducting state, that is, by maintaining the word line WL_1 at _{VH_WL} and the node BN_1 at _{VL_BUF} . can do.

This configuration can be realized by separately electrically suspending the back gate potential line BGL_1 and the back gate potential line BGL_1. That is, the back gate potential line BGL_1 and the backgate potential line BGL_1 can be individually electrically connected to each other via a switch, a transistor, or the like to realize an electrically floating state. With this configuration, the decrease in the on-current of the transistor is suppressed by boosting the back gate potential line BGL_1 with the node _{BN_1} as VH_BUF, and the backgate potential line BGL_1 is _set as _VBG with the node BN_1 as VL_BUF. It is possible to achieve both the maintenance of the off-current of the transistor in an extremely small state and the maintenance of the transistor.

In the period P2 of FIG. 1B, the time T7 is the same as the time T3 and T5.

2 (A) and 2 (B) show a configuration example of the voltage holding circuit 13 capable of realizing the operation described with reference to FIG. 1 (B). In FIGS. 2A and 2B, transistors M1_1 to M1_n and M2_1 to M2_n included in the memory cell MC having 2 rows and n columns are illustrated. The gate electrodes of the transistors M1_1 to M1_n are connected to the word line WL_1. The back gate electrodes of the transistors M1_1 to M1_n are connected to the back gate potential line BGL_1. The gate electrodes of the transistors M2_1 to M2_n are connected to the word line WL_1. The back gate electrodes of the transistors M2-1 to M2_n are connected to the back gate potential line BGL_1. In the buffer circuit 17_1, the input terminal is connected to the word line WL_1. In the buffer circuit 17_1, the output terminal is connected to one electrode of the capacitive element 18_1. The other electrode of the capacitive element 18_1 is connected to the backgate potential line BGL_1. Similarly, in the buffer circuit 17_2, the input terminal is connected to the word line WL_1. In the buffer circuit 17_2, the output terminal is connected to one electrode of the capacitive element 15_2. The other electrode of the capacitive element 18_2 is connected to the back gate potential line BGL_2.

The voltage holding circuit 13 shown in FIG. 2A includes a transistor RM1, a transistor RM2, a _transistor RM, a capacitive element CVR, and a voltage generation circuit 14. In FIG. 2A, the node to which the transistor RM1, the transistor RM2, the transistor RM, and the capacitive element _CVR are connected is shown as a node _NVR .

The voltage generation circuit 14 shown in FIG. 2A is a circuit that generates a _VBG capable of controlling the threshold voltage of the transistor included in the memory cell MC. _{The VBG} may be generated, for example, by stepping down the reference voltage (0V).

The transistor RM shown in FIG. 2A holds the _VBG of the node _NVR even if the _VBG generated by the voltage generation circuit 14 is given to the node _NVR and then the voltage generation by the voltage generation circuit 14 is stopped. It is a transistor that can be used. The transistor RM is preferably an OS transistor. The transistor RM preferably has a larger threshold voltage than the transistor included in the memory cell MC. The transistor RM is preferable because both the on current and the off current are smaller than those of the memory cell MC, so that the _VBG of the node _NVR can be easily held. The gate of the transistor RM is connected to either the source or the drain of the transistor RM. With the configuration shown in FIG. 2A, the transistor RM functions as a diode and can hold the _VBG of the node _NVR regardless of the control signal from the outside.

Transistors RM1 and RM2 shown in FIG. 2A provide _VBG held in the node NVR to the back gate potential lines BGL_1 and BGL_1, and back after the backgate potential lines _{BGL_1} and BGL_1 are set to _VBG . A transistor capable of electrically suspending the gate potential lines BGL_1 and BGL_1. The transistors RM1 and RM2 are preferably OS transistors. Like the transistor RM, the transistors RM1 and RM2 preferably have a larger threshold voltage than the transistor included in the memory cell MC. Similar to the transistor RM, the transistors RM1 and RM2 are preferable because the on-current and off-current are both smaller than those of the transistor of the memory cell MC, so that the VBGs of the back gate potential lines _{BGL_1} and BGL_1 can be easily held. Transistors RM1 and RM2 connect the gate to one of the source or drain. With the configuration shown in FIG. 2A, the transistors RM1 and RM2 function as diodes, hold the _VBGs of RM1 and RM2 regardless of external control signals, and hold the node _NVR and backgate potential lines. When BGL_1 and BGL_2 are equipotential, the back gate potential lines BGL_1 and BGL_1 can be electrically suspended.

The transistors RM, RM1 and RM2 shown in FIG. 2A can be replaced with switches. The circuit configuration in this case is shown in FIG. 2 (B). The voltage holding circuit 13 shown in FIG. 2B includes a switch SW1, a switch SW2, a switch SW, a capacitive element _CVR , and a voltage generation circuit 14. In FIG. 2B, the node to which the switch SW1, the switch SW2, the switch SW, and the capacitive element _CVR are connected is shown as a node _NVR . FIG. 2B realizes the operation described in FIG. 1B by controlling each switch to set the back gate potential lines BGL_1 and BGL_1 to _VBG and then electrically suspending them. can do.

The operation of the voltage holding circuit 13 shown in FIG. 2A, the voltage of the node BN_1 between the buffer circuit 17_1 and the capacitive element 18_1, the voltage of the node BN_1 between the buffer circuit 17_2 and the capacitive element 18_1, and the backgate potential line BGL_1 And the state of BGL_2 will be described with reference to FIGS. 3 to 6. The state of FIG. 3A corresponds to the time T1 of FIG. 1B. The state of FIG. 3B corresponds to the time T2 of FIG. 1B. The state of FIG. 4 (A) corresponds to the time T3 of FIG. 1 (B). The state of FIG. 4B corresponds to the time T4 of FIG. 1B. The state of FIG. 5A corresponds to the time T5 of FIG. 1B. The state of FIG. 5B corresponds to the time T6 of FIG. 1B. The state of FIG. 6 corresponds to the time T7 of FIG. 1 (B).

In FIG. 3A, the voltage generation circuit 14 generates _VBG . In the initial state, the node NVR, the back gate potential lines _{BGL_1} and BGL_1 are set to the reference voltage (0V).

In FIG. 3B, a potential difference occurs between the voltage generation circuit 14 and the node _NVR , so that a current flows through the transistor RM. As a result, the voltage of the node _NVR becomes _VBG . Similarly, since a potential difference occurs between the back gate potential line _{BL_1} and the node NVR, a current flows through the transistor RM1. As a result, the voltage of the back gate potential line BGL_1 becomes _VBG . Similarly, since a potential difference occurs between the back gate potential line _{BL_2} and the node NVR, a current flows through the transistor RM2. As a result, the voltage of the back gate potential line BGL_2 becomes _VBG . Actually, the voltage lowered by the threshold voltage of the transistors RM, RM1 and RM2 is given to the node NVR, the back gate potential lines _{BGL_1} and BGL_1, but in the following description, it is omitted as the threshold voltage is small. There is.

In FIG. 4A, the generation of _VBG by the voltage generation circuit 14 is stopped. As a result, the voltage between the voltage generation circuit 14 and the transistor RM becomes a reference voltage (0V). The _VBG of the node _NVR is smaller than the reference voltage (0V). The transistor that functions as a diode is in a non-conducting state. The node N _VR is electrically suspended. The off current of the transistor RM is extremely small. Therefore, the _VBG of the node _NVR can be held for a long time. The _VBG of the backgate potential line _{BGL_1} is equipotential with the _VBG of the node NVR. The transistor that functions as a diode is in a non-conducting state. The backgate potential line BGL_1 is electrically in a floating state. Further, the transistor RM1 has an extremely small off current. Therefore, the _VBG of the back gate potential line BGL_1 can be held for a long time.

In FIG. 4B, the word line WL_1 is referred to as _{VH_WL} , and the word line WL_1 is referred to as _{VL_WL} . Therefore, in FIG. 4B, the node NB_1 changes from _{VL_WL} to _{VH_BUF} , and the node NB_2 changes to _{VL_WL} . Since the voltage of the backgate potential line BGL_1 is electrically suspended, it rises by ΔV from _VBG due to capacitive coupling. Although the voltage of the backgate potential line BGL_2 is electrically suspended, it remains _VBG because the capacitive coupling between the node NB_1 and the backgate potential line BGL_1 is small. The voltage of the back gate potential line BGL_2 may fluctuate due to fluctuations in the voltage of the bit line BL, the node SN, or the like.

In FIG. 5A, the word line WL_1 is referred to as _{VL_WL} , and the word line WL_1 is referred to as _{VL_WL} . Therefore, in FIG. 5A, the node NB_1 is changed from _{VH_WL} to _{VL_BUF} , and the node NB_2 is changed to _{VL_WL} . Since the voltage of the back gate potential line BGL_1 is electrically in a floating state, it becomes _VBG by returning the node NB_1 to _{VL_BUF} .

In FIG. 5B, the word line WL_1 is referred to as _{VL_WL} , and the word line WL_1 is referred to as _{VL_WL} . Therefore, in FIG. 5B, the node NB_1 is changed to _{VL_WL} , and the node NB_2 is changed from _{VL_WL} to _{VH_BUF} . Since the voltage of the backgate potential line BGL_2 is electrically suspended, it rises by ΔV from _VBG due to capacitive coupling. Although the voltage of the backgate potential line BGL_1 is electrically suspended, it remains _VBG because the capacitive coupling between the node NB_2 and the backgate potential line BGL_1 is small. The voltage of the back gate potential line BGL_1 may fluctuate due to fluctuations in the voltage of the bit line BL or the node SN.

In FIG. 6, the word line WL_1 is referred to as _{VL_WL} , and the word line WL_1 is referred to as _{VL_WL} . Therefore, in FIG. 6, the node NB_1 is changed to _{VL_WL} , and the node NB_2 is changed from _{VH_WL} to _{VL_WL} . Since the voltage of the back gate potential line BGL_2 is electrically in a floating state, it becomes _VBG by returning the node NB_2 to _{VL_BUF} .

As described above, in one aspect of the present invention, during the period when the access transistor of the memory cell is turned off, the back gate voltage is constantly applied to the back gate potential line to positively shift the threshold voltage of the access transistor of the memory cell. Can be done. At the same time, during the period when the access transistor of the memory cell is turned on, the threshold voltage of the access transistor is increased by increasing the backgate voltage to the backgate potential line by using capacitive coupling without increasing the amplitude voltage of the word signal. Can be negatively shifted. It is possible to fluctuate the voltage of the backgate potential line without increasing the load on the ward line, and it is possible to avoid a decrease in operating speed such as turning on or off the transistor. In addition, by generating a signal in which the amplitude voltage of the word line is increased in the buffer circuit, it is possible to increase the fluctuation of the potential of the back gate potential line regardless of the amplitude voltage of the word signal, so that the access of the memory cell can be increased. The on-current of the transistor can be increased and the off-current can be reduced.

Specific examples of the configurations described with reference to FIGS. 1 to 6 described above will be described with reference to FIGS. 7 to 11.

FIG. 7A shows an example of the circuit configuration of the buffer circuit 17 applicable to the buffer circuits 17_1 and 17_2 described above.

FIG. 7A illustrates a buffer circuit 17 in which an input terminal is connected to a word line WL and an output terminal is connected to one electrode of a capacitive element 18.

As described above, the buffer circuit 17 outputs the word signal to one electrode side of the capacitive element 18, that is, the node BN, by increasing the current supply capacity of the signal of the same logic. Therefore, the buffer circuit 17 is configured to be provided by connecting a plurality of inverter circuits in series as shown in FIG. 7 (B). The inverter circuit included in the buffer circuit 17 is preferably composed of a Si transistor. With this configuration, a CMOS (complementary MOS) circuit can be configured, so that power consumption can be reduced. Further, not limited to the inverter circuit, a buffer circuit having a function of boosting the voltage of the input terminal and outputting to the output terminal can be obtained by using a level shifter circuit or the like. With this configuration, the backgate potential line can be boosted more reliably.

Further, it is preferable that the capacitive element 18 has a large capacitance due to the capacitive element so that the voltage once applied to the back gate potential lines BGL_1 and BGL_1 can be easily held. Further, in order to boost the backgate potential line by the capacitive coupling of the capacitive element 18, it is preferable to reduce the parasitic capacitance of the backgate potential line that is electrically suspended. The parasitic capacitance of the backgate potential line and the capacitance (simply referred to as capacitance) of the capacitive element 18 will be described with reference to FIG. 7 (C).

As shown in FIG. 7C, the back gate potential line BGL is provided between the capacitance C _BUF-BGL of the capacitance element 18, the capacitance C _BL-BGL between the bit lines BL_1 to BL_n, and the node SN. It has a capacitance C _SN-BGL and a capacitance C _OL-BGL to and from other wiring OLs (other wiring such as non-adjacent BLs or WLs).

FIG. 7C is an equivalent circuit diagram having a capacitance C _{BUF-BGL ,} a capacitance C _BL-BGL , a capacitance C _SN-BGL , and a capacitance COL-BGL added to the above-mentioned backgate potential line BGL. In order to change the voltage of the backgate potential line BGL, which is electrically suspended, in response to the change in the voltage of the node BN, the capacitance C _BUF-BGL , the capacitance C _BL-BGL , the capacitance C _SN-BGL , And a configuration that is larger than _COL-BGL is preferable. Specifically, the capacity C _BUF-BGL is preferably 1.2 times or more the total capacity of the capacity C _BL-BGL , the capacity C _SN-BGL , and the capacity COL _-BGL .

In FIG. 2A, the transistors RM and RM1 are shown as transistors having a top gate structure or a bottom gate structure without a back gate electrode, but the present invention is not limited to this. For example, as shown in FIG. 8A, transistors RM_A and RM1_A having a back gate electrode may be used. With the configuration of FIG. 8A, the amount of current flowing through the transistors RM_A and RM1_A can be increased, and the back gate potential line BGL can be set to _VBG in a short period of time.

Alternatively, as shown in FIG. 8B, the transistor RM1_A of FIG. 8A may be a transistor RM1_B in which the gate electrode is connected to the wiring ENL_A and the back gate electrode is connected to the wiring ENL_B. It is preferable that the wiring ENL_A and the wiring ENL_B are configured to give separate control signals. For example, the control signal given to the wiring ENL_A and the wiring ENL_B is in a non-conducting state during the period in which the transistor RM1_B is given the word signal to the word line WL, and is in a conductive state in the other period. With the configuration of FIG. 8B, the state of the transistor RM1_B can be easily controlled from the outside.

FIG. 9A shows an example of a circuit configuration applicable to the voltage generation circuit 14 described above.

The voltage generation circuit 14A shown in FIG. 9A is a four-stage charge pump having diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is given to the capacitors C1 to C5 directly or via the inverter INV. Assuming that the power supply voltage of the inverter INV is a voltage applied by _VDD and ground (0V), _VBG stepped down from 0V to a negative voltage four times _VDD can be obtained by the clock signal CLK. The forward voltage of the diodes D1 to D5 is 0V. Further, a desired _VBG can be obtained by changing the number of stages of the charge pump.

The circuit configuration of the voltage generation circuit 14A described above is not limited to the configuration of the circuit diagram shown in FIG. 9A. Modification examples of the voltage generation circuit 14A are shown in FIGS. 9 (B) and 9 (C).

The voltage generation circuit 14B shown in FIG. 9B corresponds to a configuration in which the diodes D1 to D5 of the voltage generation circuit 14A shown in FIG. 9A are replaced with transistors M11 to M15 connected by diodes. In the voltage generation circuit 14B shown in FIG. 9B, the off-current can be reduced by using the transistors M11 to M15 as OS transistors, and the leakage of electric charges held in the capacitors C1 to C5 can be suppressed. Therefore, it is possible to efficiently reduce the pressure from 0V to _VBG .

Further, the voltage generation circuit 14C shown in FIG. 9C corresponds to a configuration in which the transistors M11 to M15 of the voltage generation circuit 14B shown in FIG. 9B are replaced with transistors M21 to M25 having a back gate electrode. Since the voltage generation circuit 14C shown in FIG. 9C can apply the same voltage to the back gate electrode as the gate electrode, the amount of current flowing through the transistor can be increased. Therefore, it is possible to efficiently reduce the pressure from 0V to _VBG .

10 (A) to 10 (E) show an example of a circuit configuration that the memory cell MC described with reference to FIG. 1 (A) can take. In the circuit diagram of the memory cell shown in FIGS. 10A to 10E, the data voltage is written from the source line SL or the bit line BL, and the voltage of the write word line WWL and the read word line RWL is controlled to control the data. It is possible to control the writing or reading of the voltage.

The memory cell MC_A shown in FIG. 10A has a transistor M1, a transistor _{M2_A} , and a capacitive element CS. The transistor M1 has a back gate electrode, and the voltage applied to the back gate electrode can be controlled by the back gate potential line BGL. The transistor M2_A is a p-channel transistor. By making the transistor M1 non-conducting, it is possible to hold the electric charge corresponding to the data voltage in the node SN. The current of the transistor M2_A is controlled according to the electric charge corresponding to the held data voltage. The configuration of FIG. 10 (A) can be applied to the memory cell MC of FIG. 1 (A).

The memory cell MC_B shown in FIG. 10B has a transistor M1, a transistor _{M2_B} , and a capacitive element CS. The difference from FIG. 10A is that the transistor M2_B is an n-channel transistor. The configuration of FIG. 10B can be applied to the memory cell MC of FIG. 1A.

The memory cell MC_C shown in FIG. 10C has a transistor M1, a transistor _{M2_A} , a transistor M3, and a capacitive element CS. The memory cell MC_C has a transistor M3, which is different from FIG. 10 (A). The transistor M3 is the same p-channel transistor as the transistor M2_A. By making the transistor M3 non-conducting, the current flowing between the bit line BL and the source line SL can be controlled. The configuration of FIG. 10 (C) can be applied to the memory cell MC of FIG. 1 (A).

The memory cell MC_D shown in FIG. 10D has a transistor M1, a transistor _{M2_A} , and a capacitive element CS. The transistor M1 is connected to the write bit line WBL, and the transistor M2_A is connected to the read bit line RBL. In the configuration of FIG. 10D, for example, the read bit line RBL can be used for reading the data voltage, and the write bit line WBL can be used for writing the data voltage. The configuration of FIG. 10 (D) can be applied to the memory cell MC of FIG. 1 (A).

The memory cell MC_E shown in FIG. 10 (E) has a transistor M1, a transistor _{M2_A} , a transistor M3, and a capacitive element CS. The memory cell MC_E has a transistor M3, which is different from FIG. 10 (A). The transistor M3 is the same p-channel transistor as the transistor M2_A. By making the transistor M3 non-conducting, the current flowing between the bit line BL and the source line SL can be controlled. In addition, in the memory cell MC_E shown in FIG. 10 (E), the transistor M1 is connected to the write bit line WBL, and the transistor M2_A is connected to the read bit line RBL. In the configuration of FIG. 10E, for example, the read bit line RBL can be used for reading the data voltage, and the write bit line WBL can be used for writing the data voltage. The configuration of FIG. 10 (E) can be applied to the memory cell MC of FIG. 1 (A).

The memory cell MC_F shown in FIG. 11A has transistors M4, M5, inverters INV1, INV2, transistors M1_Q, _{M1_QB} , and a capacitance element CS constituting a SRAM (Static RAM).

The memory cell MC_F controls the control line ENL to control the backup of the data voltage of the SRAM nodes Q and QB to the nodes SN1 and SN2, and the recovery of the data voltage from the nodes SN1 and SN2 to the nodes Q and QB. do. The transistors M1_Q and M1_QB have a back gate electrode, and the voltage applied to the back gate electrode can be controlled by the back gate potential line BGL. By setting the transistors M1_Q and M1_QB in a non-conducting state, the nodes SN1 and SN2 can hold charges according to the data voltage. The configuration of FIG. 11 (A) can be applied to the memory cell MC of FIG. 1 (A).

The memory cell _{MC_G} shown in FIG. 11B has transistors M4 and M5, inverters INV1 and INV2, transistors M1 and M6, a capacitance element CS, and an inverter INV3 that constitute a SRAM (Static RAM).

The memory cell MC_G controls the write control line WEN to control the backup of the data voltage of the node Q of the SRAM to the node SN. Further, the memory cell MC_F controls the read control line REN to control the recovery of the data voltage from the node SN to the node QB via the inverter INV3. The transistor M1 has a back gate electrode, and has a configuration in which the voltage applied to the back gate electrode can be controlled by the back gate potential line BGL_A. The transistor M6 has a back gate electrode, and has a configuration in which the voltage applied to the back gate electrode can be controlled by the back gate potential line BGL_B. By making the transistor M1 non-conducting, it is possible to hold the electric charge corresponding to the data voltage in the node SN. By making the transistor M6 non-conducting, the leakage current from the node QB can be suppressed. The configuration of FIG. 11B can be applied to the memory cell MC of FIG. 1A.

As described above, one aspect of the present invention can be operated by adopting various configurations.

(Embodiment 2)
In this embodiment, a transistor configuration applicable to the configuration of the semiconductor device described in the above embodiment, specifically, a configuration in which transistors having different electrical characteristics are laminated and provided will be described. With this configuration, the degree of freedom in designing semiconductor devices can be increased. Further, by stacking transistors having different electrical characteristics, the degree of integration of the semiconductor device can be increased.

The semiconductor device shown in FIG. 12 includes a transistor 300, a transistor 500, and a capacitive element 600. 14 (A) is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 14 (B) is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 14 (C) is a cross-sectional view of the transistor 300 in the channel width direction. It is a figure.

The transistor 500 is a transistor (OS transistor) having a metal oxide in the channel forming region. Since the transistor 500 has a small off-current, it is possible to hold the written data voltage or charge for a long period of time by using the transistor 500 for an OS transistor included in a semiconductor device. That is, since the frequency of the refresh operation is low or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.

As shown in FIG. 12, the semiconductor device described in this embodiment includes a transistor 300, a transistor 500, and a capacitive element 600. The transistor 500 is provided above the transistor 300, and the capacitive element 600 is provided above the transistor 300 and the transistor 500. The capacitive element 600 can be a capacitive element Cs or the like in the memory circuit MC.

The transistor 300 is provided on the substrate 311 and has a semiconductor region 313 composed of a conductor 316, an insulator 315, and a part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b. .. The transistor 300 can be applied to, for example, the transistor included in the buffer circuit 17 in the above embodiment.

As shown in FIG. 14C, the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315. As described above, by making the transistor 300 a Fin type, the on characteristic of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.

The transistor 300 may be either a p-channel type or an n-channel type.

It is preferable to include a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like. It preferably contains crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.

In the low resistance region 314a and the low resistance region 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or p-type conductivity such as boron are imparted. Contains elements that

The conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

The transistor 300 shown in FIG. 12 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method. For example, when the semiconductor device is a unipolar circuit containing only OS transistors (meaning transistors having the same polarity as n-channel transistors only, etc.), as shown in FIG. 13, the transistor 300 is configured by using an oxide semiconductor. The configuration may be the same as that of the transistor 500. The details of the transistor 500 will be described later.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.

In the present specification, silicon nitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride as its composition means a material having a higher nitrogen content than oxygen as its composition. Is shown. Further, in the present specification, aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen, and aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.

The insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 300 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, for the insulator 324, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 500 is provided from the substrate 311 or the transistor 300.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

The amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS). For example, in the TDS analysis, the amount of hydrogen desorbed from the insulator 324 is the amount desorbed in terms of hydrogen atoms in the range of 50 ° C. to 500 ° C. in the surface temperature of the film, which is converted into the area of the insulator 324. It may be 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitive element 600, a conductor 328 connected to the transistor 500, a conductor 330, and the like. The conductor 328 and the conductor 330 have a function as a plug or wiring. Further, in the conductor having a function as a plug or wiring, a plurality of structures may be collectively given the same reference numeral. Further, in the present specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 12, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug or wiring for connecting to the transistor 300. The conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 12, the insulator 360, the insulator 362, and the insulator 364 are laminated in this order. Further, a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or wiring. The conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 360, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 366 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. 12, the insulator 370, the insulator 372, and the insulator 374 are laminated in this order. Further, a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or wiring. The conductor 376 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 370, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 376 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. 12, the insulator 380, the insulator 382, and the insulator 384 are laminated in this order. Further, a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 has a function as a plug or wiring. The conductor 386 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 380, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 386 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment is described. It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be 3 or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be 5 or more.

An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are laminated on the insulator 384 in this order. As any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516, it is preferable to use a substance having a barrier property against oxygen and hydrogen.

For example, for the insulator 510 and the insulator 514, a film having a barrier property such that hydrogen and impurities are not diffused from the region where the substrate 311 or the transistor 300 is provided to the region where the transistor 500 is provided is used. Is preferable. Therefore, the same material as the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

Further, as the film having a barrier property against hydrogen, for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

Further, for example, the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 512 and the insulator 516, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, a conductor 518, a conductor constituting the transistor 500 (for example, a conductor 503) and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. The conductor 518 has a function as a plug or wiring for connecting to the capacitive element 600 or the transistor 300. The conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.

In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

A transistor 500 is provided above the insulator 516.

As shown in FIGS. 14 (A) and 14 (B), the transistor 500 is arranged on the conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, and on the insulator 516 and the conductor 503. An insulator 520, an insulator 522 placed on the insulator 520, an insulator 524 placed on the insulator 522, an oxide 530a placed on the insulator 524, and an oxide 530a. The oxide 530b arranged on the oxide 530b, the conductors 542a and the conductors 542b arranged apart from each other on the oxide 530b, and the conductors 542a and the conductors 542b arranged on the conductors 542a and 542b. Formation of an insulator 580 in which an opening is formed by superimposing between the two, an oxide 530c arranged on the bottom surface and side surfaces of the opening, an insulator 550 arranged on a formation surface of the oxide 530c, and an insulator 550. It has a conductor 560 arranged on a surface.

Further, as shown in FIGS. 14A and 14B, it is preferable that the insulator 544 is arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. .. Further, as shown in FIGS. 14A and 14B, the conductor 560 includes a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. And, it is preferable to have. Further, as shown in FIGS. 14A and 14B, it is preferable that the insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 550.

In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

The transistor 500 shows a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated in a region where a channel is formed and in the vicinity thereof, but the present invention is limited to this. It's not a thing. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a laminated structure of four or more layers may be provided. Further, in the transistor 500, the conductor 560 is shown as a two-layer laminated structure, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers. Further, the transistor 500 shown in FIGS. 12 and 14A is an example, and the transistor 500 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

Here, the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.

Further, since the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved and high frequency characteristics can be provided.

The conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made larger than 0V, and the off-current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.

The conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done. In the present specification and the like, the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is called a slurried channel (S-channel) structure.

Further, the conductor 503 has the same structure as the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside. Although the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.

Here, as the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.) (the above oxygen is difficult to permeate). In the present specification, the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

For example, since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.

When the conductor 503 also has a wiring function, it is preferable to use a highly conductive conductive material containing tungsten, copper, or aluminum as a main component for the conductor 503b. In that case, the conductor 505 does not necessarily have to be provided. Although the conductor 503b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.

The insulator 520, the insulator 522, the insulator 524, and the insulator 550 have a function as a second gate insulating film.

Here, as the insulator 524 in contact with the oxide 530, it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 524 has an excess oxygen region formed therein. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiency in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. Oxides that desorb oxygen by heating are those whose oxygen desorption amount in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis. An oxide film of 0.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ or more, or 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.

Further, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).

Since the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, the oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 and the oxide 530.

The insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO ₃ (BST) in a single layer or in a laminated manner. As the transistor becomes finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for an insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing diffusion of impurities and oxygen (which oxygen is difficult to permeate). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator 522 is formed using such a material, the insulator 522 suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530. Functions as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride or silicon nitride may be laminated and used on the above-mentioned insulator.

Further, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon nitride nitride are suitable because they are thermally stable. Further, by combining the insulator of the high-k material with silicon oxide or silicon oxide nitride, it is possible to obtain an insulator 520 having a laminated structure that is thermally stable and has a high relative permittivity, and an insulator 526.

In the transistor 500 of FIGS. 14A and 14B, an insulator 520, an insulator 522, and an insulator 524 are shown as a second gate insulating film having a three-layer laminated structure. The gate insulating film of 2 may have a single layer, two layers, or a laminated structure of four or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

For the transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region. For example, as the oxide 530, an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium). , One or more selected from hafnium, tantalum, tungsten, magnesium and the like) and the like may be used. In particular, the In—M—Zn oxide applicable as the oxide 530 is preferably CAAC-OS or CAC-OS described in the fourth embodiment. Further, as the oxide 530, an In—Ga oxide or an In—Zn oxide may be used.

As the metal oxide that functions as a channel forming region in the oxide 530, it is preferable to use an oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.

By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b. Further, by having the oxide 530c on the oxide 530b, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b.

The oxide 530 preferably has a laminated structure due to oxides having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 530b. Is preferable. Further, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a. Further, as the oxide 530c, a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.

Further, it is preferable that the energy at the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy at the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b.

Here, at the junction of the oxide 530a, the oxide 530b, and the oxide 530c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, thereby forming a mixed layer having a low defect level density. be able to. For example, when the oxide 530b is an In—Ga—Zn oxide, In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide or the like may be used as the oxide 530a and the oxide 530c.

At this time, the main path of the carrier is the oxide 530b. By making the oxide 530a and the oxide 530c have the above-mentioned constitution, the defect level density at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

A conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b. The conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. , Iridium, strontium, a metal element selected from lanthanum, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen. Further, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

Further, in FIG. 14, the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be laminated. Further, the titanium film and the aluminum film may be laminated. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may have a two-layer structure in which copper films are laminated.

Further, a three-layer structure, a molybdenum film or a molybdenum film or a titanium film having a titanium film or a titanium nitride film and an aluminum film or a copper film laminated on the titanium film or the titanium nitride film and further forming a titanium film or a titanium nitride film on the aluminum film or the copper film. There is a three-layer structure in which a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed on the aluminum film or a copper film. A transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

Further, as shown in FIG. 14A, when the region 543a and the region 543b are formed as low resistance regions at the interface of the oxide 530 with the conductor 542a (conductor 542b) and its vicinity thereof. There is. At this time, the region 543a functions as one of the source region or the drain region, and the region 543b functions as the other of the source region or the drain region. Further, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier density of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.

The insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and come into contact with the insulator 524.

As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium and the like. Can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.

In particular, as the insulator 544, it is preferable to use aluminum or an oxide containing one or both oxides of hafnium, such as aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate). .. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the thermal history in a later step. If the conductors 542a and 542b are made of a material having oxidation resistance, or if the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.

By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b via the oxide 530c and the insulator 550. Further, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen contained in the insulator 580.

The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is arranged in contact with the inside (upper surface and side surface) of the oxide 530c. Similar to the above-mentioned insulator 524, the insulator 550 is preferably formed by using an insulator that contains excessive oxygen and releases oxygen by heating.

Specifically, silicon oxide having excess oxygen, silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, and silicon oxide to which nitrogen is added, and vacancies are used. Silicon oxide having can be used. In particular, silicon oxide and silicon nitride nitride are preferable because they are stable against heat.

By providing an insulator that releases oxygen by heating as an insulator 550 in contact with the upper surface of the oxide 530c, oxygen is effectively applied from the insulator 550 to the channel forming region of the oxide 530b through the oxide 530c. Can be supplied. Further, as with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

Further, in order to efficiently supply the excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing the metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

The insulator 550 may have a laminated structure as in the case of the second gate insulating film. As the transistor becomes finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, an insulator that functions as a gate insulating film is heat-k material and heat. By forming a laminated structure with a material that is stable, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative permittivity can be obtained.

Although the conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 14A and 14B, it may have a single-layer structure or a laminated structure of three or more layers.

The conductor 560a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ₍ N2O, NO, _NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Further, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be called an OC (Oxide Conductor) electrode.

Further, as the conductor 560b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.

The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and silicon oxide added with nitrogen, oxidation having pores. It is preferable to have silicon, resin, or the like. In particular, silicon oxide and silicon nitride nitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

The opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

In miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 may have a shape having a high aspect ratio. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.

The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 into a film by a sputtering method, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.

For example, as the insulator 574, use one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Can be done.

In particular, aluminum oxide has a high barrier property, and even a thin film of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.

Further, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. It is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the membrane, similarly to the insulator 524 and the like.

Further, the conductor 540a and the conductor 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same configuration as the conductor 546 and the conductor 548 described later.

An insulator 582 is provided on the insulator 581. As the insulator 582, it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

Further, an insulator 586 is provided on the insulator 582. As the insulator 586, the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 586, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include the conductor 546 and the conductor 548. Is embedded.

The conductor 546 and the conductor 548 have a function as a plug or wiring for connecting to the capacitive element 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be provided by using the same materials as the conductor 328 and the conductor 330.

Subsequently, a capacitive element 600 is provided above the transistor 500. The capacitive element 600 has a conductor 610, a conductor 620, and an insulator 630.

Further, the conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 has a function as a plug or wiring for connecting to the transistor 500. The conductor 610 has a function as an electrode of the capacitive element 600. The conductor 612 and the conductor 610 can be formed at the same time.

The conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components. (Tantal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) and the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium zinc oxide.

In FIG. 12, the conductor 612 and the conductor 610 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having the barrier property and the conductor having a high conductivity.

The conductor 620 is provided so as to be superimposed on the conductor 610 via the insulator 630. As the conductor 620, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be provided by using the same material as the insulator 320. Further, the insulator 640 may function as a flattening film that covers the uneven shape below the insulator 640.

By using this structure, it is possible to achieve miniaturization or high integration in a semiconductor device using a transistor having an oxide semiconductor.

(Embodiment 3)
In this embodiment, an IC chip, an electronic component, an electronic device, and the like will be described as an example of a semiconductor device.

<Example of manufacturing method of electronic parts>
FIG. 15A is a flowchart showing an example of a method for manufacturing an electronic component. Electronic components are also referred to as semiconductor packages or IC packages. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in the present embodiment, an example thereof will be described.

A semiconductor device composed of transistors is completed by combining a plurality of removable parts on a printed circuit board through an assembly process (post-process). The post-process can be completed by going through each process shown in FIG. 15 (A). Specifically, after the element substrate obtained in the previous step is completed (step ST71), the back surface of the substrate is ground. At this stage, the substrate is thinned to reduce the warpage of the substrate in the previous process and to reduce the size of the parts. Next, a dicing step of separating the substrate into a plurality of chips is performed (step ST72).

FIG. 15B is a top view of the semiconductor wafer 7100 before the dicing step is performed. 15 (C) is a partially enlarged view of FIG. 15 (B). The semiconductor wafer 7100 is provided with a plurality of circuit regions 7102. A semiconductor device according to the embodiment of the present invention is provided in the circuit region 7102.

Each of the plurality of circuit areas 7102 is surrounded by a separation area 7104. A separation line (also referred to as a “dicing line”) 7106 is set at a position overlapping the separation region 7104. In the dicing step ST72, the semiconductor wafer 7100 is cut along the separation line 7106 to cut out the chip 7110 including the circuit region 7102 from the semiconductor wafer 7100. FIG. 15 (D) shows an enlarged view of the chip 7110.

A conductive layer or a semiconductor layer may be provided in the separation region 7104. By providing the conductive layer or the semiconductor layer in the separation region 7104, ESD that may occur during the dicing step can be alleviated, and the decrease in yield due to the dicing step can be prevented. Further, in general, the dicing step is performed while supplying pure water having a reduced specific resistance by dissolving carbon dioxide gas or the like to the cutting portion for the purpose of cooling the substrate, removing shavings, preventing static electricity, and the like. By providing a conductive layer or a semiconductor layer in the separation region 7104, the amount of pure water used can be reduced. Therefore, the production cost of the semiconductor device can be reduced. In addition, the productivity of semiconductor devices can be increased.

After performing step ST72, a die bonding step is performed in which the separated chips are individually picked up, mounted on a lead frame, and bonded (step ST73). As the bonding method between the chip and the lead frame in the die bonding process, a method suitable for the product may be selected. For example, adhesion may be performed by resin or tape. In the die bonding step, the chip may be mounted on the interposer and bonded. In the wire bonding step, the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step ST74). A silver wire or a gold wire can be used as the thin metal wire. The wire bonding may be either ball bonding or wedge bonding.

The wire-bonded chips are subjected to a molding process in which they are sealed with an epoxy resin or the like (step ST75). By performing the molding process, the inside of the electronic component is filled with resin, damage to the built-in circuit part and wire due to mechanical external force can be reduced, and deterioration of characteristics due to moisture and dust can be reduced. can. The leads of the lead frame are plated. Then, the lead is cut and molded (step ST76). The plating process prevents rust on the leads, and soldering can be performed more reliably when mounting on a printed circuit board later. A printing process (marking) is applied to the surface of the package (step ST77). The electronic component is completed through the inspection step (step ST78) (step ST79).

A schematic perspective view of the completed electronic component is shown in FIG. 15 (E). FIG. 15E shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. As shown in FIG. 15E, the electronic component 7000 has a lead 7001 and a chip 7110.

The electronic component 7000 is mounted on, for example, the printed circuit board 7002. A plurality of such electronic components 7000 are combined and electrically connected to each other on the printed circuit board 7002 so that they can be mounted on an electronic device. The completed circuit board 7004 is provided inside an electronic device or the like.

Electronic components 7000 include digital signal processing, software radio, avionics (electronic equipment related to aviation such as communication equipment, navigation systems, automatic control devices, flight management systems, etc.), ASIC prototyping, medical image processing, voice recognition, encryption, etc. It can be applied to electronic components (IC chips) of electronic devices in a wide range of fields such as bioinformatics (biological information science), emulators of mechanical devices, and radio telescopes in radio astronomy. Such electronic devices include cameras (video cameras, digital still cameras, etc.), display devices, personal computers (PCs), mobile phones, game machines including portable devices, portable information terminals (smartphones, tablet information terminals, etc.). ), Electronic book terminals, wearable information terminals (clock type, head mount type, goggles type, glasses type, arm badge type, bracelet type, necklace type, etc.), navigation system, sound reproduction device (car audio, digital audio player, etc.) , Copiers, facsimiles, printers, multifunction printers, automatic cash deposit / payment machines (ATMs), vending machines, household appliances, etc.

<Example of application to electronic devices>
Next, for electronic devices such as computers, mobile information terminals (including mobile phones, portable game machines, sound reproduction devices, etc.), electronic papers, television devices (also referred to as televisions or television receivers), and digital video cameras. , The case where the above-mentioned electronic component is applied will be described.

FIG. 16A is a portable information terminal, which is composed of a housing 901, a housing 902, a first display unit 903a, a second display unit 903b, and the like. At least a part of the housing 901 and the housing 902 is provided with the semiconductor device shown in the previous embodiment.

The first display unit 903a is a panel having a touch input function. For example, as shown in the left figure of FIG. 16A, the selection button 904 displayed on the first display unit 903a "touch input". You can select whether to perform "keyboard input". Since the selection button can be displayed in various sizes, people of all ages can experience the ease of use. Here, for example, when "keyboard input" is selected, the keyboard 905 is displayed on the first display unit 903a as shown in the right figure of FIG. 16A. This makes it possible to quickly input characters by key input, as in the case of conventional information terminals.

Further, in the portable information terminal shown in FIG. 16A, one of the first display unit 903a and the second display unit 903b can be removed as shown in the right figure of FIG. 16A. .. The second display unit 903b is also a panel having a touch input function, which makes it possible to further reduce the weight when carrying it, and it is convenient because the housing 902 can be held by one hand and operated by the other hand. be.

The portable information terminal shown in FIG. 16A has a function of displaying various information (still images, moving images, text images, etc.), a function of displaying a calendar, a date, a time, etc. on the display unit, and a function of displaying the information on the display unit. It can have a function of manipulating or editing the information, a function of controlling processing by various software (programs), and the like. Further, the back surface or the side surface of the housing may be provided with an external connection terminal (earphone terminal, USB terminal, etc.), a recording medium insertion portion, or the like.

Further, the portable information terminal shown in FIG. 16A may be configured to be able to transmit and receive information wirelessly. It is also possible to purchase and download desired book data or the like from an electronic book server wirelessly.

Further, the housing 902 shown in FIG. 16A may be provided with an antenna, a microphone function, and a wireless function, and may be used as a mobile phone.

FIG. 16B is an electronic book terminal 910 on which electronic paper is mounted, and is composed of two housings, a housing 911 and a housing 912. The housing 911 and the housing 912 are provided with a display unit 913 and a display unit 914, respectively. The housing 911 and the housing 912 are connected by a shaft portion 915, and the opening / closing operation can be performed with the shaft portion 915 as an axis. Further, the housing 911 includes a power supply 916, an operation key 917, a speaker 918, and the like. At least one of the housing 911 and the housing 912 is provided with the semiconductor device shown in the previous embodiment.

FIG. 16C is a television device, which is composed of a housing 921, a display unit 922, a stand 923, and the like. The operation of the television device 920 can be performed by the switch provided in the housing 921 or the remote controller operating device 924. The housing 921 and the remote controller operating device 924 are provided with the semiconductor device shown in the previous embodiment.

FIG. 16D shows a smartphone, and the main body 930 is provided with a display unit 931, a speaker 932, a microphone 933, an operation button 934, and the like. The semiconductor device shown in the previous embodiment is provided in the main body 930.

FIG. 16E is a digital camera, which is composed of a main body 941, a display unit 942, an operation switch 943, and the like. The semiconductor device shown in the previous embodiment is provided in the main body 941.

As described above, the electronic device shown in the present embodiment is provided with the semiconductor device according to the previous embodiment.

(Additional notes regarding the description of this specification, etc.)
The above-described embodiments and explanations of the respective configurations in the embodiments will be described below.

The configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.

In addition, the content described in one embodiment (may be a part of the content) is another content (may be a part of the content) described in the embodiment, and / or one or more. It is possible to apply, combine, or replace the contents described in another embodiment (some contents may be used).

In addition, the content described in the embodiment is the content described by using various figures or the content described by using the text described in the specification in each embodiment.

It should be noted that the figure (which may be a part) described in one embodiment is another part of the figure, another figure (which may be a part) described in the embodiment, and / or one or more. By combining the figures (which may be a part) described in another embodiment of the above, more figures can be formed.

Further, in the present specification and the like, in the block diagram, the components are classified by function and shown as blocks independent of each other. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved in a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately paraphrased according to the situation.

Further, in the drawings, the size, the thickness of the layer, or the area are shown in any size for convenience of explanation. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.

In the present specification and the like, when explaining the connection relationship of transistors, "one of the source or drain" (or the first electrode or the first terminal) and the other of the source and drain are "the other of the source or drain" (or the other). The notation (second electrode or second terminal) is used. This is because the source and drain of the transistor change depending on the structure of the transistor, operating conditions, and the like. The names of the source and drain of the transistor can be appropriately paraphrased according to the situation, such as the source (drain) terminal and the source (drain) electrode.

Further, in the present specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring" and vice versa. Further, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally formed.

Further, in the present specification and the like, the voltage and the potential can be paraphrased as appropriate. The voltage is a potential difference from a reference potential. For example, if the reference potential is a ground voltage (ground voltage), the voltage can be paraphrased as a potential. The ground potential does not always mean 0V. The potential is relative, and the potential given to the wiring or the like may be changed depending on the reference potential.

In the present specification and the like, terms such as "membrane" and "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

In the present specification and the like, the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows. Alternatively, the switch means a switch having a function of selecting and switching a path through which a current flows.

In the present specification and the like, the channel length means, for example, in the top view of a transistor, a region or a channel where a semiconductor (or a part where a current flows in the semiconductor when the transistor is on) and a gate overlap is formed. The distance between the source and the drain in the area.

In the present specification and the like, the channel width is a source in, for example, a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap, or a region where a channel is formed. The length of the part where the drain and the drain face each other.

In the present specification and the like, the fact that A and B are connected includes those in which A and B are directly connected and those in which A and B are electrically connected. Here, the fact that A and B are electrically connected means that an electric signal can be exchanged between A and B when an object having some kind of electrical action exists between A and B. It means what is said.

10 Semiconductor device 11 Memory cell array 12 Peripheral circuit 13 Voltage holding circuit 14 Voltage generation circuit 17_1 Buffer circuit 17_1 Buffer circuit 18_1 Capacitive element 18_2 Capacitive element

Claims (7)

It has a memory cell, a drive circuit, a voltage holding circuit, a buffer circuit, and a capacitive element.
The memory cell has a first transistor and
The first transistor has a first semiconductor layer, a first gate electrode, and a first back gate electrode.
The first gate electrode is electrically connected to the first wiring.
The first backgate electrode is electrically connected to the second wiring.
The drive circuit has a function of giving a signal for controlling the conduction state of the first transistor to the first wiring.
The voltage holding circuit has a function of applying a voltage for controlling the threshold voltage of the first transistor to the second wiring.
The voltage holding circuit has a function of electrically suspending the second wiring during a period in which a signal for controlling the conduction state of the first transistor is given to the first wiring.
The input terminal of the buffer circuit is electrically connected to the first wiring.
The output terminal of the buffer circuit is electrically connected to one of the electrodes of the capacitive element.
A semiconductor device in which the other electrode of the capacitive element is electrically connected to the second wiring. It has a memory cell, a drive circuit, a voltage holding circuit, a buffer circuit, and a capacitive element.
The memory cell has a first transistor and
The first transistor has a first semiconductor layer, a first gate electrode, and a first back gate electrode.
The first gate electrode is electrically connected to the first wiring.
The first backgate electrode is electrically connected to the second wiring.
The drive circuit has a function of giving a signal for controlling the conduction state of the first transistor to the first wiring.
The voltage holding circuit has a function of applying a voltage for controlling the threshold voltage of the first transistor to the second wiring.
The voltage holding circuit has a second transistor and has a second transistor.
The second transistor has a second semiconductor layer and a second gate electrode.
The second gate electrode is electrically connected to one of the source or drain of the second transistor.
The input terminal of the buffer circuit is electrically connected to the first wiring.
The output terminal of the buffer circuit is electrically connected to one of the electrodes of the capacitive element.
A semiconductor device in which the other electrode of the capacitive element is electrically connected to the second wiring. In claim 2,
The second semiconductor layer is a semiconductor device characterized by having an oxide semiconductor. In claim 2 or 3,
The first transistor and the second transistor are n-channel type transistors, and are
A semiconductor device in which the threshold voltage of the second transistor is larger than the threshold voltage of the first transistor when the first gate electrode and the first back gate electrode have the same potential. In any one of claims 1 to 4,
The buffer circuit is a semiconductor device having a function of boosting the voltage of the input terminal and outputting the voltage to the output terminal. The semiconductor device according to any one of claims 1 to 5.
With at least one of the antenna, battery, operation switch, microphone, or speaker,
Have an electronic device. Having a plurality of semiconductor devices according to any one of claims 1 to 5,
A semiconductor wafer having a separation region.

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