JP6942612B2 - Storage devices, semiconductor wafers, electronic devices - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device, particularly a storage device.

Further, one embodiment of the present invention relates to a product, a method, or a manufacturing method. Alternatively, one embodiment of the invention relates to a process, machine, manufacture, or composition of matter. One embodiment of the present invention relates to a method for driving a semiconductor device or a method for manufacturing the same.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Display devices, electro-optical devices, power storage devices, semiconductor circuits and electronic devices may include semiconductor devices.

As the semiconductor storage device, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), flash memory and the like are widely used.

SRAM has a high write speed and read speed. However, since the number of transistors constituting the memory cell is large, it is difficult to improve the memory cell density, that is, to achieve high integration. In addition, the static power consumption requires high power consumption for data retention. Further, since it is a volatile storage device, it is difficult to use it as a storage device for so-called normal off-computing, in which the supply of power supply voltage is frequently stopped and the storage device operates only when necessary.

DRAM has a high write speed and read speed. Further, since the number of transistors constituting the memory cell is small, it is possible to improve the memory cell density, that is, to achieve high integration. However, a refresh operation is required for data retention, and power consumption is high. Moreover, since it is a volatile storage device, it is difficult to use it as a storage device for normal off-computing.

Since the number of transistors constituting the memory cell is small in the flash memory, the memory cell density can be improved, that is, the memory cell can be highly integrated. In addition, a laminated structure, so-called 3D, enables further high integration. Further, since it is a non-volatile storage device, the power consumption required for data retention is low. However, the writing speed and the reading speed are slow. In addition, power consumption is high because a high voltage is required for writing. Therefore, it is difficult to use it as a storage device for normal off-computing because it is difficult to write data frequently with low power consumption.

Further, a transistor using an oxide semiconductor has attracted attention (Patent Document 1). Transistors using oxide semiconductors have a very small off-current. Taking advantage of this, Patent Document 2 discloses a non-volatile memory using an oxide semiconductor transistor. These non-volatile memories have no limit on the number of times data can be rewritten, and consume less power when rewriting data.

Japanese Unexamined Patent Publication No. 2007-123861 Japanese Unexamined Patent Publication No. 2011-151383

When increasing the density of memory cells in a storage device, it is effective to arrange a large number of memory cells in a matrix. In this case, it is necessary to write (or read) data to all the memory cells connected to the signal line provided for each row at the same time. In order to write (or read) the data of all the memory cells in each row at the same time, it is necessary to supply a signal with a large number of bits. In particular, when the number of values is increased by forming the memory cells in a stacked structure, a signal having a large number of bits is supplied. It is extremely difficult to write signals having a large number of bits at the same time.

One of the problems of one embodiment of the present invention is to provide a storage device capable of efficiently writing multi-valued data. Another object of the present invention is to provide a storage device having a highly integrated memory cell. Another object of the present invention is to provide a storage device having stacked memory cells. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but may solve at least one problem. Moreover, the description of the above-mentioned problem does not prevent the existence of other problem. Issues other than these are naturally clarified from the description of the specification, claims, drawings, etc., and it is possible to extract issues other than these from the description of the specification, claims, drawings, etc. It is possible.

One embodiment of the present invention is a storage device including a memory cell, a first circuit, first to fourth signal lines, and a first power supply line. The memory cell includes a first transistor, a second transistor, and a first capacitance element. The first circuit includes a third transistor, a fourth transistor, a second capacitance element, and a second power supply line. One of the source and drain of the first transistor is electrically connected to the first signal line. The other of the source or drain of the first transistor is electrically connected to the gate of the second transistor. The gate of the first transistor is electrically connected to the second signal line. The first transistor has a metal oxide in the channel forming region. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the second transistor is electrically connected to the first power line. The first terminal of the first capacitive element is electrically connected to the gate of the second transistor. The second terminal of the first capacitance element is electrically connected to the third signal line. One of the source or drain of the third transistor is electrically connected to the first signal line. The other of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor. The third transistor has a metal oxide in the channel forming region. The gate of the third transistor is electrically connected to the fourth signal line. One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the third transistor. The other of the source or drain of the fourth transistor is electrically connected to the second power line. The first terminal of the second capacitance element is electrically connected to the gate of the fourth transistor. The second terminal of the second capacitance element is electrically connected to the second power supply line.

In the above embodiment, the first circuit has a function of storing the first analog data stored in the memory cell as the second analog data.

In the above embodiment, the storage device preferably includes a D / A converter, a fifth transistor, and a fifth signal line. The output terminal of the D / A converter is electrically connected to the gate of the fifth transistor. The drain current flowing through the fifth transistor flows through the fifth signal line. The fifth signal line is electrically connected to the first signal line.

In the above embodiment, the drain current flowing through the fifth transistor preferably flows through the fifth signal line via the current mirror circuit.

In the above embodiment, the storage device preferably includes an A / D converter, a sixth transistor, a sixth signal line, and a third power supply line. One of the source or drain of the sixth transistor is electrically connected to the sixth signal line. The other of the source or drain of the sixth transistor is electrically connected to the third power line. The input terminal of the A / D converter is electrically connected to the sixth signal line. The sixth signal line is electrically connected to the first signal line.

In the above embodiment, the A / D converter has a plurality of resistance elements connected in series and a plurality of comparators connected to one of the plurality of resistance elements.

One embodiment of the present invention is a storage device having a memory cell, a first circuit, a second circuit, first to fourth signal lines, and a first power supply line. The memory cell includes a first transistor, a second transistor, and a first capacitance element. The first circuit includes a third transistor, a fourth transistor, a second capacitance element, and a second power supply line. One of the source and drain of the first transistor is electrically connected to the first signal line. The other of the source or drain of the first transistor is electrically connected to the gate of the second transistor. The gate of the first transistor is electrically connected to the second signal line. The first transistor has a metal oxide in the channel forming region. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the second transistor is electrically connected to the first power line. The first terminal of the first capacitive element is electrically connected to the gate of the second transistor. The second terminal of the first capacitance element is electrically connected to the third signal line. One of the source or drain of the third transistor is electrically connected to the first signal line. The other of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor. The third transistor has a metal oxide in the channel forming region. The gate of the third transistor is electrically connected to the fourth signal line. One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the third transistor. The other of the source or drain of the fourth transistor is electrically connected to the second power line. The first terminal of the second capacitance element is electrically connected to the gate of the fourth transistor. The second terminal of the second capacitance element is electrically connected to the second power supply line. The first circuit has a function of storing the first analog data stored in the memory cell as the second analog data. The second circuit includes an A / D converter and a fifth signal line. The fifth signal line is electrically connected to the first signal line. The A / D converter has a function of converting the third analog data of the fifth signal line into digital data. The A / D converter has a comparator and a counter.

One embodiment of the present invention is a storage device having a memory cell, a first circuit, a second circuit, first to fourth signal lines, and a first power supply line. The memory cell includes a first transistor, a second transistor, and a first capacitance element. The first circuit includes a third transistor, a fourth transistor, a second capacitance element, and a second power supply line. One of the source and drain of the first transistor is electrically connected to the first signal line. The other of the source or drain of the first transistor is electrically connected to the gate of the second transistor. The gate of the first transistor is electrically connected to the second signal line. The first transistor has a metal oxide in the channel forming region. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the second transistor is electrically connected to the first power line. The first terminal of the first capacitive element is electrically connected to the gate of the second transistor. The second terminal of the first capacitance element is electrically connected to the third signal line. One of the source or drain of the third transistor is electrically connected to the first signal line. The other of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor. The third transistor has a metal oxide in the channel forming region. The gate of the third transistor is electrically connected to the fourth signal line. One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the third transistor. The other of the source or drain of the fourth transistor is electrically connected to the second power line. The first terminal of the second capacitance element is electrically connected to the gate of the fourth transistor. The second terminal of the second capacitance element is electrically connected to the second power supply line. The first circuit has a function of storing the first analog data stored in the memory cell as the second analog data. The second circuit includes an A / D converter and a fifth signal line. The fifth signal line is electrically connected to the first signal line. The A / D converter has a function of converting the third analog data of the fifth signal line into digital data. The A / D converter includes a comparator, a sequential conversion register, and a D / A converter.

One embodiment of the present invention is a storage device having a memory cell, a first circuit, first to fourth signal lines, a first power supply line, and a second power supply line. The memory cell includes a first transistor, a second transistor, and a first capacitance element. The first circuit includes a third transistor, a fourth transistor, and a second capacitance element. One of the source and drain of the first transistor is electrically connected to the first signal line. The other of the source or drain of the first transistor is electrically connected to the gate of the second transistor. The gate of the first transistor is electrically connected to the second signal line. The first transistor has a metal oxide in the channel forming region. One of the source or drain of the second transistor is electrically connected to one of the source or drain of the first transistor, and the other of the source or drain of the second transistor is electrically connected to the first power supply line. The second transistor is an n-channel transistor. The first terminal of the first capacitance element is electrically connected to the gate of the second transistor, and the second terminal of the first capacitance element is electrically connected to the third signal line. One of the source or drain of the third transistor is electrically connected to the first signal line, and the other of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor. The third transistor has a metal oxide in the channel forming region. The gate of the third transistor is electrically connected to the fourth signal line. One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the third transistor, and the other of the source or drain of the fourth transistor is electrically connected to the second power supply line. The first terminal of the second capacitance element is electrically connected to the gate of the fourth transistor, and the second terminal of the second capacitance element is electrically connected to the second power supply line. The fourth transistor is an n-channel transistor. The drain current flowing through the fourth transistor flows through the first signal line.

In the above embodiment, the first circuit preferably has a current mirror circuit. The drain current flowing through the fourth transistor flows through the current mirror circuit to the first signal line.

In the above embodiment, the first circuit can store the first analog data stored in the memory cell as the second analog data.

The storage device according to the above embodiment preferably includes a D / A converter, a fifth transistor, and a fifth signal line. The output terminal of the D / A converter is electrically connected to the gate of the fifth transistor. The drain current flowing through the fifth transistor flows through the fifth signal line. The fifth signal line is electrically connected to the first signal line.

The storage device according to the above embodiment preferably includes an A / D converter, a sixth transistor, a sixth signal line, and a third power supply line. One of the source or drain of the sixth transistor is electrically connected to the sixth signal line, and the other of the source or drain of the sixth transistor is electrically connected to the third power supply line. The input terminal of the A / D converter is electrically connected to the sixth signal line, and the sixth signal line is electrically connected to the first signal line.

One embodiment of the present invention is a semiconductor wafer having a plurality of storage devices according to the above embodiment and having a separation region.

One embodiment of the present invention is an electronic device having the storage device and the battery according to the above embodiment.

According to one embodiment of the present invention, it is possible to provide a storage device capable of efficiently writing multi-valued data. Further, according to one embodiment of the present invention, it is possible to provide a storage device having highly integrated memory cells. Further, according to one embodiment of the present invention, it is possible to provide a storage device having stacked memory cells. Moreover, according to one embodiment of the present invention, a novel semiconductor device can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one form of the present invention does not have to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

The block diagram which shows the configuration example of the storage device. A circuit diagram showing a configuration example of a memory cell. A circuit diagram showing a configuration example of a memory cell. A block diagram and a circuit diagram showing a configuration example of the circuit 20. The circuit diagram which shows the structural example of the A / D converter. A circuit diagram and a timing chart showing a configuration example of an A / D converter. A circuit diagram and a timing chart showing a configuration example of an A / D converter. A circuit diagram showing a configuration example of a selection circuit. A timing chart showing an operation example of the storage device. The block diagram which shows the configuration example of the storage device. A circuit diagram showing a configuration example of a selection circuit. The circuit diagram which shows the structural example of the circuit RD. A timing chart showing an operation example of the storage device. FIG. 5 is a cross-sectional view showing a configuration example of a storage device. FIG. 5 is a cross-sectional view showing a configuration example of a storage device. Top view and cross-sectional view showing a configuration example of a transistor. The cross-sectional view which shows the structural example of a transistor. The cross-sectional view which shows the structural example of a transistor. The figure explaining the range of the atomic number ratio of a metal oxide. Top view and cross-sectional view showing a configuration example of a transistor. A circuit diagram showing a configuration example of a memory cell. The block diagram which shows the configuration example of the storage device. Top view of the semiconductor wafer. A flowchart and a schematic perspective view illustrating an example of a manufacturing process of electronic components. The figure which shows the electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments, and that the embodiments and details can be variously changed without departing from the purpose and scope thereof. .. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.

In the present specification, the high power supply voltage may be referred to as H level (or _VDD ), and the low power supply voltage may be referred to as L level (or GND).

Further, in the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor, or simply OS) and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the metal oxide has at least one of an amplification action, a rectifying action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. Further, when it is described as an OS transistor or an OS FET, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

In addition, the present specification can appropriately combine the following embodiments. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

(Embodiment 1)
In the present embodiment, the storage device according to the present invention will be described with reference to FIGS. 1 to 9.

<Storage device 10A>
FIG. 1 is a block diagram showing a configuration example of the storage device 10A. The storage device 10A includes a circuit 20, a selection circuit 30, a memory cell array 40, a decoder 50, and a decoder 60.

The storage device 10A has a function of inputting data from the input terminal DIN and outputting the data from the output terminal DOUT.

The memory cell array 40 has memory cell MEMs arranged in a matrix of M rows and S × L columns. In addition, M is an integer of 2 or more, S is an integer of 2 or more, and L is an integer of 2 or more.

The memory cell MEM is a non-volatile memory. Further, the memory cell MEM can store N-bit (N is an integer of 1 or more) data. For example, for N = 2, the memory cell MEM can store data of 2 bits (4 values = ^{2 2).} For example, when N = 8, the memory cell MEM ^{can store 8} -bit (256 value = 28) data. That is, the memory cell MEM can store multi-valued data.

In addition, in this specification, multi-valued data refers to data larger than binary value.

The storage device 10A is one in each of the sets for each L column having the number of S (for example, the first column to the L column, the [(S-1) × L + 1] column to the S × L column, etc.). Data can be written and read to the memory cell MEM corresponding to the column and corresponding to one row of the first row to the Mth row. That is, data can be written and read from the memory cell MEM corresponding to one row in the S column at the same time. Assuming that the multi-valued data is N bits, the storage device 10A can write and read S × N bit data at the same time. That is, S × N bit data is input and output at the input terminal DIN and the output terminal DOUT, respectively.

The above values are examples. For example, the input terminal DIN and the output terminal DOUT may be terminals having different bit numbers. That is, it corresponds to one column in each of the S'sets of the first column to the L'column to the [(S'-1) x L'+ 1] column to the S'x L'column, and is the first column. Data can be written to the memory cell MEM corresponding to one row of rows 1 to M, and columns 1 to L'' to [(S''-1) × L'' + 1]. To read data from the memory cell MEM corresponding to one column in each of the S'' pairs of columns S'' × L'' and corresponding to one row of the first row to the Mth row. can. That is, data can be written to the memory cell MEM corresponding to one row in the S ″ column at the same time, and data can be read out from the memory cell MEM corresponding to the one row in the S ″ column at the same time. Here, assuming that the data is N bits, S ″ × N bits of data can be written at the same time, and S ″ × N bits of data can be read out. Note that S ″, L ″, S ″ and L ″ are integers of 2 or more, respectively.

The decoder 50 has a function of selecting a memory cell MEM to which data is written in row units. The decoder 50 decodes the address signal WADR and further supplies a selection signal to any of the signal lines WW [1] to WW [M] according to the control signal WRITE. Data supplied from the signal lines BL [1] to BL [S × L] is written to the memory cell MEM connected to the signal line WW selected by the decoder 50.

The decoder 60 has a function of selecting the memory cell MEM from which data is read in row units. The decoder 60 decodes the address signal RADR and further supplies a selection signal to any of the signal lines RW [1] to RW [M] according to the control signal READ. The memory cell MEM connected to the signal line RW selected by the decoder 60 supplies data to the signal lines BL [1] to BL [S × L].

The circuit 20 uses S × N-bit digital data supplied from the input terminal DIN as S N-bit digital data, and further generates S analog signals from S N-bit digital data, respectively. , Has a function of supplying signal lines WB [1] to WB [S].

Further, the circuit 20 generates N-bit digital data from each of the S analog signals supplied from the signal lines RB [1] to RB [S], and collectively outputs them as S × N-bit digital data. It has a function to output from the terminal DOUT.

The selection circuit 30 has a function of selecting a row of the memory cell array 40. The memory cell MEM selected by the selection circuit 30 writes and reads data, or reads data in advance.

The selection circuit 30 electrically connects the signal line WB [1] to any one of the signal lines BL [1] to BL [L] according to the signal supplied to the signal lines WS [1] to WS [L]. Then, the signal line WB [S] is electrically connected to any one of the signal lines BL [(S-1) × L + 1] to BL [S × L], and the power supply lines VB [1] to VB [S × L] is electrically connected to the power supply line VL described later.

Further, the selection circuit 30 electrically connects the signal line RB [1] with any one of the signal lines BL [1] to BL [L] according to the signal supplied to the signal lines RS [1] to RS [L]. Connect and electrically connect the signal line RB [S] to any one of the signal lines BL [(S-1) × L + 1] to BL [S × L], and connect the power supply lines VB [1] to VB [S]. XL] is electrically connected to the power supply line VH described later.

Further, the selection circuit 30 electrically connects the signal lines BL [1] to BL [S × L] to the circuit RD described later according to the signals supplied to the signal lines PRE [1] to PRE [L]. The power supply lines VB [1] to VB [S × L] are electrically connected to the power supply line VL described later.

<Memory cell MEM>
FIG. 2 is a circuit diagram showing a configuration example of the memory cell array 40. In FIG. 2, the memory cell MEM includes a transistor Tr1, a transistor Tr2, and a capacitance element C1. In the following, the transistor Tr1 and the transistor Tr2 will be described as n-channel transistors.

In the memory cell MEM, the gate of the transistor Tr1 is electrically connected to the signal line WW, one of the source or drain of the transistor Tr1 is electrically connected to the signal line BL, and the other of the source or drain of the transistor Tr1 is. It is electrically connected to the gate of the transistor Tr2. One of the source or drain of the transistor Tr2 is electrically connected to one of the source or drain of the transistor Tr1, and the other of the source or drain of the transistor Tr2 is electrically connected to the power supply line VB. The first terminal of the capacitive element C1 is electrically connected to the gate of the transistor Tr2, and the second terminal of the capacitive element C1 is electrically connected to the signal line RW. The gate of the transistor Tr2 may be referred to as a node N1.

The memory cell MEM can store N-bit data. Specifically, the memory cell MEM can store the potential corresponding to the N-bit data in the node N1.

An OS transistor can be used for the transistor Tr1 and the transistor Tr2. In particular, it is preferable to use an OS transistor for the transistor Tr1. The OS transistor has a small off current and is suitable. When the off-current is small, the voltage between the source and the drain is 1.8 V, and the normalized off-current per 1 μm of the channel width is 1 × 10 ^-20 A or less at room temperature and 1 at 85 ° C. × ^{10 -18} a or less, or refers to 1 × ^{10 -16} a or less that is at 125 ° C.. By using the OS transistor for the transistor Tr1, the memory cell MEM can hold the data stored in the node N1 for a long period of time. That is, the storage device 10A can be operated as a non-volatile memory.

Further, it is preferable to stack memory cells MEM sharing the same signal line BL and power supply line VB. Further, it is preferable to stack memory cells MEM sharing the same signal line WW and signal line RW. For example, the OS transistors constituting the memory cells MEM [1, 1] to MEM [1, S × L] are provided in the first layer, and the memory cells MEM [2, 1] to MEM [2, S × L] are provided. It is possible to provide the OS transistors to be configured in the second layer and to provide the OS transistors constituting the memory cells MEM [M, 1] to MEM [M, S × L] in the third layer.

FIG. 3 is an example in which memory cells MEM [1, 1] to MEM [M, 1] sharing the signal line BL [1] and the power supply line VB [1] are stacked. In this case, the transistor Tr1 and the transistor Tr2 are formed by using an OS transistor. By doing so, it is possible to provide a storage device having highly integrated memory cells.

The explanation is returned to FIG. 2 again. When the H level is given to the signal line WW, the first potential corresponding to the data supplied from the signal line BL is stored in the node N1. At this time, it is preferable that the signal line RW has a high potential and the power supply line VB has a low potential. Further, it is assumed that the transistor Tr2 operates in the saturation region.

When the L level is given to the signal line WW, the memory cell MEM turns off the transistor Tr1 and holds the first potential stored in the node N1. Since the off current of the transistor Tr1 is small, the first potential stored in the node N1 is held while the transistor Tr1 is in the off state.

When a high potential is applied to the signal line RW, the transistor Tr2 supplies a current corresponding to the first potential to the signal line BL. At this time, the transistor Tr2 is assumed to operate in the saturation region.

The storage device 10A writes multi-valued data to the memory cell MEM by converting the current value flowing through the signal line BL into a potential stored in the node N1. Further, the storage device 10A can read the multi-valued data written in the memory cell MEM by converting the potential stored in the node N1 into the current value flowing in the signal line BL. That is, the storage device 10A writes and reads multi-valued data via the current flowing through the signal line BL. By doing so, the storage device 10A is less likely to be affected by the parasitic capacitance of the signal line BL, and can write and read multi-valued data with higher accuracy.

<Circuit 20>
FIG. 4A is a block diagram showing a configuration example of the circuit 20. The circuit 20 has circuits 21 [1] to 21 [S] and circuits 22 [1] to 22 [S].

The S × N bit digital data input from the input terminal DIN is divided into N bits and distributed to the circuits 21 [1] to 21 [S], respectively. The circuits 21 [1] to 21 [S] have a function of converting the received N-bit digital data into analog data and outputting the received N-bit digital data to the signal lines WB [1] to WB [S], respectively.

The circuits 22 [1] to 22 [S] have a function of converting analog data input from the signal lines RB [1] to RB [S] into N-bit digital data and outputting the analog data. The circuits 22 [1] to 22 [S] have a function of generating digital data of S × N bits in total and outputting the digital data to the output terminal DOUT.

In the present specification, analog data refers to data that cannot be represented by two values (“1” and “0”, or “High” and “Low”). Multi-valued data such as 4-value and 8-value may be referred to as analog data.

FIG. 4B shows a specific circuit configuration example of the circuit 21, and FIG. 4C shows a specific circuit configuration example of the circuit 22.

In the present specification, the power supply line VH represents a power supply line to which a high potential is given, and the power supply line VL represents a power supply line to which a low potential is given.

The circuit 21 includes transistors Tr3 to Tr5 and a D / A converter 23. Here, it is assumed that the transistors Tr3 to Tr5 operate in the saturation region. Known configurations such as a resistance method and a capacitance method can be applied to the D / A converter 23.

The D / A converter 23 converts N-bit digital data among the S × N-bit data supplied from the input terminal DIN into analog data, and outputs this as the gate potential of the transistor Tr3. The transistor Tr3 supplies the drain current corresponding to the gate potential to the transistor Tr4. Since the transistor Tr4 and the transistor Tr5 form a current mirror circuit, the current flowing through the transistor Tr4 is supplied to the signal line WB. That is, the circuit 21 has a function of supplying a current corresponding to N-bit digital data supplied from the input terminal DIN to the signal line WB.

The circuit 22 includes a transistor Tr6 and an A / D converter 24. The transistor Tr6 functions as a constant current source by the bias voltage supplied from the signal line RBIAS. The A / D converter 24 has a function of outputting the potential (analog data) of the signal line RB to the output terminal DOUT as N-bit digital data.

<A / D converter 24>
Next, specific circuit configuration examples (A / D converters 24a, 24b, 24c) of the A / D converter 24 will be described with reference to FIGS. 5 to 7.

[A / D converter 24a]
The A / D converter 24a shown in FIG. 5 includes resistance elements 25 [1] to 25 [2 ^N ], comparators 26 [1] to 26 [2 ^N -1], and an encoder 27.

The resistance elements 25 [1] to 25 [2 ^N ] divide the voltage between the power supply line ADH and the power supply line ADL into resistors ^{to generate 2 N-} 1 reference potentials. A high potential is given to the power supply line ADH, and a low potential is given to the power supply line ADL.

One of the above-mentioned reference potentials is supplied to one input terminal of the comparator 26, and the potential (analog data) of the signal line RB is supplied to the other input terminal. When the potential is higher than the reference potential, the output of the comparator 26 is H level, and in other cases, the output of the comparator 26 is L level.

The encoder 27 encodes the outputs of the comparators 26 [1] to 26 [2 ^N -1] to output N-bit data from the output terminal DOUT.

The A / D converter 24a has a high processing speed and can perform A / D conversion at high speed.

Further, the A / D converter 24a can also handle multi-valued data of N bits or less. As a result, the storage device 10A can variably handle multi-valued data from 1 bit to N bits.

[A / D converter 24b]
The A / D converter 24b shown in FIG. 6A includes a comparator 80, a latch 81, an AND circuit 82, and a counter 83. The A / D converter 24b is a single slope type A / D converter. Further, the latch 81 and the AND circuit 82 are clock gating circuits and have a function of stabilizing the operation of the counter 83.

Hereinafter, an operation example of the A / D converter 24b will be described with reference to the timing chart shown in FIG. 6 (B). The signal RAMP is supplied to one input terminal of the comparator 80, and the analog potential of the signal line RB is supplied to the other input terminal.

At time T31 to time T40, the signal CLK (clock signal) is input while gradually increasing the potential supplied as the signal RAMP. The counter 83 counts the number of pulses of the input signal GCLK (gate clock signal). By setting the signal RST (reset signal) to H level at time T31, the output terminal DOUT outputs L level.

At time T31 to time T36, the potential of the signal line RB is higher than the potential of the signal RAMP. Therefore, the signal CMP output by the comparator 80 is at the H level, and the count value of the counter 83 increases one by one at the timing when the pulse of the signal GCLK (or signal CLK) rises. The count value (digital data) of the counter 83 is output to the output terminal DOUT.

At time T36 to time T37, the potential of the signal RAMP exceeds the potential of the signal line RB. Therefore, the signal CMP becomes L level.

After time T37, the signal GCLK is stopped by the clock gating circuit composed of the latch 81 and the AND circuit 82. Therefore, the count value of the counter 83 does not increase. The count value before the time T37 is output to the output terminal DOUT.

After the time T40, the A / D converter 24b can output N-bit digital data by using the count value of the counter 83 up to that point as the result of the A / D conversion.

The circuit scale of the A / D converter 24b can be reduced as compared with a flash type A / D converter such as the A / D converter 24a. Further, even if the number of bits of the multi-valued data to be handled becomes large, the circuit scale can be kept constant. As the degree of integration of the memory cell MEM increases, the area allocated to the circuits 22 [1] to 22 [S] decreases. The A / D converter 24b can be included in the circuits 22 [1] to 22 [S] even if the memory cell MEM has a high degree of integration.

Further, the A / D converter 24b can change the number of bits of the multi-valued data to be handled by adjusting the potential increase rate of the signal RAMP in FIG. 6B. For example, when the number of bits of the multi-valued data to be handled is large, the potential of the signal RAMP may be increased over a long period of time. For example, when the number of bits of the multi-valued data to be handled is small, the potential of the signal RAMP may be increased in a short time. As a result, the storage device 10A can arbitrarily select the number of bits of the multi-valued data to be handled.

[A / D converter 24c]
The A / D converter 24c shown in FIG. 7A is composed of a comparator 71, a SAR (sequential conversion register) 72, and a D / A converter 73. The SAR 72 has N registers 74 [N: 1], and the output terminal of each register 74 corresponds to the output terminal DOUT [N: 1] bit by bit.

The register 74 [N: 1] is reset when the signal RST, which is a reset signal, is at the H level (the output Q of the register 74 becomes the L level). Further, the register 74 [N: 1] is set when the signal SET [N: 1], which is a set signal, is at the H level (the output Q of the register 74 [N: 1] becomes the H level). Further, the register 74 [N: 1] stores the value of the input D when the pulse of the signal CLK [N: 1], which is a clock signal, rises, and becomes the output Q.

The signal output from the register 74 [N: 1] becomes a signal DACOUT (analog potential) in the D / A converter 73, and is input to one input terminal of the comparator 71. Further, the potential of the signal line RB is input to the other input terminal of the comparator 71. The output terminal of the comparator 71 is an input terminal of the register 74 [N: 1].

The signal SET [N] can be shared as a set signal of the register 74 [N] and a reset signal of the registers 74 [N-1] to 74 [1]. Further, the signal SET [N-1] can be shared as a set signal of the register 74 [N-1] and a clock signal of the register 74 [N]. Hereinafter, similarly, the signal SET [1] can be shared as a set signal of the register 74 [1] and a clock signal of the register 74 [2].

Hereinafter, an operation example of the A / D converter 24c will be described with reference to the timing chart shown in FIG. 7 (B).

At time T31, the signal RST is set to H level and the register 74 [N: 1] is reset. At this time, the output of the SAR 72 becomes the data "000 ... 00".

At time T32, the signal SET [N] is set to H level. At this time, the register 74 [N] is set, and the output of the SAR 72 becomes the data “100 ... 00”. Further, the potential of the signal DACOUT becomes the first potential corresponding to the data "100 ... 00". The comparator 71 compares the first potential with the potential of the signal line RB. Here, it is assumed that the potential of the signal line RB is higher than the first potential. That is, the signal CMP output from the comparator 71 becomes the H level.

At time T33, the signal CLK [N] and the signal SET [N-1] are set to H level. At this time, the register 74 [N] stores the H level of the signal CMP, the register 74 [N-1] is set, and the output of the SAR 72 becomes the data “110 ... 00”. Further, the potential of the signal DACOUT becomes a second potential corresponding to the data "110 ... 00". The comparator 71 compares the second potential with the potential of the signal line RB. Here, it is assumed that the potential of the signal line RB is lower than the second potential. That is, the signal CMP becomes the L level. Hereinafter, the same operation is repeated.

At time T36, the signal CLK [2] and the signal SET [1] are set to the H level. At this time, the register 74 [2] stores the L level of the signal CMP, the register 74 [1] is set, and the output of the SAR 72 becomes the data "100 ... 01". Further, the potential of the signal DACOUT becomes a third potential corresponding to the data "100 ... 01". The comparator 71 compares the potential of the third potential with the potential of the signal line RB. Here, it is assumed that the potential of the signal line RB is higher than the third potential. That is, the signal CMP becomes the H level.

At time T37, the signal CLK [1] is set to H level. At this time, the register 74 [1] stores the H level of the signal CMP, and the output of the SAR 72 becomes the data “100 ... 01”.

By setting the output of the SAR 72 to the output of the A / D converter 24c after the time T38, N-bit digital data "100 ... 01" can be acquired from the output terminal DOUT.

When the number of bits (N) of the multi-valued data handled by the A / D converter 24c is large, the circuit scale increases in proportion to N. Therefore, as ^{compared with the A / D converter 24a in which the circuit scale increases in proportion to N 2} , the circuit scale can be relatively reduced when the number of bits of the multi-valued data is large. As the degree of integration of the memory cell MEM increases, the area allocated to the circuits 22 [1] to 22 [S] decreases. The A / D converter 24c can be included in the circuits 22 [1] to 22 [S] even if the memory cell MEM has a high degree of integration.

The A / D converter 24c can also handle multi-valued data of N bits or less. As a result, the storage device 10A can arbitrarily select the number of bits of the multi-valued data to be handled in the range of 1 bit to N bits.

<Selection circuit 30>
FIG. 8 shows a circuit configuration example of the selection circuit 30. FIG. 8 shows a signal line WB [1] among the signal lines WB [1] to WB [S], a signal line RB [1] among the signal lines RB [1] to RB [S], and a signal line. The portion of BL [1] to BL [S × L] corresponding to the signal lines BL [1] to BL [L] is shown. The same applies to the parts corresponding to the other signal lines WB [2] to WB [S], the signal lines RB [2] to RB [S], and the signal lines BL [L + 1] to BL [S × L]. It is a composition.

The selection circuit 30 includes transistors Tr9 [1] to Tr9 [L], transistors Tr10 [1] to Tr10 [L], transistors Tr11 [1] to Tr11 [L], and transistors Tr12 [1] to Tr12 [L]. ], Transistors Tr13 [1] to Tr13 [L], transistors Tr14 [1] to Tr14 [L], and circuits RD [1] to RD [L].

By giving a selection signal to the signal lines WS [1] to WS [L], the on / off of the transistors Tr9 [1] to Tr9 [L] is controlled, and the signal lines WB [1] and the signal lines BL [1] It is possible to switch between conduction and non-conduction with BL [L].

By giving a selection signal to the signal lines WS [1] to WS [L], the on / off of the transistors Tr10 [1] to Tr10 [L] is controlled, and the power supply line VL and the power supply lines VB [1] to VB [1] to VB [ It is possible to switch between conduction and non-conduction with [L].

By giving a selection signal to the signal lines RS [1] to RS [L], the on / off of the transistors Tr11 [1] to Tr11 [L] is controlled, and the signal line RB [1] and the signal line BL [1] It is possible to switch between conduction and non-conduction with BL [L].

By giving a selection signal to the signal lines RS [1] to RS [L], the on / off of the transistors Tr12 [1] to Tr12 [L] is controlled, and the power supply line VH and the power supply lines VB [1] to VB [1] to VB [ It is possible to switch between conduction and non-conduction with [L].

By giving a selection signal to the signal lines PRE [1] to PRE [L], the on / off of the transistors Tr13 [1] to Tr13 [L] is controlled, and the circuits RD [1] to RD [L] and the signal line It is possible to switch between conduction and non-conduction with BL [1] to BL [L].

By giving a selection signal to the signal lines PRE [1] to PRE [L], the on / off of the transistors Tr14 [1] to Tr14 [L] is controlled, and the power supply line VL and the power supply lines VB [1] to VB [1] to VB [ It is possible to switch between conduction and non-conduction with [L].

The circuit RD includes a transistor Tr7, a transistor Tr8, and a capacitive element C2. The transistor Tr7 is an n-channel transistor, and the transistor Tr8 is a p-channel transistor. Further, it is assumed that the transistor Tr8 operates in the saturation region.

The gate of the transistor Tr7 is electrically connected to the signal line PR, one of the source or drain of the transistor Tr7 is electrically connected to the signal line BL via the transistor Tr13, and the other of the source or drain of the transistor Tr7 is. It is electrically connected to the gate of the transistor Tr8. One of the source or drain of the transistor Tr8 is electrically connected to one of the source or drain of the transistor Tr7, and the other of the source or drain of the transistor Tr8 is electrically connected to the power supply line VH. The first terminal of the capacitive element C2 is electrically connected to the other of the source and drain of the transistor Tr7, and the second terminal of the capacitive element C2 is electrically connected to the power supply line VH.

In the circuit RD, the potential corresponding to the current flowing in the signal line BL is stored in the capacitive element C2 by setting the signal line PR to the H level.

It is preferable to use an OS transistor as the transistor Tr7. By using the OS transistor for the transistor Tr7, the circuit RD can hold the data stored in the capacitive element C2 for a long period of time.

<Timing chart>
FIG. 9 is a timing chart showing an example of the operation of the storage device 10A. Time T01 to time T13 correspond to an operation of writing data to the memory cell MEM, and time T21 to time T27 correspond to an operation of reading data from the memory cell MEM. Although the operation of the memory cell MEMs arranged in the first to the Lth columns will be described here, the operation of the memory cell MEMs arranged in the other columns can also be described in the same manner.

At time T01 to time T02, the signal lines PR and PRE [1] to PRE [L] are set to H level, and the signal line RW [1] is set to high potential. At this time, in each of the signal lines BL [1] to BL [L], the first current corresponding to the data stored in the memory cell MEM of the first row flows. After that, the potential at which the first current can flow is set in the capacitive element C2 of the circuits RD [1] to RD [L].

At time T02 to time T03, signal line WS [1], WW [1], PRE [2] to PRE [L] are H level, signal line PRE [1], PR is L level, signal line RW [1]. Is set to a high potential. At this time, the second current corresponding to the data D11 generated by the circuit 21 [1] is supplied to the signal line WB [1]. The second current is supplied to the signal line BL [1]. On the other hand, the above-mentioned first current is supplied to the signal lines BL [2] to BL [L] from the circuits RD [2] to RD [L]. Here, in the memory cells MEM [1, 1], a potential through which a second current can flow is stored in the capacitive element C1. Further, in the memory cells MEM [1, 2] to MEM [1, L], a potential capable of passing a first current is stored in the capacitance element C1. That is, the potential corresponding to the data D11 is stored in the memory cell MEM [1, 1], and the memory cells MEM [1, 2] to MEM [1, L] correspond to the data written at the time T02. The electric potential is stored. Therefore, among the memory cells MEM [1, 1] to MEM [1, L], only the data of the memory cell MEM [1, 1] can be updated.

Similarly, similarly, at time T03 to time T05, the potential corresponding to the data D1L is stored in the memory cell MEM [1, L], and in the time T05 to time T07, the data D21 is stored in the memory cell MEM [2, 1]. The corresponding potential is stored, the potential corresponding to the data D2L is stored in the memory cell MEM [2, L] at time T07 to time T09, and the data is stored in the memory cell MEM [M, 1] at time T09 to time T11. The potential corresponding to DM1 is stored, and the potential corresponding to the data DML is stored in the memory cells MEM [M, L] at time T11 to time T13.

At time T21 to time T22, the signal line RS [1] is set to H level, and the signal line RW [1] is set to high potential. At this time, the transistor Tr2 of the memory cell MEM [1, 1] and the transistor Tr6 of the circuit 22 [1] form a source follower circuit using the transistor Tr6 as a current source, and the data of the memory cell MEM [1, 1] is used. The corresponding potential, that is, the potential (analog data) corresponding to the data D11 is output to the signal line RB [1]. The potential can be converted into digital data by the A / D converter 24, and the data D11 can be output from the output terminal DOUT.

Similarly, in the same manner, at the time T22 to the time T23, in the data D1L of the memory cell MEM [1, L], in the time T23 to the time T24, in the data D21 of the memory cell MEM [2, 1], in the time T24 to the time T25. Data D2L of memory cell MEM [2, L], data DM1 of memory cell MEM [M, 1] at time T25 to time T26, data DML of memory cell MEM [M, L] at time T26 to time T27, Can be obtained.

As described above, the storage device 10A is more efficient than the case where all the memory cells connected to the same row are written (or read) at the same time by selecting the memory cell to be written (or read). Data can be written (or read) to the memory cell. As a result, the storage device 10A can efficiently exchange data with the highly integrated memory cells. Further, since the storage device 10A has a highly integrated memory cell, the storage capacity per chip can be increased. As a result, the price per bit of the storage device can be kept low.

As described above, by configuring the storage device 10A as described above, it is possible to provide a storage device capable of storing multi-valued data. Further, it is possible to provide a storage device having a highly integrated memory cell. It is also possible to provide a storage device having stacked memory cells.

(Embodiment 2)
In the present embodiment, the storage device according to the present invention will be described with reference to FIGS. 10 to 13.

<Storage device 10B>
FIG. 10 is a block diagram showing a configuration example of the storage device 10B. The storage device 10B includes a circuit 20, a selection circuit 30, a memory cell array 40, a decoder 50, and a decoder 60.

The storage device 10B shown in FIG. 10 has a different selection circuit 30 as compared with the storage device 10A shown in FIG. FIG. 10 is different from FIG. 1 in that the signal line PR and the signal line PRB are connected to the selection circuit 30. The other components of the storage device 10B (circuit 20, memory cell array 40, decoder 50 and decoder 60) are the same as the storage device 10A, and details thereof may be referred to the description of the first embodiment.

FIG. 11 shows a circuit configuration example of the selection circuit 30 included in the storage device 10B. FIG. 11 shows a signal line WB [1] among the signal lines WB [1] to WB [S], a signal line RB [1] among the signal lines RB [1] to RB [S], and a signal line BL [ Of the 1] to BL [S × L], the portions corresponding to the signal lines BL [1] to BL [L] are shown. The same applies to the parts corresponding to the other signal lines WB [2] to WB [S], the signal lines RB [2] to RB [S], and the signal lines BL [L + 1] to BL [S × L]. It is a composition.

The selection circuit 30 includes transistors Tr9 [1] to Tr9 [L], transistors Tr10 [1] to Tr10 [L], transistors Tr11 [1] to Tr11 [L], and transistors Tr12 [1] to Tr12 [L]. ], Transistors Tr13 [1] to Tr13 [L], transistors Tr14 [1] to Tr14 [L], and circuits RD [1] to RD [L].

By giving a selection signal to the signal lines WS [1] to WS [L], the on / off of the transistors Tr9 [1] to Tr9 [L] is controlled, and the signal lines WB and the signal lines BL [1] to BL [L] It is possible to switch between conduction and non-conduction with [L].

By giving a selection signal to the signal lines WS [1] to WS [L], the on / off of the transistors Tr10 [1] to Tr10 [L] is controlled, and the power supply line VL and the power supply lines VB [1] to VB [1] to VB [ It is possible to switch between conduction and non-conduction with [L].

By giving a selection signal to the signal lines RS [1] to RS [L], the on / off of the transistors Tr11 [1] to Tr11 [L] is controlled, and the signal lines RB and the signal lines BL [1] to BL [L] It is possible to switch between conduction and non-conduction with [L].

By giving a selection signal to the signal lines RS [1] to RS [L], the on / off of the transistors Tr12 [1] to Tr12 [L] is controlled, and the power supply line VH and the power supply lines VB [1] to VB [1] to VB [ It is possible to switch between conduction and non-conduction with [L].

By giving a selection signal to the signal lines PRE [1] to PRE [L], the on / off of the transistors Tr13 [1] to Tr13 [L] is controlled, and the circuits RD [1] to RD [L] and the signal line It is possible to switch between conduction and non-conduction with BL [1] to BL [L].

By giving a selection signal to the signal lines PRE [1] to PRE [L], the on / off of the transistors Tr14 [1] to Tr14 [L] is controlled, and the power supply line VL and the power supply lines VB [1] to VB [1] to VB [ It is possible to switch between conduction and non-conduction with [L].

FIG. 12 shows a configuration example of the circuit RD included in the storage device 10B. The circuit RD includes a transistor Tr7, a transistor Tr8, a transistor Tr15, a transistor Tr16, a transistor Tr17, a transistor Tr18, and a capacitive element C2. The transistor Tr7 and the transistor Tr8 are n-channel transistors, and the transistors Tr15 to Tr18 are p-channel transistors. Further, it is assumed that the transistor Tr8, the transistor Tr15 and the transistor Tr16 operate in the saturation region.

The gate of the transistor Tr15 is electrically connected to the gate of the transistor Tr16, one of the source or drain of the transistor Tr15 is electrically connected to the signal line BL, and the other of the source or drain of the transistor Tr15 is electrically connected to the power supply line VH. Connected to. One of the source or drain of the transistor Tr16 is electrically connected to one of the source or drain of the transistor Tr8, and the other of the source or drain of the transistor Tr16 is electrically connected to the power supply line VH. The gate of the transistor Tr8 is electrically connected to the first terminal of the capacitive element C2, and the other of the source or drain of the transistor Tr8 is electrically connected to the power supply line VL. The second terminal of the capacitive element C2 is electrically connected to the power supply line VL.

The gate of the transistor Tr15 is electrically connected to one of the source or drain of the transistor Tr15 via the transistor Tr17, and the gate of the transistor Tr16 is electrically connected to one of the source or drain of the transistor Tr16 via the transistor Tr18. Connected to. The gate of the transistor Tr8 is electrically connected to either the source or the drain of the transistor Tr8 via the transistor Tr7.

The gate of the transistor Tr17 is electrically connected to the signal line PRB, the gate of the transistor Tr18 is electrically connected to the signal line PR, and the gate of the transistor Tr7 is electrically connected to the signal line PR.

The gate of the transistor Tr7 is electrically connected to the signal line PR, one of the source or drain of the transistor Tr7 is electrically connected to the gate of the transistor Tr8, and the other of the source or drain of the transistor Tr7 is the source of the transistor Tr8. Or it is electrically connected to one of the drains. The gate of the transistor Tr8 is electrically connected to the first terminal of the capacitive element C2, one of the source or drain of the transistor Tr8 is electrically connected to one of the source or drain of the transistor Tr16, and the source or drain of the transistor Tr8 is connected. The other is electrically connected to the power line VL. The second terminal of the capacitive element C2 is electrically connected to the power supply line VL.

In the circuit RD, the signal line PR is set to H level and the signal line PRB is set to L level, so that the transistor Tr17 and the transistor Tr7 are turned on and the transistor Tr18 is turned off. The transistor Tr15 and the transistor Tr16 function as a current mirror circuit, and a potential corresponding to the current flowing through the signal line BL is stored in the capacitive element C2. That is, data is written to the capacitive element C2.

In the circuit RD, the signal line PR is set to L level and the signal line PRB is set to H level, so that the transistor Tr17 and the transistor Tr7 are turned off and the transistor Tr18 is turned on. A drain current flows through the transistor Tr8 according to the potential stored in the capacitive element C2. Further, the transistor Tr15 and the transistor Tr16 function as a current mirror circuit, and the drain current flowing through the transistor Tr8 is supplied to the signal line BL. That is, the data stored in the capacitive element C2 is read out.

It is preferable to use an OS transistor as the transistor Tr7. By using the OS transistor for the transistor Tr7, the circuit RD can hold the data stored in the capacitive element C2 for a long period of time.

In the memory cell MEM shown in FIG. 2, an n-channel type transistor Tr1 and an n-channel type transistor Tr2 are connected to the capacitance element C1. Further, in the circuit RD shown in FIG. 8, an n-channel transistor Tr7 and a p-channel transistor Tr8 are connected to the capacitance element C2, and in the circuit RD shown in FIG. 12, an n-channel transistor Tr7 and an n-channel are connected to the capacitance element C2. A type transistor Tr8 is connected. That is, the memory cell MEM and the circuit RD shown in FIG. 12 are common in that two n-channel transistors are connected to one capacitive element.

In the circuit RD shown in FIG. 12, the threshold value and the gain can be set to values close to those of the memory cell MEM by making the transistor size (channel length, channel width) the same as that of the memory cell MEM. That is, the circuit RD shown in FIG. 12 can more accurately copy and store the data stored in the memory cell MEM than the circuit RD shown in FIG.

<Timing chart>
FIG. 13 is a timing chart showing an example of the operation of the storage device 10B. Time T01 to time T13 correspond to an operation of writing data to the memory cell MEM, and time T21 to time T27 correspond to an operation of reading data from the memory cell MEM. Although the operation of the memory cell MEMs arranged in the first to the Lth columns will be described here, the operation of the memory cell MEMs arranged in the other columns can also be described in the same manner.

At time T01 to time T02, the signal line PR, PRE [1] to PRE [L] are set to H level, the signal line PRB is set to L level, and the signal line RW [1] is set to high potential. At this time, in each of the signal lines BL [1] to BL [L], the first current corresponding to the data stored in the memory cell MEM of the first row flows. After that, the potential at which the first current can flow is set in the capacitive element C2 of the circuits RD [1] to RD [L].

At time T02 to time T03, signal line PRB, WS [1], WW [1], PRE [2] to PRE [L] are H level, signal line PR, PRE [1] is L level, signal line RW [ 1] is set to a high potential. At this time, the second current corresponding to the data D11 generated by the circuit 21 [1] is supplied to the signal line WB [1]. The second current is supplied to the signal line BL [1]. On the other hand, the above-mentioned first current is supplied to the signal lines BL [2] to BL [L] from the circuits RD [2] to RD [L]. Here, in the memory cells MEM [1, 1], a potential through which a second current can flow is stored in the capacitive element C1. Further, in the memory cells MEM [1, 2] to MEM [1, L], a potential capable of passing a first current is stored in the capacitance element C1. That is, the potential corresponding to the data D11 is stored in the memory cell MEM [1, 1], and the memory cells MEM [1, 2] to MEM [1, L] correspond to the data written at the time T02. The electric potential is stored. Therefore, among the memory cells MEM [1, 1] to MEM [1, L], only the data of the memory cell MEM [1, 1] can be updated.

Similarly, similarly, at time T03 to time T05, the potential corresponding to the data D1L is stored in the memory cell MEM [1, L], and in the time T05 to time T07, the data D21 is stored in the memory cell MEM [2, 1]. The corresponding potential is stored, the potential corresponding to the data D2L is stored in the memory cell MEM [2, L] at time T07 to time T09, and the data is stored in the memory cell MEM [M, 1] at time T09 to time T11. The potential corresponding to DM1 is stored, and the potential corresponding to the data DML is stored in the memory cells MEM [M, L] at time T11 to time T13.

At time T21 to time T22, the signal line PR and RS [1] are set to H level, the signal line PRB is set to L level, and the signal line RW [1] is set to high potential. At this time, the transistor Tr2 of the memory cell MEM [1, 1] and the transistor Tr6 of the circuit 22 [1] form a source follower circuit using the transistor Tr6 as a current source, and the data of the memory cell MEM [1, 1] is used. The corresponding potential, that is, the potential (analog data) corresponding to the data D11 is output to the signal line RB [1]. The potential can be converted into digital data by the A / D converter 24, and the data D11 can be output from the output terminal DOUT.

Similarly, in the same manner, at the time T22 to the time T23, in the data D1L of the memory cell MEM [1, L], in the time T23 to the time T24, in the data D21 of the memory cell MEM [2, 1], in the time T24 to the time T25. Data D2L of memory cell MEM [2, L], data DM1 of memory cell MEM [M, 1] at time T25 to time T26, data DML of memory cell MEM [M, L] at time T26 to time T27, Can be obtained.

After time T13, when all the signal lines PRE [1] to PRE [L] are at L level, that is, when neither writing nor reading of the circuit RD is performed, the signal line PR is set to H level and the signal line PRB is set to L level. By setting the level, in the circuit RD, the gate potential of the transistor Tr15 is fixed to the potential at which the transistor Tr15 is turned off, and the transistor Tr16 is also turned off. Further, the potential set in the capacitance element C2 turns off the transistor Tr8. Therefore, the power consumption in the circuit RD can be reduced.

As described above, the storage device 10B is more efficient than the case where all the memory cells connected to the same row are written (or read) at the same time by selecting the memory cell to be written (or read). Data can be written (or read) to the memory cell. As a result, the storage device 10B can efficiently exchange data with the highly integrated memory cells. Further, since the storage device 10B has a highly integrated memory cell, the storage capacity per chip can be increased. As a result, the price per bit of the storage device can be kept low.

As described above, by configuring the storage device 10B as described above, it is possible to provide a storage device capable of storing multi-valued data. Further, it is possible to provide a storage device having a highly integrated memory cell. It is also possible to provide a storage device having stacked memory cells.

(Embodiment 3)
In the present embodiment, one embodiment of the storage device 10A and the storage device 10B (hereinafter collectively referred to as the storage device 10) described in the above embodiment will be described with reference to FIGS. 14 and 15.

<Cross-sectional structure of storage device 10>
FIG. 14 is a schematic cross-sectional view showing an example of the storage device 10. The storage device 10 includes a transistor 300, a transistor 200, and a capacitive element 100. The transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200.

The transistor 200 is an OS transistor having an oxide semiconductor in the channel forming region. Since the OS transistor can be formed with a good yield even if it is miniaturized, the transistor 200 can be miniaturized. By using such a transistor in a storage device, the storage device can be miniaturized or highly integrated. Since the OS transistor has a small off current, it is possible to retain the stored contents for a long period of time by using the OS transistor as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

The transistor 300 is provided on the substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 composed of a part of the substrate 311 and a low resistance region 314a and a low resistance region 314b that function as a source region or a drain region. Have.

The transistor 300 may be either a p-channel type or an n-channel type.

It is preferable to include a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like. It preferably contains crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.

In the low resistance region 314a and the low resistance region 314b, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic and phosphorus, or a p-type conductivity such as boron is imparted. Contains elements that

The conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A material or a conductive material such as a metal oxide material can be used.

The threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

In the transistor 300 shown in FIG. 14, the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. The conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

The transistor 300 shown in FIG. 14 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, aluminum nitride and the like can be used. Just do it.

The insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 300 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, as the insulator 324, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 200 is provided from the substrate 311 or the transistor 300.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 200, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

The amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 in the range of 50 ° C. to 500 ° C. in the TDS analysis, in which the amount desorbed in terms of hydrogen atoms is converted into the area of the insulator 324. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ^{2 or less.}

The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative permittivity of the insulator 324. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

Further, a conductor 328, a conductor 330, and the like are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 have a function as a plug or a wiring. Further, a conductor having a function as a plug or a wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is single-layered or laminated. Can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 14, insulator 350, insulator 352, insulator 354, insulator 360, insulator 362, insulator 364, insulator 370, insulator 372, insulator 374, insulator 380, insulator 382 and Insulators 384 are laminated and provided in order. Further, a conductor 356, a conductor 366, a conductor 376 and a conductor 386 are formed on these insulators. These conductors have a function as a plug or a wiring. These conductors can be provided by using the same materials as the conductor 328 and the conductor 330.

As the insulator 350, the insulator 360, the insulator 370, and the insulator 380, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 356, the conductor 366, the conductor 376 and the conductor 386 preferably contain a conductor having a barrier property against hydrogen. For example, in the case of the insulator 350 and the conductor 356, the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed by forming the conductor 356 in the opening of the insulator 350. The same is true for other insulators and conductors.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring.

Insulator 214 and insulator 216 are laminated and provided on the insulator 384. As either the insulator 214 or the insulator 216, it is preferable to use a substance having a barrier property against oxygen and hydrogen.

For example, for the insulator 214, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 200 is provided, for example, from the region where the substrate 311 or the transistor 300 is provided. Therefore, the same material as the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 200, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

Further, as a film having a barrier property against hydrogen, for example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the insulator 214.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 200 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 200. Therefore, it is suitable for use as a protective film for the transistor 200.

Further, for example, the same material as the insulator 320 can be used for the insulator 216. Further, by using a material having a relatively low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 216, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, in the insulator 214 and the insulator 216, a conductor 218, a conductor constituting the transistor 200 (for example, an electrode functioning as a back gate) and the like are embedded. The conductor 218 can be provided by using the same material as the conductor 328 and the conductor 330.

The conductor 218 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 200 can be completely separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. ..

A transistor 200 is provided above the insulator 216. As the transistor 200, an OS transistor may be used. Details of the transistor 200 will be described in the fourth embodiment described later.

An insulator 280 is provided above the transistor 200. It is preferable that the insulator 280 is formed with an excess oxygen region. In particular, when an oxide semiconductor is used for the transistor 200, the oxygen deficiency of the metal oxide 406 of the transistor 200 can be reduced by providing an insulator having an excess oxygen region in the interlayer film or the like in the vicinity of the transistor 200. Reliability can be improved. Further, the insulator 280 that covers the transistor 200 may function as a flattening film that covers the uneven shape below the insulator 280. The insulator 280 is provided in contact with the insulator 225 formed on the upper portion of the transistor 200.

Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. Oxides that desorb oxygen by heating have an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ^{20 in terms of oxygen atoms in TDS analysis.} It is an oxide film having atoms / cm ^{3 or more.} The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower.

For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxide nitride. Alternatively, a metal oxide can be used. In the present specification, silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride as its composition means a material having a higher nitrogen content than oxygen as its composition. Is shown.

The insulator 282 may be provided on the insulator 280. As the insulator 282, it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, the same material as that of the insulator 214 can be used for the insulator 282. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 282. Further, for example, when the insulator 282 is formed into a film by a sputtering method using plasma containing oxygen, oxygen can be added to the insulator 280 which is the base layer of the oxide.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 200 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 200. Therefore, it is suitable for use as a protective film for the transistor 200.

Further, an insulator 286 is provided on the insulator 282. As the insulator 286, the same material as the insulator 320 can be used. Further, by using a material having a relatively low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 286, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, a conductor 246, a conductor 248 and the like are embedded in the insulator 220, the insulator 222, the insulator 224, the insulator 225, the insulator 280, the insulator 282, and the insulator 286.

The conductor 246 and the conductor 248 can be provided by using the same materials as the conductor 328 and the conductor 330.

Subsequently, a capacitance element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110, a conductor 120, and an insulator 130.

Further, the conductor 112 may be provided on the conductor 246 and the conductor 248. The conductor 112 and the conductor 110 can be formed at the same time.

The conductor 112 and the conductor 110 are formed of a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components. (Tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) and the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.

In FIG. 14, the conductor 112 and the conductor 110 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.

Further, an insulator 130 is provided on the conductor 112 and the conductor 110 as a dielectric of the capacitance element 100. The insulator 130 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, hafnium nitride, and the like. It may be used and may be provided in a laminated or single layer.

For example, for the insulator 130, a material having a large dielectric strength such as silicon oxide may be used. With this configuration, the capacitive element 100 has the insulator 130, so that the dielectric strength is improved and the electrostatic breakdown of the capacitive element 100 can be suppressed.

The conductor 120 is provided on the insulator 130 so as to overlap with the conductor 110. As the conductor 120, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as another structure such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 150 can be provided by using the same material as the insulator 320. Further, the insulator 150 may function as a flattening film that covers the uneven shape below the insulator 150.

The above is the description of the configuration example. By using this configuration, in a storage device using an OS transistor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a storage device using an OS transistor. Alternatively, in a storage device using an OS transistor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated storage device can be provided with high productivity.

<Modification 1 of storage device 10>
Further, an example of a modification of the present embodiment is shown in FIG.

FIG. 15 is a schematic cross-sectional view when the transistor 200 of FIG. 14 is replaced with the transistor 201. Like the transistor 200, the transistor 201 is an OS transistor. The details of the transistor 201 will be described in the fourth embodiment described later.

For details of the other configuration examples of FIG. 15, the description of FIG. 14 may be referred to.

(Embodiment 4)
In the present embodiment, the details of the transistor 200 and the transistor 201 shown in the third embodiment will be described with reference to FIGS. 16 to 20.

<< Transistor 200 >>
First, the details of the transistor 200 shown in FIG. 14 will be described.

FIG. 16A is a top view of the semiconductor device having the transistor 200. Further, FIG. 16B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 16A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 16C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 16A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 16A, some elements are omitted for the sake of clarity of the figure.

As shown in FIGS. 16A to 16C, the conductor 200 includes an insulator 224 arranged on a substrate (not shown), a metal oxide 406a arranged on the insulator 224, and the like. A metal oxide 406b arranged in contact with at least a part of the upper surface of the metal oxide 406a, an insulator 412 arranged on the metal oxide 406b, and a conductor 404a arranged on the insulator 412. , The conductor 404b arranged on the conductor 404a, the insulator 419 arranged on the conductor 404b, the insulator 412, the conductor 404a, and the conductor 404b, and the side surface of the insulator 419. The insulator 418 is arranged in contact with the upper surface of the metal oxide 406b, and the insulator 225 is arranged in contact with the side surface of the insulator 418. Here, as shown in FIG. 16B, it is preferable that the upper surface of the insulator 418 substantially coincides with the upper surface of the insulator 419. Further, the insulator 225 is preferably provided so as to cover the insulator 419, the conductor 404, the insulator 418, and the metal oxide 406.

In the following, the metal oxide 406a and the metal oxide 406b may be collectively referred to as the metal oxide 406. Although the transistor 200 shows a configuration in which the metal oxide 406a and the metal oxide 406b are laminated, the present invention is not limited to this. For example, only the metal oxide 406b may be provided. Further, the conductor 404a and the conductor 404b may be collectively referred to as the conductor 404. Although the transistor 200 shows a configuration in which the conductor 404a and the conductor 404b are laminated, the present invention is not limited to this. For example, only the conductor 404b may be provided.

The conductor 440 is in contact with the inner wall of the opening of the insulator 384 to form the conductor 440a, and the conductor 440b is further formed inside. Here, the height of the upper surface of the conductor 440a and the conductor 440b can be made the same as the height of the upper surface of the insulator 384. Although the transistor 200 shows a configuration in which the conductor 440a and the conductor 440b are laminated, the present invention is not limited to this. For example, only the conductor 440b may be provided.

In the conductor 310, the conductor 310a is formed in contact with the inner wall of the opening of the insulator 214 and the insulator 216, and the conductor 310b is further formed inside. Therefore, it is preferable that the conductor 310a is in contact with the conductor 440b. Here, the heights of the upper surfaces of the conductors 310a and 310b and the heights of the upper surfaces of the insulator 216 can be made about the same. Although the transistor 200 shows a configuration in which the conductor 310a and the conductor 310b are laminated, the present invention is not limited to this. For example, only the conductor 310b may be provided.

The conductor 404 can function as a top gate, and the conductor 310 can function as a back gate. The potential of the back gate may be the same potential as that of the top gate, or may be a ground potential or an arbitrary potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate independently without interlocking with the top gate.

The conductor 440 is stretched in the channel width direction like the conductor 404, and functions as a wiring for applying an electric potential to the conductor 310, that is, the back gate. Here, by stacking on the conductor 440 that functions as the wiring of the back gate and providing the conductor 310 embedded in the insulator 214 and the insulator 216, insulation is provided between the conductor 440 and the conductor 404. A body 214, an insulator 216, and the like are provided, and the parasitic capacitance between the conductor 440 and the conductor 404 can be reduced, and the insulation withstand voltage can be increased. By reducing the parasitic capacitance between the conductor 440 and the conductor 404, the switching speed of the transistor can be improved and the transistor can have high frequency characteristics. Further, the reliability of the transistor 200 can be improved by increasing the withstand voltage between the conductor 440 and the conductor 404. Therefore, it is preferable to increase the film thickness of the insulator 214 and the insulator 216. The stretching direction of the conductor 440 is not limited to this, and may be stretched in the channel length direction of the transistor 200, for example.

Here, as the conductor 310a and the conductor 440a, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen (difficult to permeate). For example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used, and may be a single layer or a laminated layer. This makes it possible to prevent impurities such as hydrogen and water from diffusing from the lower layer to the upper layer through the conductor 440 and the conductor 310. Incidentally, the conductor 310a and the conductor 440a is a hydrogen atom, a hydrogen molecule, a water molecule, an oxygen atom, an oxygen molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule _(N 2 O, NO, etc. NO _2), copper atoms etc. It is preferable to have a function of suppressing the permeation of at least one of the impurities or oxygen (for example, oxygen atom, oxygen molecule, etc.). Further, the same applies to the case where the conductive material having a function of suppressing the permeation of impurities is described below. Since the conductor 310a and the conductor 440a have a function of suppressing the permeation of oxygen, it is possible to prevent the conductor 310b and the conductor 440b from being oxidized and the conductivity from being lowered.

Further, as the conductor 310b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, although not shown, the conductor 310b may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.

Further, since the conductor 440b functions as a wiring, it is preferable to use a conductor having a higher conductivity than the conductor 310b, and for example, a conductive material containing copper or aluminum as a main component can be used. Further, although not shown, the conductor 440b may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.

The insulator 214 can function as a barrier insulating film that prevents impurities such as water and hydrogen from being mixed into the transistor from the lower layer. As the insulator 214, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it is preferable to use silicon nitride or the like as the insulator 214. This makes it possible to prevent impurities such as hydrogen and water from diffusing into the upper layer of the insulator 214. The insulating member 214 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule _(N 2 O, NO, etc. NO _2), inhibit at least one transmission of impurities such as copper atoms It is preferable to have a function. The same applies to the case where an insulating material having a function of suppressing the permeation of impurities is described below.

Further, as the insulator 214, it is preferable to use an insulating material having a function of suppressing the permeation of oxygen (for example, oxygen atom or oxygen molecule). As a result, it is possible to suppress the downward diffusion of oxygen contained in the insulator 224 and the like.

Further, by stacking the conductor 310 on the conductor 440, the insulator 214 can be provided between the conductor 440 and the conductor 310. Here, even if a metal such as copper that is easily diffused is used for the conductor 440b, it is possible to prevent the metal from diffusing into the layer above the insulator 214 by providing silicon nitride or the like as the insulator 214.

Further, as the insulator 222, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, and for example, aluminum oxide or hafnium oxide is preferably used. This makes it possible to prevent impurities such as hydrogen and water from diffusing from the layer below the insulator 222 to the layer above the insulator 222. Further, it is possible to suppress the downward diffusion of oxygen contained in the insulator 224 and the like.

Further, it is preferable that the concentration of impurities such as water, hydrogen or nitrogen oxides in the insulator 224 is reduced. For example, the amount of hydrogen desorbed from the insulator 224 is determined by the amount of desorption converted into hydrogen molecules in the range of 50 ° C. to 500 ° C. in the temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). In terms of the area of the body 224, it may be 2 × 10 ¹⁵ molecules / cm ² or less, preferably 1 × 10 ¹⁵ molecules / cm ² or less, and more preferably 5 × 10 ¹⁴ molecules / cm ² or less. Further, the insulator 224 is preferably formed by using an insulator in which oxygen is released by heating.

The insulator 412 can function as a first gate insulating film, and the insulator 220, the insulator 222, and the insulator 224 can function as a second gate insulating film. Although the transistor 200 shows a configuration in which an insulator 220, an insulator 222, and an insulator 224 are laminated, the present invention is not limited to this. For example, the structure may be such that any two layers of the insulator 220, the insulator 222, and the insulator 224 are laminated, or a structure using any one layer may be used.

As the metal oxide 406, it is preferable to use a metal oxide that functions as an oxide semiconductor. As the metal oxide, it is preferable to use an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using the metal oxide having a wide energy gap, the off-current of the transistor can be reduced.

A transistor using a metal oxide has an extremely small leakage current in a non-conducting state, so that a semiconductor device having low power consumption can be provided. Further, since the metal oxide can be formed into a film by using a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device.

The metal oxide 406 preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.

Here, consider the case where the metal oxide 406 is an In—M—Zn oxide having indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Examples of elements applicable to the other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

In addition, in this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

Here, in the metal oxide used for the metal oxide 406a, the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used for the metal oxide 406b. Is preferable. Further, in the metal oxide used for the metal oxide 406a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the metal oxide 406b. Further, in the metal oxide used for the metal oxide 406b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the metal oxide 406a.

Using the above metal oxide as the metal oxide 406a, the energy at the lower end of the conduction band of the metal oxide 406a is higher than the energy at the lower end of the conduction band in the region where the energy at the lower end of the conduction band of the metal oxide 406b is low. Is preferable. In other words, it is preferable that the electron affinity of the metal oxide 406a is smaller than the electron affinity of the metal oxide 406b in the region where the energy at the lower end of the conduction band is low.

Here, in the metal oxide 406a and the metal oxide 406b, the energy level at the lower end of the conduction band changes gently. In other words, it can also be said to be continuously changing or continuously joining. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 406a and the metal oxide 406b.

Specifically, since the metal oxide 406a and the metal oxide 406b have a common element (main component) other than oxygen, a mixed layer having a low defect level density can be formed. For example, when the metal oxide 406b is an In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like as the metal oxide 406a.

At this time, the main path of the carrier is the narrow gap portion formed in the metal oxide 406b. Since the defect level density at the interface between the metal oxide 406a and the metal oxide 406b can be lowered, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.

Further, the metal oxide 406 has a region 426a, a region 426b, and a region 426c. As shown in FIG. 16B, the region 426a is sandwiched between the region 426b and the region 426c. The region 426b and the region 426c are regions whose resistance has been reduced by the film formation of the insulator 225, and are regions having higher conductivity than the region 426a. Impurity elements such as hydrogen and nitrogen contained in the film forming atmosphere of the insulator 225 are added to the regions 426b and 426c. As a result, oxygen deficiency is formed by the added impurity element mainly in the region overlapping the insulator 225 of the metal oxide 406b, and the impurity element enters the oxygen deficiency, so that the carrier density becomes high and the resistance is low. Be transformed.

Therefore, it is preferable that the concentration of at least one of hydrogen and nitrogen in the region 426b and the region 426c is higher than that in the region 426a. The concentration of hydrogen or nitrogen may be measured by using secondary ion mass spectrometry (SIMS) or the like. Here, as the concentration of hydrogen or nitrogen in the region 426a, the distance from both sides in the channel length direction of the vicinity of the center of the region overlapping the insulator 412 of the metal oxide 406b (for example, the insulator 412 of the metal oxide 406b) is used. The concentration of hydrogen or nitrogen in approximately equal parts) may be measured.

The resistance of the region 426b and the region 426c is reduced by adding an element that forms an oxygen deficiency or an element that binds to the oxygen deficiency. Typical examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of noble gas elements include helium, neon, argon, krypton, xenon and the like. Therefore, the region 426b and the region 426c may be configured to contain one or more of the above elements.

Further, it is preferable that the atomic number ratio of In to the element M of the metal oxide 406a is about the same as the atomic number ratio of In to the element M of the metal oxide 406b in the region 426b and the region 426c. In other words, in the metal oxide 406a, it is preferable that the atomic number ratio of In to the element M in the region 426b and 426c is larger than the atomic number ratio of In to the element M in the region 426a. Here, the metal oxide 406 can increase the carrier density and reduce the resistance by increasing the indium content. With such a configuration, even when the film thickness of the metal oxide 406b becomes thin and the electric resistance of the metal oxide 406b increases in the manufacturing process of the transistor 200, the metal oxidation occurs in the region 426b and the region 426c. The resistance of the object 406a is sufficiently lowered, and the region 426b and the region 426c of the metal oxide 406 can function as a source region and a drain region.

An enlarged view of the vicinity of the region 426a shown in FIG. 16 (B) is shown in FIG. 17 (A). As shown in FIG. 17 (A), the region 426b and the region 426c are formed in a region overlapping with at least the insulator 225 of the metal oxide 406. Here, one of the region 426b and the region 426c of the metal oxide 406b can function as a source region and the other can function as a drain region. Further, the region 426a of the metal oxide 406b can function as a channel forming region.

In addition, in FIG. 16B and FIG. 17A, the region 426a, the region 426b, and the region 426c are formed in the metal oxide 406b and the metal oxide 406a, but these regions are at least the metal oxide. It suffices if it is formed in 406b. Further, in FIG. 16B and the like, the boundary between the region 426a and the region 426b and the boundary between the region 426a and the region 426c are displayed substantially perpendicular to the upper surface of the metal oxide 406. It is not limited to this. For example, the region 426b and the region 426c may project toward the conductor 404 near the surface of the metal oxide 406b and recede toward the insulator 225 near the lower surface of the metal oxide 406a.

In the transistor 200, as shown in FIG. 17A, the region 426b and the region 426c overlap the region in contact with the insulator 225 of the metal oxide 406, the insulator 418, and the vicinity of both ends of the insulator 412. It is formed. At this time, the portion of the region 426b and the region 426c that overlaps with the conductor 404 functions as a so-called overlapping region (also referred to as a Lov region). By adopting a structure having a Lov region, a high resistance region is not formed between the channel formation region of the metal oxide 406 and the source region and the drain region, so that the on-current and mobility of the transistor can be increased. ..

However, the semiconductor device shown in this embodiment is not limited to this. For example, as shown in FIG. 17B, the region 426b and the region 426c may be formed in a region overlapping the insulator 225 and the insulator 418 of the metal oxide 406. In other words, the configuration shown in FIG. 17B is such that the width of the conductor 404 in the channel length direction and the width of the region 426a are substantially the same. With the configuration shown in FIG. 17B, since a high resistance region is not formed between the source region and the drain region, the on-current of the transistor can be increased. Further, by adopting the configuration shown in FIG. 17B, since the source region and the drain region and the gate do not overlap in the channel length direction, it is possible to suppress the formation of unnecessary capacitance.

By appropriately selecting the ranges of the region 426b and the region 426c in this way, it is possible to easily provide a transistor having electrical characteristics that meet the requirements according to the circuit design.

The insulator 412 is preferably arranged in contact with the upper surface of the metal oxide 406b. The insulator 412 is preferably formed by using an insulator that releases oxygen by heating. By providing such an insulator 412 in contact with the upper surface of the metal oxide 406b, oxygen can be effectively supplied to the metal oxide 406b. Further, similarly to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 412 is reduced. The film thickness of the insulator 412 is preferably 1 nm or more and 20 nm or less, and for example, the film thickness may be about 1 nm.

The insulator 412 preferably contains oxygen. For example, in a heated desorption gas spectroscopy analysis (TDS analysis), the amount of desorption of oxygen molecules per area of the insulator 412 is determined in the range of surface temperature of 100 ° C. or higher and 700 ° C. or lower or 100 ° C. or higher and 500 ° C. or lower. In terms of, it may be 1 × 10 ¹⁴ moles / cm ² or more, preferably 2 × 10 ¹⁴ moles / cm ² or more, and more preferably 4 × 10 ¹⁴ moles / cm ² or more.

The insulator 412, the conductor 404, and the insulator 419 have a region overlapping the metal oxide 406b. Further, it is preferable that the side surfaces of the insulator 412, the conductor 404a, the conductor 404b, and the insulator 419 are substantially the same.

It is preferable to use a conductive oxide as the conductor 404a. For example, a metal oxide that can be used as the metal oxide 406a or the metal oxide 406b can be used. In particular, among In-Ga-Zn-based oxides, the atomic number ratio of the metal having high conductivity is [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, or a value close thereto. It is preferable to use one. By providing such a conductor 404a, it is possible to suppress the permeation of oxygen into the conductor 404b and prevent the electric resistance value of the conductor 404b from increasing due to oxidation.

Further, by forming such a conductive oxide into a film by using a sputtering method, oxygen can be added to the insulator 412 and oxygen can be supplied to the metal oxide 406b. Thereby, the oxygen deficiency in the region 426a of the metal oxide 406 can be reduced.

As the conductor 404b, a metal such as tungsten can be used. Further, as the conductor 404b, a conductor capable of improving the conductivity of the conductor 404a by adding an impurity such as nitrogen to the conductor 404a may be used. For example, it is preferable to use titanium nitride or the like for the conductor 404b. Further, the conductor 404b may have a structure in which a metal nitride such as titanium nitride and a metal such as tungsten are laminated on the metal nitride.

Here, the conductor 404 having the function of the gate electrode is provided so as to cover the upper surface in the vicinity of the region 426a of the metal oxide 406b and the side surface in the channel width direction via the insulator 412. Therefore, the electric field of the conductor 404 having a function as a gate electrode can electrically surround the upper surface of the metal oxide 406b near the region 426a and the side surface in the channel width direction. The structure of the transistor that electrically surrounds the channel formation region by the electric field of the conductor 404 is called a surroundd channel (s-channel) structure. Therefore, since a channel can be formed on the upper surface near the region 426a of the metal oxide 406b and the side surface in the channel width direction, a large current can flow between the source and the drain, and the current (on current) at the time of conduction can be increased. Can be made larger. Further, since the upper surface of the metal oxide 406b near the region 426a and the side surface in the channel width direction are surrounded by the electric field of the conductor 404, the leakage current (off current) at the time of non-conduction can be reduced.

It is preferable that the insulator 419 is arranged on the conductor 404b. Further, it is preferable that the side surfaces of the insulator 419, the conductor 404a, the conductor 404b, and the insulator 412 substantially coincide with each other. The insulator 419 is preferably formed by using an atomic layer deposition (ALD) method. Thereby, the film thickness of the insulator 419 can be formed to be about 1 nm or more and 20 nm or less, preferably about 5 nm or more and 510 nm or less. Here, as the insulator 419, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen as in the insulator 418. For example, aluminum oxide or hafnium oxide is used. It is preferable to use it.

By providing such an insulator 419, the upper surface and the side surface of the conductor 404 can be covered with the insulator 419 and the insulator 418 having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. This makes it possible to prevent impurities such as water and hydrogen from being mixed into the metal oxide 406 via the conductor 404. As described above, the insulator 418 and the insulator 419 have a function as a gate cap for protecting the gate.

The insulator 418 is provided in contact with the side surfaces of the insulator 412, the conductor 404, and the insulator 419. Further, it is preferable that the upper surface of the insulator 418 substantially coincides with the upper surface of the insulator 419. The insulator 418 is preferably formed by using the ALD method. As a result, the film thickness of the insulator 418 can be formed at about 1 nm or more and 20 nm or less, preferably about 1 nm or more and 3 nm or less, for example, 1 nm.

As described above, the regions 426b and 426c of the metal oxide 406 are formed by the impurity elements added in the film formation of the insulator 225. When the transistor is miniaturized and the channel length is formed to be about 10 nm to 30 nm, the impurity elements contained in the source region or the drain region may diffuse, and the source region and the drain region may be electrically conductive. On the other hand, as shown in the present embodiment, by forming the insulator 418, the distance between the regions in contact with the insulator 225 of the metal oxide 406 can be increased, so that the distance from the source region can be increased. It is possible to prevent the drain region from being electrically conductive. Furthermore, by forming the insulator 418 using the ALD method, the film thickness is made equal to or less than the miniaturized channel length, the distance between the source region and the drain region is increased more than necessary, and the resistance is increased. You can block things.

Here, as the insulator 418, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, and for example, aluminum oxide or hafnium oxide is preferably used. This makes it possible to prevent oxygen in the insulator 412 from diffusing to the outside. Further, it is possible to suppress the infiltration of impurities such as hydrogen and water into the metal oxide 406 from the end portion of the insulator 412 and the like.

The insulator 418 is subjected to anisotropic etching after forming an insulating film by the ALD method, and the portion of the insulating film in contact with the side surfaces of the insulator 412, the conductor 404, and the insulator 419. It is preferable to form the residue. As a result, it is possible to easily form an insulator having a thin film thickness as described above. Further, at this time, by providing the insulator 419 on the conductor 404, even if the insulator 419 is partially removed by the anisotropic etching, the insulator 412 and the conductor 404 of the insulator 418 are provided. The part in contact with is sufficiently left.

The insulator 225 is provided so as to cover the insulator 419, the insulator 418, the metal oxide 406, and the insulator 224. Here, the insulator 225 is provided in contact with the upper surface of the insulator 419 and the insulator 418 and in contact with the side surface of the insulator 418. As described above, the insulator 225 adds an impurity such as hydrogen or nitrogen to the metal oxide 406 to form a region 426b and a region 426c. For this reason, the insulator 225 preferably has at least one of hydrogen and nitrogen.

Further, the insulator 225 is preferably provided in contact with the side surface of the metal oxide 406b and the side surface of the metal oxide 406a in addition to the upper surface of the metal oxide 406b. Thereby, in the region 426b and the region 426c, the resistance can be reduced to the side surface of the metal oxide 406b and the side surface of the metal oxide 406a.

Further, as the insulator 225, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, silicon nitride nitride, aluminum nitride, aluminum nitride or the like as the insulator 225. By forming such an insulator 225, it is possible to prevent oxygen from infiltrating through the insulator 225 and supplying oxygen to the oxygen deficiency in the region 426b and the region 426c to reduce the carrier density. .. Further, it is possible to prevent impurities such as water and hydrogen from infiltrating through the insulator 225 and causing the region 426b and the region 426c to excessively expand to the region 426a side.

It is preferable to provide the insulator 280 on the insulator 225. Like the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

The conductor 450a and the conductor 451a, and the conductor 450b and the conductor 451b are arranged in the openings formed in the insulator 280 and the insulator 225. It is preferable that the conductor 450a and the conductor 451a and the conductor 450b and the conductor 451b are provided so as to face each other with the conductor 404 interposed therebetween.

Here, the conductor 450a is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 225, and the conductor 451a is further formed inside. A region 426b of the metal oxide 406 is located at least in part of the bottom of the opening, and the conductor 450a is in contact with the region 426b. Similarly, the conductor 450b is formed in contact with the inner wall of the opening of the insulator 280 and the insulator 225, and the conductor 451b is further formed inside. A region 426c of the metal oxide 406 is located at least in part of the bottom of the opening, and the conductor 450b is in contact with the region 426c.

Here, FIG. 18 (A) shows a cross-sectional view of the portion shown by the alternate long and short dash line in FIG. 16 (A). Although FIG. 18A shows a cross-sectional view of the conductor 450b and the conductor 451b, the structures of the conductor 450a and the conductor 451a are also the same.

As shown in FIGS. 16B and 18A, it is preferable that the conductor 450b is in contact with at least the upper surface of the metal oxide 406 and further in contact with the side surface of the metal oxide 406. In particular, as shown in FIG. 18A, it is preferable that the conductor 450b is in contact with both or one of the side surface on the A5 side and the side surface on the A6 side in the channel width direction of the metal oxide 406. Further, as shown in FIG. 16B, the conductor 450b may be configured to be in contact with the side surface of the metal oxide 406 on the A2 side in the channel length direction. In this way, by forming the conductor 450b in contact with the side surface of the metal oxide 406 in addition to the upper surface of the metal oxide 406, the upper area of the contact portion between the conductor 450b and the metal oxide 406 is not increased. , The contact area of the contact portion can be increased, and the contact resistance between the conductor 450b and the metal oxide 406 can be reduced. As a result, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor. The same can be said for the conductor 450a and the conductor 451a.

Here, the conductor 450a is in contact with a region 426b that functions as one of the source region and the drain region of the transistor 200, and the conductor 450b is in contact with a region 426c that functions as the other of the source region and the drain region of the transistor 200. .. Therefore, the conductor 450a and the conductor 451a can function as one of the source electrode and the drain electrode, and the conductor 450b and the conductor 451b can function as the other of the source electrode and the drain electrode. Since the regions 426b and 426c have low resistances, the contact resistance between the conductor 450a and the region 426b and the contact resistance between the conductor 450b and the region 426c can be reduced, and the on-current of the transistor 200 can be increased.

Here, as the conductor 450a and the conductor 450b, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen, similarly to the conductor 310a and the like. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used, and a single layer or a laminated layer may be used. As a result, it is possible to prevent impurities such as hydrogen and water from being mixed into the metal oxide 406 from the layer above the insulator 280 through the conductor 451a and the conductor 451b.

Further, as the conductor 451a and the conductor 451b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, although not shown, the conductor 451a and the conductor 451b may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.

In addition, in FIG. 16B and FIG. 18A, the conductor 450a and the conductor 450b are in contact with both the metal oxide 406a and the metal oxide 406b, but the present invention is not limited to this, and for example, metal oxidation. It may be configured to be in contact with only the object 406b. Further, the heights of the upper surfaces of the conductor 450a, the conductor 451a, the conductor 450b, and the conductor 451b can be made the same. Further, in the transistor 200, the configuration in which the conductor 450a and the conductor 451a are laminated and the conductor 450b and the conductor 451b are laminated is shown, but the present invention is not limited to this. For example, only the conductor 451a and the conductor 451b may be provided.

Further, in FIGS. 16B and 18A, the insulator 224 is the bottom of the opening in which the conductor 450a and the conductor 450b are provided, but the present embodiment is not limited to this. No. As shown in FIG. 18B, the insulator 222 may be the bottom of the opening in which the conductor 450a and the conductor 450b are provided. In the case shown in FIGS. 16B and 18A, the conductor 450b (conductor 450a) is in contact with the insulator 224, the metal oxide 406a, the metal oxide 406b, the insulator 225, and the insulator 280. .. In the case shown in FIG. 18B, the conductor 450b (conductor 450a) is in contact with the insulator 222, the insulator 224, the metal oxide 406a, the metal oxide 406b, the insulator 225, and the insulator 280.

Next, the constituent materials of the transistor 200 will be described.

<Board>
As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like. Further, examples of the semiconductor substrate include a semiconductor substrate such as silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

Further, a flexible substrate may be used as the substrate. As a method of providing the transistor on the flexible substrate, there is also a method of forming the transistor on the non-flexible substrate, peeling the transistor, and transposing it to the substrate which is the flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. As the substrate, a sheet, film, foil, or the like in which fibers are woven may be used. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Alternatively, it may have a property of not returning to the original shape. The substrate has, for example, a region having a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of the semiconductor device having a transistor can be reduced. Further, by making the substrate thinner, it may have elasticity even when glass or the like is used, or it may have a property of returning to the original shape when bending or pulling is stopped. Therefore, it is possible to alleviate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, it is possible to provide a durable semiconductor device.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. As for the substrate which is a flexible substrate, the lower the coefficient of linear expansion, the more the deformation due to the environment is suppressed, which is preferable. As the substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less may be used. .. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like. In particular, aramid has a low coefficient of linear expansion and is therefore suitable as a substrate that is a flexible substrate.

<Insulator>
Examples of the insulator include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like having insulating properties.

By surrounding the transistor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. For example, as the insulator 222 and the insulator 214, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulators containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers.

Further, for example, examples of the insulator 222 and the insulator 214 include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, and nitrided oxides. Silicon oxide, silicon nitride, or the like may be used. The insulator 222 and the insulator 214 preferably have aluminum oxide, hafnium oxide, or the like.

Examples of the insulator 384, insulator 216, insulator 220, insulator 224 and insulator 412 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, and the like. Insulators containing yttrium, gallium, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers. For example, as the insulator 384, the insulator 216, the insulator 220, the insulator 224, and the insulator 412, it is preferable to have silicon oxide, silicon oxide nitride, or silicon nitride.

The insulator 220, the insulator 222, the insulator 224, and / or the insulator 412 preferably has an insulator having a high relative permittivity. For example, insulator 220, insulator 222, insulator 224, and / or insulator 412 may be gallium oxide, hafnium oxide, zirconium oxide, oxides with aluminum and hafnium, nitrides with aluminum and hafnium, silicon and It is preferable to have an oxide having hafnium, an oxide nitride having silicon and hafnium, a nitride having silicon and hafnium, and the like. Alternatively, the insulator 220, the insulator 222, the insulator 224, and / or the insulator 412 preferably has a laminated structure of silicon oxide or silicon oxide nitride and an insulator having a high relative permittivity. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with an insulator having a high relative permittivity to form a laminated structure that is thermally stable and has a high relative permittivity. For example, in the insulator 224 and the insulator 412, by adopting a structure in which aluminum oxide, gallium oxide or hafnium oxide is in contact with the metal oxide 406, silicon contained in the silicon oxide or silicon oxide nitride is mixed in the metal oxide 406. Can be suppressed. Further, for example, in the insulator 224 and the insulator 412, by forming the silicon oxide or silicon oxide nitride in contact with the metal oxide 406, aluminum oxide, gallium oxide or hafnium oxide, silicon oxide or silicon nitride nitride can be obtained. A trap center may be formed at the interface of. The trap center may be able to fluctuate the threshold voltage of the transistor in the positive direction by capturing electrons.

The insulator 384, the insulator 216, and the insulator 280 preferably have an insulator having a low relative permittivity. For example, the insulator 384, the insulator 216, and the insulator 280 were added with silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon added, carbon and nitrogen. It is preferable to have silicon oxide, silicon oxide having pores, a resin, or the like. Alternatively, the insulator 384, the insulator 216, and the insulator 280 were added with silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon added, carbon and nitrogen. It is preferable to have a laminated structure of silicon oxide or silicon oxide having pores and a resin. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

As the insulator 418 and the insulator 419, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used. Examples of the insulator 418 and the insulator 419 include metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, and silicon nitride. Alternatively, silicon nitride or the like may be used.

<Conductor>
The conductors 404a, 404b, conductor 310a, conductor 310b, conductor 450a, conductor 450b, conductor 451a and conductor 451b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and the like. A material containing one or more metal elements selected from titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium and the like can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.

Further, as the conductor, particularly the conductor 404a, the conductor 310a, the conductor 450a, and the conductor 450b, a conductive material containing a metal element and oxygen contained in the metal oxide applicable to the metal oxide 406 is used. You may. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide 406. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

When an oxide is used in the channel forming region of the transistor, it is preferable to use a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined as a gate electrode. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.

<Metal oxide applicable to metal oxide 406>
The metal oxide 406 according to the present invention will be described below. As the metal oxide 406, it is preferable to use a metal oxide that functions as an oxide semiconductor.

The metal oxide 406 preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.

Here, consider the case where the metal oxide 406 has indium, the element M, and zinc. The terms of the atomic number ratios of indium, element M, and zinc contained in the metal oxide 406 are [In], [M], and [Zn].

Hereinafter, the preferable range of the atomic number ratio of indium, element M, and zinc contained in the metal oxide 406 will be described with reference to FIGS. 19 (A), 19 (B), and 19 (C). Note that FIGS. 19 (A), 19 (B), and 19 (C) do not describe the atomic number ratio of oxygen.

In FIGS. 19 (A), 19 (B), and 19 (C), the broken line indicates the atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line where (-1 ≤ α ≤ 1), [In]: [M]: [Zn] = (1 + α): (1-α): Line where the atomic number ratio is 2, [In]: [M] : [Zn] = (1 + α): (1-α): A line having an atomic number ratio of 3, [In]: [M]: [Zn] = (1 + α): (1-α): 4 atomic numbers It represents a line having a ratio and a line having an atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 5.

The one-point chain line is a line having an atomic number ratio of [In]: [M]: [Zn] = 5: 1: β (β ≧ 0), [In]: [M]: [Zn] = 2: Line with an atomic number ratio of 1: β, [In]: [M]: [Zn] = 1: 1: Line with an atomic number ratio of β, [In]: [M]: [Zn] = 1: 2: Atomic number ratio of β, [In]: [M]: [Zn] = 1: 3: β atomic number ratio, and [In]: [M]: [Zn] = 1 : Represents a line having an atomic number ratio of 4: β.

Further, the atomic number ratio of [In]: [M]: [Zn] = 0: 2: 1 and its vicinity values shown in FIGS. 19 (A), 19 (B), and 19 (C). Metal oxides tend to have a spinel-type crystal structure.

In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic number ratio is in the vicinity of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel-type crystal structure and a layered crystal structure tend to coexist. Further, when the atomic number ratio is in the vicinity of [In]: [M]: [Zn] = 1: 0: 0, two phases of a big bite-type crystal structure and a layered crystal structure tend to coexist. When a plurality of phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.

The region A shown in FIG. 19A shows an example of a preferable range of atomic number ratios of indium, element M, and zinc contained in the metal oxide 406.

By increasing the content of indium in the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide having a high indium content has a higher carrier mobility than a metal oxide having a low indium content.

On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility is low. Therefore, when the atomic number ratio is [In]: [M]: [Zn] = 0: 1: 0 and its neighboring values (for example, region C shown in FIG. 19C), the insulating property is high. ..

For example, the metal oxide used for the metal oxide 406b preferably has a high carrier mobility and has an atomic number ratio shown in region A in FIG. 19 (A). The metal oxide used for the metal oxide 406b may be, for example, In: Ga: Zn = 4: 2: 3 to 4.1, or a value in the vicinity thereof. On the other hand, the metal oxide used for the metal oxide 406a preferably has an atomic number ratio shown in region C of FIG. 19C, which has a relatively high insulating property. The metal oxide used for the metal oxide 406a may be, for example, about In: Ga: Zn = 1: 3: 4.

In particular, in the region B shown in FIG. 19B, an excellent metal oxide having high carrier mobility and high reliability can be obtained even in the region A.

The region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1, and values in the vicinity thereof. The neighborhood value includes, for example, [In]: [M]: [Zn] = 5: 3: 4. Further, the region B includes [In]: [M]: [Zn] = 5: 1: 6 and its neighboring values, and [In]: [M]: [Zn] = 5: 1: 7 and its vicinity. Includes neighborhood values.

When In-M-Zn oxide is used as the metal oxide 406, it is preferable to use a target containing polycrystalline In-M-Zn oxide as the sputtering target. The atomic number ratio of the metal oxide to be formed includes a fluctuation of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide 406 is In: Ga: Zn = 4: 2: 4.1 [atomic number ratio], the composition of the metal oxide to be formed is In: Ga: Zn. = It may be in the vicinity of 4: 2: 3 [atomic number ratio]. When the composition of the sputtering target used for the metal oxide 406 is In: Ga: Zn = 5: 1: 7 [atomic number ratio], the composition of the metal oxide to be formed is In: Ga: Zn = 5. It may be in the vicinity of 1: 6 [atomic number ratio].

The properties of metal oxides are not uniquely determined by the atomic number ratio. Even if the atomic number ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when the metal oxide 406 is formed by a sputtering apparatus, a film having an atomic number ratio deviating from the target atomic number ratio is formed. Further, depending on the substrate temperature at the time of film formation, the [Zn] of the film may be smaller than the [Zn] of the target. Therefore, the region shown is a region showing an atomic number ratio in which the metal oxide tends to have a specific property, and the boundary between the regions A and C is not strict.

<Composition of metal oxide>
Hereinafter, the configuration of the CAC (Cloud-Aligned Company) -OS that can be used for the OS transistor will be described.

In addition, in this specification and the like, it may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Company). In addition, CAAC represents an example of a crystal structure, and CAC represents an example of a function or a composition of a material.

The CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. When CAC-OS or CAC-metal oxide is used for the active layer of the transistor, the conductive function is the function of flowing electrons (or holes) that serve as carriers, and the insulating function is the function of flowing electrons (or holes) that serve as carriers. It is a function that does not shed. By making the conductive function and the insulating function act in a complementary manner, a switching function (on / off function) can be imparted to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carriers flow, the carriers mainly flow in the components having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of metal oxide>
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystal oxide semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide semiconductor (a-lique). OS: atomous-like oxide semiconductor) and amorphous oxide semiconductors.

CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. It is thought that this is the reason.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as the (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can be expressed as the (In, M) layer.

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since a clear crystal grain boundary cannot be confirmed, it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

<Transistor with metal oxide>
Subsequently, a case where the above metal oxide is used for a transistor will be described.

By using the metal oxide in the transistor, a transistor having high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.

Further, it is preferable that the transistor has a low carrier density in the region 426a of the metal oxide 406b. When the carrier density of the metal oxide is lowered, the impurity concentration in the metal oxide may be lowered and the defect level density may be lowered. In the present specification and the like, a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the carrier density in region 426a of the metal oxide 406b ^{is less than 8 × 10 11} / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^It may be -9 / cm ³ or more.

In addition, a metal oxide having high purity intrinsicity or substantially high purity intrinsicity may have a low trap level density because of its low defect level density.

In addition, the charge captured at the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the region 426a of the metal oxide 406b. Further, in order to reduce the impurity concentration in the region 426a of the metal oxide 406b, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

<Impurities>
Here, the influence of each impurity in the metal oxide will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the metal oxide, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon (concentration obtained by SIMS) in the region 426a of the metal oxide 406b is set to 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the region 426a of the metal oxide 406b. Specifically, the concentration of the alkali metal or alkaline earth metal in the region 426a of the metal oxide 406b obtained by SIMS is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To.

Further, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density is increased, and the metal oxide is easily formed into an n-type. As a result, the transistor containing nitrogen in the region 426a of the metal oxide 406b tends to have a normally-on characteristic. Therefore, it is preferable that the nitrogen is reduced as much as possible in the region 426a of the metal oxide 406b, for example, the nitrogen concentration in the region 426a of the metal oxide 406b is less than ^{5 × 10 19} atoms / cm ^{3 in SIMS.} , Preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor containing a large amount of hydrogen in the region 426a of the metal oxide 406b tends to have a normally-on characteristic. Therefore, it is preferable that the hydrogen in the region 426a of the metal oxide 406b is reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS ^{is less than 1 × 10 20} atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. ^{Less than 3} , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By sufficiently reducing the impurities in the region 426a of the metal oxide 406b, stable electrical characteristics can be imparted to the transistor.

<< Transistor 201 >>
Next, the details of the transistor 201 shown in FIG. 15 will be described.

FIG. 20A is a top view of the semiconductor device having the transistor 201. Further, FIG. 20B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 20A, and is also a cross-sectional view of the transistor 201 in the channel length direction. Further, FIG. 20C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 20A, and is also a cross-sectional view of the transistor 201 in the channel width direction. In the top view of FIG. 20 (A), some elements are omitted for the sake of clarity of the figure. Further, among the components of the transistor 201, those common to the transistor 200 have the same reference numerals.

As shown in FIGS. 20A to 20C, the conductor 201 includes an insulator 224 arranged on a substrate (not shown), a metal oxide 406a arranged on the insulator 224, and the like. A metal oxide 406b arranged in contact with at least a part of the upper surface of the metal oxide 406a, a conductor 452a and a conductor 452b arranged in contact with at least a part of the upper surface of the metal oxide 406b, and a metal oxide. On the metal oxide 406c, which is in contact with at least a part of the upper surface of the 406b and is arranged on the conductor 452a and the conductor 452b, the insulator 413 which is arranged on the metal oxide 406c, and the insulator 413. It has a conductor 405a arranged, a conductor 405b arranged on the conductor 405a, and an insulator 420 arranged on the conductor 405b.

The conductor 405 (conductor 405a and conductor 405b) can function as a top gate, and the conductor 310 can function as a back gate. The potential of the back gate may be the same potential as that of the top gate, or may be a ground potential or an arbitrary potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate independently without interlocking with the top gate.

The conductor 405a can be provided by using the same material as the conductor 404a of FIG. The conductor 405b can be provided by using the same material as the conductor 404b of FIG.

The conductor 452a has a function as one of the source electrode and the drain electrode, and the conductor 452b has a function as the other of the source electrode and the drain electrode.

As the conductors 452a and 452b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component can be used. Further, although the single-layer structure is shown in the figure, a laminated structure of two or more layers may be used. Further, a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

In the transistor 201, the channel is preferably formed in the metal oxide 406b. Therefore, it is preferable to use a material having a relatively high insulating property as the metal oxide 406c as compared with the metal oxide 406b. As the metal oxide 406c, the same material as the metal oxide 406a may be used.

By providing the metal oxide 406c in the transistor 201, the transistor 201 can be made into an embedded channel type transistor. In addition, oxidation of the ends of the conductor 452a and the conductor 452b can be prevented. Further, it is possible to prevent a leakage current between the conductor 405 and the conductor 452a (or the conductor 405 and the conductor 452b). The metal oxide 406c may be omitted in some cases.

For the insulator 420, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. For example, as the insulator 420, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, silicon nitride or silicon nitride, etc. It may be used.

By providing the insulator 420 in the transistor 201, it is possible to prevent the conductor 405 from being oxidized. In addition, impurities such as water and hydrogen can be prevented from entering the metal oxide 406.

The transistor 201 can have a larger contact area between the metal oxide 406b and the electrode (source electrode or drain electrode) than the transistor 200. Further, the step of producing the region 426b and the region 426c shown in FIG. 16 becomes unnecessary. Therefore, the transistor 201 can have a larger on-current than the transistor 200. Moreover, the manufacturing process can be simplified.

For details of the other components of the transistor 201, refer to the description of the transistor 200.

(Embodiment 5)
In the present embodiment, the storage device according to the present invention will be described with reference to FIGS. 21 and 22.

<Configuration example of memory cell 600>
The memory cell 600 shown in FIG. 21 (A) is composed of a signal line S1, a word line WL, a transistor 601, a transistor 602, and a capacitance element 603. The transistor 601 is formed of a material other than an oxide semiconductor, and it is preferable that the transistor 602 uses an OS transistor. Here, it is preferable that the transistor 602 has the same configuration as the transistor 200 or the transistor 201 shown in the fourth embodiment. Further, the transistor 601 preferably has the same configuration as the transistor 300 shown in the third embodiment. Further, the memory cell 600 is electrically connected to the source line SL and the bit line B1 and is electrically connected to the source line SL and the bit line B1 via a transistor (including those constituting other memory cells). May be connected.

Here, the gate electrode of the transistor 601, one of the source electrode or the drain electrode of the transistor 602, and one of the electrodes of the capacitive element 603 are electrically connected. Further, the source line SL and the source electrode of the transistor 601 are electrically connected, the bit line B1 and the drain electrode of the transistor 601 are electrically connected, and the signal line S1 and the gate electrode of the transistor 602 are electrically connected. Is electrically connected, and the word wire WL, the other of the source electrode or drain electrode of the transistor 602, and the other of the electrodes of the capacitive element 603 are electrically connected. The source line SL and the source electrode of the transistor 601 may be connected via a transistor (including those constituting other memory cells). Further, the bit wire B1 and the drain electrode of the transistor 601 may be connected via a transistor (including those constituting other memory cells).

<Configuration example of storage device 11>
FIG. 22 shows a block circuit diagram of a storage device 11 having a storage capacity of m × n bits. Here, as an example, a NAND type semiconductor device in which memory cells 600 are connected in series is shown.

The semiconductor device according to one aspect of the present invention includes m word lines WL, n bit lines B1 and signal lines S1, two selection lines SEL (1) and SEL (2), and a plurality of memories. A memory cell array 610 in which cells 600 (1, 1) to 600 (m, n) are arranged in a matrix of m vertical (rows) x n horizontal (columns) (m, n are integers of 2 or more). Transistors 615 (1, 1) arranged between bit lines B1 (1) to B1 (n) and memory cells 600 (1, 1) to 600 (1, n) along the selection line SEL (1). To 615 (1, n) and along the selection line SEL (2) between the source lines SL (1) to SL (n) and the memory cells 600 (m, 1) to 600 (m, n). It is composed of peripheral circuits such as transistors 615 (2, 1) to 615 (2, n), a bit line and signal line drive circuit 611, a word line drive circuit 613, and a read circuit 612. A refresh circuit or the like may be provided as another peripheral circuit.

The memory cells 600 (i, j) (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) are connected to the signal line S1 (j) and the word line WL (i), respectively. Further, the memory cell _{600 (i 1, j) (} i 1 is 2 or more, an integer m) the drain electrode of the transistor 601 included in the memory cell ₆₀₀ (i 1 -1, j) the source electrode of the transistor 601 has Connected to. The drain electrode of the transistor 601 of the memory cell 600 (1, j) is connected to the source electrode of the transistor 615 (1, j), and the source electrode of the transistor 601 of the memory cell 600 (m, j) is the transistor 615. It is connected to the drain electrode of (2, j). The drain electrode of the transistor 615 (1, j) is connected to the bit line B1 (j), and the source electrode of the transistor 615 (2, j) is connected to the source line SL (j). Further, the gate electrode of the transistor 615 (1, j) is connected to the selection line SEL (1), and the gate electrode of the transistor 615 (2, j) is connected to the selection line SEL (2).

Further, the bit lines B1 (1) to B1 (n) and the signal lines S1 (1) to S1 (n) are connected to the drive circuit 611 with the word lines WL (1) to WL (m) and the selection line SEL (1). The SEL (2) is connected to the drive circuit 613, respectively. Further, the bit lines B1 (1) to B1 (n) are also connected to the read circuit 612. The potential Vs is given to the source lines SL (1) to SL (n). The source lines SL (1) to SL (n) do not necessarily have to be separated, and may be configured to be electrically connected to each other.

<Operation example of storage device 11>
Next, the operation of the storage device shown in FIG. 22 will be described. In this configuration, writing is performed column by column and reading is performed row by row.

When writing to the memory cells 600 (1, j) to 600 (m, j) in the jth column, the potential of the signal line S1 (j) is set to V1 (arbitrary potential, for example, 2V), and the target memory cell. The transistor 602 of the above is turned on. On the other hand, the potential of the signal line S1 other than the j-th column is set to V0 (arbitrary potential, for example, 0V), and the transistor 602 of the non-target memory cell is turned off. In the other wiring, the potentials of the bit lines B1 (1) to B1 (n) are V0, the potentials of the selection lines SEL (1) and SEL (2) are V0, and the potentials of the source lines SL (1) to SL (n). Let Vs be V0. Here, the potential V1 is set to a potential that turns on the transistor 601 and the transistor 602 and the transistor 615 by applying the potential V1 to the gate electrode, and the potential V0 is applied to the gate electrode to set the transistor 601 and the transistor 602. The potential is set so that the transistor 615 is turned off.

In this state, data is written by setting the potential VWL of the word line WL to a predetermined potential. For example, when writing data "1", the potential of the word line WL connected to the target memory cell is set to Vw_1, and when writing data "0", the potential of the word line WL connected to the target memory cell is set. Is Vw_0. At the end of writing, the potential of the signal line S1 (j) is set to V0 and the transistor 602 of the target memory cell is turned off before the potential of the word line WL changes.

Here, a charge QA corresponding to the potential VWL of the word line WL at the time of writing is accumulated in the node connected to the gate electrode of the transistor 601 (hereinafter referred to as node A), whereby data is stored. .. Here, since the off-current of the transistor 602 is extremely small, the written data is held for a long time. In the memory cells of the other columns, the charge QA stored in node A does not change.

The potential of the bit lines B1 (1) to B1 (n) at the time of writing was set to V0, but the transistor 615 (1,1) to 615 (1, n) was in the off state, and was in a floating state or an arbitrary state. It may be charged to an electric potential.

Further, when the semiconductor device does not have the substrate potential, such as when a transistor is formed on the SOI substrate at the time of writing, data is written to the memory cell as follows, for example. First, the potential of the selection line SEL (1) is set to V0, the potential of the selection line SEL (2) is set to V1, the transistor 615 (1, j) is turned off, and the transistor 615 (2, j) is turned on. Further, the potential of the signal line S1 (j) is set to V1, and the transistors 602 of the memory cells 600 (1, j) to 600 (m, j) in the jth column are turned on. Further, the potential of the word lines WL (1) to WL (m) is set to V1, and the transistor 601 of the memory cells 600 (1, j) to 600 (m, j) in the jth column is turned on. Next, the above-mentioned data is written by setting the potential VWL of the word line WL to a predetermined potential in order from the memory cell 600 (1, j) in the first row. When the writing of data up to the memory cell 600 (m, j) in the mth row is completed, the potential of the selection line SEL (2) is set to V0, and the transistor 615 (2, j) is turned off. As a result, data can be written while the potential of the source electrode of the transistor 601 of the memory cell in the j-th column is set to about V0. Further, for other wiring, the same as the above-mentioned data writing may be performed. Although the method of writing data in the order of the first line to the mth line has been described, the method is not limited to this, and the potential of the bit lines B1 (1) to B1 (n) is set to V0 and the selection line SEL is used. Data may be written in the order of the mth row to the first row with the potential of (1) set to V1 and the transistor 615 (1, j) turned on.

On the other hand, when the semiconductor device has a substrate potential, such as when a transistor is formed on a single crystal semiconductor substrate, the above data may be written with the substrate potential set to 0V.

The reading of the memory cells 600 (i, 1) to 600 (i, n) in the i-th row is also performed by setting the potential VWL of the word line WL to a predetermined potential. When reading the memory cells 600 (i, 1) to 600 (i, n) in the i-th row, the potentials of the selection lines SEL (1) and SEL (2) are set to V1, and the potentials of the signal lines S1 (1) to S1 are set. The potential of (n) is V0, the potential Vs of the source lines SL (1) to SL (n) is V0, and the read circuit 612 connected to the bit lines B1 (1) to B1 (n) is in the operating state. As a result, the transistors 615 (1, 1) to 615 (2, n) are turned on, and the transistors 602 of all memory cells are turned off.

Then, the potential of the word line WL (i) is Vr_1, and the potential of the word line WL other than the i-th line is Vr_0. At this time, the transistors 601 of the memory cells other than the i-th row are turned on. As a result, the resistance state of the memory cell column is determined depending on whether the transistor 601 of the memory cell in row i is on or off. Among the memory cells in the i-th row, in the memory cell having the data "0", the transistor 601 is turned off and the memory cell column is in the high resistance state. On the other hand, among the memory cells in the i-th row, in the memory cell having the data "1", the transistor 601 is turned on and the memory cell column is in the low resistance state. As a result, the read circuit 612 can read the data "0" and "1" from the difference in the resistance state of the memory cell sequence.

Next, a method for determining the potentials Vw_0 and Vw_1 of the word line WL at the time of writing and the potentials Vr_0 and Vr_1 of the word line WL at the time of reading will be described.

The potential VA of the node A that determines the state of the transistor 601 depends on the capacitance CGS between the gate and the source (drain) of the transistor 601 and the capacitance CS of the capacitance element 603. VA can be expressed as follows by using the potential VWL (book) of the word line WL at the time of writing and the potential VWL (reading) of the word line WL at the time of reading.
VA = (CGS / VWL (book) + CS / VWL (reading)) / (CGS + CS)

In the memory cell 600 in which the read is in the selected state, VWL (read) = Vr_1, and in the memory cell 600 in which the read is in the non-selected state, VWL (read) = Vr_1. Further, when writing the data "1", VWL (book) = Vw_1, and when writing the data "0", VWL (book) = Vw_1. That is, the potential of the node A in each state can be expressed as follows.
Read is selected, data "1"
VA ≒ (CGS / Vw_1 + CS / Vr_1) / (CGS + CS)
Read is selected, data "0"
VA ≒ (CGS ・ Vw_0 + CS ・ Vr_1) / (CGS + CS)
Read is not selected, data "1"
VA ≒ (CGS / Vw_1 + CS / Vr_0) / (CGS + CS)
Read is not selected, data "0"
VA ≒ (CGS ・ Vw_0 + CS ・ Vr_0) / (CGS + CS)

When the read is in the selected state and the data "1" is written, it is desirable that the transistor 601 is turned on, and the potential VA of the node A sets the threshold voltage Vth of the transistor 601. It is desirable to exceed. That is, it is desirable to satisfy the following equation.
(CGS / Vw_1 + CS / Vr_1) / (CGS + CS)> Vth

When the read is in the selected state and the data "0" is written, it is desirable that the transistor 601 is in the off state, and the potential VA of the node A sets the threshold voltage Vth of the transistor 601. It is desirable to fall below. That is, it is desirable to satisfy the following equation.
(CGS / Vw_0 + CS / Vr_1) / (CGS + CS) <Vth

When the read is in the non-selected state, the transistor 601 needs to be in the ON state regardless of whether data “1” or data “0” is written, so that the potential VA of the node A is VA. Is required to exceed the threshold voltage Vth of the transistor 601. That is, it is necessary to satisfy the following equation.
(CGS / Vw_1 + CS / Vr_0) / (CGS + CS)> Vth
(CGS / Vw_0 + CS / Vr_0) / (CGS + CS)> Vth

The semiconductor device can be operated by determining Vw_0, Vw_1, Vr_0, Vr_1, etc. so as to satisfy the above relationship. For example, when the threshold voltage Vth = 0.3 (V) of the transistor 601 and CGS / CS = 1, V0 = 0 (V), V1 = 2 (V), Vw_0 = 0 (V), Vw_1 = 2 (V), Vr_0 = 2 (V), Vr_1 = 0 (V). It should be noted that these potentials are only examples, and can be appropriately changed within a range satisfying the above conditions.

Here, under the condition of CGS / CS << 1, the node A and the word line WL are strongly coupled to each other. Therefore, regardless of whether the transistor 602 is on or off, the potential of the word line WL and the potential of the node A Is about the same. Therefore, even if the transistor 602 is turned on and writing is performed, the charge that can be accumulated by the node A is small, so that the difference between the data "0" and the data "1" becomes small.

Specifically, when the above-mentioned reading is performed with the potential of the selected word line WL as Vr_1, the potential of the node A of the memory cell is the potential regardless of whether data “0” or data “1” is written. It descends and the transistor 601 is turned off. As a result, it becomes difficult to read the data.

On the other hand, under the condition of CGS / CS >> 1, since the connection between the node A and the word line WL is weak, the potential of the node A hardly changes even if the potential of the word line WL is changed. Therefore, the potential of the node A capable of controlling the on / off state of the transistor 601 is very limited, and it becomes difficult to control the on / off state of the transistor 601.

Specifically, when the above-mentioned reading is performed with the potential of the non-selected word line WL as Vr_0, the potential of the node A of the memory cell hardly rises, and the transistor 601 of the data “0” is turned off. As a result, it becomes difficult to read the data.

As described above, since the operation may be difficult depending on the size of CGS and CS, it is necessary to pay attention to these decisions. When Vw_0 = 0 (V), Vw_1 = Vdd, Vr_0 = 0 (V), and Vr_1 = Vdd, CGS / CS is Vth / (Vdd-Vth) or more (Vdd-Vth) / Vth or less. If it is in between, it can be operated sufficiently.

Since the data "1" and the data "0" are merely distinctions for convenience, they may be interchanged. Further, a ground potential GND or the like may be adopted as V0, and a power supply potential Vdd or the like may be adopted as V1.

Since the off-current of the OS transistor is extremely small, it is possible to retain the stored contents for an extremely long period of time by using the OS transistor. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Moreover, even when there is no power supply, it is possible to retain the stored contents for a long period of time.

In addition, a high voltage is not required for writing information, and there is no problem of element deterioration. Further, since information is written depending on whether the transistor is on or off, high-speed operation can be easily realized. In addition, there is an advantage that the operation for erasing the information required in the flash memory or the like is unnecessary.

<Configuration example of memory cell 620>
Next, a form of a memory cell different from the memory cell 600 is shown in FIG. 21 (B). The memory cell 620 shown in FIG. 21B is composed of a signal line S1, a word line WL, a transistor 621, a transistor 622, and a capacitance element 623. The transistor 621 is formed of a material other than an oxide semiconductor, and the transistor 622 preferably uses an OS transistor. Here, it is preferable that the transistor 621 has the same configuration as the transistor 300 shown in the third embodiment. Further, the transistor 622 preferably has the same configuration as the transistor 200 or the transistor 201 shown in the fourth embodiment. Further, the memory cell 620 is electrically connected to the source line SL and the bit line B1 and is electrically connected to the source line SL and the bit line B1 via a transistor (including those constituting other memory cells). It may be connected to.

Here, the gate electrode of the transistor 621, one of the source electrode or the drain electrode of the transistor 622, and one of the electrodes of the capacitive element 623 are electrically connected. Further, the source line SL and the source electrode of the transistor 621 are electrically connected, the bit line B1 and the drain electrode of the transistor 621 are electrically connected, and the signal line S1 and the source electrode of the transistor 622 are electrically connected. Alternatively, the other of the drain electrodes is electrically connected, and the word wire WL, the gate electrode of the transistor 622, and the other of the electrodes of the capacitive element 623 are electrically connected. The source line SL and the source electrode of the transistor 621 may be connected via a transistor (including those constituting other memory cells). Further, the bit wire B1 and the drain electrode of the transistor 621 may be connected via a transistor (including those constituting other memory cells).

<Operation of memory cell 620>
Next, the operation of the memory cell 620 will be specifically described.

When writing to the memory cell 620, the potential of the source electrode or drain electrode of the transistor 621 is V0 (arbitrary potential, for example 0V), and the potential of the word line WL is V1 (arbitrary potential, for example 2V). At this time, the transistor 622 is turned on.

In this state, data is written by setting the potential VS1 of the signal line S1 to a predetermined potential. For example, when writing the data "1", the potential of the signal line S1 is Vw_1, and when writing the data "0", the potential of the signal line S1 is Vw_1. At the end of writing, the potential of the word line WL is set to V0 and the transistor 622 is turned off before the potential of the signal line S1 changes.

A charge QA corresponding to the potential of the signal line S1 at the time of writing is accumulated in the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 621, whereby data is stored. Here, since the off-current of the transistor 622 is extremely small or substantially zero, the written data is retained for a long time.

The reading of the memory cell 620 is performed by setting the potential VWL of the word line WL to a predetermined potential. For example, the memory cell 620 that reads out has the potential of the word line WL set to Vr_1, and the memory cell 620 that does not read out has the potential of the word line WL set to Vr_1. In either case, the potential of the signal line S1 is V1.

The potentials Vw_1 and Vw_0 of the signal line S1 at the time of writing and the potentials Vr_1 and Vr_1 of the word line WL at the time of reading are the memory cells in which the data "1" is stored when the potential of the word line WL is Vr_1. The transistor 621 is turned on, and the transistor 621 of the memory cell in which the data "0" is stored is set to be turned off. Further, the transistor 622 is set to be in the off state. Further, when the potential of the word line WL is set to Vr_0, the transistor 621 of the memory cell is in the ON state and the transistor 622 is in the OFF state regardless of whether the data “0” or the data “1” is stored. Set to be.

When a NAND-type non-volatile memory is configured by using the memory cell 620, the read operation can be performed by using the potentials having the above-mentioned relationship. That is, in the memory cell for which reading is selected, the resistance state can be changed depending on the stored data, and in the other memory cells in the memory cell column, the resistance state can be set to the low resistance state regardless of the stored data. .. As a result, the data in the memory cell can be read out by using the read-out circuit that detects the difference in the resistance state of the bit line B1.

Since the data "1" and the data "0" are merely distinctions for convenience, they may be interchanged. Further, a ground potential GND or the like may be adopted as V0, and a power supply potential Vdd or the like may be adopted as V1.

Even when the memory cell 620 shown in the present embodiment is used, a matrix-like semiconductor device can be realized. The matrix-shaped semiconductor device can be realized by using a circuit similar to the configuration shown in the previous embodiment and appropriately configuring a drive circuit, a read circuit, and a write circuit according to the configuration of the signal line. When the memory cell 620 is used, both reading and writing are performed row by row.

(Embodiment 6)
In the present embodiment, one form of the semiconductor device having the storage device of the above-described embodiment will be described with reference to FIGS. 23 and 24.

<Semiconductor wafers and chips>
FIG. 23A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a "semiconductor wafer") can be used. A plurality of circuit regions 712 are provided on the substrate 711. A semiconductor device or the like according to one aspect of the present invention can be provided in the circuit area 712.

Each of the plurality of circuit areas 712 is surrounded by a separation area 713. A separation line (also referred to as a “dicing line”) 714 is set at a position overlapping the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit area 712 can be cut out from the substrate 711. FIG. 23 (B) shows an enlarged view of the chip 715.

Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD that may occur during the dicing step can be alleviated, and a decrease in yield due to the dicing step can be prevented. Further, in general, the dicing step is performed while supplying pure water with reduced specific resistance by dissolving carbon dioxide gas or the like to the cutting portion for the purpose of cooling the substrate, removing shavings, preventing antistatic, and the like. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Moreover, the productivity of the semiconductor device can be increased.

<Electronic components>
An example of an electronic component using the chip 715 will be described with reference to FIGS. 24 (A) and 24 (B). The electronic component is also referred to as a semiconductor package or an IC package. Electronic components have a plurality of standards, names, etc., depending on the terminal take-out direction, the shape of the terminal, and the like.

In the assembly process (post-process), the electronic component is completed by combining the semiconductor device shown in the above embodiment and a component other than the semiconductor device.

The post-process will be described with reference to the flowchart shown in FIG. 24 (A). After forming the semiconductor device or the like according to one aspect of the present invention on the substrate 711 in the previous step, a "back surface grinding step" for grinding the back surface of the substrate 711 (the surface on which the semiconductor device or the like is not formed) is performed (step S721). .. By thinning the substrate 711 by grinding, it is possible to reduce the size of electronic components.

Next, a "dicing step" for separating the substrate 711 into a plurality of chips 715 is performed (step S722). Then, a "die bonding step" is performed in which the separated chips 715 are bonded onto the individual lead frames (step S723). For joining the chip 715 and the lead frame in the die bonding step, a method suitable for the product is appropriately selected, such as joining with a resin or joining with a tape. The chip 715 may be bonded on the interposer substrate instead of the lead frame.

Next, a "wire bonding step" is performed in which the leads of the lead frame and the electrodes on the chip 715 are electrically connected by a thin metal wire (wire) (step S724). A silver wire, a gold wire, or the like can be used as the thin metal wire. Further, as the wire bonding, for example, ball bonding or wedge bonding can be used.

The wire-bonded chip 715 is subjected to a "sealing step (molding step)" in which the chip 715 is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and the characteristics deteriorate (reliability) due to moisture, dust, etc. (Decrease) can be reduced.

Next, a "lead plating step" for plating the leads of the lead frame is performed (step S726). The plating process prevents rust on the leads, and soldering can be performed more reliably when mounting on a printed circuit board later. Next, a "molding step" of cutting and molding the lead is performed (step S727).

Next, a "marking step" is performed in which a printing process (marking) is performed on the surface of the package (step S728). Then, the electronic component is completed through an "inspection step" (step S729) for checking the quality of the appearance shape, the presence or absence of malfunction, and the like.

Further, a schematic perspective view of the completed electronic component is shown in FIG. 24 (B). FIG. 24B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. The electronic component 750 shown in FIG. 24B has a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.

The electronic component 750 shown in FIG. 24B is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are combined and electrically connected to each other on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted. The completed mounting board 754 is used for electronic devices and the like.

(Embodiment 7)
<Electronic equipment>
The storage device shown in the above embodiment can be used for various electronic devices. FIG. 25 shows a specific example of an electronic device using the storage device 10.

FIG. 25A is an external view showing an example of an automobile. The car 2980 has a body 2981, wheels 2982, dashboard 2983, lights 2984 and the like. Further, the automobile 2980 includes an antenna, a battery and the like.

The information terminal 2910 shown in FIG. 25B has a housing 2911, a display unit 2912, a microphone 2917, a speaker unit 2914, a camera 2913, an external connection unit 2916, an operation switch 2915, and the like. The display unit 2912 includes a display panel and a touch screen using a flexible substrate. Further, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet-type information terminal, a tablet-type personal computer, an electronic book terminal, or the like.

The notebook personal computer 2920 shown in FIG. 25C has a housing 2921, a display unit 2922, a keyboard 2923, a pointing device 2924, and the like. Further, the notebook personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

The video camera 2940 shown in FIG. 25 (D) has a housing 2941, a housing 2942, a display unit 2943, an operation switch 2944, a lens 2945, a connection unit 2946, and the like. The operation switch 2944 and the lens 2945 are provided in the housing 2941, and the display unit 2943 is provided in the housing 2942. Further, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected by a connecting portion 2946, and the angle between the housing 2941 and the housing 2942 can be changed by the connecting portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display unit 2943 can be changed, and the display / non-display of the image can be switched.

FIG. 25 (E) shows an example of a bangle type information terminal. The information terminal 2950 has a housing 2951, a display unit 2952, and the like. Further, the information terminal 2950 includes an antenna, a battery, and the like inside the housing 2951. The display unit 2952 is supported by a housing 2951 having a curved surface. Since the display unit 2952 includes a display panel using a flexible substrate, it is possible to provide an information terminal 2950 that is flexible, light, and easy to use.

FIG. 25F shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display unit 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, the information terminal 2960 includes an antenna, a battery, and the like inside the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games.

The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. Further, the display unit 2962 is provided with a touch sensor and can be operated by touching the screen with a finger or a stylus. For example, the application can be started by touching the icon 2967 displayed on the display unit 2962. In addition to setting the time, the operation switch 2965 can have various functions such as power on / off operation, wireless communication on / off operation, manner mode execution / cancellation, and power saving mode execution / cancellation. .. For example, the function of the operation switch 2965 can be set by the operating system incorporated in the information terminal 2960.

In addition, the information terminal 2960 can execute short-range wireless communication standardized for communication. For example, by communicating with a headset capable of wireless communication, it is possible to make a hands-free call. Further, the information terminal 2960 is provided with an input / output terminal 2966, and data can be directly exchanged with another information terminal via a connector. It is also possible to charge via the input / output terminal 2966. The charging operation may be performed by wireless power supply without going through the input / output terminal 2966.

For example, the storage device shown in the above embodiment can hold the above-mentioned control information of the electronic device, the control program, and the like for a long period of time. By using the semiconductor device according to one aspect of the present invention, a highly reliable electronic device can be realized.

In the present specification, unless otherwise specified, the on-current means the drain current when the transistor is in the on-state. The ON state (sometimes referred to as turned on), unless otherwise specified, the n-channel transistor, the voltage between the gate and source (V _G) is the threshold voltage (V _th) or more states, p in channel transistor, _{V G} refers to the following state _{V th.} For example, the on-current of the n-channel transistor, V _G refers to a drain current when the above V _th. The on-current of the transistor may be dependent on the voltage (V _D) between the drain and the source.

In the present specification, unless otherwise specified, the off current means the drain current when the transistor is in the off state. The OFF state (sometimes referred to as OFF), unless otherwise specified, the n-channel type transistor, V _G is lower than V _th state, the p-channel type transistor, V _G is higher than V _th state To say. For example, the off-current of the n-channel transistor, refers to the drain current when V _G is lower than V _th. Off-state current of the transistor may be dependent on the V _G. Accordingly, the off current of the transistor is less than ^{10 -21} A, and may refer to the value of _{V G} to off-current of the transistor is less than ^{10 -21} A are present.

Further, the off current of the transistor may depend on _{V D.} In this specification, off-state current, unless otherwise, 0.1 V the absolute value of _{V D} is, 0.8V, 1V, 1.2V, 1.8V , 2.5V, 3V, 3.3V, 10V , 12V, 16V, or 20V may represent off-current. Or it may represent an off current at V _D for use in a semiconductor device or the like includes the transistor.

In the present specification and the like, when explaining the connection relationship of transistors, one of the source and the drain is referred to as "one of the source or the drain" (or the first electrode or the first terminal), and the source and the drain are referred to. The other is referred to as "the other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of the transistor change depending on the structure or operating conditions of the transistor. The names of the source and drain of the transistor can be appropriately paraphrased according to the situation, such as the source (drain) terminal and the source (drain) electrode.

In the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y are directly connected are directly connected. It is assumed that the case is disclosed in the present specification and the like.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. This is a case where X and Y are connected without going through an element, a light emitting element, a load, etc.).

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch is in a conductive state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows. Alternatively, the switch has a function of selecting and switching the path through which the current flows. The case where X and Y are electrically connected includes the case where X and Y are directly connected.

B1 bit line, BL signal line, C1 capacitive element, C2 capacitive element, D1L data, D2L data, D11 data, D21 data, DM1 data, DML data, MEM memory cell, N1 node, PR signal line, PRB signal line, PRE Signal line, RB signal line, RBIAS signal line, RD circuit, RS signal line, RW signal line, S1 signal line, T01 time, T02 time, T03 time, T05 time, T07 time, T09 time, T11 time, T13 time, T21 time, T22 time, T23 time, T24 time, T25 time, T26 time, T27 time, T31 time, T32 time, T33 time, T36 time, T37 time, T38 time, T40 time, Tr1 transistor, Tr2 transistor, Tr3 transistor , Tr4 transistor, Tr5 transistor, Tr6 transistor, Tr7 transistor, Tr8 transistor, Tr9 transistor, Tr10 transistor, Tr11 transistor, Tr12 transistor, Tr13 transistor, Tr14 transistor, Tr15 transistor, Tr16 transistor, Tr17 transistor, Tr18 transistor, V0 potential, V1 Potential, VA potential, Vs potential, Vr_1 potential, Vr_1 potential, VS1 potential, Vw_1 potential, Vw_1 potential, VWL potential, WB signal line, WS signal line, WW signal line, 10 storage device, 10A storage device, 10B storage device, 11 storage device, 20 circuits, 21 circuits, 22 circuits, 23 D / A converters, 24 A / D converters, 24a A / D converters, 24b A / D converters, 24c A / D converters, 25 resistance elements, 2 6 comparator, 27 encoder, 30 selection circuit, 40 memory cell array, 50 decoder, 60 decoder, 71 comparator, 73 D / A converter, 74 register, 80 comparator, 81 latch, 82 AND circuit, 83 counter, 100 capacitive element, 110 Conductor, 112 Conductor, 120 Insulator, 130 Insulator, 150 Insulator, 200 Insulator, 201 Insulator, 214 Insulator, 216 Insulator, 218 Insulator, 220 Insulator, 222 Insulator, 224 Insulator, 225 Insulator, 246 Insulator, 248 Insulator, 280 Insulator, 282 Insulator, 286 Insulator, 300 Transistor, 310 Conductor, 310a Conductor, 310b Conductor, 311 Substrate, 313 Semiconductor Region, 314a Low Resistance Region, 314b Low Resistance Region, 315 Insulator, 316 Insulator, 320 Insulator, 322 Insulator, 324 Insulator, 326 Insulator, 328 Insulator, 330 Insulator, 350 Insulator, 352 Insulator, 354 Insulator, 356 Conductor, 360 Insulator, 362 Insulator, 364 Insulator, 366 Insulator, 370 Insulator, 372 Insulator, 374 Insulator, 376 Insulator, 380 Insulator, 382 Insulator, 384 Insulator, 386 Insulator , 404 Conductor, 404a Conductor, 404b Conductor, 405 Conductor, 405a Conductor, 405b Conductor, 406 Metal Oxide, 406a Metal Oxide, 406b Metal Oxide, 406c Metal Oxide, 412 Insulator, 413 Insulator, 418 Insulator, 419 Insulator, 420 Insulator, 426a Region, 426b Region, 426c Region, 440 Conductor, 440a Conductor, 440b Conductor, 450a Conductor, 450b Conductor, 451a Conductor, 451b Conductor, 452a Conductor, 452b Conductor, 600 Memory Cell, 601 Transistor, 602 Transistor, 603 Capacitive Element, 610 Memory Array, 611 Drive Circuit, 612 Circuit, 613 Drive Circuit, 615 transistor, 620 memory cell, 621 transistor, 622 transistor, 623 capacitive element, 711 board, 712 circuit area, 713 separation area, 714 separation line, 715 chip, 750 electronic components, 752 printed circuit board, 754 printed circuit board, 755 Read, 2910 information terminal, 2911 housing, 2912 display, 2913 camera, 2914 speaker, 2915 operation switch, 2916 external connection, 2917 microphone, 2920 notebook personal computer, 2921 housing, 2922 display, 2923 keyboard, 2924 pointing device, 2940 video camera, 2941 housing, 2942 housing, 2943 display unit, 2944 operation switch, 2945 lens, 2946 connection part, 2950 information terminal, 2951 housing, 2952 display unit, 2960 information terminal, 2961 housing , 2962 display, 2963 band, 2964 buckle, 2965 operation switch, 2966 input / output terminal, 2967 icon, 2980 car, 2981 body, 2982 wheels, 2983 dashboard, 2984 light

Claims (7)

With memory cells
The first circuit and
The first signal line and
The second signal line and
The third signal line and
4th signal line and
1st power line and
Has a second power line,
The memory cell has a first transistor, a second transistor, and a first capacitance element.
The first circuit includes a third transistor, a fourth transistor, and a second capacitance element.
One of the source or drain of the first transistor is electrically connected to the first signal line.
The other of the source or drain of the first transistor is electrically connected to the gate of the second transistor.
The gate of the first transistor is electrically connected to the second signal line,
The first transistor has a metal oxide in the channel forming region and has a metal oxide.
One of the source or drain of the second transistor is electrically connected to one of the source or drain of the first transistor.
The other of the source or drain of the second transistor is electrically connected to the first power line.
The second transistor is an n-channel transistor and is an n-channel transistor.
The first terminal of the first capacitance element is electrically connected to the gate of the second transistor.
The second terminal of the first capacitance element is electrically connected to the third signal line, and the second terminal is electrically connected to the third signal line.
One of the source or drain of the third transistor is electrically connected to the first signal line.
The other of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor.
The third transistor has a metal oxide in the channel forming region and has a metal oxide.
The gate of the third transistor is electrically connected to the fourth signal line.
One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the third transistor.
The other of the source or drain of the fourth transistor is electrically connected to the second power line.
The first terminal of the second capacitance element is electrically connected to the gate of the fourth transistor.
The second terminal of the second capacitance element is electrically connected to the second power supply line.
The fourth transistor is an n-channel transistor and is an n-channel transistor.
A storage device characterized in that the drain current flowing through the fourth transistor flows through the first signal line. In claim 1 ,
The first circuit has a current mirror circuit.
A storage device characterized in that the drain current flowing through the fourth transistor flows through the first signal line via the current mirror circuit. In claim 1 or 2 ,
The first circuit is a storage device having a function of storing the first analog data stored in the memory cell as the second analog data. In any one of claims 1 to 3 ,
It has a D / A converter, a fifth transistor, and a fifth signal line.
The output terminal of the D / A converter is electrically connected to the gate of the fifth transistor.
The drain current flowing through the fifth transistor flows through the fifth signal line,
The storage device is characterized in that the fifth signal line is electrically connected to the first signal line. In any one of claims 1 to 4 ,
It has an A / D converter, a sixth transistor, a sixth signal line, and a third power supply line.
One of the source or drain of the sixth transistor is electrically connected to the sixth signal line.
The other of the source or drain of the sixth transistor is electrically connected to the third power line.
The input terminal of the A / D converter is electrically connected to the sixth signal line.
A storage device characterized in that the sixth signal line is electrically connected to the first signal line. The storage device according to any one of claims 1 to 5 is provided.
A semiconductor wafer having a separation region. An electronic device having the storage device according to any one of claims 1 to 5 and a battery.

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