JP7083727B2 - Semiconductor equipment - Google Patents

Description

One embodiment of the present invention disclosed in the specification, drawings, and claims of the present application (hereinafter referred to as the present specification and the like) relates to a semiconductor device, an operation method thereof, and the like. It should be noted that one embodiment of the present invention is not limited to the illustrated technical field.

Semiconductor devices that use a negative potential lower than the ground potential are known. For example, in order to reduce the subshouldered leak current, the substrate bias potential of the n-channel type MOS transistor is a negative potential, and the substrate bias potential of the P-channel type MOS transistor is a positive potential (Patent Document 1). Further, in the flash memory, a negative potential is used depending on the operation (Patent Document 2).

Negative potentials can be generated by the charge pump circuit. Patent Document 2 discloses a charge pump circuit using a capacitor and a diode-connected transistor. Since the charge pump circuit is a circuit that can generate a potential lower than, for example, an input potential without using a coil, it can be easily integrated into one IC chip together with a processor, a memory, or the like.

Examples of the transistor provided in the charge pump circuit include a transistor having silicon in the channel forming region (hereinafter, Si transistor), a transistor having a metal oxide in the channel forming region (hereinafter, OS transistor), and the like. For example, Patent Document 3 discloses a charge pump circuit having an OS transistor.

Japanese Unexamined Patent Publication No. 11-191611 Japanese Unexamined Patent Publication No. 2000-270541 Japanese Unexamined Patent Publication No. 2011-171700

Examples of the material used for the Si transistor include single crystal silicon and non-single crystal silicon (for example, polycrystalline silicon, microcrystalline silicon, amorphous silicon, etc.). For example, when single crystal silicon is used for the Si transistor, the on-current is larger than that of the OS transistor. Therefore, the charge pump circuit composed of Si transistors may operate at a higher speed than the charge pump circuit composed of OS transistors. In the present specification and the like, the following description will be given on the assumption that single crystal silicon is used for the Si transistor.

However, the charge pump circuit composed of Si transistors may not operate normally due to an increase in substrate leakage current in a high temperature environment. On the other hand, the charge pump circuit composed of the OS transistor does not generate a substrate leak current even in a high temperature environment and operates normally.

One of the problems of the present invention is to provide a semiconductor device that operates normally even in a high temperature environment. Alternatively, one of the problems is to provide a semiconductor device that operates at high speed. Alternatively, one of the issues is to provide a low-priced semiconductor device. Alternatively, one of the issues is to provide a semiconductor device having low power consumption. Alternatively, one of the problems is to provide a semiconductor device that is miniaturized and highly integrated. Alternatively, one of the problems is to provide a semiconductor device having a small circuit area. Alternatively, one of the issues is to provide a highly reliable semiconductor device. Alternatively, one of the issues is to provide a new semiconductor device. Alternatively, one of the problems is to provide a method of operating a new semiconductor device.

It should be noted that one form of the present invention does not need to solve all of these problems. The description of multiple issues does not prevent the existence of each other's issues. Issues other than those listed are self-evident from the description of the present specification and the like, and these issues can also be issues of one form of the present invention.

One aspect of the present invention is a semiconductor device having an input terminal and an output terminal and having a function of outputting a potential lower than the potential input to the input terminal from the output terminal, wherein the semiconductor device is the first. It has a charge transfer switch, a second charge transfer switch, and a pumping capacitor, and the first charge transfer switch has a plurality of Si transistors, which are transistors having silicon in the channel forming region, and has a second charge. The transfer switch has a plurality of OS transistors which are transistors having a metal oxide in the channel forming region, the input terminal is electrically connected to the first and second charge transfer switches, and the output terminal is the first and second. One electrode of the pumping transistor, which is electrically connected to the second charge transfer switch, is a semiconductor device which is electrically connected to the first and second charge transfer switches.

Alternatively, in the above embodiment, all the transistors included in the second charge transfer switch may be OS transistors.

Alternatively, one aspect of the present invention is a semiconductor device having an input terminal and an output terminal and having a function of outputting a potential lower than the potential input to the input terminal from the output terminal. The first charge transfer switch has one charge transfer switch, a second charge transfer switch, and a pumping capacitor, and the first charge transfer switch has a plurality of Si transistors which are transistors having silicon in the channel forming region, and is the first. The charge transfer switch has one OS transistor which is a transistor having an oxide semiconductor in the channel forming region, and the second charge transfer switch has a plurality of OS transistors and has a transistor of the second charge transfer switch. Are all OS transistors, the input terminal is electrically connected to the first and second charge transfer switches, and the output terminal is connected to one of the source or drain of the OS transistor of the first charge transfer switch. A semiconductor device that is electrically connected, the output terminal is electrically connected to the second charge transfer switch, and one electrode of the pumping transistor is electrically connected to the first and second charge transfer switches. Is.

Alternatively, in the above embodiment, the Si transistor included in the first charge transfer switch may be a p-channel transistor.

According to one aspect of the present invention, it is possible to provide a semiconductor device that operates normally even in a high temperature environment. Alternatively, it is possible to provide a semiconductor device that operates at high speed. Alternatively, a low-priced semiconductor device can be provided. Alternatively, it is possible to provide a semiconductor device having low power consumption. Alternatively, it is possible to provide a semiconductor device that is miniaturized and highly integrated. Alternatively, it is possible to provide a semiconductor device having a small circuit area. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a new semiconductor device can be provided. Alternatively, it is possible to provide a method of operating a novel semiconductor device.

One embodiment of the invention does not necessarily have all of the illustrated effects. The description of multiple effects does not preclude the existence of other effects. Further, with respect to one embodiment of the present invention, problems, effects, and novel features other than the above will be self-evident from the description and drawings of the present specification.

A circuit diagram showing a configuration example of a semiconductor device. A circuit diagram showing a configuration example of a semiconductor device. The figure which shows the structural example of a transistor. A circuit diagram showing a configuration example of a semiconductor device. A circuit diagram showing a configuration example of a semiconductor device. A circuit diagram showing a configuration example of a semiconductor device. A timing chart showing an operation example of a semiconductor device. The cross-sectional view which shows the structural example of the semiconductor device. The cross-sectional view which shows the structural example of a transistor. The cross-sectional view which shows the structural example of the semiconductor device. A circuit diagram showing a configuration example of a semiconductor device. A block diagram showing a configuration example of a storage device, and a circuit diagram showing a configuration example of a memory cell. Top view and sectional view showing a configuration example of a transistor. Top view and sectional view showing a configuration example of a transistor. Top view and sectional view showing a configuration example of a transistor. Top view and sectional view showing a configuration example of a transistor. Top view and sectional view showing a configuration example of a transistor. The figure which shows an example of the electronic device. The figure which shows an example of the electronic device. The figure which shows an example of the electronic device. A circuit diagram showing the configuration of a simulated semiconductor device. A graph showing the simulation results.

An embodiment of the present invention is shown below. However, the embodiments described herein can be combined as appropriate. Further, when a plurality of configuration examples (including operation examples and manufacturing method examples) are shown in one embodiment, it is possible to appropriately combine the configuration examples with each other. Further, it is easily understood by those skilled in the art that the present invention can be carried out in many different forms, and the forms and details can be variously changed without departing from the spirit and scope thereof. To. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

In the drawings, the size, layer thickness, area, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show an ideal example, and are not limited to the shapes, values, and the like shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.

In the present specification, words and phrases indicating arrangements such as "above" and "below" may be used for convenience in order to explain the positional relationship between configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

The arrangement of each circuit block in the block diagram described in the drawings specifies the positional relationship for the sake of explanation, and the arrangement of the circuit blocks of one embodiment of the present invention is not limited to this. Even if the block diagram shows that different circuit blocks realize different functions, the actual circuit block may be provided so that different functions can be realized in the same circuit block. Further, the function of each circuit block is for specifying the function for explanation, and even if it is shown as one circuit block, in the actual circuit block, the processing performed by one circuit block is performed by a plurality of circuit blocks. In some cases, it is provided as such.

In the present specification and the like, the semiconductor device is a device utilizing semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit and a chip provided with an integrated circuit are examples of semiconductor devices. Further, the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like may be a semiconductor device itself, or may have a semiconductor device.

In the present specification and the like, the ground potential is regarded as 0V, and the positive potential and the negative potential are potentials with the ground potential as a reference.

In the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y are functionally connected. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and the connection relationship other than the connection relationship shown in the figure or text is also disclosed in the figure or text. It is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Transistors have three terminals called gates, sources, and drains. The gate is a node having a function as a control node for controlling the conduction state of the transistor. Two input / output nodes having a function as a source or a drain have one as a source and the other as a drain depending on the type of transistor and the high and low potentials given to each terminal. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably.

A node can be paraphrased as a terminal, wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like, depending on a circuit configuration, a device structure, or the like. In addition, terminals, wiring, etc. can be paraphrased as nodes.

The voltage often indicates the potential difference between a certain potential and a reference potential (eg, ground potential or source potential). Therefore, it is possible to paraphrase voltage as electric potential.

In the present specification and the like, the word "body", the word "membrane", and the word "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the word "conductor" to the word "conductive film" or the word "conductive layer". For example, it may be possible to change the word "insulator" to the word "insulating film" or the word "insulating layer".

In the present specification and the like, the ordinal numbers "first", "second", and "third" may be added to avoid confusion of the components, in which case the order is not limited numerically. It does not limit.

In the present specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS FET, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

Further, in the present specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide.

(Embodiment 1)
The present embodiment describes the semiconductor device of one aspect of the present invention.

One aspect of the present invention relates to a charge pump circuit which is a kind of semiconductor device. For example, the present invention relates to a charge pump circuit having a function of outputting a potential lower than an input potential. The semiconductor device of one aspect of the present invention includes a first charge transfer switch and a second charge transfer switch. The input potential is input to the first and second charge transfer switches.

The first charge transfer switch has a plurality of Si transistors connected by diodes, and the Si transistors are connected in series. The second charge transfer switch has a plurality of diode-connected OS transistors, and the OS transistors are connected in series.

The Si transistor has a larger on-current than the OS transistor. Therefore, the first charge transfer switch operates at a higher speed than the second charge transfer switch. Therefore, when the first charge transfer switch operates normally, the output potential of the first charge transfer switch is lower than the output potential of the second charge transfer switch.

However, the Si transistor has a characteristic that the substrate leakage current increases in a high temperature environment or the like. Therefore, the first charge transfer switch may not operate normally in a high temperature environment or the like. On the other hand, the OS transistor has a characteristic that a substrate leakage current does not occur even in a high temperature environment or the like. Therefore, the second charge transfer switch operates normally even in a high temperature environment or the like.

The semiconductor device of one aspect of the present invention can output the potential corresponding to the lower potential of the output potential of the first charge transfer switch or the output potential of the second charge transfer switch. Therefore, in an environment in which the first charge transfer switch operates normally, such as in a room temperature environment (typically 25 ° C.), the output potential of the first charge transfer switch is output from the semiconductor device. On the other hand, in an environment where the first charge transfer switch does not operate normally, such as in a high temperature environment, the output potential of the second charge transfer switch is output from the semiconductor device.

As described above, the semiconductor device according to one aspect of the present invention can operate at high speed in an environment in which the first charge transfer switch normally operates, such as in a room temperature environment. On the other hand, the semiconductor device of one aspect of the present invention can be normally operated by the second charge transfer switch even in an environment where the first charge transfer switch does not normally operate, such as in a high temperature environment.

In the above operation, for example, the temperature is measured by a temperature sensor, and the potential output from the semiconductor device is selected from the output potential of the first charge transfer switch and the output potential of the second charge transfer switch according to the measurement result. It can be performed without any special control such as. Therefore, the semiconductor device of one aspect of the present invention can be made inexpensive.

<Semiconductor device configuration example>
FIG. 1A is a circuit diagram showing a configuration example of a semiconductor device 10, which is a semiconductor device according to an aspect of the present invention. The semiconductor device 10 can be, for example, a charge pump circuit.

The semiconductor device 10 includes an input terminal IN, an output terminal OUT, a charge transfer switch 20, a charge transfer switch 30, a capacitive element group 40, a clock signal generation circuit 11, and a capacitive element 12. The charge transfer switch 20 has two or more transistors 21. The charge transfer switch 30 has two or more transistors 31. The capacitive element group 40 has one or more capacitive elements 41. The clock signal generation circuit 11 has a clock signal input terminal ICK, a clock signal output terminal OCK, and a clock signal output terminal OCKB.

Here, the transistor 21 and the transistor 31 can be n-channel type transistors.

FIG. 1A shows a configuration in which the charge transfer switch 20 has five transistors 21, the charge transfer switch 30 has five transistors 31, and the capacitive element group 40 has four capacitive elements 41. However, one aspect of the present invention is not limited to this. For example, the number of transistors 21 included in the charge transfer switch 20 may be 4 or less, or 6 or more. Further, the number of transistors 31 included in the charge transfer switch 30 may be 4 or less, or 6 or more. Further, the number of the capacitive elements 41 included in the capacitive element group 40 can be 3 or less or 5 or more depending on the number of the transistors 21 or the number of the transistors 31.

In FIG. 1A, the five transistors 21 are described as transistors 21 [1] to 21 [5], respectively, to distinguish them. Further, the five transistors 31 are described as transistors 31 [1] to 31 [5], respectively, to distinguish them. Further, the four capacitive elements 41 are described as capacitive elements 41 [1] to 41 [4], respectively, to distinguish them. The same notation may be used in other drawings, other elements, and the like.

Further, in the present specification and the like, an element having a large number in parentheses is referred to as an element after the element having a small number in parentheses. For example, the transistor 21 [2] is a transistor 21 after the transistor 21 [1], and the capacitive element 41 [4] is a capacitive element 41 after the capacitive element 41 [1] to the capacitive element 41 [3]. be.

The transistor 21 and the transistor 31 are connected by a diode. Diode connection means connecting the gate and drain of a transistor. In a diode-connected transistor, the drain potential is equal to the gate potential. When the transistor is an n-channel type transistor and the difference between the gate potential and the source potential (gate voltage) becomes larger than the threshold voltage of the transistor, the current according to the Ids-Vgs characteristic flows from the drain of the transistor to the source. Flow to. On the other hand, when the gate voltage is equal to or lower than the threshold voltage of the transistor, no current flows between the source and drain of the transistor. From the above, it can be said that the diode-connected n-channel transistor has a function as a diode having a drain as an anode and a source as a cathode.

When the diode-connected transistor is a p-channel type transistor, when the gate voltage becomes smaller than the threshold voltage of the transistor, a current according to the Ids-Vgs characteristic flows from the source of the transistor to the drain. On the other hand, when the gate voltage is equal to or higher than the threshold voltage of the transistor, no current flows between the source and drain of the transistor. From the above, it can be said that the diode-connected p-channel transistor has a function as a diode having an anode as a source and a cathode as a drain.

In the semiconductor device 10 having the configuration shown in FIG. 1A, the source of the transistor 21 [1] and the source of the transistor 31 [1] are electrically connected to the input terminal IN.

Further, one electrode of the capacitive element 41 [1] includes a gate and drain of the transistor 21 [1], a source of the transistor 21 [2], a gate and drain of the transistor 31 [1], and a source of the transistor 31 [2]. It is electrically connected. One electrode of the capacitive element 41 [2] is electrically connected to the gate and drain of the transistor 21 [2], the source of the transistor 21 [3], the gate and drain of the transistor 31 [2], and the source and drain of the transistor 31 [3]. It is connected to the. One electrode of the capacitive element 41 [3] is electrically connected to the gate and drain of the transistor 21 [3], the source of the transistor 21 [4], the gate and drain of the transistor 31 [3], and the source and drain of the transistor 31 [4]. It is connected to the. One electrode of the capacitive element 41 [4] is electrically connected to the gate and drain of the transistor 21 [4], the source of the transistor 21 [5], the gate and drain of the transistor 31 [4], and the source and drain of the transistor 31 [5]. It is connected to the. That is, it can be said that the transistors 21 [1] to 21 [5] are connected in series, and the transistors 31 [1] to 31 [5] are connected in series.

Further, the gate and drain of the transistor 21 [5] and the gate and drain of the transistor 31 [5] are electrically connected to the output terminal OUT. Further, the output terminal OUT is electrically connected to one of the electrodes of the capacitive element 12. That is, the gate and drain of the transistor 21 in the final stage, the gate and drain of the transistor 31 in the final stage are electrically connected to one of the electrodes of the output terminal OUT and the capacitive element 12.

The clock signal output terminal OCK included in the clock signal generation circuit 11 is electrically connected to the other electrode of the capacitive element 41 [1] and the other electrode of the capacitive element 41 [3]. The clock signal output terminal OCKB included in the clock signal generation circuit 11 is electrically connected to the other electrode of the capacitive element 41 [2] and the other electrode of the capacitive element 41 [4].

The clock signal generation circuit 11 has a function of generating two types of clock signals based on the clock signal input from the clock signal input terminal ICK and outputting them from the clock signal output terminal OCK and the clock signal output terminal OCKB, respectively. Have. For example, a clock signal having the same phase as the clock signal input to the clock signal input terminal ICK can be output from the clock signal output terminal OCK. On the other hand, the clock signal output terminal OCKB can output a clock signal having a phase opposite to that of the clock signal input to the clock signal input terminal ICK.

From the above, the clock signal output from the clock signal output terminal OCK and the clock signal output from the clock signal output terminal OCKB can be in opposite phase to each other. As a result, clock signals having opposite phases can be input to the other electrodes of the adjacent capacitive elements 41. That is, it can be said that the clock signal input to the other electrode of the capacitive element 41 [1] and the clock signal input to the other electrode of the capacitive element 41 [2] are out of phase with each other. Further, it can be said that the clock signal input to the other electrode of the capacitive element 41 [2] and the clock signal input to the other electrode of the capacitive element 41 [3] are out of phase with each other. Further, it can be said that the clock signal input to the other electrode of the capacitive element 41 [3] and the clock signal input to the other electrode of the capacitive element 41 [4] are out of phase with each other.

The charge transfer switch 20 and the charge transfer switch 30 can transfer the charge held in the capacitive element 41 when the phase of the clock signal input to the other electrode of the capacitive element 41 is switched. Therefore, it can be said that the capacitive element 41 has a function as a pumping capacitor.

The potential VSS can be input to the input terminal IN. The potential VSS can be, for example, a ground potential.

From the input terminal OUT, a potential corresponding to the lower potential of the potential output from the charge transfer switch 20 or the potential output from the charge transfer switch 30 is output. The potential output from the charge transfer switch 20 or the potential output from the charge transfer switch 30 is lower than the potential input to the input terminal IN. Therefore, the potential output from the output terminal OUT is lower than the potential input from the input terminal IN. That is, it can be said that the semiconductor device 10 is a step-down type charge pump circuit.

The capacitive element 12 has a function of holding the charge transferred from the charge transfer switch 20 and the charge transferred from the charge transfer switch 30. By providing the capacitive element 12, it is possible to suppress fluctuations in the potential output from the output terminal OUT. When the gate capacitance of the transistor 21 [5] and the transistor 31 [5] is large, the capacitive element 12 may not be provided.

A potential VSS can be supplied to the other electrode of the capacitive element 12. In FIG. 1A, the potential input to the input terminal IN and the potential supplied to the other electrode of the capacitance element 12 are both potential VSS, but the potential and capacitance input to the input terminal IN The potentials supplied to the other electrode of the element 12 do not have to be equal.

A Si transistor can be used as the transistor 21. On the other hand, an OS transistor can be used as the transistor 31. As the OS transistor, a transistor having a metal oxide containing indium or the like can be used.

The Si transistor has a feature that the on-current is larger than that of the OS transistor. Therefore, the charge transfer switch 20 operates at a higher speed than the charge transfer switch 30. Therefore, when the charge transfer switch 20 operates normally, the output potential of the charge transfer switch 20 is lower than the output potential of the charge transfer switch 30, so that the potential of the output terminal OUT becomes the output potential of the charge transfer switch 20. It becomes the corresponding potential.

However, the Si transistor has a characteristic that the substrate leakage current increases in a high temperature environment or the like. Therefore, the charge transfer switch 20 may not operate normally in a high temperature environment or the like. On the other hand, the OS transistor has a characteristic that a substrate leakage current does not occur even in a high temperature environment or the like. Therefore, the charge transfer switch 30 operates normally even in a high temperature environment or the like. Therefore, in a high temperature environment where the charge transfer switch 20 does not operate normally, the potential of the output terminal OUT becomes a potential corresponding to the output potential of the charge transfer switch 30.

As described above, the semiconductor device 10 can operate at high speed in an environment in which the charge transfer switch 20 normally operates, such as in a room temperature environment. On the other hand, the semiconductor device 10 can be normally operated by the charge transfer switch 30 even in an environment where the charge transfer switch 20 does not operate normally, such as in a high temperature environment. In particular, it is preferable to use all the transistors 31 included in the charge transfer switch 30 as OS transistors because it is possible to suppress a decrease in reliability of the semiconductor device 10 even if the semiconductor device 10 is placed in a high temperature environment, for example.

In the above operation, for example, the temperature is measured by a temperature sensor, and the potential of the output terminal OUT corresponds to the potential corresponding to the output potential of the charge transfer switch 20 and the potential corresponding to the output potential of the charge transfer switch 30 according to the measurement result. It can be performed without any special control such as selecting from. Therefore, the semiconductor device 10 can be made inexpensive.

As described above, the charge transfer switch 30 composed of the OS transistor has a slower operating speed than the charge transfer switch 20 composed of the Si transistor. Therefore, in an environment where the charge transfer switch 20 does not operate normally, such as in a high temperature environment, it is preferable to set the frequency of the clock signal higher than in an environment in which the charge transfer switch 20 normally operates. As a result, it is possible to suppress a decrease in the operating speed of the semiconductor device 10 even in an environment in which the charge transfer switch 20 does not operate normally.

Further, the transistor 21 does not have to be a Si transistor as long as the on-current is larger than that of the transistor 31. Further, the transistor 31 does not have to be an OS transistor as long as the charge transfer switch 30 operates normally even in an environment where the charge transfer switch 20 does not operate normally, such as in a high temperature environment.

FIG. 1A shows a configuration example of the semiconductor device 10 in the case where the charge transfer switch 20 is provided with the transistor 21 which is an n-channel transistor, but the charge transfer switch 20 is provided with the p-channel transistor. You may. FIG. 1B is a circuit diagram showing a configuration example of a semiconductor device 10 when a transistor 22 which is a p-channel type transistor is provided in a charge transfer switch 20. Although FIG. 1B shows a configuration in which the charge transfer switch 20 has five transistors 22, the number of transistors 22 included in the charge transfer switch 20 may be four or less, as in the transistor 21. , 6 or more may be used.

The transistor 22 is diode-connected like the transistor 21. That is, the transistor 22 is connected to the gate and the drain.

In the semiconductor device 10 having the configuration shown in FIG. 1B, the gate and drain of the transistor 22 [1] and the source of the transistor 31 [1] are electrically connected to the input terminal IN.

Further, one electrode of the capacitive element 41 [1] includes a source of the transistor 22 [1], a gate and drain of the transistor 22 [2], a gate and drain of the transistor 31 [1], and a source of the transistor 31 [2]. It is electrically connected. One electrode of the capacitive element 41 [2] is electrically connected to the source of the transistor 22 [2], the gate and drain of the transistor 22 [3], the gate and drain of the transistor 31 [2], and the source and drain of the transistor 31 [3]. It is connected to the. One electrode of the capacitive element 41 [3] is the source of the transistor 22 [3], the gate and drain of the transistor 22 [4], the gate and drain of the transistor 31 [3], and the source and electrical of the transistor 31 [4]. It is connected to the. One electrode of the capacitive element 41 [4] is the source of the transistor 22 [4], the gate and drain of the transistor 22 [5], the gate and drain of the transistor 31 [4], and the source and electrical of the transistor 31 [5]. It is connected to the. That is, it can be said that the transistor 22 [1] to the transistor 22 [5] are connected in series as in the transistor 21 [1] to the transistor 21 [5].

Further, the source of the transistor 22 [5] and the gate and drain of the transistor 31 [5] are electrically connected to the output terminal OUT. That is, the source of the transistor 22 in the final stage and the gate and drain of the transistor 31 in the final stage are electrically connected to the output terminal OUT. Other connection relationships and the like are the same as those of the semiconductor device 10 having the configuration shown in FIG. 1 (A).

As the transistor 22, a Si transistor can be used as in the transistor 21. As with the transistor 21, the transistor 22 does not have to be a Si transistor as long as the on-current is larger than that of the transistor 31.

In the semiconductor device 10 having the configuration shown in FIG. 1 (A), all the transistors provided in the charge transfer switch 20 are used as transistors 21, and the semiconductor device 10 having the configuration shown in FIG. 1 (B) is a transistor provided in the charge transfer switch 20. However, one aspect of the present invention is not limited to this. For example, the charge transfer switch 20 may have both the transistor 21 and the transistor 22. That is, the charge transfer switch 20 may have both an n-channel transistor and a p-channel transistor.

The semiconductor device 10 having the configuration shown in FIGS. 1A and 1B is a step-down type charge pump, but may be a step-up type charge pump. 2A and 2B are circuit diagrams of the semiconductor device 10 when the semiconductor device 10 is a step-up charge pump.

In the semiconductor device 10 having the configuration shown in FIGS. 2A and 2B, the source and drain of the transistor provided in the charge transfer switch 20 and the transistor provided in the charge transfer switch 30 are shown in FIGS. 1A and 1B. It is replaced with the semiconductor device 10 having the configuration shown in (B). Further, the potential VDD can be input to the input terminal IN. Even if the semiconductor device 10 is a step-up type charge pump, the potential VSS may be input to the input terminal IN.

Hereinafter, the description will be made assuming that the semiconductor device 10 is a step-down type charge pump, but even if the semiconductor device 10 is a step-up type charge pump by appropriately reversing the magnitude relationship of the potentials, the following description will be given. Can be applied.

<Transistor configuration example>
FIG. 3A is a schematic diagram showing a cross-sectional configuration example and a connection configuration example of the transistor 21 [1] and the transistor 21 [2] shown in FIG. 1 (A). The configuration shown in FIG. 3A can also be applied to the other transistor 21.

The transistor 21 can be formed on the substrate 70. The substrate 70 can be a p-type substrate. When the transistor 21 is a Si transistor, the substrate 70 can be a silicon substrate containing a silicon-based semiconductor material. When the substrate 70 is a silicon substrate, the substrate 70 preferably contains single crystal silicon.

Alternatively, the substrate 70 may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 21 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.

The substrate 70 is provided with a p + region 71, and n-type wells 72a, n-type wells 72b, n-type wells 72c, and n-type wells 73a and n-type wells 73b. The region surrounded by the n-type well 72a, the n-type well 73a, and the n-type well 72b inside the substrate 70 becomes the p-type well 74 [1], and the n-type well 72b, the n-type well 73b, and the n-type well 72c. The area surrounded by is the p-type well 74 [2]. The n-type well 72a is provided with an n + region 75a, the n-type well 72b is provided with an n + region 75b, and the n-type well 72c is provided with an n + region 75c.

Here, the n-type well 73a is provided below the p-type well 74 [1], and the n-type well 73b is provided below the p-type well 74 [2]. That is, it can be said that the n-type well 73a and the n-type well 73b are provided at a deep position inside the substrate 70.

The p-type well 74 [1] is provided with a p + region 76 [1], an n + region 77 [1], and an n + region 78 [1]. The p-type well 74 [2] is provided with a p + region 76 [2], an n + region 77 [2], and an n + region 78 [2].

When the substrate 70 is a p-type substrate, the substrate 70, the p-type well, and the p + region contain, in addition to the above-mentioned semiconductor material, an element that imparts p-type conductivity such as boron. The concentration of the element contained in the p-type well can be about the same as the concentration of the element contained in the substrate 70. Further, the concentration of the element that imparts p-type conductivity contained in the p + region can be higher than the concentration of the element contained in the substrate 70 and the p-type well. Therefore, the electric resistance in the p + region can be made lower than the electric resistance of the substrate 70 and the p-type well.

The n-type well and the n + region contain, in addition to the above-mentioned semiconductor material, an element such as phosphorus that imparts n-type conductivity. The concentration of the element contained in the n + region can be higher than the concentration of the element contained in the n-type well. Therefore, the electric resistance in the n + region can be made lower than the electric resistance of the n-type well.

An insulator 80 [1] is provided on the substrate 70 so as to have a region overlapping the region between the n + region 77 [1] and the n + region 78 [1], and the n + region 77 [2] and the n + region 78 [1] are provided. The insulator 80 [2] is provided on the substrate 70 so as to have a region overlapping the region between 2]. Further, the conductor 81 [1] is provided so as to have a region in contact with the insulator 80 [1], and the conductor 81 [2] is provided so as to have a region in contact with the insulator 80 [2]. The insulator 80 [1] and the conductor 81 [1] may have a region overlapping with the n + region 77 [1] or may have a region overlapping with the n + region 78 [1]. Further, the insulator 80 [2] and the conductor 81 [2] may have a region overlapping with the n + region 77 [2] or may have a region overlapping with the n + region 78 [2].

The input terminal IN is electrically connected to the p + region 71, the n + region 75a, the n + region 77 [1], the n + region 75b, and the n + region 75c. Further, the p + region 76 [1], the conductor 81 [1], the n + region 78 [1], and the n + region 77 [2] are electrically connected to each other. Further, the p + region 76 [2], the conductor 81 [2], and the n + region 78 [2] are electrically connected to each other.

The n + region 77 [1] has a function as a source region of the transistor 21 [1], and the n + region 77 [2] has a function as a source region of the transistor 21 [2]. The n + region 78 [1] has a function as a drain region of the transistor 21 [1], and the n + region 78 [2] has a function as a drain region of the transistor 21 [2].

The insulator 80 [1] has a function as a gate insulating film of the transistor 21 [1], and the insulator 80 [2] has a function as a gate insulating film of the transistor 21 [2]. The conductor 81 [1] has a function as a gate electrode of the transistor 21 [1], and the conductor 81 [2] has a function as a gate electrode of the transistor 21 [2].

Here, in the p-type well 74 [1], of the regions between the n + region 77 [1] and the n + region 78 [1], the region overlapping the conductor 81 [1] is the channel of the transistor 21 [1]. It becomes a forming region. Further, in the region between the n + region 77 [2] and the n + region 78 [2] in the p-type well 74 [2], the region overlapping the conductor 81 [2] forms the channel of the transistor 21 [2]. It becomes an area.

The potential supplied to the p + region 71 is the potential of the substrate 70. The potential supplied to the n + region 75a is the potential of the n-type well 72a. The potential supplied to the n + region 75b is the potential of the n-type well 72b. The potential supplied to the n + region 75c is the potential of the n-type well 72c. The potential supplied to the p + region 76 [1] is the potential of the p-type well 74 [1]. The potential supplied to the p + region 76 [2] is the potential of the p-type well 74 [2].

From the above, the transistor 21 [1] includes a p-type well 74 [1], a p + region 76 [1], an n + region 77 [1], an n + region 78 [1], an insulator 80 [1], and a conductor 81. It can be said that it has [1]. Further, the transistor 21 [2] includes a p-type well 74 [2], a p + region 76 [2], an n + region 77 [2], an n + region 78 [2], an insulator 80 [2], and a conductor 81 [2]. 2] can be said to have. Further, it can be said that the transistor 21 [1] and the transistor 21 [2] are separated by an n-type well 72a, an n-type well 73a, an n-type well 72b, an n-type well 73b, and an n-type well 72c.

The potential VSS can be supplied to the p + region 71, the n + region 75a, the n + region 77 [1], the n + region 75b, and the n + region 75c. Further, the potential supplied to the p + region 76 [1], the conductor 81 [1], the n + region 78 [1], and the n + region 77 [2] is defined as the potential V1. Further, the potential supplied to the p + region 76 [2], the conductor 81 [2], and the n + region 78 [2] is defined as the potential V2. When the semiconductor device 10 is a step-down type charge pump, the potential V1 is lower than the potential VSS, and the potential V2 is lower than the potential V1. That is, the relationship "VSS> V1> V2" is established.

When the relationship "VSS> V1> V2" is established, the potential of the substrate 70, which is a p-type substrate, and the potential of the n-type well do not have a forward bias relationship. In addition, the potential of the p-type well and the potential of the n-type well do not have a forward bias relationship. From the above, it is possible to suppress the current flowing from the substrate 70 to the n-type well and the current flowing from the p-type well to the n-type well.

Here, the difference between the source potential (potential supplied to the n + region 77 [1]) and the body potential (potential supplied to the p + region 76 [1]) in the transistor 21 [1] is “VSS-V1”. Will be. Further, the difference between the source potential (potential supplied to the n + region 77 [2]) and the body potential (potential supplied to the p + region 76 [2]) in the transistor 21 [2] is "V1-V2". Become. Therefore, even in the transistor 21 in the subsequent stage, it is possible to suppress that the difference between the source potential and the body potential is significantly increased as compared with the difference between the source potential and the body potential in the transistor 21 [1]. .. Therefore, even in the transistor 21 in the subsequent stage, it is possible to suppress an increase in the threshold voltage of the transistor due to the substrate bias effect that occurs when the difference between the source potential and the body potential becomes large. From the above, even if the output potential of the charge transfer switch 20 is lowered by increasing the number of transistors 21 provided in the charge transfer switch 20, the threshold voltage of the transistor 21 in the subsequent stage increases due to the substrate bias effect. It can be suppressed.

FIG. 3B is a schematic diagram showing a cross-sectional configuration example and a connection configuration example of the transistor 22 [1] and the transistor 22 [2] shown in FIG. 1 (B). The configuration shown in FIG. 3B can also be applied to the other transistors 22.

Similar to the transistor 21, the transistor 22 can be formed on a substrate 70 which can be a p-type substrate.

The substrate 70 is provided with a p + region 71 and an n-type well 90 [1] and an n-type well 90 [2]. The n-type well 90 [1] is provided with n + region 91 [1], and the p + region 92 [1] and p + region 93 [1], and the n-type well 90 [2] is provided with n + region 91 [2]. In addition, p + region 92 [2] and p + region 93 [2] are provided.

An insulator 80 [1] is provided on the substrate 70 so as to have a region overlapping the region between the p + region 92 [1] and the p + region 93 [1], and the p + region 92 [2] and the p + region 93 [1] are provided. The insulator 80 [2] is provided on the substrate 70 so as to have a region overlapping the region between 2]. Further, the conductor 81 [1] is provided so as to have a region in contact with the insulator 80 [1], and the conductor 81 [2] is provided so as to have a region in contact with the insulator 80 [2]. The insulator 80 [1] and the conductor 81 [1] may have a region overlapping the p + region 92 [1] or may have a region overlapping the p + region 93 [1]. Further, the insulator 80 [2] and the conductor 81 [2] may have a region overlapping with the p + region 92 [2] or may have a region overlapping with the p + region 93 [2].

The input terminal IN is electrically connected to the p + region 71, the n + region 91 [1], the p + region 92 [1], the conductor 81 [1], and the n + region 91 [2]. Further, the p + region 93 [1] is electrically connected to the p + region 92 [2] and the conductor 81 [2].

The p + region 92 [1] has a function as a drain region of the transistor 22 [1], and the p + region 92 [2] has a function as a drain region of the transistor 22 [2]. The p + region 93 [1] has a function as a source region of the transistor 22 [1], and the p + region 93 [2] has a function as a source region of the transistor 22 [2].

The insulator 80 [1] has a function as a gate insulating film of the transistor 22 [1], and the insulator 80 [2] has a function as a gate insulating film of the transistor 22 [2]. The conductor 81 [1] has a function as a gate electrode of the transistor 22 [1], and the conductor 81 [2] has a function as a gate electrode of the transistor 22 [2].

Here, in the n-type well 90 [1], of the regions between the p + region 92 [1] and the p + region 93 [1], the region overlapping the conductor 81 [1] is the channel of the transistor 22 [1]. It becomes a forming region. Further, in the region between the p + region 92 [2] and the p + region 93 [2] in the n-type well 90 [2], the region overlapping the conductor 81 [2] forms the channel of the transistor 22 [2]. It becomes an area.

The potential supplied to the p + region 71 is the potential of the substrate 70, as in the case shown in FIG. 3A. The potential supplied to the n + region 91 [1] is the potential of the n-type well 90 [1], and the potential supplied to the n + region 91 [2] is the potential of the n-type well 90 [2].

From the above, the transistor 22 [1] includes an n-type well 90 [1], an n + region 91 [1], a p + region 92 [1], a p + region 93 [1], an insulator 80 [1], and a conductor 81. It can be said that it has [1]. Further, the transistor 22 [2] includes an n-type well 90 [2], an n + region 91 [2], a p + region 92 [2], a p + region 93 [2], an insulator 80 [2], and a conductor 81 [2]. 2] can be said to have. Further, it can be said that the transistor 22 [1] and the transistor 22 [2] are separated by the n-type well 90 [1] and the n-type well 90 [2].

The transistor 22 can separate the elements of the transistor 22 without providing a well at a deep position inside the substrate 70. Therefore, the transistor 22 can be manufactured by a simple process.

The potential VSS can be supplied to the p + region 71, the n + region 91 [1], the p + region 92 [1], the conductor 81 [1], and the n + region 91 [2]. By supplying the same potential to the p + region 71 [1] and the n + region 91 [1] and n + region 91 [2], the potential of the substrate 70 and the n-type well 90 [1] and the n-type well 90 [2] ] Can be equal to the potential. As a result, the potential of the substrate 70, which is a p-type substrate, and the potentials of the n-type well 90 [1] and the n-type well 90 [2] do not have a forward bias relationship. Therefore, it is possible to suppress the flow of current from the substrate 70 to the n-type well 90 [1] and the n-type well 90 [2].

It should be noted that the same potential as the potential supplied to the p + region 71 can be supplied to all the n + regions 91 provided in the transistor 22 included in the charge transfer switch 20. Thereby, the potentials of all the n-type wells 90 can be made equal to the potentials of the substrate 70.

Further, the potential supplied to the p + region 93 [1], the p + region 92 [2], and the conductor 81 [2] is defined as the potential V1. Further, the potential supplied to the p + region 93 [2] is defined as the potential V2. Similar to the case shown in FIG. 3A, when the semiconductor device 10 is a step-down charge pump, the potential V1 is lower than the potential VSS, and the potential V2 is lower than the potential V1. That is, the relationship "VSS> V1> V2" is established.

As described above, the potential of the n-type well 90 is the potential VSS. Therefore, when the relationship "VSS> V1> V2" is established, the potential supplied to the p + region other than the p + region 71 is lower than the potential of the n-type well 90. Therefore, the potential of the p + region and the potential of the n-type well 90 do not have a forward bias relationship. Therefore, it is possible to suppress the flow of current from the p + region to the n-type well 90.

The source potential of the transistor 22 in the subsequent stage (potential supplied to the p + region 93) is lower than the source potential of the transistor 22 in the previous stage. On the other hand, for example, in all the transistors 22, the body potential (potential supplied to the n + region 91) is constant at the potential VSS. From the above, the difference between the source potential and the body potential in the transistor 22 in the subsequent stage is larger than the difference between the source potential and the body potential in the transistor 22 in the previous stage. Therefore, in order to suppress the increase in the threshold voltage of the transistor 22 due to the substrate bias effect, the number of transistors 22 provided in the charge transfer switch 20 is reduced so that the output potential of the charge transfer switch 20 does not become too low. It is preferable to do so.

In the semiconductor device 10 having the configurations shown in FIGS. 1A and 1B, the number of transistors 21 or transistors 22 provided in the charge transfer switch 20 is equal to the number of transistors 31 provided in the charge transfer switch 30. However, one aspect of the present invention is not limited to this. For example, a Si transistor has a higher charge transfer rate than an OS transistor. Therefore, even if the number of transistors 21 or 22 that can be Si transistors is smaller than the number of transistors 31 that can be OS transistors, the potential of the output terminal OUT can be lowered.

FIG. 4A is a modification of the semiconductor device 10 having the configuration shown in FIG. 1A, and shows a configuration example of the semiconductor device 10 when the number of transistors 21 is one less than the number of transistors 31. ing. FIG. 4B is a modification of the semiconductor device 10 having the configuration shown in FIG. 1B, and shows a configuration example of the semiconductor device 10 when the number of transistors 22 is one less than the number of transistors 31. ing. The number of transistors 21 or 22 may be two or more less than the number of transistors 31. Alternatively, the number of transistors 31 may be smaller than the number of transistors 21 or 22.

By reducing the number of the transistors 21 or the transistors 22, it is possible to reduce the influence of the variation in the threshold voltage of the transistors 21 or the transistors 22 on the output potential of the charge transfer switch 20. Therefore, the variation in the output potential of the charge transfer switch 20 can be reduced.

In the semiconductor device 10 having the configuration shown in FIGS. 1A and 1B, one electrode of the capacitive element 41 having a function as a pumping capacitor is electrically connected to both the transistor 21 or the transistor 22 and the transistor 31. Has been done. That is, the capacitive element 41 having a function as a pumping capacitor is shared by the charge transfer switch 20 and the charge transfer switch 30, but one aspect of the present invention is not limited to this. The capacitive element having a function as a pumping capacitor may not be shared by the charge transfer switch 20 and the charge transfer switch 30.

5 (A) is a modification of the semiconductor device 10 having the configuration shown in FIG. 1 (A), and FIG. 5 (B) is a modification of the semiconductor device 10 having the configuration shown in FIG. 1 (B). FIGS. 5A and 5B show a configuration example of the semiconductor device 10 when the semiconductor device 10 does not have the capacitive element group 40 but has the capacitive element group 50 and the capacitive element group 60.

The capacitive element group 50 has one or more capacitive elements 51. The capacitive element group 60 has one or more capacitive elements 61.

In FIGS. 5A and 5B, the number of the capacitive elements 51 included in the capacitive element group 50 is 4, but the number of the capacitive elements 51 is the number of the transistors 21 or the transistors 22 of the charge transfer switch 20. Depending on the number, the number may be 3 or less, or 5 or more. Further, in FIGS. 5A and 5B, the number of the capacitive elements 61 included in the capacitive element group 60 is four, but the number of the capacitive elements 61 depends on the number of transistors 31 included in the charge transfer switch 30. The number may be 3 or less, or 5 or more. Specifically, the number of the capacitive elements 51 can be one less than the number of the transistors 21 or the transistors 22, and the number of the capacitive elements 61 can be one less than the number of the transistors 31.

In the semiconductor device 10 having the configuration shown in FIG. 5A, one electrode of the capacitive element 51 [1] is electrically connected to the gate and drain of the transistor 21 [1] and the source of the transistor 21 [2]. There is. One electrode of the capacitive element 51 [2] is electrically connected to the gate and drain of the transistor 21 [2] and the source of the transistor 21 [3]. One electrode of the capacitive element 51 [3] is electrically connected to the gate and drain of the transistor 21 [3] and the source of the transistor 21 [4]. One electrode of the capacitive element 51 [4] is electrically connected to the gate and drain of the transistor 21 [4] and the source of the transistor 21 [5].

In the semiconductor device 10 having the configuration shown in FIG. 5B, one electrode of the capacitive element 51 [1] is electrically connected to the source of the transistor 22 [1] and the gate and drain of the transistor 22 [2]. There is. One electrode of the capacitive element 51 [2] is electrically connected to the source of the transistor 22 [2] and the gate and drain of the transistor 22 [3]. One electrode of the capacitive element 51 [3] is electrically connected to the source of the transistor 22 [3] and the gate and drain of the transistor 22 [4]. One electrode of the capacitive element 51 [4] is electrically connected to the source of the transistor 22 [4] and the gate and drain of the transistor 22 [5].

In the semiconductor device 10 having the configuration shown in FIGS. 5A and 5B, one electrode of the capacitive element 61 [1] is electrically connected to the gate and drain of the transistor 31 [1] and the source of the transistor 31 [2]. It is connected to the. One electrode of the capacitive element 61 [2] is electrically connected to the gate and drain of the transistor 31 [2] and the source of the transistor 31 [3]. One electrode of the capacitive element 61 [3] is electrically connected to the gate and drain of the transistor 31 [3] and the source of the transistor 31 [4]. One electrode of the capacitive element 61 [4] is electrically connected to the gate and drain of the transistor 31 [4] and the source of the transistor 31 [5].

Further, the clock signal output terminal OCK included in the clock signal generation circuit 11 includes the other electrode of the capacitive element 51 [1], the other electrode of the capacitive element 51 [3], and the other electrode of the capacitive element 61 [1]. It is electrically connected to the other electrode of the capacitive element 61 [3]. The clock signal output terminal OCKB included in the clock signal generation circuit 11 includes the other electrode of the capacitive element 51 [2], the other electrode of the capacitive element 51 [4], and the other electrode and the capacitive element of the capacitive element 61 [2]. It is electrically connected to the other electrode of 61 [4].

In the semiconductor device 10 having the configurations shown in FIGS. 5A and 5B, the charge transfer switch 20 is held by the capacitive element 51 when the phase of the clock signal input to the other electrode of the capacitive element 51 is switched. Charges can be transferred. Further, the charge transfer switch 30 can transfer the charge held by the capacitive element 61 when the phase of the clock signal input to the other electrode of the capacitive element 61 is switched. From the above, it can be said that the capacitive element 51 and the capacitive element 61 have a function as a pumping capacitor like the capacitive element 41.

By configuring the semiconductor device 10 as shown in FIGS. 5A and 5B, the capacity of the capacitive element having a function of holding the charge transferred by the charge transfer switch 20 and the charge transferred by the charge transfer switch 30 are transferred. The capacity of the capacitance element having the function of holding can be different from that of the capacitance element. For example, as will be described in detail later, since the off-current of the OS transistor is smaller than the off-current of the Si transistor, the capacitance of the capacitive element 61 can be smaller than the capacitance of the capacitive element 51.

In the semiconductor device 10 having the configurations shown in FIGS. 1A and 1B, the transistors provided in the charge transfer switch 20 are all Transistors 21 or Transistors 22 which can be Si transistors. The embodiment is not limited to this. A part of the transistor included in the charge transfer switch 20 may be an OS transistor.

6 (A) and 6 (B) are modification examples of the semiconductor device 10 having the configuration shown in FIG. 1 (A), and are transistors 21 having m-1 charge transfer switches 20 (m is an integer of 2 or more) or A configuration example of the semiconductor device 10 in the case of having the transistor 22 and one transistor 32 is shown. In the semiconductor device 10 having the configurations shown in FIGS. 6A and 6B, the charge transfer switch 30 has m transistors 31, and the capacitive element group 40 has m-1 capacitive elements 41. The number of transistors 31 included in the charge transfer switch 30 may be larger than, for example, m, and in this case, the number of capacitive elements 41 included in the capacitive element group 40 is also larger than m-1.

The transistor 32 is an OS transistor and can be an n-channel type transistor. The transistor 32 can have the same configuration as the transistor 31. Further, the transistor 32 is connected to a diode.

In the semiconductor device 10 having the configuration shown in FIG. 6A, the source of the transistor 32 is electrically connected to the gate and drain of the transistor 21 [m-1]. In the semiconductor device 10 having the configuration shown in FIG. 6B, the source of the transistor 32 is electrically connected to the source of the transistor 22 [m-1].

In the semiconductor device 10 having the configuration shown in FIGS. 6A and 6B, the source of the transistor 32 is the gate and drain of the transistor 31 [m-1], the source of the transistor 31 [m], and the capacitive element 41 [m−. 1] It is electrically connected to one of the electrodes. Further, the gate and drain of the transistor 32 are electrically connected to one electrode of the gate and drain of the transistor 31 [m], the output terminal OUT, and the capacitive element 12. That is, it can be said that the transistor 32 is the transistor at the final stage of the charge transfer switch 20.

Since the OS transistor uses a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more as a semiconductor material, the off-current is extremely small. Therefore, by using the OS transistor not only in the final stage transistor provided in the charge transfer switch 30 but also in the final stage transistor provided in the charge transfer switch 20, the charge can be retained in the capacitive element 12 for a long period of time. Can be done. As a result, it is possible to suppress fluctuations in the potential output from the output terminal OUT without performing charge transfer by the charge transfer switch 20 and the charge transfer switch 30 for a long period of time. Therefore, the clock frequencies of the clock signal OCK and the clock signal OCKB can be reduced. Alternatively, clock gating can be performed on the clock signal OCK and the clock signal OCKB. As a result, the power consumption of the semiconductor device 10 can be reduced. The transistor 32 does not have to be an OS transistor as long as the off current is extremely low.

As described above, the Si transistor has a larger on-current than the OS transistor. Therefore, when the configuration shown in FIGS. 6A and 6B is applied when the value of m is large, the charge transfer is caused by replacing the Si transistor in the final stage of the charge transfer switch 20 with an OS transistor. It is preferable because it is possible to suppress a decrease in the operating speed of the switch 20. For example, the value of m is preferably 5 or more, and more preferably 10 or more. On the other hand, if the value of m is too large, the variation in the threshold voltage of the transistor of the charge transfer switch 20 and the variation of the threshold voltage of the transistor of the charge transfer switch 30 have an effect on the potential of the output terminal OUT. Becomes larger. Therefore, the value of m is preferably 20 or less, for example.

<Operation example of semiconductor device>
FIG. 7 shows timings showing an example of the operation method of the semiconductor device 10 having the configurations shown in FIGS. 1 (A), 1 (B), 4 (A), (B) to 6 (A), (B), and the like. It is a chart. FIG. 7 shows the potential of the clock signal output terminal OCK, the potential of the clock signal output terminal OCKB, and the potential of the output terminal OUT. When the semiconductor device 10 has the configuration shown in FIGS. 6A and 6B, the timing chart shown in FIG. 7 corresponds to the case where the value of m is 5.

In FIG. 7 and the like, the potential VDD shows a potential higher than the potential VSS. For example, when the potential VSS is the ground potential, the potential VDD becomes a positive potential. The potential of the clock signal output terminal OCK and the potential of the clock signal output terminal OCKB can be the potential VDD or the potential VSS.

In the present specification and the like, switching the potential of the clock signal from, for example, the potential VDD to the potential VSS, or switching from the potential VSS to the potential VDD is referred to as switching the phase of the clock signal.

As shown in FIG. 7, the phase of the clock signal output from the clock signal output terminal OCKB can be 180 ° different from the phase of the clock signal output from the clock signal output terminal OCK. That is, when the potential of the clock signal output terminal OCK is the potential VDD, the potential of the clock signal output terminal OCKB is set to the potential VSS, and when the potential of the clock signal output terminal OCK is the potential VSS, the potential of the clock signal output terminal OCKB is set. It can be the potential VDD. It should be noted that there may be a period in which both the potential of the clock signal output terminal OCK and the potential of the clock signal output terminal OCKB are potential VDD, or there may be a period in which both are potential VSS.

The charge transfer switch 20 and the charge transfer switch 30 can transfer charges when the phase of the clock signal is switched. For example, in the case shown in FIG. 7, the electric charge is transferred when the potential of the clock signal is switched from the potential VDD to the potential VSS, that is, when the clock signal falls. As a result, the potential of the output terminal OUT is lowered. For example, when the potential of the input terminal IN is set to the potential VSS, the potential of the output terminal OUT finally drops to "5 (VSS- VDD + Vth)".

Here, "Vth" is the threshold voltage of the transistor included in the charge transfer switch. As described above, the potential of the output terminal OUT is the potential corresponding to the lower potential of the potential output from the charge transfer switch 20 or the potential output from the charge transfer switch 30. Therefore, when the output potential of the charge transfer switch 20 becomes the potential of the output terminal OUT, such as when the semiconductor device 10 is placed in an environment where the charge transfer switch 20 normally operates, "Vth" is the charge transfer. This is the threshold voltage of the transistor included in the switch 20. Further, when the output potential of the charge transfer switch 30 becomes the potential of the output terminal OUT, such as when the semiconductor device 10 is placed in an environment where the charge transfer switch 20 does not operate normally, "Vth" is the charge transfer. This is the threshold voltage of the transistor included in the switch 30.

In FIG. 7 and the like, the threshold voltages of the transistors of the charge transfer switch 20 are all the same, and the threshold voltages of the transistors of the charge transfer switch 30 are all the same. Further, when the charge transfer switch 20 has m transistors and the output potential of the charge transfer switch 20 becomes the potential of the output terminal OUT, the potential of the output terminal OUT is finally “m (VSS- VDD + Vth)). ". Further, even when the charge transfer switch 30 has m transistors and the output potential of the charge transfer switch 30 becomes the potential of the output terminal OUT, the potential of the output terminal OUT is finally “m (VSS- VDD + Vth)). ".

From the above, the smaller the threshold voltage Vth, the lower the potential of the output terminal OUT. Therefore, as the threshold voltage is smaller, the potential of the output terminal OUT can be lowered even if the number of transistors (value of m in the above equation) of the charge transfer switch is reduced. Therefore, for example, when the threshold voltage Vth of the Si transistor is smaller than that of the OS transistor, the number of transistors 21 or 22 is smaller than the number of transistors 31 as shown in FIGS. 4A and 4B. be able to.

<Cross-sectional configuration example 1 of semiconductor device>
FIG. 8 is a cross-sectional view showing a configuration example of a semiconductor device 10 having a transistor 22 and a transistor 31 and a capacitive element 12. FIG. 8 can be applied to, for example, the semiconductor device 10 having the configurations shown in FIGS. 1 (B), 4 (B), and 5 (B). Here, the transistor 22 and the transistor 31 shown in FIG. 8 are the transistor 22 in the final stage and the transistor 31 in the final stage, but the configuration shown in FIG. 8 shall be applied to the transistor 22 and the transistor 31 other than the final stage. Can be done.

9 (A) is a cross-sectional view of the transistor 31 in the channel length direction, and FIG. 9 (B) is a cross-sectional view of the transistor 31 in the channel width direction.

As shown in FIG. 8, a transistor 31 that can be an OS transistor and a capacitive element 12 can be provided on the upper layer of the transistor 22 that can be a Si transistor.

As described above, the transistor 22 can be formed on the substrate 70. The substrate 70 can be, for example, a p-type substrate. The substrate 70 is provided with a p + region 71 and an n-type well 90. The n-type well 90 is provided with an n + region 91, and a p + region 92 and a p + region 93.

The insulator 80 is provided on the substrate 70 so as to have a region overlapping the region between the p + region 92 and the p + region 93. Further, the conductor 81 is provided so as to have a region in contact with the insulator 80. The insulator 80 may have a region that overlaps with the p + region 92, or may have a region that overlaps with the p + region 93.

Here, as described above, the p + region 92 has a function as a source region of the transistor 22, and the p + region 93 has a function as a drain region of the transistor 22. Further, in the n-type well 90, a region between the p + region 92 and the p + region 93 that overlaps with the conductor 81 having a function as a gate electrode is a channel forming region of the transistor 22.

The substrate 70 preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 22 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.

The p + region 71, the p + region 92, and the p + region 93 contain, in addition to the semiconductor material applied to the substrate 70, an element such as boron that imparts p-type conductivity. Further, the n-type well 90 and the n + region 91 contain an element that imparts n-type conductivity such as phosphorus in addition to the semiconductor material applied to the substrate 70.

As the conductor 81, a semiconductor material such as silicon containing an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a conductive material such as a metal oxide material can be used. Alternatively, as the conductor 81, a semiconductor material such as silicon containing an element that imparts n-type conductivity such as phosphorus, a metal material, an alloy material, or a conductive material such as a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

The transistor 22 shown in FIG. 8 is an example, and the transistor 22 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 22.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.

The insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 22 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, for the insulator 324, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 31 and the like are provided from the substrate 70 or the transistor 22 and the like.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by the CVD method can be used. Here, the characteristics of the OS transistor may deteriorate due to the diffusion of hydrogen in the OS transistor such as the transistor 31. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 31 and the transistor 22. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

The amount of hydrogen desorbed can be analyzed using, for example, a thermal desorption gas analysis method (Thermal Desorption Spectroscopy; TDS) or the like. For example, in the TDS analysis, the amount of hydrogen desorbed from the insulator 324 is such that the amount desorbed in terms of hydrogen atoms is converted per area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C. to 500 ° C. It may be 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 324. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

Further, the conductor 328 is embedded in the insulator 320 and the insulator 322, and the conductor 330 is embedded in the insulator 324 and the insulator 326. The conductor 81 having a function as a gate electrode and the p + region 93 having a function as a drain region are electrically connected via the conductor 328 and the conductor 330.

The conductor 328 and the conductor 330 have a function as a plug or wiring. Further, in the conductor having a function as a plug or wiring, a plurality of structures may be collectively given the same reference numeral. Further, in the present specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may have a function as a wiring, and a part of the conductor may have a function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is single-layered or laminated. Can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 8, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug or wiring for connecting to the transistor 22. The conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 22 and the transistor 31 can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 22 to the transistor 31 can be suppressed.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 22 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided on the insulator 354 and on the conductor 356. For example, in FIG. 8, the insulator 360, the insulator 362, and the insulator 364 are laminated and provided in this order. Further, a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or wiring. The conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 360, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 366 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 22 and the transistor 31 can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 22 to the transistor 31 can be suppressed.

A wiring layer may be provided on the insulator 364 and on the conductor 366. For example, in FIG. 8, the insulator 370, the insulator 372, and the insulator 374 are laminated in this order. Further, a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or wiring. The conductor 376 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 370, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 376 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen. With this configuration, the transistor 22 and the transistor 31 can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 22 to the transistor 31 can be suppressed.

A wiring layer may be provided on the insulator 374 and on the conductor 376. For example, in FIG. 8, the insulator 380, the insulator 382, and the insulator 384 are laminated in this order. Further, a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 has a function as a plug or wiring. The conductor 386 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 380, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 386 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 22 and the transistor 31 can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 22 to the transistor 31 can be suppressed.

In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the configuration of the semiconductor device 10 is limited to this. It is not something that can be done. The number of wiring layers similar to the wiring layer including the conductor 356 may be 3 or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be 5 or more.

An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are laminated in this order on the insulator 384. As any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516, it is preferable to use a substance having a barrier property against oxygen and hydrogen.

For example, for the insulator 510 and the insulator 514, for example, a film having a barrier property so that hydrogen and impurities do not diffuse from the area where the substrate 70 or the transistor 22 is provided to the area where the transistor 31 is provided is used. Is preferable. Therefore, the same material as the insulator 324 can be used.

Further, as the film having a barrier property against hydrogen, for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 31 during and after the manufacturing process of the transistor. Further, it is possible to suppress the release of oxygen from the metal oxide constituting the transistor 31. Therefore, it is suitable for use as a protective film for the transistor 31.

Further, for example, the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by using a material having a relatively low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 512 and the insulator 516, a silicon oxide film, a silicon nitride film, or the like can be used.

As shown in FIGS. 9A and 9B, the transistor 31 is arranged on the conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, and on the insulator 516 and the conductor 503. Insulator 520, an insulator 522 placed on the insulator 520, an insulator 524 placed on the insulator 522, a metal oxide 530a placed on the insulator 524, and a metal. On the metal oxide 530b arranged on the oxide 530a, the conductor 542a and the conductor 542b arranged apart from each other on the metal oxide 530b, and on the insulator 524, the conductor 542a and the conductor 542b. The insulator 580, which is arranged in the conductor 542a and the conductor 542b and has an opening formed therein, the conductor 560 arranged in the opening, the metal oxide 530b, the conductor 542a, and the conductor. Between the insulator 550 disposed between the 542b and the insulator 580 and the conductor 560, and between the metal oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580 and the insulator 550. It has a metal oxide 530c and a metal oxide arranged in 530c.

Further, as shown in FIGS. 9A and 9B, there is an insulator 544 between the insulator 524, the metal oxide 530a, the metal oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580. It is preferable to be arranged. Further, as shown in FIGS. 9A and 9B, the conductor 560 is a conductor 560a provided inside the insulator 550 and a conductor provided so as to be embedded inside the conductor 560a. It is preferable to have 560b. Further, as shown in FIGS. 9A and 9B, it is preferable that the insulator 574 is arranged on the insulator 580, the conductor 560, the insulator 550, and the metal oxide 530c.

In the following, the metal oxide 530a, the metal oxide 530b, and the metal oxide 530c may be collectively referred to as the metal oxide 530. Further, the conductor 542a and the conductor 542b may be collectively referred to as a conductor 542.

The transistor 31 shows a configuration in which three layers of a metal oxide 530a, a metal oxide 530b, and a metal oxide 530c are laminated in a channel forming region and its vicinity, but the present invention is limited to this. It's not a thing. For example, a single layer of the metal oxide 530b, a two-layer structure of the metal oxide 530b and the metal oxide 530a, a two-layer structure of the metal oxide 530b and the metal oxide 530c, or a laminated structure of four or more layers is provided. May be good. Further, in the transistor 31, the conductor 560 is shown as a two-layer laminated structure, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers. Further, the transistor 31 shown in FIGS. 8 and 9 (A) and 9 (B) is an example, and the transistor is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

Here, the conductor 560 functions as a gate electrode of the transistor 31, the conductor 542a functions as a drain electrode of the transistor 31, and the conductor 542b has a function of a source electrode of the transistor 31. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 31, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 31 can be reduced. As a result, the semiconductor device 10 can be miniaturized and highly integrated.

Further, since the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 31 can be improved and the frequency characteristic of the transistor 31 can be improved.

The conductor 560 may have a function as a first gate electrode. Further, the conductor 503 may have a function as a second gate electrode. In that case, the threshold voltage of the transistor 31 can be controlled by changing the potential applied to the conductor 503 independently without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 31 can be made larger than 0V and the off-current can be made smaller. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.

In the present specification and the like, the first gate electrode indicates, for example, a top gate electrode. Further, the second gate electrode indicates, for example, a back gate electrode. The first gate electrode may be a back gate electrode and the second gate electrode may be a top gate electrode.

The conductor 503 is arranged so as to have a region overlapping the metal oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the metal oxide 530. be able to. In the present specification and the like, the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (s-channel) structure.

Further, the conductor 503 is in contact with the inner wall of the opening of the insulator 514 and the insulator 516 to form the conductor 503a, and the conductor 503b is further formed inside.

The insulator 520, the insulator 522, and the insulator 524 have a function as a gate insulating film of the second gate electrode. The insulator 550 has a function as a gate insulating film of the first gate electrode.

Here, as the insulator 524 in contact with the metal oxide 530, it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 524 has an excess oxygen region formed therein. By providing such an insulator containing excess oxygen in contact with the metal oxide 530, oxygen deficiency in the metal oxide 530 can be reduced and the reliability of the transistor 31 can be improved.

As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. Oxides that desorb oxygen by heating have an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ¹⁹ in terms of oxygen atoms in TDS analysis. An oxide film having atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ or more, or 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.

Further, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).

Since the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, the oxygen contained in the metal oxide 530 does not diffuse to the insulator 520 side, which is preferable. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 and the metal oxide 530.

The insulator 522 is a so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), (Ba, Sr) TiO ₃ (BST) and the like. -It is preferable to use an insulator containing a k material in a single layer or in a laminated manner. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for an insulator having a function as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the above-mentioned oxygen is difficult to permeate). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator 522 is formed by using such a material, the insulator 522 releases oxygen from the metal oxide 530 and mixes impurities such as hydrogen from the peripheral portion of the transistor 31 into the metal oxide 530. It has a function as a suppressing layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride, or silicon nitride may be laminated and used on the above-mentioned insulator.

Further, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon nitride nitride are suitable because they are thermally stable. Further, by combining the insulator of the high-k material with silicon oxide or silicon oxide nitride, it is possible to obtain an insulator 520 having a laminated structure that is thermally stable and has a high relative permittivity.

The insulator 520, the insulator 522, and the insulator 524 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

For the transistor 31, it is preferable to use a metal oxide having a function as an oxide semiconductor for the metal oxide 530 including the channel forming region. For example, as the metal oxide 530, In—M—Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, etc. It is preferable to use a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, magnesium and the like. Further, In—Ga oxide or In—Zn oxide may be used as the metal oxide 530.

As described above, it is preferable to use a metal oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide having a function as a channel forming region in the metal oxide 530. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.

By having the metal oxide 530a under the metal oxide 530b, the metal oxide 530 can suppress the diffusion of impurities from the structure formed below the metal oxide 530a to the metal oxide 530b. can. Further, by having the metal oxide 530c on the metal oxide 530b, it is possible to suppress the diffusion of impurities from the structure formed above the metal oxide 530c to the metal oxide 530b.

The metal oxide 530 preferably has a laminated structure due to oxides having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the metal oxide 530a, the atomic number ratio of the element M in the constituent elements is higher than the atomic number ratio of the element M in the constituent elements in the metal oxide used for the metal oxide 530b. , Preferably large. Further, in the metal oxide used for the metal oxide 530a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the metal oxide 530b. Further, in the metal oxide used for the metal oxide 530b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the metal oxide 530a. Further, as the metal oxide 530c, a metal oxide that can be used for the metal oxide 530a or the metal oxide 530b can be used.

Further, it is preferable that the energy at the lower end of the conduction band of the metal oxide 530a and the metal oxide 530c is higher than the energy at the lower end of the conduction band of the metal oxide 530b. In other words, it is preferable that the electron affinity of the metal oxide 530a and the metal oxide 530c is smaller than the electron affinity of the metal oxide 530b.

Here, at the junction of the metal oxide 530a, the metal oxide 530b, and the metal oxide 530c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the metal oxide 530a, the metal oxide 530b, and the metal oxide 530c is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 530a and the metal oxide 530b and the interface between the metal oxide 530b and the metal oxide 530c.

Specifically, the metal oxide 530a and the metal oxide 530b, and the metal oxide 530b and the metal oxide 530c have a common element (main component) other than oxygen, so that the defect level density is low. Layers can be formed. For example, when the metal oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the metal oxide 530a and the metal oxide 530c.

At this time, the main path of the carrier is the metal oxide 530b. By configuring the metal oxide 530a and the metal oxide 530c as described above, the defect level density at the interface between the metal oxide 530a and the metal oxide 530b and the interface between the metal oxide 530b and the metal oxide 530c can be determined. Can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 31 can obtain a high on-current.

On the metal oxide 530b, a conductor 542a having a function as a drain electrode and a conductor 542b having a function as a source electrode are provided. The conductors 542 (conductors 542a and 542b) include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, and berylium. , Indium, ruthenium, iridium, strontium, a metal element selected from lanthanum, an alloy containing the above-mentioned metal element as a component, or an alloy in which the above-mentioned metal element is combined is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen.

Further, as shown in FIG. 9A, when a region 543 (region 543a and region 543b) is formed as a low resistance region at the interface of the metal oxide 530 with the conductor 542 and its vicinity thereof. There is. At this time, the region 543a functions as a drain region, and the region 543b functions as a source region. Further, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

By providing the conductor 542 so as to be in contact with the metal oxide 530, the oxygen concentration in the region 543 may be reduced. Further, a metal compound layer containing the metal contained in the conductor 542 and the component of the metal oxide 530 may be formed in the region 543. In such a case, the carrier density of the region 543 increases, and the region 543 becomes a low resistance region.

The insulator 544 is provided so as to cover the conductor 542 and suppresses the oxidation of the conductor 542. At this time, the insulator 544 may be provided so as to cover the side surface of the metal oxide 530 and come into contact with the insulator 524.

As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used. can.

In particular, as the insulator 544, it is preferable to use aluminum, or an oxide containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, aluminum and an oxide containing hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step. If the conductor 542 is a material having oxidation resistance, or if the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.

The insulator 550 has a function as a gate insulating film. The insulator 550 is preferably arranged in contact with the inside (upper surface and side surface) of the metal oxide 530c. The insulator 550 is preferably formed by using an insulator that releases oxygen by heating. For example, in TDS analysis, the amount of oxygen desorbed in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ¹⁹ atoms / cm ³ or more, and more preferably 2. It is an oxide film having a ratio of 0.0 × 10 ¹⁹ atoms / cm ³ or more, or 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower.

Specifically, it has silicon oxide having excess oxygen, silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. Silicon oxide can be used. In particular, silicon oxide and silicon nitride nitride are preferable because they are stable against heat.

By providing an insulator that releases oxygen by heating as an insulator 550 in contact with the upper surface of the metal oxide 530c, it is effective from the insulator 550 through the metal oxide 530c to the channel forming region of the metal oxide 530b. Oxygen can be supplied. Further, as with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

Further, in order to efficiently supply the excess oxygen contained in the insulator 550 to the metal oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing the metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the metal oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide provided between the insulator 550 and the conductor 560, a material that can be used for the insulator 544 may be used.

The conductor 560 having a function as the first gate electrode is shown as a two-layer structure in FIGS. 9A and 9B, but may be a single-layer structure or a laminated structure having three or more layers. May be good.

The conductor 560a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ₍ N2O, NO, _NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.

Further, as the conductor 560b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also has a function as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.

The insulator 580 is provided on the conductor 542 via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores are used. , Or a resin or the like is preferable. In particular, silicon oxide and silicon nitride nitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 in which oxygen is released by heating in contact with the metal oxide 530c, the oxygen in the insulator 580 is efficiently transferred to the metal oxide 530a and the metal oxide 530b through the metal oxide 530c. Can be supplied. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

The opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

In miniaturizing the semiconductor device 10, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 may have a shape having a high aspect ratio. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.

The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, the upper surface of the insulator 550, and the metal oxide 530c. By forming the insulator 574 into a film by a sputtering method, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied into the metal oxide 530 from the excess oxygen region.

For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, ittrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like is used. Can be done.

In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.

Further, it is preferable to provide an insulator 581 having a function as an interlayer film on the insulator 574. It is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the membrane, similarly to the insulator 524 and the like.

As shown in FIG. 8, the capacitive element 12 includes an insulator 516, an insulator 514, an insulator 512, a conductor 518 embedded in the insulator 510, and an insulator 520 arranged on the conductor 518. It has an insulator 522, an insulator 524, and a conductor 541 arranged on the insulator 524.

The conductor 518 functions as one electrode of the capacitive element 12, and serves as a source region of the transistor 22 via the conductor 386, the conductor 376, the conductor 366, the conductor 356, the conductor 330, and the conductor 328. It is electrically connected to the p + region 92 having the function of. The insulator 520, the insulator 522, and the insulator 524 have a function as a dielectric of the capacitive element 12. The conductor 541 has a function as the other electrode of the capacitive element 12.

The conductor 518 can be formed by the same material and the same process as the conductor 503. The conductor 541 can be formed by the same material and the same process as the conductor 542a and the conductor 542b.

By configuring the capacitive element 12 as shown in FIG. 8, the three layers of the insulator 520, the insulator 522, and the insulator 524 can be used as the dielectric of the capacitive element 12. Therefore, the thickness of the dielectric of the capacitive element 12 can be made thicker than, for example, when the insulator 550 is used as the dielectric of the capacitive element 12 without increasing the number of manufacturing steps and the throughput of the semiconductor device 10. Therefore, it is possible to prevent the electric charge held in the capacitive element 12 from leaking through the dielectric of the capacitive element 12, so that the electric charge can be retained in the capacitive element 12 for a long period of time. Therefore, the power consumption of the semiconductor device 10 can be reduced.

An insulator 582 is provided on the insulator 581. As the insulator 582, it is preferable to use a substance having a barrier property against oxygen and hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 31 during and after the manufacturing process of the transistor. Further, it is possible to suppress the release of oxygen from the oxide constituting the transistor 31. Therefore, it is suitable for use as a protective film for the transistor 31.

Further, an insulator 586 is provided on the insulator 582. As the insulator 586, the same material as the insulator 320 can be used. Further, by using a material having a relatively low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 586, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include a conductor 546 and a conductor 548. It is embedded.

The conductor 546 and the conductor 548 have a function as a plug or wiring for connecting to the capacitive element 12, the transistor 31, or the transistor 22. The conductor 546 and the conductor 548 can be provided by using the same materials as the conductor 328 and the conductor 330.

A conductor 610, a conductor 612, and a conductor 614 are provided on the conductor 546 and the conductor 548. The conductor 610 has a function as a plug or wiring for connecting to the transistor 31. The conductor 612 has a function as a plug or wiring for connecting the conductor 560, the conductor 542a, and the conductor 518 to each other. The conductor 614 has a function as a plug or wiring for connecting to the capacitive element 12.

The conductor 610, the conductor 612, and the conductor 614 are composed of a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or the above-mentioned elements. A metal nitride film (tantal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium-tin oxide.

In FIG. 8, the conductor 610, the conductor 612, and the conductor 614 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having the barrier property and the conductor having a high conductivity.

An insulator 650 is provided on the conductor 610, the conductor 612, the conductor 614, and the insulator 586. The insulator 650 can be provided by using the same material as the insulator 320. Further, the insulator 650 may function as a flattening film that covers the uneven shape below the insulator 650.

The capacitive element 41, or the capacitive element 51 and the capacitive element 61 can be provided on the insulator 586. In this case, the circuit area of the semiconductor device 10 can be reduced. Further, the capacitive element 41, or the capacitive element 51 and the capacitive element 61 can be provided in the same layer as the capacitive element 12. That is, the capacitive element 41, or the capacitive element 51 and the capacitive element 61 can be formed by the same process as the capacitive element 12. In this case, since the manufacturing process of the semiconductor device 10 can be simplified, the semiconductor device 10 can be made inexpensive.

By using this structure, it is possible to suppress fluctuations in electrical characteristics and improve reliability in a semiconductor device using a transistor having a metal oxide. Alternatively, it is possible to provide a transistor having a metal oxide having a large on-current. Alternatively, a transistor having a metal oxide having a small off-current can be provided. Alternatively, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, in a semiconductor device using a transistor having a metal oxide, miniaturization or high integration can be achieved.

<Cross-sectional configuration example 2 of semiconductor device>
FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device 10 having a transistor 31, a transistor 32, and a capacitive element 12. FIG. 10 can be applied to, for example, the semiconductor device 10 having the configurations shown in FIGS. 6A and 6B. Here, the transistor 31 shown in FIG. 10 is the transistor 31 in the final stage, but the configuration shown in FIG. 10 can be applied to the transistor 31 other than the final stage.

Although the lower layer is omitted from the insulator 512 in FIG. 10, the configuration can be the same as that in FIG.

The transistor 31 can have the same configuration as that shown in FIG. The transistor 32 can have the same configuration as the transistor 31, and can be provided on the same layer as the transistor 31.

In the semiconductor device 10 having the configuration shown in FIG. 10, the conductor 542a can be used as one electrode of the capacitive element 12. Further, the conductor 518, which is made of the same material as the conductor 503 and can be formed in the same process, can be used as the other electrode of the capacitive element 12. Further, the conductor 620, the conductor 622, the conductor 624, the conductor 626, and the conductor 628 are provided on the conductor 546 and the conductor 548. The conductor 620 has a function as a plug or wiring for connecting to the transistor 31. The conductor 622 has a function as a plug or wiring for connecting the conductor 560 of the transistor 31 and the conductor 542a to each other. The conductor 624 has a function as a plug or wiring for connecting to the capacitive element 12. The conductor 626 has a function as a plug or wiring for connecting the conductor 560 of the transistor 32 and the conductor 542a to each other. The conductor 628 has a function as a plug or wiring for connecting to the transistor 32. Here, the conductor 624 can be electrically connected to the output terminal OUT.

For the conductor 620, the conductor 622, the conductor 624, the conductor 626, and the conductor 628, the same materials as those of the conductor 610, the conductor 612, and the conductor 614 shown in FIG. 8 can be used. Further, an insulator 650 is provided on the conductor 620, the conductor 622, the conductor 624, the conductor 626, the conductor 628, and the insulator 586.

<Potential supply destination output by the semiconductor device>
Next, the supply destination of the potential output from the output terminal OUT of the semiconductor device 10 will be described. FIG. 11 is a circuit diagram showing a connection destination of the output terminal OUT included in the semiconductor device 10. As shown in FIG. 11, the potential of the output terminal OUT can be supplied to, for example, the cell array 200 in which the memory cells 209 are arranged. The cell array 200 constitutes, for example, a part of a storage device, a CPU (Central Processing Unit), an image pickup device, or the like. Although FIG. 11 shows a configuration in which only one row of memory cells 209 is provided in the cell array 200, the memory cells 209 can be provided in a matrix in the cell array 200.

The memory cell 209 includes a transistor MW and a capacitive element CS. One of the source or drain of the transistor MW is electrically connected to one electrode of the capacitive element CS. The first gate of the transistor MW is electrically connected to a wiring WL having a function as a word line. The second gate of the transistor MW is electrically connected to the output terminal OUT of the semiconductor device 10 via the wiring BGL. Further, for example, a potential VSS can be supplied to the other electrode of the capacitive element CS.

As shown in FIG. 11, the potential output from the output terminal OUT of the semiconductor device 10 can be supplied to the second gate of the transistor MW. As described above, the potential of the output terminal OUT can be lower than the potential of the input terminal IN, and can be, for example, a negative potential. When the potential of the output terminal OUT is a negative potential, the negative potential is supplied to the second gate of the transistor MW, so that the threshold voltage of the transistor MW is positively shifted and the off current can be reduced. can. As a result, the electric charge can be retained in the capacitive element CS for a long period of time. Therefore, since the frequency of writing the electric charge to the capacitive element CS can be reduced, the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

The transistor MW is preferably an OS transistor. As mentioned above, the off current of the OS transistor is extremely small. Therefore, by using the transistor MW as an OS transistor, the frequency of writing charges to the capacitive element CS can be further reduced, and the power consumption of the semiconductor device according to one aspect of the present invention can be further reduced.

Although FIG. 11 shows a configuration in which one semiconductor device 10 is provided for one cell array 200, two or more semiconductor devices 10 may be provided for one cell array 200. .. By increasing the number of semiconductor devices 10, signal delay and the like can be reduced, so that the operation of the semiconductor device according to one aspect of the present invention can be speeded up.

Hereinafter, a case where the cell array 200 is applied to the storage device will be described. FIG. 12A is a block diagram showing a configuration example of the storage device 210 to which the cell array 200 is applied. As described above, the memory cells 209 can be arranged in a matrix in the cell array 200.

The storage device 210 includes a potential generation unit 201, a control unit 202, and a peripheral circuit 208 in addition to the cell array 200. The potential generation unit 201 has a semiconductor device 10. The peripheral circuit 208 includes a sense amplifier circuit 204, a driver 205, a main amplifier 206, and an input / output circuit 207.

The memory cell 209 is electrically connected to the wiring WL, the wiring LBL (or the wiring LBLB), and the wiring BGL. As described above, the wiring WL has a function as a word line. Further, the wiring LBL and the wiring LBLB have a function as a local bit line.

FIG. 12B is a configuration example of the memory cell 209. 12 (B) shows the memory cell 209 having the configuration shown in FIG. 11 with the wiring LBL added. The wiring LBL is electrically connected to the other of the source or drain of the transistor MW.

A plurality of wiring WLs and a plurality of wiring CSELs are electrically connected to the driver 205. The driver 205 generates a signal to be output to a plurality of wiring WLs and a plurality of wiring CSELs.

The cell array 200 is provided so as to be laminated on the sense amplifier circuit 204. The sense amplifier circuit 204 has a plurality of sense amplifiers SA. The sense amplifier SA is electrically connected to adjacent wiring LBL and wiring LBLB (local bit line pair), wiring GBL and wiring GBLB (global bit line pair), and a plurality of wiring CSELs. The sense amplifier SA has a function of amplifying the potential difference between the wiring LBL and the wiring LBLB.

In the sense amplifier circuit 204, one wiring GBL is provided for each of the four wiring LBBLs, and one wiring GBLB is provided for each of the four wiring LBLBs. The configuration is not limited to the configuration example of FIG. 12 (A).

The main amplifier 206 is connected to the sense amplifier circuit 204 and the input / output circuit 207. The main amplifier 206 has a function of amplifying the voltage of the wiring GBL. The main amplifier 206 can be omitted.

The input / output circuit 207 has a function of inputting a potential corresponding to write data to the wiring GBL. Further, the input / output circuit 207 has a function of reading out the potential of the wiring GBL or the output potential of the main amplifier 206 to the outside as read data.

A sense amplifier SA for reading data and a sense amplifier SA for writing data can be selected by the signal of the wiring CSEL. Therefore, since the input / output circuit 207 does not require a selection circuit such as a multiplexer, the circuit configuration can be simplified and the occupied area can be reduced.

The control unit 202 has a function of controlling the storage device 210. For example, the control unit 202 controls the driver 205, the main amplifier 206, and the input / output circuit 207.

The potential VDD and the potential VSS are input to the storage device 210 as the power potential. The potentials other than the potential VDD and the potential VSS are generated by the potential generation unit 201. The potential generated by the potential generation unit 201 is input to each circuit of the storage device 210. The potential VDD can be used, for example, as the drive potential of the transistor MW. The drive potential of the transistor MW may be generated by the potential generation unit 201.

The semiconductor device 10 provided in the potential generation unit 201 has a function of generating the potential VBG. The potential VBG is input to the wiring BGL.

In the example of FIG. 12A, although it is an example of a folded bit line type random access memory (RAM), it can also be an open bit line type RAM.

This embodiment can be implemented in combination with other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a transistor that can be used in the semiconductor device of one aspect of the present invention will be described.

<Transistor structure example 1>
A structural example of the transistor 510A will be described with reference to FIGS. 13A, 13B and 13C. FIG. 13A is a top view of the transistor 510A. 13 (B) is a cross-sectional view of a portion shown by the alternate long and short dash line L1-L2 in FIG. 13 (A). 13 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line W1-W2 in FIG. 13 (A). In the top view of FIG. 13A, some elements are omitted for the sake of clarity of the figure.

In FIGS. 13A, 13B and 13C, the transistor 510A and the insulator 511, the insulator 512, the insulator 514, the insulator 516, the insulator 580, the insulator 582, which have a function as an interlayer film, are shown. And insulator 584 are shown. Further, a conductor 546 (conductor 546a and a conductor 546b) that is electrically connected to the transistor 510A and has a function as a contact plug and a conductor 503 that has a function as a wiring are shown.

The conductor 510A has a conductor 560 (conductor 560a and conductor 560b) having a function as a first gate electrode and a conductor 505 (conductor 505a and a conductor) having a function as a second gate electrode. 505b), an insulator 550 having a function as a first gate insulating film, an insulator 521 having a function as a second gate insulating film, an insulator 522, and an insulator 524, and a channel forming region. A metal oxide 530 (metal oxide 530a, a metal oxide 530b, and a metal oxide 530c), a conductor 542a having a function as one of a source or a drain, and a conductor having a function as one of a source or a drain. It has 542b and an insulator 574.

Further, in the transistor 510A shown in FIG. 13, the metal oxide 530c, the insulator 550, and the conductor 560 are arranged in the opening provided in the insulator 580 via the insulator 574. Further, the metal oxide 530c, the insulator 550, and the conductor 560 are arranged between the conductor 542a and the conductor 542b.

The insulator 511 and the insulator 512 have a function as an interlayer film.

As the interlayer film, silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) An insulator such as TiO ₃ (BST) can be used in a single layer or in a laminated manner. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride or silicon nitride may be laminated and used on the above-mentioned insulator.

For example, the insulator 511 preferably has a function as a barrier membrane for suppressing impurities such as water and hydrogen from being mixed into the transistor 510A from the substrate side. Therefore, it is preferable to use an insulating material for the insulator 511, which has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the above oxygen is difficult to permeate). Further, for example, aluminum oxide, silicon nitride or the like may be used as the insulator 511. With this configuration, it is possible to prevent impurities such as hydrogen and water from diffusing from the substrate side to the transistor 510A side of the insulator 511.

For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

The conductor 503 is formed so as to be embedded in the insulator 512. Here, the height of the upper surface of the conductor 503 and the height of the upper surface of the insulator 512 can be made equal to each other. Although the conductor 503 is shown to have a single layer structure, the present invention is not limited to this. For example, the conductor 503 may have a multilayer film structure having two or more layers. As the conductor 503, it is preferable to use a highly conductive material containing tungsten, copper, or aluminum as a main component.

In the transistor 510A, the conductor 560 may have a function as a first gate electrode. Further, the conductor 505 may have a function as a second gate electrode. In that case, the threshold voltage of the transistor 510A can be controlled by changing the potential applied to the conductor 505 independently without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 505, the threshold voltage of the transistor 510A can be made larger than 0V, and the off-current can be reduced. Therefore, when a negative potential is applied to the conductor 505, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.

Further, for example, when a potential is applied to the conductor 560 and the conductor 505 by superimposing the conductor 505 and the conductor 560, the electric field generated from the conductor 560 and the electric field generated from the conductor 505 are generated. And can cover the channel forming region formed in the metal oxide 530. That is, it can take an s-channel structure.

The insulator 514 and the insulator 516 have a function as an interlayer film, similarly to the insulator 511 or the insulator 512. For example, the insulator 514 preferably has a function as a barrier membrane for suppressing impurities such as water and hydrogen from being mixed into the transistor 510A from the substrate side. With this configuration, it is possible to prevent impurities such as hydrogen and water from diffusing from the substrate side to the transistor 510A side of the insulator 514. Further, for example, the insulator 516 preferably has a lower dielectric constant than the insulator 514. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

In the conductor 505 having a function as a second gate, the conductor 505a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 505b is further formed inside. Here, the height of the upper surface of the conductor 505a and the conductor 505b can be made the same as the height of the upper surface of the insulator 516. The transistor 510A shows a configuration in which the conductors 505a and the conductors 505b are laminated, but the present invention is not limited to this. For example, the conductor 505 may be provided as a single layer or a laminated structure having three or more layers.

Here, as the conductor 505a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the above oxygen is difficult to permeate). In the present specification, the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

For example, since the conductor 505a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 505b from being oxidized and the conductivity from being lowered.

When the conductor 505 also has a wiring function, it is preferable to use a highly conductive conductive material containing tungsten, copper, or aluminum as a main component for the conductor 505b. In that case, the conductor 503 does not necessarily have to be provided. Although the conductor 505b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.

The insulator 521, the insulator 522, and the insulator 524 have a function as a second gate insulating film.

Further, the insulator 522 preferably has a barrier property. Since the insulator 522 has a barrier property, it has a function as a layer for suppressing the mixing of impurities such as hydrogen from the peripheral portion of the transistor 510A into the transistor 510A.

For example, the insulator 521 is preferably thermally stable. For example, silicon oxide and silicon nitride nitride are suitable because they are thermally stable. Further, by combining the insulator of the high-k material with silicon oxide or silicon oxide nitride, it is possible to obtain an insulator 522 having a laminated structure that is thermally stable and has a high relative permittivity.

Although FIG. 13 shows a laminated structure of three layers as the second gate insulating film, it may be a single layer or a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

The metal oxide 530 having a region having a function as a channel forming region has a metal oxide 530a, a metal oxide 530b on the metal oxide 530a, and a metal oxide 530c on the metal oxide 530b. By having the metal oxide 530a under the metal oxide 530b, it is possible to suppress the diffusion of impurities from the structure formed below the metal oxide 530a to the metal oxide 530b. Further, by having the metal oxide 530c on the metal oxide 530b, it is possible to suppress the diffusion of impurities from the structure formed above the metal oxide 530c to the metal oxide 530b. As the metal oxide 530, an oxide semiconductor which is a kind of the above-mentioned metal oxide can be used.

The metal oxide 530c is preferably provided in the opening provided in the insulator 580 via the insulator 574. When the insulator 574 has a barrier property, it is possible to prevent impurities from the insulator 580 from diffusing into the metal oxide 530.

One of the conductors 542 functions as a source electrode and the other functions as a drain electrode.

The insulator 550 has a function as a first gate insulating film. The insulator 550 is preferably provided in the opening provided in the insulator 580 via the metal oxide 530c and the insulator 574.

As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. In that case, the insulator 550 may have a laminated structure like the second gate insulating film. By forming an insulator that functions as a gate insulating film into a laminated structure of a high-k material and a thermally stable material, the gate potential during transistor operation is reduced while maintaining the physical film thickness. Is possible. In addition, a laminated structure that is thermally stable and has a high relative permittivity can be obtained.

An insulator 574 is arranged between the insulator 580 and the transistor 510A. As the insulator 574, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. By having the insulator 574, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the metal oxide 530b via the metal oxide 530c and the insulator 550. Further, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen contained in the insulator 580.

The insulator 580, the insulator 582, and the insulator 584 have a function as an interlayer film.

Like the insulator 514, the insulator 582 preferably has a function as a barrier insulating film that prevents impurities such as water and hydrogen from being mixed into the transistor 510A from the outside.

Further, it is preferable that the insulator 580 and the insulator 584 have a lower dielectric constant than the insulator 582, like the insulator 516. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

Further, the transistor 510A may be electrically connected to another structure via a plug or wiring such as an insulator 580, an insulator 582, and a conductor 546 embedded in the insulator 584.

Further, as the material of the conductor 546, similarly to the conductor 505, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or laminated. .. For example, it is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

For example, as the conductor 546, for example, by using a laminated structure of tantalum nitride, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity, the conductivity as a wiring can be improved. While holding it, it is possible to suppress the diffusion of impurities from the outside.

By having the above structure, it is possible to provide a semiconductor device having a transistor having an oxide semiconductor having a large on-current. Alternatively, it is possible to provide a semiconductor device having a transistor having an oxide semiconductor having a small off-current. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

<Transistor structure example 2>
A structural example of the transistor 510B will be described with reference to FIGS. 14 (A), (B) and (C). FIG. 14A is a top view of the transistor 510B. 14 (B) is a cross-sectional view of a portion shown by the alternate long and short dash line L1-L2 in FIG. 14 (A). 14 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line W1-W2 in FIG. 14 (A). In the top view of FIG. 14A, some elements are omitted for the sake of clarity of the figure.

The transistor 510B is a modification of the transistor 510A. Therefore, in order to prevent the explanation from being repeated, the points different from the transistor 510A will be mainly described.

The transistor 510B has a region in which the conductor 542 (conductor 542a and conductor 542b) and the metal oxide 530c, the insulator 550, and the conductor 560 overlap each other. With this structure, it is possible to provide a transistor having a high on-current. Further, it is possible to provide a transistor having high controllability.

The conductor 560 having a function as the first gate electrode has a conductor 560a and a conductor 560b on the conductor 560a. As the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms, similarly to the conductor 505a. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.).

Since the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, it is possible to suppress the oxidation of the conductor 560b and prevent the conductivity from being lowered.

Further, it is preferable to provide the insulator 574 so as to cover the upper surface and the side surface of the conductor 560, the side surface of the insulator 550, and the side surface of the metal oxide 530c. As the insulator 574, it is preferable to use an insulating material having a function of suppressing impurities such as water or hydrogen and diffusion of oxygen. By providing the insulator 574, the oxidation of the conductor 560 can be suppressed. Further, by having the insulator 574, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 to the transistor 510B.

Further, an insulator 576 (insulator 576a and insulator 576b) having a barrier property may be arranged between the conductor 546 and the insulator 580. By providing the insulator 576, it is possible to suppress the oxygen of the insulator 580 from reacting with the conductor 546 and oxidizing the conductor 546.

Further, by providing the insulator 576 having a barrier property, it is possible to widen the range of material selection of the conductor used for the plug and the wiring. For example, by using a metal material having a property of absorbing oxygen and having high conductivity in the conductor 546, it is possible to provide a semiconductor device having low power consumption. Specifically, materials such as tungsten and aluminum, which have low oxidation resistance but high conductivity, can be used. Further, for example, a conductor that is easy to form a film or process can be used.

<Transistor structure example 3>
A structural example of the transistor 510C will be described with reference to FIGS. 15 (A), (B) and (C). FIG. 15A is a top view of the transistor 510C. 15 (B) is a cross-sectional view of a portion shown by the alternate long and short dash line L1-L2 in FIG. 15 (A). 15 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line W1-W2 in FIG. 15 (A). In the top view of FIG. 15A, some elements are omitted for the sake of clarity of the figure.

The transistor 510C is a modification of the transistor 510A. Therefore, in order to prevent the explanation from being repeated, the points different from the transistor 510A will be mainly described.

In the transistor 510C shown in FIG. 15, the conductor 547a is arranged between the conductor 542a and the metal oxide 530b, and the conductor 547b is arranged between the conductor 542b and the metal oxide 530b. Here, the conductor 542a (conductor 542b) extends beyond the upper surface of the conductor 547a (conductor 547b) and the side surface on the conductor 560 side, and has a region in contact with the upper surface of the metal oxide 530b. Here, as the conductor 547, a conductor that can be used for the conductor 542 may be used. Further, the film thickness of the conductor 547 is preferably at least thicker than that of the conductor 542.

By having the above-mentioned configuration, the transistor 510C shown in FIG. 15 can bring the conductor 542 closer to the conductor 560 than the transistor 510A. Alternatively, the conductor 560 can be overlapped with the end of the conductor 542a and the end of the conductor 542b. As a result, the substantial channel length of the transistor 510C can be shortened, and the on-current and frequency characteristics can be improved.

Further, it is preferable that the conductor 547a (conductor 547b) is provided so as to be superimposed on the conductor 542a (conductor 542b). With such a configuration, the conductor 547a (conductor 547b) functions as a stopper and the metal oxide 530b is overetched in the etching for forming the opening for embedding the conductor 546a (conductor 546b). Can be prevented.

Further, the transistor 510C shown in FIG. 15 may be configured such that the insulator 545 is arranged in contact with the insulator 544. The insulator 544 preferably has a function as a barrier insulating film that suppresses impurities such as water or hydrogen and excess oxygen from being mixed into the transistor 510C from the insulator 580 side. As the insulator 545, an insulator that can be used for the insulator 544 can be used. Further, as the insulator 544, a nitride insulator such as aluminum nitride, titanium nitride, titanium nitride, silicon nitride, or silicon nitride may be used.

Further, unlike the transistor 510A shown in FIG. 13, the transistor 510C shown in FIG. 15 may be provided with the conductor 505 in a single layer structure. In this case, an insulating film to be an insulator 516 is formed on the patterned conductor 505, and the upper portion of the insulating film is removed by a CMP method or the like until the upper surface of the conductor 505 is exposed. good. Here, it is preferable to improve the flatness of the upper surface of the conductor 505. For example, the average surface roughness (Ra) of the upper surface of the conductor 505 may be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. As a result, the flatness of the insulator formed on the conductor 505 can be improved, and the crystallinity of the metal oxide 530b and the metal oxide 530c can be improved.

<Transistor structure example 4>
A structural example of the transistor 510D will be described with reference to FIGS. 16A, 16B and 16C. FIG. 16A is a top view of the transistor 510D. 16 (B) is a cross-sectional view of a portion shown by the alternate long and short dash line L1-L2 in FIG. 16 (A). 16 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line W1-W2 in FIG. 16 (A). In the top view of FIG. 16A, some elements are omitted for the sake of clarity of the figure.

The transistor 510D is a modification of the above transistor. Therefore, in order to prevent the explanation from being repeated, the points different from the above-mentioned transistor will be mainly described.

In FIGS. 16A to 16C, the conductor 505 having a function as a second gate is also used as wiring without providing the conductor 503. Further, the insulator 550 is provided on the metal oxide 530c, and the metal oxide 552 is provided on the insulator 550. Further, the conductor 560 is provided on the metal oxide 552, and the insulator 570 is provided on the conductor 560. It also has an insulator 571 on the insulator 570.

The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 that suppresses the diffusion of oxygen between the insulator 550 and the conductor 560, the diffusion of oxygen to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the metal oxide 530. In addition, it is possible to suppress the oxidation of the conductor 560 by oxygen.

The metal oxide 552 may have a function as a part of the first gate. For example, an oxide semiconductor that can be used as the metal oxide 530 can be used as the metal oxide 552. In that case, by forming the conductor 560 into a film by a sputtering method, the electric resistance value of the metal oxide 552 can be lowered to form a conductor. This can be called an OC (Oxide Conductor) electrode.

Further, the metal oxide 552 may have a function as a part of the gate insulating film. Therefore, when silicon oxide, silicon nitride nitride, or the like is used for the insulator 550, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity as the metal oxide 552. By adopting the laminated structure, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator having a function as a gate insulating film.

In the transistor 510D, the metal oxide 552 is shown as a single layer, but a laminated structure of two or more layers may be used. For example, a metal oxide having a function as a part of a gate electrode and a metal oxide having a function as a part of a gate insulating film may be laminated and provided.

When the metal oxide 552 has a function as a gate electrode, the on-current of the transistor 510D can be improved without weakening the influence of the electric field from the conductor 560. Alternatively, when it has a function as a gate insulating film, it is conductive by keeping a distance between the conductor 560 and the metal oxide 530 due to the physical thickness of the insulator 550 and the metal oxide 552. The leakage current between the body 560 and the metal oxide 530 can be suppressed. Therefore, by providing the laminated structure with the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the metal oxide 530 and the electric field strength applied from the conductor 560 to the metal oxide 530 are provided. Can be easily and appropriately adjusted.

Specifically, the metal oxide 552 can be used as the metal oxide 552 by lowering the resistance of the oxide semiconductor that can be used for the metal oxide 530. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used.

In particular, it is preferable to use aluminum oxide, an oxide containing hafnium oxide, aluminum oxide, and an oxide containing hafnium (hafnium aluminate), which is an insulator containing an oxide of one or both of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step. The metal oxide 552 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.

As the insulator 570, it is preferable to use an insulating material having a function of suppressing impurities such as water or hydrogen and oxygen permeation. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. As a result, it is possible to suppress the oxidation of the conductor 560 by oxygen from above the insulator 570. Further, it is possible to prevent impurities such as water or hydrogen from above the insulator 570 from being mixed into the oxide 230 via the conductor 560 and the insulator 550.

The insulator 571 has a function as a hard mask. By providing the insulator 571, when the conductor 560 is processed, the side surface of the conductor 560 is approximately vertical, specifically, the angle formed by the side surface of the conductor 560 and the surface of the substrate is 75 degrees or more and 100 degrees or less. It can be preferably 80 degrees or more and 95 degrees or less.

By using an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen in the insulator 571, the insulator may also function as a barrier layer. In that case, the insulator 570 does not have to be provided.

By using the insulator 571 as a hard mask to selectively remove a part of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the metal oxide 530c, these aspects are substantially matched. It is possible to expose a part of the surface of the metal oxide 530b.

Further, the transistor 510D has a region 531a and a region 531b on a part of the surface of the exposed metal oxide 530b. One of the regions 531a and 531b functions as a source region, and the other functions as a drain region.

For the formation of the region 531a and the region 531b, for example, an ion implantation method, an ion doping method, a plasma implantation ion implantation method, a plasma treatment, or the like is used to introduce an impurity element such as phosphorus or boron into the surface of the exposed metal oxide 530b. It can be realized by doing. In the present embodiment and the like, the "impurity element" means an element other than the main component element.

Further, by exposing a part of the surface of the metal oxide 530b, a metal film is formed, and then heat treatment is performed, the elements contained in the metal film are diffused into the metal oxide 530b, and the regions 531a and 531b are diffused. Can also be formed.

The electrical resistivity decreases in the region where the impurity element of the metal oxide 530b is introduced. Therefore, the region 531a and the region 531b may be referred to as an "impurity region" or a "low resistance region".

By using the insulator 571 and / or the conductor 560 as a mask, the region 531a and the region 531b can be formed in a self-alignment manner. Therefore, the conductor 560 does not overlap with the region 531a and / or the region 531b, and the parasitic capacitance can be reduced. Further, no offset region is formed between the channel forming region and the source / drain region (region 531a or region 531b). By forming the region 531a and the region 531b in a self-alignment manner, it is possible to increase the on-current, reduce the threshold voltage, improve the operating frequency, and the like.

In addition, in order to further reduce the off-current, an offset region may be provided between the channel formation region and the source / drain region. The offset region is a region having a high electrical resistivity and is a region in which the above-mentioned impurity element is not introduced. The formation of the offset region can be realized by introducing the above-mentioned impurity element after the formation of the insulator 575. In this case, the insulator 575 also has a function as a mask like the insulator 571 and the like. Therefore, the impurity element is not introduced into the region of the metal oxide 530b overlapping with the insulator 575, and the electrical resistivity of the region can be kept high.

Further, the transistor 510D has an insulator 570, a conductor 560, a metal oxide 552, an insulator 550, and an insulator 575 on the side surface of the metal oxide 530c. The insulator 575 is preferably an insulator having a low relative permittivity. For example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or a resin. It is preferable to have. In particular, it is preferable to use silicon oxide, silicon oxide nitride, silicon nitride oxide, and silicon oxide having pores in the insulator 575 because an excess oxygen region can be easily formed in the insulator 575 in a later step. Further, silicon oxide and silicon nitride nitride are preferable because they are thermally stable. Further, the insulator 575 preferably has a function of diffusing oxygen.

Further, the transistor 510D has an insulator 574 on the insulator 575 and the metal oxide 530. The insulator 574 is preferably formed by a sputtering method. By using the sputtering method, it is possible to form an insulator having few impurities such as water or hydrogen. For example, aluminum oxide may be used as the insulator 574.

The oxide film using the sputtering method may extract hydrogen from the structure to be filmed. Therefore, the insulator 574 absorbs hydrogen and water from the oxide 230 and the insulator 575, so that the hydrogen concentration of the oxide 230 and the insulator 575 can be reduced.

<Transistor structure example 5>
A structural example of the transistor 510E will be described with reference to FIGS. 17 (A) to 17 (C). FIG. 17A is a top view of the transistor 510E. 17 (B) is a cross-sectional view of a portion shown by the alternate long and short dash line L1-L2 in FIG. 17 (A). 17 (C) is a cross-sectional view of a portion shown by the alternate long and short dash line W1-W2 in FIG. 17 (A). In the top view of FIG. 17A, some elements are omitted for the sake of clarity of the figure.

The transistor 510E is a modification of the above transistor. Therefore, in order to prevent the explanation from being repeated, the points different from the above-mentioned transistor will be mainly described.

17 (A) to 17 (C) have a region 531a and a region 531b on a part of the surface of the exposed metal oxide 530b without providing the conductor 542. One of the regions 531a and 531b functions as a source region, and the other functions as a drain region. Further, an insulator 573 is provided between the metal oxide 530b and the insulator 574.

The region 531 (region 531a and region 531b) shown in FIG. 17 is a region in which the following elements are added to the metal oxide 530b. The region 531 can be formed by using, for example, a dummy gate.

Specifically, it is preferable to provide a dummy gate on the metal oxide 530b, use the dummy gate as a mask, and add an element that lowers the resistance of the metal oxide 530b. That is, the element is added to the region where the metal oxide 530 does not overlap with the dummy gate, and the region 531 is formed. The method for adding the element includes an ion implantation method in which ionized raw material gas is added by mass separation, an ion implantation method in which ionized raw material gas is added without mass separation, a plasma immersion ion implantation method, and the like. Can be used.

Typical examples of the element that lowers the resistance of the metal oxide 530 include boron and phosphorus. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gas and the like may be used. Typical examples of noble gases include helium, neon, argon, krypton, xenon and the like. The concentration of the element may be measured by using a secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or the like.

In particular, boron and phosphorus are preferable because the equipment of the production line of amorphous silicon or low temperature polysilicon can be used. Existing equipment can be diverted and capital investment can be curtailed.

Subsequently, an insulating film to be an insulator 573 and an insulating film to be an insulator 574 may be formed on the metal oxide 530b and the dummy gate. By stacking and providing the insulating film to be the insulator 573 and the insulating film to be the insulator 574, it is possible to provide a region where the region 531 and the metal oxide 530c and the insulator 550 are overlapped with each other.

Specifically, after the insulating film to be the insulator 580 is provided on the insulating film to be the insulator 574, the insulating film to be the insulator 580 is subjected to CMP (Chemical Mechanical Exposure) treatment to obtain the insulator 580. A part of the insulating film is removed to expose the dummy gate. Subsequently, when removing the dummy gate, it is preferable to remove a part of the insulator 573 in contact with the dummy gate. Therefore, the insulator 574 and the insulator 573 are exposed on the side surface of the opening provided in the insulator 580, and a part of the region 531 provided in the metal oxide 530b is exposed on the bottom surface of the opening. Be exposed. Next, an oxide film to be a metal oxide 530c, an insulating film to be an insulator 550, and a conductive film to be a conductor 560 are sequentially formed in the opening, and then CMP treatment or the like is performed until the insulator 580 is exposed. The transistor shown in FIG. 17 can be formed by removing a part of the oxide film which becomes the metal oxide 530c, the insulating film which becomes the insulator 550, and the conductive film which becomes the conductor 560.

The insulator 573 and the insulator 574 are not essential configurations. It may be appropriately designed according to the desired transistor characteristics.

The transistor shown in FIG. 17 can be diverted from an existing device, and further, since the conductor 542 is not provided, the cost can be reduced.

This embodiment can be implemented in combination with other embodiments as appropriate.

(Embodiment 3)
In this embodiment, the configuration of the metal oxide that can be used for the OS transistor described in the above embodiment will be described.

<Composition of metal oxide>
In the present specification and the like, it may be described as CAAC (c-axis aligned composite) and CAC (Cloud-Aligned Composite). In addition, CAAC represents an example of a crystal structure, and CAC represents an example of a function or a composition of a material.

The CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function in the whole material. When CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, the conductive function is the function of flowing electrons (or holes) to be carriers, and the insulating function is the carrier. It is a function that does not allow electrons to flow. By making the conductive function and the insulating function act in a complementary manner, a switching function (on / off function) can be imparted to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carrier is flown, the carrier mainly flows in the component having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel forming region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on state of the transistor.

That is, the CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of metal oxide>
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystal linear semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide semiconductor (a-lik). OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

As the oxide semiconductor used for the semiconductor of the transistor, it is preferable to use a thin film having high crystallinity. By using the thin film, the stability or reliability of the transistor can be improved. Examples of the thin film include a thin film of a single crystal oxide semiconductor and a thin film of a polycrystalline oxide semiconductor. However, in order to form a thin film of a single crystal oxide semiconductor or a thin film of a polycrystalline oxide semiconductor on a substrate, a high temperature or laser heating step is required. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

It is reported in Non-Patent Document 2 and Non-Patent Document 3 that an In-Ga-Zn oxide (referred to as CAAC-IGZO) having a CAAC structure was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, grain boundaries are not clearly confirmed, and can be formed on a substrate at a low temperature. Furthermore, it has been reported that transistors using CAAC-IGZO have excellent electrical characteristics and reliability.

Further, in 2013, an In-Ga-Zn oxide (referred to as nc-IGZO) having an nc structure was discovered (see Non-Patent Document 4). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity in crystal orientation is observed between the different regions. There is.

Non-Patent Document 5 and Non-Patent Document 6 show changes in the average crystal size of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO thin films having low crystallinity by irradiation with an electron beam. In a thin film of IGZO having low crystallinity, crystalline IGZO of about 1 nm is observed even before irradiation with an electron beam. Therefore, it is reported here that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, it has been shown that the CAAC-IGZO thin film and the nc-IGZO thin film are more stable to electron beam irradiation than the IGZO thin film having low crystallinity. Therefore, it is preferable to use a CAAC-IGZO thin film or an nc-IGZO thin film as the semiconductor of the transistor.

CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have non-regular hexagonal shapes. Further, in the strain, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the replacement of metal elements. It is thought that this is the reason.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as a (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can also be expressed as a (In, M) layer.

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since a clear crystal grain boundary cannot be confirmed, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities, the generation of defects, etc., CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

<Transistor with oxide semiconductor>
Subsequently, a case where the oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor as a transistor, a transistor having high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

Further, the transistor using the oxide semiconductor has an extremely small leakage current in a non-conducting state, specifically, the off current per 1 μm of the channel width of the transistor is on the order of yA / μm ( ^10-24 A / μm). It is shown in Non-Patent Document 7 that there is. For example, a low power consumption CPU or the like that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is low is disclosed (see Non-Patent Document 8).

Further, it has been reported that the transistor using an oxide semiconductor has a low leakage current, and that the transistor is applied to a display device (see Non-Patent Document 9). On the display device, the displayed image is switched several tens of times per second. The number of image switchings per second is called the refresh rate. Also, the refresh rate may be called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is considered to be the cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device to reduce the number of times the image is rewritten. In addition, it is possible to reduce the power consumption of the display device by driving with a reduced refresh rate. Such a drive method is called an idling stop (IDS) drive.

Further, it is preferable to use an oxide semiconductor having a low carrier density for the transistor. When the carrier density of the oxide semiconductor film is lowered, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density. In the present specification and the like, a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, oxide semiconductors have a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^-9 /. It may be cm ³ or more.

Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

In addition, the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

<Impurities>
Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible in the oxide semiconductor, for example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ³ in SIMS, preferably 5 × 10 ¹⁸ Atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably 5 × 10 ¹⁸ atoms / cm. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

The discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of the transistor using the CAAC structure or the oxide semiconductor having the nc structure, as well as the reduction of the cost of the manufacturing process and the improvement of the throughput. Further, research on application of the transistor to a display device and an LSI utilizing the characteristic that the leakage current of the transistor is low is underway.

This embodiment can be implemented in combination with other embodiments as appropriate.

(Embodiment 4)
In the present embodiment, an electronic device to which the semiconductor device of one aspect of the present invention can be applied will be described.

<Electronic devices / systems>
The semiconductor device of one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include television devices, desktop or notebook personal chips, monitors for chips, digital signage (electronic signage), large game machines such as pachinko machines, and the like, which are relatively large. In addition to electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, mobile information terminals, sound reproduction devices, and the like can be mentioned.

The electronic device of one aspect of the present invention may have an antenna. By receiving the signal with the antenna, the display unit can display images, information, and the like. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

The electronic device of one aspect of the present invention includes sensors (force, displacement, position, speed, acceleration, angular speed, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, current flow, humidity, gradient, vibration, odor or infrared rays).

The electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like. FIG. 18 shows an example of an electronic device.

[cell phone]

FIG. 18A illustrates a mobile phone (smartphone) which is a kind of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and a button is provided in the housing 5510.

By applying the semiconductor device of one aspect of the present invention to the information terminal 5500, it can operate at high speed in a room temperature environment and can operate normally even in a high temperature environment.

[Information terminal 1]
FIG. 18B illustrates the desktop information terminal 5300. The desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

By applying the semiconductor device of one aspect of the present invention to the desktop information terminal 5300, it can operate at high speed in a room temperature environment and can operate normally even in a high temperature environment.

In the above description, smartphones and desktop information terminals are taken as examples as electronic devices, and although they are shown in FIGS. 18A and 18B, respectively, information terminals other than smartphones and desktop information terminals can be applied. can. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[Information terminal 2]
FIG. 18C shows a tablet-type information terminal 5000. The tablet-type information terminal 5000 has a housing 5002 and a display unit 5001, and as an input interface, a touch panel is provided in the display unit 5001 and a button is provided in the housing 5002.

By applying the semiconductor device of one aspect of the present invention to the tablet-type information terminal 5000, it can operate at high speed in a room temperature environment and can operate normally even in a high temperature environment.

The tablet-type information terminal 5000 can be held in the central portion of the controller 5010. By using the controller 5010, the tablet-type information terminal 5000 can accept more precise and high-speed operations than the touch panel. As a result, the tablet-type information terminal 5000 can be used as a portable game machine.

Further, the controller 5010 may have one or more of the above-mentioned sensors. Further, the controller 5010 can be connected by wire or wirelessly even when the tablet type information terminal 5000 is not held.

Further, the tablet type information terminal 5000 can be held in the cradle 5020. The cradle 5020 has a function of charging the tablet-type information terminal 5000 and its accessories, a function of outputting output data (for example, video data, audio data, text data, etc.) of the tablet-type information terminal 5000, and an input device (for example,). A function to connect to a mouse, keyboard, recording media drive, controller 5010, etc.) and transmit input data to the tablet-type information terminal 5000, or a function to electrically connect the tablet-type information terminal 5000 to a communication line by wire or wirelessly. Have at least one.

By using such a cradle 5020, the tablet-type information terminal 5000 can be used as a personal computer, a workstation, or a stationary game machine.

Further, the cradle 5020 may have a GPU chip, main memory, storage, or the like. By having these, for example, the video data output from the tablet-type information terminal 5000 can be up-converted.

[Stationary game console]
FIG. 18D shows a stationary game machine 5100, which is an example of a game machine. The stationary game machine 5100 has a game machine main body 5101, a controller 5102 that can be connected wirelessly or by wire, and the like.

By applying the semiconductor device of one aspect of the present invention to the stationary game machine 5100, it can operate at high speed in a room temperature environment and can operate normally even in a high temperature environment.

[Handheld game console]
FIG. 18E shows a portable game machine 5200, which is an example of a game machine. The portable game machine has a housing 5201, a display unit 5202, a button 5203, and the like.

By applying the semiconductor device of one aspect of the present invention to the portable game machine 5200, it can operate at high speed in a room temperature environment and can operate normally even in a high temperature environment.

In the above, a stationary game machine and a portable game machine are illustrated as an example of the game machine, but the game machine to which the semiconductor device of one aspect of the present invention is applied is not limited to this. Examples of the game machine to which the semiconductor device of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a throwing machine for batting practice installed in a sports facility, and the like. Can be mentioned.

[electric appliances]
FIG. 19A shows an electric freezer / refrigerator 5800, which is an example of an electric appliance. The electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

By applying the semiconductor device of one aspect of the present invention to the electric freezer / refrigerator 5800, it can operate at high speed in a room temperature environment and can operate normally even in a high temperature environment.

In this example, an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an microwave oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Examples include appliances, washing machines, dryers, audiovisual equipment, and the like.

[Mobile]
The semiconductor device of one aspect of the present invention can be applied to an automobile which is a moving body and around the driver's seat of the automobile.

FIG. 19 (B1) shows an automobile 5700 which is an example of a moving body, and FIG. 19 (B2) is a diagram showing the periphery of a windshield in the interior of an automobile. FIG. 19B1 illustrates the display panel 5701, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar, which are attached to the dashboard.

The display panel 5701 to the display panel 5703 can provide various other information such as a speedometer, a tachometer, a mileage, a refueling amount, a gear state, and an air conditioner setting. In addition, the display items, layout, and the like displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panel 5701 to 5703 can also be used as a lighting device.

The display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an image pickup device (not shown) provided in the automobile 5700. That is, by displaying the image from the image pickup device provided on the outside of the automobile 5700, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, it is possible to confirm safety more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

By applying the semiconductor device of one aspect of the present invention to the automobile 5700, it can operate at high speed in a room temperature environment and can operate normally even in a high temperature environment.

In the above description, the automobile is described as an example of the moving body, but the moving body is not limited to the automobile. For example, examples of moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, it is possible to provide a system using artificial intelligence.

<Parallel computer>
A parallel computer can be configured by forming a cluster using a plurality of computers having the semiconductor device of one aspect of the present invention. The parallel computer operates at high speed in a room temperature environment and can operate normally even in a high temperature environment.

FIG. 20A illustrates a large parallel computer 5400. In the parallel computer 5400, a plurality of rack-mounted computers 5420 are stored in the rack 5410.

The computer 5420 may have, for example, the configuration of the perspective view shown in FIG. 20 (B). In FIG. 20B, the computer 5420 has a motherboard 5430, which has a plurality of slots 5431, a plurality of connection terminals 5432, and a plurality of connection terminals 5433. A PC card 5421 is inserted in the slot 5431. In addition, the PC card 5421 has a connection terminal 5423, a connection terminal 5424, and a connection terminal 5425, each of which is connected to the motherboard 5430.

The PC card 5421 is a processing board provided with a semiconductor device or the like according to one aspect of the present invention. For example, in FIG. 20C, the PC card 5421 has a board 5422, and the board 5422 has a connection terminal 5423, a connection terminal 5424, a connection terminal 5425, a chip 5426, a chip 5427, and a connection terminal 5428. The configuration having is shown. Although chips other than the chip 5426 and the chip 5427 are shown in FIG. 20 (C), the description of the chip 5426 and the chip 5427 described below will be taken into consideration for these chips.

The connection terminal 5428 has a shape that can be inserted into the slot 5431 of the motherboard 5430, and the connection terminal 5428 functions as an interface for connecting the PC card 5421 and the motherboard 5430. Examples of the standard of the connection terminal 5428 include PCIe and the like.

The connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 can be, for example, an interface for supplying power to the PC card 5421, inputting a signal, or the like. Further, for example, it can be an interface for outputting a signal calculated by the PC card 5421 and the like. Examples of the standards of the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), and the like. When a video signal is output from the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425, HDMI (registered trademark) and the like can be mentioned as the respective standards.

The chip 5426 has a terminal (not shown) for inputting / outputting signals, and by inserting the terminal into a socket (not shown) included in the PC card 5421, the chip 5426 and the PC card 5421 can be combined. Can be electrically connected. The chip 5426 can be, for example, the GPU of one aspect of the present invention.

The chip 5427 has a plurality of terminals, and the chip 5427 and the PC card 5421 are electrically connected to the wiring provided by the PC card 5421 by, for example, reflow soldering. can do. Examples of the chip 5427 include a storage device, an FPGA (Field Programmable Gate Array), a CPU, and the like.

This embodiment can be implemented in combination with other embodiments as appropriate.

In this embodiment, the result of simulating the semiconductor device of one aspect of the present invention will be described.

21 (A) and 21 (B) are circuit diagrams showing the configuration of the semiconductor device on which the simulation was performed. The semiconductor device having the configuration shown in FIG. 21 (A) includes an input terminal IN, an output terminal OUTa, an output terminal OUTb, a charge transfer switch 20, a charge transfer switch 30, a capacitive element group 50, and a capacitive element group 60. A clock signal generation circuit 11, a capacitive element 12a, and a capacitive element 12b. The charge transfer switch 20 has a transistor 21 [1] to a transistor 21 [5]. The charge transfer switch 30 has a transistor 31 [1] to a transistor 31 [5]. The capacitive element group 50 has a capacitive element 51 [1] to a capacitive element 51 [4]. The capacitive element group 60 has a capacitive element 61 [1] to a capacitive element 61 [4].

In the semiconductor device having the configuration shown in FIG. 21A, the source of the transistor 21 [1] and the source of the transistor 31 are electrically connected to the input terminal IN.

One electrode of the capacitive element 51 [1] is electrically connected to the gate and drain of the transistor 21 [1] and the source of the transistor 21 [2]. One electrode of the capacitive element 51 [2] is electrically connected to the gate and drain of the transistor 21 [2] and the source of the transistor 21 [3]. One electrode of the capacitive element 51 [3] is electrically connected to the gate and drain of the transistor 21 [3] and the source of the transistor 21 [4]. One electrode of the capacitive element 51 [4] is electrically connected to the gate and drain of the transistor 21 [4] and the source of the transistor 21 [5].

One electrode of the capacitive element 61 [1] is electrically connected to the gate and drain of the transistor 31 [1] and the source of the transistor 31 [2]. One electrode of the capacitive element 61 [2] is electrically connected to the gate and drain of the transistor 31 [2] and the source of the transistor 31 [3]. One electrode of the capacitive element 61 [3] is electrically connected to the gate and drain of the transistor 31 [3] and the source of the transistor 31 [4]. One electrode of the capacitive element 61 [4] is electrically connected to the gate and drain of the transistor 31 [4] and the source of the transistor 31 [5].

The gate and drain of the transistor 21 [5] are electrically connected to the output terminal OUTa. The output terminal OUTa is electrically connected to one of the electrodes of the capacitive element 12a. The gate and drain of the transistor 31 [5] are electrically connected to the output terminal OUTb. The output terminal OUTb is electrically connected to one of the electrodes of the capacitive element 12b.

That is, in the semiconductor device having the configuration shown in FIG. 21, the output terminal of the charge transfer switch 20 and the output terminal of the charge transfer switch 30 are not electrically connected from the semiconductor device 10 having the configuration shown in FIG. 5 (A). It can be said that it is a separate configuration. Further, the configuration of the semiconductor device shown in FIG. 21B is the same as the configuration of the semiconductor device 10 shown in FIG. 5A.

In the semiconductor device having the configuration shown in FIGS. 21 (A) and 21 (B), the transistor 21 [1] to the transistor 21 [5] are designated as a Si transistor, and the transistor 31 [1] to the transistor 31 [5] are designated as an OS transistor. The channel length of the transistors 21 [1] to 21 [5] is 0.48 μm and the channel width is 0.36 μm, the channel length of the transistors 31 [1] to 31 [5] is 0.36 μm, and the channel width is 0. It was set to .36 μm. Further, the capacitance of the capacitive element 51 [1] to the capacitive element 51 [4] and the capacitive element 61 [1] to the capacitive element 61 [4] is set to 1 pF, and the capacitance of the capacitive element 12a, the capacitive element 12b, and the capacitive element 12 is set to 1 pF. Was 2 pF.

In this embodiment, when the ground potential is supplied to the input terminal IN as the potential VSS, the changes over time of the potentials of the output terminal OUTa, the output terminal OUTb, and the output terminal OUT are calculated by simulation. Here, the temperature of the semiconductor device was set to 27 ° C. FIG. 22A is a diagram showing simulation results of changes in potentials of the output terminal OUTa and the output terminal OUTb with time. FIG. 22B is a diagram showing a simulation result of a time-dependent change in the potential of the output terminal OUT.

As shown in FIG. 22A, it was confirmed that the potential of the output terminal OUTa was lower than the potential of the output terminal OUTb. Further, as shown in FIG. 22B, it was confirmed that the potential of the output terminal OUT is the potential of the output terminal OUTa, which is the lower potential of the potential of the output terminal OUTa and the potential of the output terminal OUTb. Was done.

10 Semiconductor device 11 Clock signal generation circuit 12 Capacitive element 12a Capacitive element 12b Capacitive element 20 Charge transfer switch 21 Transistor 22 Transistor 30 Charge transfer switch 31 Transistor 32 Transistor 40 Capacitive element group 41 Capacitive element 50 Capacitive element group 51 Capacitive element 60 Capacitive element Group 61 Capacitive element 70 Substrate 71 p + Region 72an n-type well 72b n-type well 72c n-type well 73a n-type well 73b n-type well 74 p-type well 75an + region 75b n + region 75c n + region 76 p + region 77 n + region 78 n + Area 80 Insulator 81 Conductor 90 n-type well 91 n + Area 92 p + Area 93 p + Area 200 Cellular array 201 Potential generator 202 Control unit 204 Sense amplifier circuit 205 Driver 206 Main amplifier 207 Input / output circuit 208 Peripheral circuit 209 Memory cell 210 Storage Device 230 Oxide 320 Insulator 322 Insulator 324 Insulator 326 Insulator 328 Insulator 330 Conductor 350 Insulator 352 Insulator 354 Insulator 356 Insulator 360 Insulator 362 Insulator 364 Insulator 366 Insulator 376 Insulator 372 Insulator 374 Insulator 376 Conductor 380 Insulator 382 Insulator 384 Insulator 386 Conductor 503 Conductor 503a Conductor 503b Conductor 505 Conductor 505a Conductor 505b Conductor 510 Insulator 510A Transistor 510B Transistor 510C Transistor 510D Transistor 511 Insulator 512 Insulator 514 Insulator 516 Insulator 518 Conductor 520 Insulator 521 Insulator 522 Insulator 524 Insulator 530 Metal Oxide 530a Metal Oxide 530b Metal Oxide 530c Metal Oxide 531 Region 531a Region 531b Region 541 Conductor 542 Conductor 542a Conductor 542b Conductor 543 Region 543a Region 543b Region 544 Insulator 545 Insulator 546 Conductor 546a Conductor 546b Conductor 547 Conductor 547a Conductor 547b Conductor 548 Conductor 555 Metallic Oxide 560 Conductor 560a Conductor 560b Conductor 570 Insulator 571 Insulator 573 Insulator 574 Insulator 575 Insulator 576 Insulator 576a Insulator 576a Insulator 576b Insulator 580 Insulator 5 81 Insulator 582 Insulator 584 Insulator 586 Insulator 610 Conductor 612 Conductor 614 Conductor 620 Conductor 622 Conductor 624 Conductor 626 Conductor 628 Conductor 650 Insulator 5000 Tablet-type information terminal 5001 Display 5002 Housing 5010 Controller 5020 Cradle 5100 Type Game Machine 5101 Game Machine Main Body 5102 Controller 5200 Portable Game Machine 5201 Housing 5202 Display 5203 Button 5300 Desktop Information Terminal 5301 Main Body 5302 Display 5303 Keyboard 5400 Parallel Computer 5410 Rack 5420 Computer 5421 PC Card 5422 Board 5423 connection terminal 5424 connection terminal 5425 connection terminal 5426 chip 5427 chip 5428 connection terminal 5430 motherboard 5431 slot 5432 connection terminal 5433 connection terminal 5500 information terminal 5510 housing 511 display unit 5700 automobile 5701 display panel 5702 display panel 5703 display panel 5800 display panel 5800 Electric Refrigerator / Refrigerator 5801 Housing 5802 Refrigerator Door 5803 Freezer Door

Claims (4)

A semiconductor device having an input terminal and an output terminal and having a function of outputting a potential lower than the potential input to the input terminal from the output terminal.
The semiconductor device includes a first charge transfer switch, a second charge transfer switch, and a pumping capacitor.
The first charge transfer switch has a plurality of first transistors having silicon in the channel forming region.
The second charge transfer switch has a plurality of second transistors having a metal oxide in the channel forming region.
The input terminal is electrically connected to the first charge transfer switch and the second charge transfer switch.
The output terminal is electrically connected to the first charge transfer switch and the second charge transfer switch.
A semiconductor device, wherein one electrode of the pumping capacitor is electrically connected to the first charge transfer switch and the second charge transfer switch. In claim 1,
A semiconductor device characterized in that all the transistors included in the second charge transfer switch have a metal oxide in a channel forming region . A semiconductor device having an input terminal and an output terminal and having a function of outputting a potential lower than the potential input to the input terminal from the output terminal.
The semiconductor device includes a first charge transfer switch, a second charge transfer switch, and a pumping capacitor.
The first charge transfer switch has a plurality of first transistors having silicon in the channel forming region.
The first charge transfer switch has one second transistor having a metal oxide in the channel forming region.
The second charge transfer switch has a plurality of third transistors having a metal oxide in the channel forming region .
All the transistors of the second charge transfer switch have a metal oxide in the channel forming region .
The input terminal is electrically connected to the first charge transfer switch and the second charge transfer switch.
The output terminal is electrically connected to one of the source and drain of the second transistor.
The output terminal is electrically connected to the second charge transfer switch.
A semiconductor device, wherein one electrode of the pumping capacitor is electrically connected to the first charge transfer switch and the second charge transfer switch. In any one of claims 1 to 3,
The first transistor is a semiconductor device characterized by being a p-channel type transistor.

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