JP2020017327A - Storage device, semiconductor device, and electronic apparatus - Google Patents

Abstract

To provide a storage device having a gain-cell type memory cell and capable of storing large amounts of data per unit area.SOLUTION: A memory cell included in a storage device comprises a plurality of write transistors and read transistors, and a precharge transistor. The plurality of write transistors are connected to each other in series. Data is stored by accumulating electric charge in capacity of nodes in which the write transistors are connected and nodes in which the gates of the write transistors and the gates of the read transistors are connected. Since the write transistors and the precharge transistor have metal oxide in channel formation areas and very small off-state current, the capacity can be reduced.SELECTED DRAWING: Figure 4

Description

One embodiment of the present invention relates to a storage device. In particular, the present invention relates to a memory device that can function by utilizing semiconductor characteristics.

One embodiment of the present invention relates to a semiconductor device. In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including the integrated circuit, an electronic component including the chip in a package, and an electronic device including the integrated circuit are examples of the semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacturer, or a composition (composition of matter).

A DRAM (Dynamic Random Access Memory) is widely used as a storage device (also referred to as a memory) built in various electronic devices. A memory cell of a DRAM includes one transistor and one capacitor, and the DRAM is a memory that stores data by accumulating charges in the capacitor.

The memory cell of the DRAM may be composed of two transistors and one capacitor. By amplifying the accumulated charge by a nearby transistor, operation as a memory can be performed even when the capacitance of the capacitor is small (hereinafter, referred to as a gain cell type memory cell).

On the other hand, a transistor including a metal oxide in a channel formation region (also referred to as an oxide semiconductor transistor or an OS transistor) has attracted attention in recent years. Since the OS transistor has extremely low drain current (also referred to as off-state current) when the transistor is in an off state, by using the OS transistor for a memory cell of a DRAM, electric charge accumulated in a capacitor can be held for a long time. .

In addition, since the OS transistor is a thin film transistor, the OS transistor can be stacked. For example, a first circuit can be formed using a Si transistor formed over a single crystal silicon substrate, and a second circuit can be formed above the first circuit using an OS transistor. By using an OS transistor in a DRAM, for example, a peripheral circuit such as a driver circuit or a control circuit can be formed as a first circuit, and a memory cell can be formed as a second circuit, so that the chip area of the DRAM can be reduced. .

Patent Literature 1 discloses an example of a semiconductor device having a plurality of memory cells using OS transistors over a semiconductor substrate including a peripheral circuit. Patent Document 2 discloses an example in which an OS transistor and a transistor other than the OS transistor (for example, a Si transistor) are used for a gain cell type memory cell (capacitance element may be omitted).

Note that in this specification and the like, a semiconductor device including a gain cell memory cell using an OS transistor is referred to as a NOSRAM (registered trademark, Nonvolatile Oxide Semiconductor Random Access Memory). A semiconductor device including a memory cell, a NOSRAM, a semiconductor device including a peripheral circuit and a plurality of memory cells, and the like are hereinafter referred to as a storage device or a memory.

In addition, regarding an oxide semiconductor (also referred to as oxide semiconductor), for example, not only a single metal oxide such as indium oxide and zinc oxide but also a multimetal oxide is known. Among oxides of multi-component metals, research on In-Ga-Zn oxide (also referred to as IGZO) has been actively conducted.

Through research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline line) structure, which are neither single crystal nor amorphous, have been found in oxide semiconductors (Non-Patent Documents 1 to 3). reference).

Non-Patent Documents 1 and 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Further, Non-Patent Documents 4 and 5 show that even an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure has minute crystals.

Non-Patent Document 6 reports that the off-state current of a transistor including an oxide semiconductor is extremely small, and Non-Patent Documents 7 and 8 use an LSI and a transistor utilizing the property of an extremely small off-state current. Display has been reported.

JP 2012-256820 A JP 2012-256400 A

S. Yamazaki et al. , "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. , "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. , "The Procedures of AM-FPD'13 Digest of Technical Papers", 2013, p. 151-154 S. Yamazaki et al. , "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, "ECS Transactions", 2014, volume 64, issue 10, p. 155-164 K. Kato et al. , “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217 S. Amano et al. , "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p. 626-629

In a DRAM, a memory cell of a gain cell type can amplify accumulated charge by a nearby transistor, so that the capacitance of a capacitor can be reduced. Alternatively, it is not necessary to form a capacitor by using a gate capacitance of a transistor, a parasitic capacitance of a wiring, or the like (the capacitor may be omitted).

However, the gain cell type memory cell requires at least two transistors per memory cell, and has a problem that it is difficult to increase the number of memory cells that can be arranged per unit area (arrangement density). That is, there is a problem that it is difficult to increase the storage density (the amount of data that can be stored per unit area) of the storage device by increasing the arrangement density of the memory cells.

An object of one embodiment of the present invention is to provide a storage device having a gain cell type memory cell, which has a large amount of data that can be stored per unit area. Another object of one embodiment of the present invention is to provide an electronic device including a memory device having a gain cell type memory cell and having a large amount of data that can be stored per unit area.

Note that one embodiment of the present invention does not necessarily need to solve all of the above problems, and it is sufficient that at least one of the problems can be solved. Further, the above description of the object does not disturb the existence of other objects. Problems other than these are obvious from the description of the specification, claims, drawings, etc., and it is possible to extract other problems from the description of the specification, claims, drawings, etc. It is possible.

One embodiment of the present invention is a semiconductor device including first to k-th write word lines (k is an integer of 2 or more), a read word line, a precharge line, a write bit line, a read bit line, and k write transistors. , A read transistor, and a precharge transistor. One of a source and a drain of the first write transistor is electrically connected to a gate of the read transistor and one of a source and a drain of the precharge transistor, and is connected to a first (1 is an integer of 2 to k) write transistor. One of the source and the drain is electrically connected to the other of the source and the drain of the (1-1) th writing transistor, and the other of the source and the drain of the k-th writing transistor is electrically connected to the writing bit line. The gate of the first write transistor is electrically connected to the first write word line, and the gate of the first write transistor is electrically connected to the first write word line. One of a source and a drain of the read transistor is electrically connected to a read word line, and the other of the source and the drain of the read transistor is electrically connected to a read bit line. The gate of the precharge transistor is electrically connected to a precharge line, and the other of the source and the drain of the precharge transistor is electrically connected to a wiring to which a predetermined potential is supplied.

In the above embodiment, the first to k-th write transistors and the precharge transistor each include a metal oxide in a channel formation region.

In the above embodiment, the first to k-th write transistors, the precharge transistor, and the read transistor each include a metal oxide in a channel formation region.

Another embodiment of the present invention is a storage device including a memory cell array and a peripheral circuit. The memory cell array includes m × n memory cells (m and n are integers of 1 or more), m first to k-th write word lines (k is an integer of 2 or more), and m read words, respectively. It has lines, m precharge lines, n write bit lines, and n read bit lines. The m × n memory cells are arranged in a matrix, and each of the memory cells is electrically connected to a first to a k-th write word line, a read word line, a precharge line, a write bit line, and a read bit line. , And each of the memory cells has k write transistors, read transistors, and precharge transistors. One of a source and a drain of the first write transistor is electrically connected to a gate of the read transistor and one of a source and a drain of the precharge transistor, and is connected to a first (1 is an integer of 2 to k) write transistor. One of the source and the drain is electrically connected to the other of the source and the drain of the (1-1) th writing transistor, and the other of the source and the drain of the k-th writing transistor is electrically connected to the writing bit line. The gate of the first write transistor is electrically connected to the first write word line, and the gate of the first write transistor is electrically connected to the first write word line. One of a source and a drain of the read transistor is electrically connected to a read word line, and the other of the source and the drain of the read transistor is electrically connected to a read bit line. The gate of the precharge transistor is electrically connected to a precharge line, and the other of the source and the drain of the precharge transistor is electrically connected to a wiring to which a predetermined potential is supplied. The peripheral circuit has a first circuit, a second circuit, and a controller, the first circuit is electrically connected to a write bit line and a read bit line, and the first circuit writes data to a memory cell It has a function and a function of reading data from a memory cell. The second circuit is electrically connected to the first to k-th write word lines, read word lines, and precharge lines, and the second circuit is connected to the first to k-th write word lines, read word lines, and The controller has a function of driving the precharge line, and the controller has a function of controlling the first circuit and the second circuit.

In the above embodiment, the first to k-th write transistors and the precharge transistor each include a metal oxide in a channel formation region.

In the above embodiment, the first to k-th write transistors, the precharge transistor, and the read transistor each include a metal oxide in a channel formation region.

In the above embodiment, the first circuit, the second circuit, and the controller have transistors formed on the semiconductor substrate, and the first to k-th write transistors and the precharge transistor are respectively located above the semiconductor substrate. Characterized in that they are formed by laminating them.

In the above embodiment, the first circuit, the second circuit, and the controller each include a transistor formed on a semiconductor substrate, and the first to k-th write transistors, the precharge transistor, and the read transistor each include a semiconductor. It is characterized in that it is formed by being stacked above a substrate.

According to one embodiment of the present invention, a storage device having a large amount of data per unit area can be provided in a storage device including a gain cell memory cell. Alternatively, according to one embodiment of the present invention, an electronic device including a memory device including a gain cell memory cell and having a large amount of data that can be stored per unit area can be provided.

Note that the description of these effects does not disturb the existence of other effects. Further, one embodiment of the present invention does not necessarily need to have all of these effects. The effects other than these are obvious from the description of the specification, claims, drawings, etc., and extracting other effects from the description, the claims, drawings, etc. Is possible.

FIG. 3 is a schematic perspective view illustrating a configuration example of a storage device. FIG. 3 is a block diagram illustrating a configuration example of a storage device. FIG. 3 is a diagram illustrating a configuration example of a memory cell array. FIGS. 3A and 3B are circuit diagrams each illustrating a configuration example of a memory cell. FIGS. Timing chart. FIGS. 3A and 3B are circuit diagrams each illustrating a configuration example of a memory cell. FIGS. FIG. 3 is a circuit diagram illustrating a configuration example of a memory cell. FIG. 4 is a diagram illustrating a configuration example of a circuit included in a bit line driver circuit. FIG. 3 is a block diagram illustrating a configuration example of a storage device. FIG. 3 is a cross-sectional view illustrating a configuration example of a semiconductor device. 3A to 3C are cross-sectional views illustrating a structure example of a transistor. FIG. 13 is a cross-sectional view illustrating a structure example of a transistor. 3A is a top view illustrating a structure example of a transistor, and FIG. 3B is a cross-sectional view illustrating a structure example of a transistor. 3A is a top view illustrating a structure example of a transistor, and FIG. 3B is a cross-sectional view illustrating a structure example of a transistor. 3A is a top view illustrating a structure example of a transistor, and FIG. 3B is a cross-sectional view illustrating a structure example of a transistor. 3A is a top view illustrating a structure example of a transistor, and FIG. 3B is a cross-sectional view illustrating a structure example of a transistor. 3A is a top view illustrating a structure example of a transistor, and FIG. 3B is a cross-sectional view illustrating a structure example of a transistor. 3A is a top view illustrating a structural example of a transistor, and FIG. 3B is a perspective view illustrating a structural example of a transistor. 3A and 3B are cross-sectional views illustrating a structure example of a transistor. 4A and 4B are cross-sectional views of a transistor and FIGS. 4B and 4D are diagrams illustrating electric characteristics of the transistor. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device. FIG. 9 illustrates a configuration example of an electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiment can be implemented in many different forms, and that the form and details can be variously changed without departing from the spirit and scope. You. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Further, a plurality of embodiments described below can be appropriately combined. In the case where a plurality of configuration examples are described in one embodiment, the configuration examples can be combined with each other as appropriate.

Note that, in the drawings attached to this specification, components are classified by function and block diagrams are shown as blocks independent of each other. However, it is difficult to completely separate actual components by function, and one A component may be responsible for more than one function.

In the drawings and the like, the size, the layer thickness, the region, and the like are exaggerated in some cases for clarity. Therefore, it is not necessarily limited to the scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.

In the drawings and the like, the same element or an element having a similar function, an element of the same material, an element formed at the same time, or the like may be denoted by the same reference numeral, and a repeated description thereof may be omitted. is there.

In this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, in some cases, the term “conductive layer” can be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

Further, in this specification and the like, a term indicating an arrangement such as “above” or “below” does not limit that the positional relationship between components is “directly above” or “directly below”. For example, the expression “a gate electrode over a gate insulating layer” does not exclude the case where another component is included between the gate insulating layer and the gate electrode.

Further, in this specification and the like, ordinal numbers such as “first”, “second”, and “third” are given in order to avoid confusion of components, and are not limited in number.

In this specification and the like, the term "electrically connected" includes the case where components are connected through an "object having any electric function". Here, there is no particular limitation on the “something having an electrical action” as long as it allows transmission and reception of an electric signal between connection targets. For example, the "object having any electric function" includes a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements having various functions, including an electrode and a wiring.

In this specification and the like, “voltage” often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential). Therefore, the voltage and the potential difference can be rephrased.

In this specification and the like, a transistor is an element having at least three terminals, including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and the source and the drain are connected to each other through the channel formation region. A current can flow between them. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.

In addition, the functions of the source and the drain may be switched when transistors with different polarities are used or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms of source and drain can be used interchangeably.

In this specification and the like, unless otherwise specified, an off-state current refers to a drain current when a transistor is in an off state (also referred to as a non-conductive state or a cut-off state). Unless otherwise specified, the off state refers to a state in which a gate voltage Vgs with respect to a source is lower than a threshold voltage Vth in an n-channel transistor, and a threshold voltage Vgs with respect to a source in a p-channel transistor. The state is higher than the voltage Vth. That is, the off-state current of an n-channel transistor may be a drain current when the voltage Vgs of the gate with respect to the source is lower than the threshold voltage Vth.

In the description of the off-state current, a drain may be read as a source. That is, the off-state current sometimes refers to a source current when the transistor is in an off state. Further, the term “leak current” may have the same meaning as the off-state current. In this specification and the like, off-state current sometimes refers to current flowing between a source and a drain when a transistor is off.

In this specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like.

For example, in the case where a metal oxide is used for a channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. That is, a transistor including a metal oxide in a channel formation region can be referred to as an "oxide semiconductor transistor" or an "OS transistor." Similarly, the above-described “transistor using an oxide semiconductor” is a transistor including a metal oxide in a channel formation region.

In this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as metal oxynitride. Details of the metal oxide will be described later.

(Embodiment 1)
In this embodiment, an example of a structure of a storage device according to one embodiment of the present invention will be described. A storage device according to one embodiment of the present invention is a storage device that can function by utilizing semiconductor characteristics and is also called a memory. Further, a memory device according to one embodiment of the present invention has a structure in which memory cells each including an OS transistor are stacked over a semiconductor substrate over which a peripheral circuit is formed.

<Schematic schematic diagram of storage device>
FIG. 1 is a schematic perspective view illustrating a configuration example of a storage device 100 according to one embodiment of the present invention.

The memory device 100 includes a layer 101 and a layer 201, and has a structure in which the layer 201 is stacked over the layer 101. The layers 101 and 201 each include a circuit which can function by utilizing semiconductor characteristics. The layer 101 includes a peripheral circuit 110, and the layer 201 includes a memory cell array 210. . In the drawings described in this specification and the like, main signal flows are indicated by arrows or lines, and power supply lines and the like may be omitted.

The peripheral circuit 110 has a row decoder 121, a word line driver circuit 122, a column decoder 131, a bit line driver circuit 132, a page buffer 138, an output circuit 140, and a control logic circuit 160. Note that the peripheral circuit 110 has a function as a drive circuit and a control circuit of the memory cell array 210.

The peripheral circuit 110 is configured using a transistor formed on the semiconductor substrate SUB. The semiconductor substrate SUB is not particularly limited as long as a channel region of a transistor can be formed. For example, a single crystal silicon substrate, a single crystal germanium substrate, a compound semiconductor substrate (eg, a SiC substrate, a GaN substrate), an SOI (Silicon on Insulator) substrate, or the like can be used.

In addition, as an SOI substrate, oxygen ions were implanted into a mirror-polished wafer and then heated to a high temperature to form an oxide layer at a certain depth from the surface and to eliminate defects generated in the surface layer. A SIMOX (Separation by Implanted Oxygen) substrate, a smart cut method in which a semiconductor substrate is cleaved using growth by heat treatment of microvoids formed by hydrogen ion implantation, an ELTRAN method (registered trademark: Epitaxial Layer Transfer), or the like is used. The formed SOI substrate may be used. A transistor formed using a single crystal substrate has a single crystal semiconductor in a channel formation region.

In this embodiment, a case where a single crystal silicon substrate is used as the semiconductor substrate SUB will be described. A transistor formed over a single crystal silicon substrate is called a Si transistor. The peripheral circuit 110 including the Si transistor can operate at high speed.

The memory cell array 210 has a plurality of memory cells 211, and the memory cells 211 are configured using OS transistors. Since the OS transistor is a thin film transistor, the memory cell array 210 can be provided over the semiconductor substrate SUB.

Here, the band gap of the oxide semiconductor is 2.5 eV or more, preferably 3.0 eV or more; therefore, the OS transistor has low leakage current due to thermal excitation and extremely low off-state current. Note that off-state current refers to current which flows between a source and a drain when a transistor is off.

The metal oxide used for the channel formation region of the OS transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). A typical example of such an oxide semiconductor is an In-M-Zn oxide (element M is, for example, Al, Ga, Y, or Sn). The oxide semiconductor can be made i-type (intrinsic) or substantially i-type by reducing impurities such as moisture and hydrogen serving as electron donors (donors) and reducing oxygen vacancies. Such an oxide semiconductor can be referred to as a highly purified oxide semiconductor. Note that details of the OS transistor are described in Embodiment 4.

The memory cell 211 has a function of storing data by accumulating and holding electric charge. The memory cell 211 may have a function of storing binary (high-level or low-level) data, or may have a function of storing quaternary or more data. Alternatively, it may have a function of storing analog data.

The OS transistor is suitable as a transistor used for the memory cell 211 because the off-state current is extremely small. For example, the OS transistor can have an off-state current per 1 μm of channel width of 100 zA / μm or less, 10 zA / μm or less, 1 zA / μm or less, or 10 yA / μm or less. By using the OS transistor for the memory cell 211, data stored in the memory cell 211 can be held for a long time.

Since the OS transistor has a feature in which the off-state current does not easily increase even at a high temperature, the memory device 100 can operate even when the temperature of an environment where the OS transistor is installed is high. In addition, even at a high temperature due to heat generated by the peripheral circuit 110, data stored in the memory cell 211 is unlikely to be lost. With the use of the OS transistor, the reliability of the storage device 100 can be improved.

Alternatively, as the transistor used for the memory cell 211, a transistor other than the OS transistor may be used as long as the off-state current is low. For example, a transistor including a semiconductor with a large band gap in a channel formation region may be used. A semiconductor having a large band gap may refer to a semiconductor having a band gap of 2.2 eV or more, and examples thereof include silicon carbide, gallium nitride, and diamond.

As shown in FIG. 1, in the memory cell array 210, the memory cells 211 are arranged in a matrix (also referred to as a matrix), and each memory cell 211 is connected to a wiring WL and a wiring BL. The memory cell 211 is selected by a potential applied to the wiring WL, and data is written to the selected memory cell 211 through the wiring BL. Alternatively, the memory cell 211 is selected by a potential applied to the wiring WL, and data is read from the selected memory cell 211 through the wiring BL.

That is, the wiring WL has a function as a word line of the memory cell 211, and the wiring BL has a function as a bit line of the memory cell 211. Although not shown in FIG. 1, the wiring WL includes a write word line wl, a read word line rwl, and a precharge line prl, and the wiring BL includes a write bit line wbl and a read bit line rbl (see FIG. 2). As will be described later, the write word line wl is composed of write word lines wl1 to wlk (k is an integer of 2 or more).

<Block diagram of storage device>
FIG. 2 is a block diagram illustrating a configuration example of the storage device 100.

The storage device 100 includes a peripheral circuit 110 and a memory cell array 210. The peripheral circuit 110 has a row decoder 121, a word line driver circuit 122, a column decoder 131, a bit line driver circuit 132, a page buffer 138, an output circuit 140, and a control logic circuit 160. The memory cell array 210 includes a memory cell 211, a write word line wl, a read word line rwl, a precharge line prl, a write bit line wbl, and a read bit line rbl.

The potential Vss, the potential Vdd, the potential Vdh, the precharge potential Vpre, and the reference potential Vref are input to the storage device 100. The potential Vdh is a high power supply potential of the word line wl.

A clock signal CLK, a chip enable signal CE, a global write enable signal GW, a byte write enable signal BW, an address signal ADDR, and a data signal WDATA are input to the storage device 100, and the storage device 100 outputs a data signal RDATA I do. Note that these signals are digital signals represented by a high level or a low level (in some cases, represented by High or Low, H or L, 1 or 0, or the like).

Note that in this embodiment, the high level of the digital signal is represented using the potential Vdd, and the low level is represented using the potential Vss. The potential Vdh is used for the high level of the word line wl, and the potential Vss is used for the low level of the word line wl. The byte write enable signal BW, the address signal ADDR, the data signal WDATA, and the data signal RDATA are signals having a plurality of bits.

In this specification and the like, when a byte write enable signal BW has four bits with respect to a signal having a plurality of bits, for example, it is described as a byte write enable signal BW [3: 0]. This means that the byte write enable signal has BW [0] to BW [3], and when it is necessary to specify one bit, it is expressed as, for example, the byte write enable signal BW [0]. In addition, when expressed as a byte write enable signal BW, it indicates an arbitrary bit.

For example, the byte write enable signal BW can be 4 bits, and the data signal WDATA and the data signal RDATA can be 32 bits. That is, the byte write enable signal BW, the data signal WDATA, and the data signal RDATA are respectively a byte write enable signal BW [3: 0], a data signal WDATA [31: 0], and a data signal RDATA [31: 0]. Notation.

Note that in the storage device 100, the above-described circuits, signals, and potentials can be appropriately discarded as necessary. Alternatively, another circuit, another signal, or another potential may be added.

The control logic circuit 160 processes the chip enable signal CE and the global write enable signal GW to generate control signals for the row decoder 121 and the column decoder 131. For example, when the chip enable signal CE is at a high level and the global write enable signal GW is at a low level, the row decoder 121 and the column decoder 131 perform a read operation, and the chip enable signal CE is at a high level and the global write enable signal GW is at a high level. , The row decoder 121 and the column decoder 131 perform a write operation, and when the chip enable signal CE is at a low level, the row decoder 121 and the column decoder 131 are in a standby state regardless of whether the global write enable signal GW is at a high level or a low level. Operation. The signal processed by the control logic circuit 160 is not limited to this, and another signal may be input as needed.

Further, the control logic circuit 160 processes the byte write enable signal BW [3: 0] to control the write operation. Specifically, when the byte write enable signal BW [0] is at a high level, the row decoder 121 and the column decoder 131 perform a write operation of the data signal WDATA [7: 0]. Similarly, when the byte write enable signal BW [1] is at a high level, the write operation of the data signal WDATA [15: 8] is performed. When the byte write enable signal BW [2] is at a high level, the data signal WDATA [23:16] is used. When the byte write enable signal BW [3] is at a high level, the write operation of the data signal WDATA [31:24] is performed.

The row decoder 121 and the column decoder 131 receive an address signal ADDR in addition to the control signal generated by the control logic circuit 160 described above.

The row decoder 121 decodes the address signal ADDR and generates a control signal for the word line driver circuit 122. The word line driver circuit 122 has a function of driving the write word line wl, the read word line rwl, and the precharge line prl. The word line driver circuit 122 selects a write word line wl, a read word line rwl, or a precharge line prl of a row to be accessed based on a control signal of the row decoder 121.

When the memory cell array 210 is divided into a plurality of blocks, a predecoder 123 may be provided. The predecoder 123 has a function of decoding the address signal ADDR to determine a block to be accessed.

The column decoder 131, the bit line driver circuit 132, and the page buffer 138 have a function of writing data input by the data signal WDATA to the memory cell array 210, a function of reading data from the memory cell array 210, and amplifying and outputting read data. It has a function of outputting to the circuit 140 and the like.

The output circuit 140 outputs data read from the memory cell array 210 by the column decoder 131 and the bit line driver circuit 132 and stored in the page buffer 138 as a data signal RDATA.

In the example of FIG. 2, the bit line driver circuit 132 has a precharge circuit 133, a sense amplifier circuit 134, an output MUX (multiplexer) circuit 135, and a write driver circuit 136. The precharge circuit 133, the sense amplifier circuit 134, the output MUX circuit 135, and the write driver circuit 136 will be described later.

<Memory cell array>
FIG. 3 shows a configuration example of the memory cell array 210. The memory cell array 210 includes m (m is an integer of 1 or more) in one column, and n (n is an integer of 1 or more) in a row, and a total of m × n memory cells 211, and the memory cells 211 are arranged in a matrix. Are located in

FIG. 3 also shows the addresses of the memory cells 211, and [1,1], [i, 1], [m, 1], [1, j], [i, j], [m, j]. , [1, n], [i, n], [m, n] (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) are addresses of the memory cell 211. For example, the memory cell 211 described as [i, j] is the memory cell 211 in the i-th row and the j-th column.

The memory cell array 210 includes m write word lines wl (wl (1) to wl (m)), m read word lines rwl (rwl (1) to rwl (m)), and m precharges. Line prl (prl (1) to prl (m)), n write bit lines wbl (wbl (1) to wbl (n)), and n read bit lines rbl (rbl (1) to rbl ( n)).

Each memory cell 211 is electrically connected to a write word line wl, a read word line rwl, a precharge line prl, a write bit line wbl, and a read bit line rbl. For example, as shown in FIG. 3, a memory cell 211 whose address is [i, j] is connected via a write word line wl (i), a read word line rwl (i), and a precharge line prl (i). It is electrically connected to the word line driver circuit 122, and is electrically connected to the bit line driver circuit 132 via the write bit line wbl (j) and the read bit line rbl (j).

<Memory cell 1>
FIG. 4A is a circuit diagram illustrating a configuration example of the memory cell 211. Note that in this embodiment, an example in which the write word line wl includes four write word lines wl1 to wl4 will be described; however, the present invention is not limited to this configuration.

As illustrated in FIG. 4A, the memory cell 211 includes transistors M11 to M16 and capacitors C11 to C14. Here, the transistors M11 to M14 may be referred to as write transistors, the transistor M15 may be referred to as a read transistor, and the transistor M16 may be referred to as a precharge transistor.

One of a source and a drain of the transistor M11 is electrically connected to a gate of the transistor M15, one of a source and a drain of the transistor M16, and a first terminal of the capacitor C11. One of the source and the drain of the transistor M12 is electrically connected to the other of the source and the drain of the transistor M11 and the first terminal of the capacitor C12. One of the source and the drain of the transistor M13 is connected to the source or the drain of the transistor M12. One of the source and the drain of the transistor M14 is electrically connected to the other of the drain and the first terminal of the capacitor C13, and one of the source and the drain of the transistor M14 is electrically connected to the other of the source and the drain of the transistor M13 and the first terminal of the capacitor C14. You.

The gate of the transistor M11 is electrically connected to the write word line wl1, the gate of the transistor M12 is electrically connected to the write word line wl2, the gate of the transistor M13 is electrically connected to the write word line wl3, and the transistor M14 Is electrically connected to the write word line wl4. The other of the source and the drain of the transistor M14 is electrically connected to the write bit line wbl, the one of the source and the drain of the transistor M15 is electrically connected to the read word line rwl, and the other of the source and the drain of the transistor M15 Is electrically connected to the read bit line rbl, and the gate of the transistor M16 is electrically connected to the precharge line prl.

The other of the source and the drain of the transistor M16 is electrically connected to the wiring pre, and the second terminal of the capacitor C11, the second terminal of the capacitor C12, the second terminal of the capacitor C13, and the second terminal of the capacitor C14. The two terminals are electrically connected to the wiring CAL. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminals of the capacitors C11 to C14, and the wiring pre functions as a wiring for supplying a precharge potential Vpre.

Here, a node to which one of the source and the drain of the transistor M11, the gate of the transistor M15, one of the source and the drain of the transistor M16, and the first terminal of the capacitor C11 are electrically connected is referred to as a node SN1. A node to which one of the source and the drain of the transistor M12, the other of the source and the drain of the transistor M11, and the first terminal of the capacitor C12 are electrically connected is referred to as a node SN2, and one of the source and the drain of the transistor M13. The node to which the other of the source and the drain of the transistor M12 and the first terminal of the capacitor C13 are electrically connected is referred to as a node SN3, and one of the source and the drain of the transistor M14 and the source or the drain of the transistor M13. On the other hand, And, the first terminal of the capacitor C14 is called an electrically connected nodes and node SN4.

The memory cell 211 can store data by storing and holding electric charge in the nodes SN1 to SN4. In this embodiment, it is assumed that binary data (high level or low level) can be stored in each of the nodes SN1 to SN4. That is, the memory cell 211 can store 4-bit data.

As the transistors M11 to M14 and the transistor M16, a transistor including a metal oxide in a channel formation region (OS transistor) can be used. For example, indium and an element M (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, or zirconium are formed in the channel formation regions of the transistors M11 to M14 and the transistor M16. , Molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium or the like), or a metal oxide containing zinc. In particular, a metal oxide composed of indium, gallium, and zinc is preferable.

Since the off-state current of the OS transistor is extremely small, the potential written to the nodes SN1 to SN4 can be held for a long time by using an OS transistor for the transistors M11 to M14 and the transistor M16. That is, data written to the memory cell 211 can be held for a long time.

In addition, by using OS transistors for the transistors M11 to M14 and the transistor M16, the capacitance of the capacitors C11 to C14 can be reduced. For example, a gate capacitance of a transistor, a parasitic capacitance of a wiring, or the like can be used as the capacitors C11 to C14. Therefore, in the memory cell 211, it is not necessary to form a capacitor separately from the transistor and the wiring, and the area of the memory cell 211 can be reduced. Alternatively, the number of memory cells 211 that can be arranged per unit area can be increased.

In the case where a capacitor is not required to be formed separately from a transistor and a wiring in the memory cell 211, the circuit diagram illustrated in FIG. 4A includes the capacitors C11 to C14 as illustrated in FIG. It may be illustrated by a dotted line.

The transistor used as the transistor M15 is not particularly limited. Although an OS transistor, a Si transistor, or another transistor may be used as the transistor M15, an OS transistor is also used as the transistor M15 in addition to the transistors M11 to M14 and the transistor M16, so that the memory cell array 210 Can be provided by being stacked on the peripheral circuit 110, which is preferable.

The transistor M11 functions as a switch that turns on or off the node SN1 and the node SN2, the transistor M12 functions as a switch that turns on or off the node SN2 and the node SN3, and the transistor M13 turns on or off the node SN3. The transistor M14 functions as a switch for conducting or non-conducting between the node SN4 and the write bit line wbl.

<Data writing>
Writing of data to the nodes SN1 to SN4 is performed in order from the node SN1. After writing data to the node SN1, data is written to the node SN2, then data is written to the node SN3, and finally, data is written to the node SN4. Note that during the data writing period, a low-level potential is applied to the precharge line prl, the transistor M16 is off, and the transistor M15 is not used.

In writing data to the node SN1, a high-level potential is applied to the write word lines wl1 to wl4 to make the transistors M11 to M14 conductive, and the node SN1 is electrically connected to the write bit line wbl. It is done by doing. Specifically, when the transistors M11 to M14 are on, a potential corresponding to data to be written to the write bit line wbl is applied, and the potential is written to the node SN1. After that, a low-level potential is applied to the write word lines wl1 to wl4 and the transistors M11 to M14 are turned off, so that the potential of the node SN1 is held.

In writing data to the node SN2, a high-level potential is applied to the write word lines wl2 to wl4 to turn on the transistors M12 to M14, so that the node SN2 and the write bit line wbl are electrically connected. It is done by doing. Specifically, when the transistors M12 to M14 are on, a potential corresponding to data to be written to the write bit line wbl is applied, and the potential is written to the node SN2. After that, a low-level potential is applied to the write word lines wl2 to wl4 and the transistors M12 to M14 are turned off, so that the potential of the node SN2 is held.

To write data to the node SN3, a high-level potential is applied to the write word line wl3 and the write word line wl4 to make the transistors M13 and M14 conductive, and the node SN3 and the write bit line wbl are electrically connected. It is done by doing. Specifically, when the transistors M13 and M14 are on, a potential corresponding to data to be written to the write bit line wbl is applied, and the potential is written to the node SN3. After that, a low-level potential is applied to the write word line wl3 and the write word line wl4 to turn off the transistor M13 and the transistor M14, so that the potential of the node SN3 is held.

Writing of data to the node SN4 is performed by applying a high-level potential to the write word line wl4 to turn on the transistor M14 and electrically connecting the node SN4 to the write bit line wbl. Specifically, when the transistor M14 is on, a potential corresponding to data to be written to the write bit line wbl is applied, and the potential is written to the node SN4. After that, a low-level potential is applied to the write word line wl4 to turn off the transistor M14, so that the potential of the node SN4 is held.

<Reading data>
Reading of data from the nodes SN1 to SN4 is also performed sequentially from the node SN1. After reading the data of the node SN1, the data of the node SN2 is read, then the data of the node SN3 is read, and finally, the data of the node SN4 is read.

Data reading is performed by applying a predetermined potential to the read bit line rbl, thereafter bringing the read bit line rbl into an electrically floating state, and applying a low-level potential to the read word line rwl. Done. Hereinafter, applying a predetermined potential to the read bit line rbl and then setting the read bit line rbl in a floating state is referred to as precharging the read bit line rbl.

The manner in which data is read from the nodes SN1 to SN4 will be described with reference to the timing chart shown in FIG.

Note that FIG. 5 illustrates a state in which data is read from the node SN1 in the period Trd1, data is read from the node SN2 in the period Trd2, data is read from the node SN3 in the period Trd3, and data is read from the node SN4 in the period Trd4. . Further, the period Trd1 includes a period T11, a period T12, and a period T13, the period Trd2 includes a period T21, a period T22, and a period T23, and the period Trd3 includes a period T31, a period T32, and a period T33. The period Trd4 includes a period T41, a period T42, and a period T43.

Reading of data from the node SN1 is performed by precharging the read bit line rbl with a high-level potential and applying a low-level potential to the read word line rwl.

Specifically, in the periods T11 and T12, a high-level potential is precharged to the read bit line rbl and a high-level potential is applied to the read word line rwl. At this time, a low-level potential is applied to the precharge line prl and the write word lines wl1 to wl4, and the transistor M16 and the transistors M11 to M14 are off. Note that in the period Trd1, the period T11 and the period T12 are in the same state, and either one of them may be omitted.

In the period T13, when a low-level potential is applied to the read word line rwl, the transistor M15 has a potential difference between the source and the drain, and has a potential difference between the source and the drain of the transistor M15 in accordance with the potential held at the node SN1. The current flowing between the gate and the drain is determined. That is, when a high-level potential is held at the node SN1, the transistor M15 is on, and the potential of the read bit line rbl in a floating state falls by ΔV4 from the high level (see FIG. 5). When a low-level potential is held at the node SN1, the transistor M15 is off, and the potential of the read bit line rbl remains at a high level. Thus, the potential held at the node SN1 can be read from the change in the potential of the read bit line rbl.

In reading data from the node SN2, the node SN1 is precharged with a precharge potential Vpre, and then the transistor M11 is turned on to electrically connect the node SN1 to the node SN2. This is performed by precharging the read bit line rbl with a high-level potential and applying a low-level potential to the read word line rwl. Note that in this embodiment, the precharge potential Vpre is a low-level potential (potential Vss).

Specifically, in the period T21, a high-level potential is applied to the precharge line prl and the transistor M16 is turned on, so that the node SN1 is precharged with a low-level potential. In a period T22, a high-level potential is applied to the write word line wl1, the transistor M11 is turned on, and the nodes SN1 and SN2 are electrically connected. When a low-level potential is held at the node SN2, the potential of the node SN1 maintains a low-level state. However, when a high-level potential is held at the node SN2, the potential of the node SN1 changes from a high level. The potential drops by ΔV1 (see FIG. 5). The read bit line rbl is precharged with a high-level potential.

In the period T23, when the potential applied to the read word line rwl changes from the high level to the low level, the transistor M15 has a potential difference between the source and the drain, and depends on the potential held at the node SN1. The current flowing between the source and the drain of M15 is determined. When a high-level potential or a potential close to the high level is held at the node SN1, the transistor M15 is turned on, and the potential of the read bit line rbl in a floating state falls by ΔV5 from the high level (see FIG. 5). ). When a low-level potential is held at the node SN1, the transistor M15 is off, and the potential of the read bit line rbl remains at a high level. Thus, the potential held at the node SN1, that is, the potential held at the node SN2 can be read from the change in the potential of the read bit line rbl.

In reading data from the node SN3, the node SN1 and the node SN2 are precharged with a low-level potential, and then the transistor M11 and the transistor M12 are turned on to electrically connect the node SN1 to the node SN3. This is performed by precharging the read bit line rbl with a high-level potential and applying a low-level potential to the read word line rwl.

Specifically, in a period T31, a high-level potential is applied to the precharge line prl and the write word line wl1, and the transistors M16 and M11 are turned on, so that a low-level potential is applied to the nodes SN1 and SN2. Is precharged. In a period T32, a high-level potential is applied to the write word line wl1 and the write word line wl2, the transistors M11 and M12 are turned on, and the nodes SN1 and SN3 are electrically connected. When a low-level potential is held at the node SN3, the potential of the node SN1 maintains a low-level state. However, when a high-level potential is held at the node SN3, the potential of the node SN1 changes from a high level. The potential drops by ΔV2 (see FIG. 5). The read bit line rbl is precharged with a high-level potential.

In the period T33, when the potential applied to the read word line rwl changes from the high level to the low level, the transistor M15 has a potential difference between the source and the drain, and depends on the potential held at the node SN1. The current flowing between the source and the drain of M15 is determined. When a high-level potential or a potential close to the high level is held at the node SN1, the transistor M15 is turned on, and the potential of the read bit line rbl in a floating state drops by ΔV6 from the high level (see FIG. 5). ). When a low-level potential is held at the node SN1, the transistor M15 is off, and the potential of the read bit line rbl remains at a high level. In this manner, the potential held at the node SN1, that is, the potential held at the node SN3 can be read from the change in the potential of the read bit line rbl.

In reading data from the node SN4, a low-level potential is precharged to the nodes SN1 to SN3, and then the transistors M11 to M13 are turned on to electrically connect the nodes SN1 and SN4. This is performed by precharging the read bit line rbl with a high-level potential and applying a low-level potential to the read word line rwl.

Specifically, in the period T41, a high-level potential is applied to the precharge line prl, the write word line wl1, and the write word line wl2, and the transistors M16, M11, and M12 are turned on. A low-level potential is precharged to the nodes SN1 to SN3. In a period T42, a high-level potential is applied to the write word lines wl1 to wl3, the transistors M11 to M13 are turned on, and the nodes SN1 and SN4 are electrically connected. When a low-level potential is held at the node SN4, the potential of the node SN1 maintains a low-level state; however, when a high-level potential is held at the node SN4, the potential of the node SN1 changes from a high level. The potential drops by ΔV3 (see FIG. 5). The read bit line rbl is precharged with a high-level potential.

In the period T43, when the potential applied to the read word line rwl changes from the high level to the low level, the transistor M15 has a potential difference between the source and the drain, and depends on the potential held at the node SN1. The current flowing between the source and the drain of M15 is determined. When a high-level potential or a potential close to the high level is held at the node SN1, the transistor M15 is turned on, and the potential of the read bit line rbl in a floating state drops by ΔV7 from the high level (see FIG. 5). ). When a low-level potential is held at the node SN1, the transistor M15 is off, and the potential of the read bit line rbl remains at a high level. In this manner, the potential held at the node SN1, that is, the potential held at the node SN4 can be read from the change in the potential of the read bit line rbl.

<Memory cell 2>
The memory cell 211 may be formed using transistors M21 to M26 having a back gate instead of the transistors M11 to M16. Alternatively, at least one of the transistors M11 to M16 may be replaced with a transistor having a back gate. FIG. 6A is a circuit diagram illustrating a configuration example of the memory cell 212.

The memory cell 212 is a memory cell in which the transistors M11 to M16 included in the memory cell 211 are replaced with transistors M21 to M26, respectively. Each of the transistors M21 to M26 has a front gate and a back gate.

The memory cell 212 includes transistors M21 to M26, and capacitors C11 to C14. In the memory cell 212, the back gates of the transistors M21 to M26 are electrically connected to the respective front gates. A transistor in which the back gates and the front gates of the transistors M21 to M26 are electrically connected to each other corresponds to the gates of the transistors M11 to M16 in the memory cell 211, and the other connections correspond to the memory cells 212 and 211. Is similar. The description of the memory cell 211 is referred to for the circuit configuration of the memory cell 212.

The transistors M21 to M26 each have a back gate in addition to a front gate, so that on-state current can be increased. That is, the memory cell 212 can perform high-speed operation.

<Memory cell 3>
A predetermined potential may be applied to the back gates of the transistors M21 to M26 included in the memory cell 212. FIG. 6B is a circuit diagram illustrating a configuration example of the memory cell 213.

The memory cell 213 includes transistors M21 to M26 and capacitor elements C11 to C14 similarly to the memory cell 212.

In the memory cell 213, the back gates of the transistors M21 to M26 are electrically connected to the wiring VBG. The wiring VBG functions as a wiring for applying a predetermined potential to the back gates of the transistors M21 to M26.

By applying a predetermined potential to the back gates of the transistors M21 to M26 through the wiring VBG, the threshold voltages of the transistors M21 to M26 can be increased or decreased. Specifically, by increasing the potential applied to the back gates of the transistors M21 to M26, the threshold voltage shifts to a negative value, and the potential applied to the back gates of the transistors M21 to M26 is reduced. , The threshold voltage shifts to positive. By shifting the threshold voltage to a negative value, the on-state current of the transistor can be increased, and the memory cell 213 can operate at high speed. By shifting the threshold voltage to plus, the off-state current of the transistor can be reduced, and the memory cell 213 can hold stored data for a long time.

Note that in the memory cell 213, the back gates of the transistors M21 to M26 are electrically connected to the wiring VBG; however, the back gates of the transistors M21 to M26 are electrically connected to a plurality of different wirings. You may. For example, the back gates of the transistors M21 to M24 and the transistor M26 are electrically connected to a wiring VBG1 (not illustrated), and the back gate of the transistor M25 is electrically connected to a wiring VBG2 (not illustrated). It may be configured. The off-state current of the transistors M21 to M24 and the transistor M26 is reduced by lowering the potential applied to the wiring VBG1, and the on-state current of the transistor M25 is increased by increasing the potential applied to the wiring VBG2. Can be.

By reducing the off-state current of the transistors M21 to M24 and the transistor M26, the potential written to the nodes SN1 to SN4 can be held for a long time. That is, the memory cell 213 can hold the stored data for a long time. Further, the read operation of the memory cell 213 can be performed at high speed by increasing the on-state current of the transistor M25. The transistors M21 to M26 can be transistors that meet respective purposes.

Further, the potential applied to the wiring VBG2 to which the back gate of the transistor M25 is electrically connected may be temporarily increased. For example, in the memory cell array 210 illustrated in FIG. 3, a memory cell 213 is provided instead of the memory cell 211, and the memory cell array 210 includes a wiring VBG2 (like a write word line wl (1) to a write word line wl (m)). 1) to VBG2 (m), and the wirings VBG2 (1) to VBG2 (m) are driven by the word line driver circuit 122. The memory cell 213 in the i-th row is electrically connected to the wiring VBG2 (i). When a data read operation is performed in the memory cell 213 in the i-th row, the potential applied to the wiring VBG2 (i) is changed. And the potential applied to the other wiring VBG2 can be lowered.

By increasing the on-state current of the transistor M25 included in the memory cell 213 from which data is being read, the reading operation of the memory cell 213 is performed at high speed and the off-state current of the transistor M25 included in the other memory cells 213 is reduced. By doing so, the current leaking to the read bit line rbl can be reduced. By reducing the current leaking to the read bit line rbl, the accuracy of the read operation can be improved.

<Memory cell 4>
In the transistors M21 to M24 included in the memory cell 213, the capacitances formed between the back gate and the channel formation region, between the back gate and the source region, and between the back gate and the drain region are changed to those of the capacitors C11 to C14. It may be used instead. FIG. 7 is a circuit diagram showing a configuration example of the memory cell 214.

In the memory cell 214, the capacitors C11 to C14 can be omitted from the memory cell 213. The memory cell 214 includes transistors M21 to M26.

In the memory cell 214, the back gates of the transistors M21 to M24 are electrically connected to the wiring CAL. The wiring CAL functions as a wiring for applying a predetermined potential. The back gates of the transistor M25 and the transistor M26 are electrically connected to the wiring VBG. The wiring VBG functions as a wiring for applying a predetermined potential to the back gates of the transistors M25 and M26.

With the use of transistors with small off-state current as the transistors M21 to M24 and the transistor M26, the capacitance of the capacitors C11 to C14 in the memory cell 213 can be reduced. That is, instead of the capacitors C11 to C14, capacitors formed on the back gates of the transistors M21 to M24 can be used.

The memory cell 214 does not require the formation of the capacitors C11 to C14 and can be a small memory cell. Alternatively, the memory cell 214 can be a large number of memory cells that can be arranged per unit area.

<Bit line driver circuit>
The bit line driver circuit 132 is provided with a circuit 30 shown in FIG. 8 for each column. FIG. 8 is a circuit diagram showing a configuration example of the circuit 30. In this embodiment, the memory cell array 210 has 128 memory cells 211 in one row (n = 128).

The circuit 30 includes transistors M31 to M36, a sense amplifier circuit 31, an AND circuit 32, an analog switch 33, and an analog switch.

The circuit 30 complies with the signals SEN [3: 0], SEP [3: 0], BPR, RSEL [3: 0], WSEL, GRSEL [3: 0], and GWSEL [15: 0]. ,Operate. Note that one circuit 30 receives a signal of any one bit of the signal SEN [3: 0] of 4 bits. The same applies to other signals having a plurality of bits (such as SEP [3: 0]).

The bit line driver circuit 132 writes data DIN [31: 0] to the memory cell array 210, and reads data DOUT [31: 0] from the memory cell array 210. One circuit 30 writes any one bit of the data DIN [31: 0] of 32 bits to the memory cell array 210, and writes any one bit of the data DOUT [31: 0] of 32 bits. It has a function of reading data from the memory cell array 210.

Note that data DIN [31: 0] and data DOUT [31: 0] are internal signals, and data DIN [31: 0] is a signal supplied from the page buffer 138 to the bit line driver circuit 132. DOUT [31: 0] is a signal output from the bit line driver circuit 132 to the page buffer 138. Further, the data signal WDATA is input to the page buffer 138 from outside the storage device 100, and the page buffer 138 outputs the data signal RDATA to the outside of the storage device 100 via the output circuit 140.

It is preferable that the page buffer 138 can store at least a data amount (n × k bits) that can be stored in one row in the memory cell array 210. In this embodiment, it is preferable that data of 128 × 4 bits or more can be stored.

<< Precharge circuit >>
The transistor M31 forms the precharge circuit 133. The read bit line rbl is precharged to the potential Vdd (high level) by the transistor M31. The signal BPR is a precharge signal, and the conduction state of the transistor M31 is controlled by the signal BPR.

<< sense amplifier circuit >>
The sense amplifier circuit 31 forms the sense amplifier circuit 134. At the time of a read operation, the sense amplifier circuit 31 determines the high level or the low level of the data input to the read bit line rbl. In addition, the sense amplifier circuit 31 functions as a latch circuit that temporarily holds the data DIN input from the write driver circuit 136 during a write operation.

The sense amplifier circuit 31 shown in FIG. 8 is a latch type sense amplifier. The sense amplifier circuit 31 has two inverter circuits, and an input node of one inverter circuit is connected to an output node of the other inverter circuit. Assuming that the input node of one of the inverter circuits is a node NS and the output node is a node NSB, complementary data is held at the nodes NS and NSB.

The signal SEN and the signal SEP are sense amplifier enable signals for activating the sense amplifier circuit 31, and the reference potential Vref is a read determination potential. The sense amplifier circuit 31 determines whether the potential of the node NSB at the time of activation is at a high level or a low level based on the reference potential Vref.

The AND circuit 32 controls the conduction state between the node NS and the write bit line wbl. Further, the analog switch 33 controls the conduction state between the node NSB and the read bit line rbl, and the analog switch 34 controls the conduction state between the node NS and the wiring supplying the reference potential Vref.

That is, the potential of the read bit line rbl is transmitted to the node NSB by the analog switch 33. In FIG. 5, for example, when the potential of the read bit line rbl falls from the high level by ΔV4 and becomes lower than the reference potential Vref, the sense amplifier circuit 31 determines that the read bit line rbl is at low level. If the potential of the read bit line rbl does not become lower than the reference potential Vref, the sense amplifier circuit 31 determines that the read bit line rbl is at the high level.

The signal WSEL is a write selection signal and controls the AND circuit 32. The signal RSEL [3: 0] is a read selection signal, and controls the analog switch 33 and the analog switch 34.

<< output MUX circuit >>
The transistor M32 and the transistor M33 form an output MUX circuit 135. The signal GRSEL [3: 0] is a global read selection signal, and controls the output MUX circuit 135. The output MUX circuit 135 has a function of selecting 32 read bit lines rbl from which data is read out of the 128 read bit lines rbl. The output MUX circuit 135 functions as a 128-input, 32-output multiplexer.

The output MUX circuit 135 reads the data DOUT [31: 0] from the sense amplifier circuit 134 and outputs the data DOUT [31: 0] to the page buffer 138.

<< Write driver circuit >>
The transistors M34 to M36 form a write driver circuit 136. The signal GWSEL [15: 0] is a global write selection signal and controls the write driver circuit 136. The write driver circuit 136 has a function of writing data DIN [31: 0] to the sense amplifier circuit 134.

The write driver circuit 136 has a function of selecting a column in which the data DIN [31: 0] is to be written. The write driver circuit 136 writes data in byte units, half word units, or one word units according to the signal GWSEL [15: 0].

The circuit 30 is electrically connected to data DIN [h] (h is an integer of 0 or more and 31 or less) every four columns. The circuit 30 is electrically connected to the data DOUT [h] every four columns.

Further, the circuit 30 may have a configuration including k sense amplifier circuits 31. In the present embodiment, a configuration having four sense amplifier circuits 31 may be employed. By setting the signal WSEL to be a 4-bit signal WSEL [3: 0], the four sense amplifier circuits 31 can use any one of the sense amplifier circuits 31 by the signals RSEL [3: 0] and WSEL [3: 0]. Whether the read bit line rbl or the write bit line wbl is electrically connected is controlled.

Similarly, the four sense amplifier circuits 31 write data DIN [31: 0] to which sense amplifier circuits 31 or which sense amplifiers by the signals GRSEL [3: 0] and GWSEL [15: 0]. It is possible to control whether the circuit 31 outputs data DOUT [31: 0].

Since the sense amplifier circuit 31 is a latch type sense amplifier and has a function of holding data at the node NS and the node NSB, the page buffer 138 can be omitted when the circuit 30 includes four sense amplifier circuits 31. .

As described above, the memory cell 211 to the memory cell 214 operate as a memory by amplifying the stored charge by the nearest transistor (the transistor M15 or the transistor M25) even when the capacity for storing the charge is small. be able to. In addition, by using a transistor with a small off-state current such as an OS transistor for the transistors M11 to M14 and the transistor M16 (or the transistors M21 to M24 and the transistor M26), the capacitance of the capacitor C11 to the capacitor C14 can be increased. Can be reduced.

Therefore, a gate capacitance of a transistor, a parasitic capacitance of a wiring, or the like can be used as the capacitors C11 to C14. Unlike the memory cell 214 described above, there is no need to form a capacitor separately from a transistor and a wiring, and the area of the memory cell 214 can be reduced.

Further, a gain cell type memory cell requires at least two transistors per memory cell, and it was difficult to increase the number of memory cells that can be arranged per unit area. Thus, the amount of data that can be stored per memory cell can be increased. In this embodiment, the memory cell 211 can store 4-bit data using six transistors. That is, the amount of data that can be stored per unit area can be increased.

In addition, when all the transistors included in the memory cell 211 are OS transistors, the memory cell array 210 can be stacked over the peripheral circuit 110. Therefore, the chip area of the storage device 100 can be reduced.

Note that this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, an example in which the storage device described in any of the above embodiments has a serial peripheral interface (SPI) will be described. The serial peripheral interface is one of serial interfaces used for communication between semiconductor devices that input and output digital signals, and has a feature that the number of terminals required for input and output of signals can be reduced. For example, it is used for communication between a CPU (Central Processing Unit) and a storage device.

<Block diagram of storage device>
FIG. 9 is a block diagram illustrating a configuration example of the storage device 105. The storage device 105 includes a peripheral circuit 115 and a memory cell array 210. As in the storage device 100 described in the above embodiment, in the storage device 105, the peripheral circuit 115 is formed using Si transistors, the memory cell array 210 includes a plurality of memory cells 211, and the memory cells 211 include OS transistors. It is configured using.

The peripheral circuit 115 has a row decoder 121, a word line driver circuit 122, a column decoder 131, a bit line driver circuit 132, a page buffer 138, a potential generation circuit 150, an SPI controller 161, and a status register 168. The memory cell array 210 includes a memory cell 211, a write word line wl, a read word line rwl, a precharge line prl, a write bit line wbl, and a read bit line rbl.

Note that the memory cell array 210, the row decoder 121, the word line driver circuit 122, the column decoder 131, the bit line driver circuit 132, and the page buffer 138 are the same as those in the above-described embodiment, and will not be described.

The potential Vss and the potential Vdh are input to the storage device 105. Further, the clock signal SCLK, the chip select signal CS, the data input signal SI, the data output signal SO, the hold signal HOLD, and the write protection signal WP are input to the storage device 105.

The potential generation circuit 150 includes regulators 151 to 153 and a power switch 154. From the potential Vss and the potential Vdh input to the storage device 105, the regulator 151 generates the potential Vdd, the regulator 152 generates the precharge potential Vpre, the regulator 153 generates the reference potential Vref, and the power switch 154 The output of the potential Vdh can be controlled.

The potential generation circuit 150 has a function of supplying the potential Vdh, the potential Vdd, and the potential Vss to the peripheral circuit 115. For example, the potential Vdh can be 3.3 V, the potential Vdd can be 1.2 V, and the potential Vss can be 0 V (GND).

In the case where the memory cell 211 is formed using a transistor having a back gate, the potential generation circuit 150 may have a function of generating and supplying a potential applied to the back gate.

The SPI controller 161 has a serial / parallel converter 162, an instruction decoder circuit 163, a page address generation circuit 164, a command generation circuit 165, a byte address generation circuit 166, and a parallel / serial converter 167.

The SPI controller 161 processes a signal input to the storage device 105 and outputs a chip enable signal CE and a global write enable signal GW to the row decoder 121 and the column decoder 131.

For example, when the chip enable signal CE is at a high level and the global write enable signal GW is at a low level, the row decoder 121 and the column decoder 131 perform a read operation, and the chip enable signal CE is at a high level and the global write enable signal GW is at a high level. , The row decoder 121 and the column decoder 131 perform a write operation, and when the chip enable signal CE is at a low level, the row decoder 121 and the column decoder 131 are in a standby state regardless of whether the global write enable signal GW is at a high level or a low level. Operation.

The SPI controller 161 processes a signal input to the storage device 105 and outputs a data signal WDATA to the page buffer 138. The page buffer 138 outputs the data signal RDATA read from the memory cell array 210 to the SPI controller 161.

The page address generation circuit 164 outputs a row address signal RADR to the row decoder 121, and the byte address generation circuit 166 outputs a column address signal CADR to the column decoder 131. The memory cell 211 to be read or written is determined by the row address signal RADR and the column address signal CADR.

The page buffer 138 has a function of temporarily storing a data signal to be read or written, and the status register 168 is a memory for storing an operation mode of the SPI controller 161.

For example, the memory cell 211 can store 4-bit data, the memory cell array 210 has 512 memory cells 211 in one row and 1024 memory cells in one column, and the data amount that can be stored in the page buffer 138 is 256 bytes ( 2048 bits), the storage device 105 can be a storage device capable of storing a data amount of 256 Kbytes.

The write protection signal WP is a signal for preventing writing to the status register 168, and the hold signal HOLD is a signal for temporarily stopping the operation of the storage device 105.

The signals processed by the SPI controller 161 are not limited to those described above, and other signals may be input or output as needed.

Note that this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, structural examples of a Si transistor applicable to the peripheral circuit 110 described in the above embodiment and an OS transistor applicable to the memory cell 211 will be described. In this embodiment, the Si transistor and the OS transistor are collectively called a semiconductor device.

<Configuration example of semiconductor device>
The semiconductor device illustrated in FIG. 10 includes a transistor 300, a transistor 500, and a capacitor 600. 11A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 11B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. FIG.

The transistor 500 is a transistor including a metal oxide in a channel formation region (OS transistor). Since the transistor 500 has low off-state current, stored data can be held for a long time by using the transistor 500 in a semiconductor device. Alternatively, the capacity for storing electric charges can be reduced.

The semiconductor device described in this embodiment includes a transistor 300, a transistor 500, and a capacitor 600 as illustrated in FIG. The transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistor 300 and the transistor 500.

The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 which is part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b which function as a source or drain region. Have.

In the transistor 300, as illustrated in FIG. 11C, the top surface of the semiconductor region 313 and the side surface in the channel width direction are covered with a conductor 316 with an insulator 315 interposed therebetween. In this manner, by making the transistor 300 a Fin type, the on-state characteristics of the transistor 300 can be improved by increasing the effective channel width. Further, the contribution of the electric field of the gate electrode can be increased, so that the off-state characteristics of the transistor 300 can be improved.

Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor.

The region where the channel of the semiconductor region 313 is formed, a region near the channel, a low-resistance region 314a serving as a source region or a drain region, a low-resistance region 314b, or the like preferably contains a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, it may be formed using a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A structure using silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be formed using HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs.

The low-resistance regions 314a and 314b have an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor region 313. Containing elements.

The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, or an alloy including an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Note that since the work function is determined by the material of the conductor, Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and burying property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

Note that the transistor 300 illustrated in FIG. 10 is an example, and there is no limitation on the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are provided so as to cover the transistor 300 in that order.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. I just need.

The insulator 322 may have a function as a planarization film that planarizes a step formed due to the transistor 300 and the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

Further, as the insulator 324, a film having a barrier property such that hydrogen or an impurity is not diffused is preferably used in a region where the transistor 500 is provided from the substrate 311 or the transistor 300 or the like.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may be reduced. Therefore, a film which suppresses diffusion of hydrogen is preferably used between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film from which the amount of desorbed hydrogen is small.

The amount of desorbed hydrogen can be analyzed using, for example, a thermal desorption gas analysis (TDS analysis) method. For example, in the TDS analysis, when the surface temperature of the film is in the range of 50 ° C. to 500 ° C., the amount of desorbed hydrogen in the insulator 324 is converted into hydrogen atoms per area of the insulator 324 in the TDS analysis. Therefore, it may be 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Further, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative permittivity of the insulator 324. By using a material having a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

In the insulator 320, the insulator 322, the insulator 324, and the insulator 326, a conductor 328 connected to the capacitor 600 or the transistor 500, a conductor 330, or the like is embedded. Note that the conductor 328 and the conductor 330 have a function as a plug or a wiring. In some cases, the same reference numeral is given to a plurality of structures collectively for a conductor having a function as a plug or a wiring. Further, in this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, a part of the conductor functions as a wiring and a part of the conductor functions as a plug in some cases.

As a material of each plug and a wiring (the conductor 328, the conductor 330, and the like), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 10, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug connected to the transistor 300 or a wiring. Note that the conductor 356 can be provided using the same material as the conductor 328 and the conductor 330.

Note that for example, as the insulator 350, an insulator having a barrier property to hydrogen is preferably used, like the insulator 324. Further, the conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With such a structure, the transistor 300 and the transistor 500 can be separated from each other by the barrier layer, so that diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

Note that as the conductor having a barrier property to hydrogen, for example, tantalum nitride or the like may be used. In addition, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while the conductivity as a wiring is maintained. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 10, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. A conductor 366 is formed over the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that, for example, as the insulator 360, an insulator having a barrier property to hydrogen is preferably used, like the insulator 324. Further, the conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 360 having a barrier property against hydrogen. With such a structure, the transistor 300 and the transistor 500 can be separated from each other by the barrier layer, so that diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 10, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed over the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that for example, the insulator 370 is preferably an insulator having a barrier property to hydrogen, like the insulator 324. Further, the conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With such a structure, the transistor 300 and the transistor 500 can be separated from each other by the barrier layer, so that diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 10, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 has a function as a plug or a wiring. Note that the conductor 386 can be provided using the same material as the conductor 328 and the conductor 330.

Note that, for example, as the insulator 380, an insulator having a barrier property to hydrogen is preferably used, like the insulator 324. Further, the conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With such a structure, the transistor 300 and the transistor 500 can be separated from each other by the barrier layer, so that diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described. However, it is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are provided over the insulator 384 in this order. It is preferable that any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 be formed using a substance having a barrier property to oxygen and hydrogen.

For example, as the insulators 510 and 514, a film having a barrier property such that hydrogen or an impurity is not diffused from a substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided is used. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

As an example of a film having a barrier property to hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may be reduced. Therefore, a film which suppresses diffusion of hydrogen is preferably used between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film from which the amount of desorbed hydrogen is small.

Further, as the film having a barrier property to hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 510 and the insulator 514.

In particular, aluminum oxide has a high blocking effect on both oxygen and impurities such as hydrogen and moisture which cause a change in electric characteristics of a transistor, without passing through the film. Accordingly, the aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. Further, release of oxygen from an oxide included in the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500.

For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 512 and the insulator 516, a silicon oxide film, a silicon oxynitride film, or the like can be used.

In the insulator 510, the insulator 512, the insulator 514, and the insulator 516, a conductor 518, a conductor included in the transistor 500 (a conductor 503), and the like are embedded. Note that the conductor 518 has a function as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.

In particular, the conductor 518 in a region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated from each other with a layer having a barrier property to oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

The transistor 500 is provided over the insulator 516.

As illustrated in FIGS. 11A and 11B, the transistor 500 includes a conductor 503 which is provided so as to be embedded in the insulator 512 and the insulator 516, and is provided over the insulator 516 and the conductor 503. An insulator 520, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, and an oxide An oxide 530b disposed over the oxide 530a; a conductor 542a and a conductor 542b disposed apart from each other over the oxide 530b; and a conductor 542a disposed over the conductor 542a and the conductor 542b. An insulator 580 having an opening formed so as to overlap between the conductors 542b; a conductor 560 arranged in the opening; an oxide 530b; a conductor 542a; a conductor 542b; The insulator 550 is provided between the insulator 580 and the conductor 560, and the insulator 550 is provided between the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580 and the insulator 550. An oxide 530c.

As illustrated in FIGS. 11A and 11B, the insulator 544 is preferably provided between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. . 11A and 11B, a conductor 560 includes a conductor 560a provided inside the insulator 550 and a conductor 560a provided so as to be embedded inside the conductor 560a. 560b. As illustrated in FIGS. 11A and 11B, the insulator 574 is preferably provided over the insulator 580, the conductor 560, and the insulator 550.

Note that in the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as an oxide 530. The conductor 542a and the conductor 542b may be collectively referred to as a conductor 542.

Note that in the transistor 500, a structure in which three layers of an oxide 530a, an oxide 530b, and an oxide 530c are stacked in a region where a channel is formed and in the vicinity thereof is shown; however, the present invention is not limited thereto. Not something. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a stacked structure of four or more layers may be provided. In the transistor 500, the conductor 560 is illustrated as having a two-layer structure, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. Further, the transistor 500 illustrated in FIGS. 10 and 11A and 11B is an example, and there is no limitation on the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.

Here, the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b each function as a source electrode or a drain electrode. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region between the conductors 542a and 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a positioning margin, so that the area occupied by the transistor 500 can be reduced. Thus, miniaturization and high integration of the semiconductor device can be achieved.

Further, since the conductor 560 is formed in a self-aligned manner in a region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Accordingly, parasitic capacitance formed between conductor 560 and conductors 542a and 542b can be reduced. Thus, the switching speed of the transistor 500 can be improved and high frequency characteristics can be provided.

The conductor 560 may function as a first gate (also referred to as a top gate) electrode. In some cases, the conductor 503 functions as a second gate (also referred to as a bottom gate) electrode. In that case, Vth of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential. In particular, by applying a negative potential to the conductor 503, Vth of the transistor 500 can be made higher than 0 V and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be smaller than when no negative potential is applied.

The conductor 503 is provided so as to overlap with the oxide 530 and the conductor 560. Thus, when a potential is applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected to each other, so that a channel formation region formed in the oxide 530 is covered. Can be. In this specification and the like, a structure of a transistor that electrically surrounds a channel formation region with an electric field of the first gate electrode and the electric field of the second gate electrode is referred to as a surrounded channel (S-channel) structure.

The conductor 503 has the same structure as the conductor 518. A conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and a conductor 503b is formed inside.

The insulator 520, the insulator 522, the insulator 524, and the insulator 550 each have a function as a gate insulating film.

Here, as the insulator 524 in contact with the oxide 530, an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used. That is, it is preferable that an excess oxygen region be formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as the insulator having an excess oxygen region. An oxide from which oxygen is desorbed by heating is defined as having an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1 in terms of oxygen atoms, as determined by TDS (Thermal Desorption Spectroscopy) analysis. .0 × ¹⁰ 19 atoms / cm ³ or more, more preferably 2.0 × ¹⁰ 19 atoms / cm ³ or more, or 3.0 × ¹⁰ 20 atoms / cm ³ or more at which the oxide film. Note that the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C to 700 ° C, or 100 ° C to 400 ° C.

In the case where the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing diffusion of oxygen (eg, an oxygen atom or an oxygen molecule) (the oxygen is hardly transmitted).

Since the insulator 522 has a function of suppressing diffusion of oxygen and impurities, oxygen included in the oxide 530 does not diffuse to the insulator 520, which is preferable. In addition, the conductor 503 can be prevented from reacting with oxygen included in the insulator 524 and the oxide 530.

The insulator 522 is formed of, for example, so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator containing a -k material in a single layer or a stack. As the size of a transistor is reduced and the degree of integration is increased, a problem such as a leak current may occur due to a reduction in the thickness of a gate insulating film. With the use of a high-k material for an insulator functioning as a gate insulating film, reduction in gate potential at the time of transistor operation can be performed while the physical thickness is maintained.

In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material having a function of suppressing diffusion of impurities and oxygen (the above oxygen is difficult to transmit), is preferably used. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium. In the case where the insulator 522 is formed using such a material, the insulator 522 suppresses release of oxygen from the oxide 530 and entry of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530. Functions as a layer.

Alternatively, to these insulators, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

It is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Further, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a stacked structure that is thermally stable and has a high relative dielectric constant can be obtained.

Note that the insulator 520, the insulator 522, and the insulator 524 may have a stacked structure of two or more layers. In that case, the structure is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, as the oxide 530, an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, or neodymium , Or one or more selected from hafnium, tantalum, tungsten, magnesium, or the like. Further, as the oxide 530, an In—Ga oxide or an In—Zn oxide may be used.

In the oxide 530, a metal oxide serving as a channel formation region has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a large band gap as described above, off-state current of a transistor can be reduced.

Since the oxide 530 includes the oxide 530a below the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b can be suppressed. In addition, when the oxide 530c is provided over the oxide 530b, diffusion of impurities from a structure formed above the oxide 530c to the oxide 530b can be suppressed.

Note that the oxide 530 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is larger than that in the metal oxide used for the oxide 530b. Is preferred. In the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than that in the metal oxide used for the oxide 530b. In the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than that in the metal oxide used for the oxide 530a. Further, as the oxide 530c, a metal oxide which can be used for the oxide 530a or the oxide 530b can be used.

Further, it is preferable that the energy of the bottom of the conduction band of the oxide 530a and the oxide 530c be higher than the energy of the bottom of the conduction band of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than the electron affinity of the oxide 530b.

Here, at the junction of the oxides 530a, 530b, and 530c, the energy level at the bottom of the conduction band changes gradually. In other words, the energy level at the bottom of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c can be said to be continuously changed or continuously joined. In order to achieve this, the defect state density of a mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c may be reduced.

Specifically, the oxide 530a and the oxide 530b and the oxide 530b and the oxide 530c each have a common element other than oxygen (as a main component), so that a mixed layer having a low density of defect states is formed. be able to. For example, in the case where the oxide 530b is an In-Ga-Zn oxide, an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like may be used as the oxide 530a and the oxide 530c.

At this time, the main path of the carriers is the oxide 530b. With the above structure of the oxides 530a and 530c, the density of defect states at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, influence of carrier scattering due to interface scattering is small, and the transistor 500 can have high on-state current.

A conductor 542 (a conductor 542a and a conductor 542b) functioning as a source electrode and a drain electrode is provided over the oxide 530b. As the conductor 542, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above-described metal element as a component, an alloy in which the above-described metal elements are combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are not easily oxidized. A conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.

In addition, as illustrated in FIG. 11A, a region 543 (a region 543a and a region 543b) is formed as a low-resistance region in and near an interface of the oxide 530 with the conductor 542. is there. At this time, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. Further, a channel formation region is formed in a region between the region 543a and the region 543b.

When the conductor 542 is provided so as to be in contact with the oxide 530, the oxygen concentration in the region 543 may be reduced in some cases. Further, in some cases, a metal compound layer containing a metal contained in the conductor 542 and a component of the oxide 530 is formed in the region 543. In such a case, the carrier density of the region 543 increases, and the region 543 becomes a low-resistance region.

The insulator 544 is provided to cover the conductor 542 and suppresses oxidation of the conductor 542. At this time, the insulator 544 may be provided so as to cover a side surface of the oxide 530 and be in contact with the insulator 524.

As the insulator 544, a metal oxide containing one or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used. it can.

In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later step. Note that the insulator 544 is not an essential component in the case where the conductor 542 has a material having oxidation resistance or has a structure in which conductivity is not significantly reduced even when oxygen is absorbed. An appropriate design may be made according to the required transistor characteristics.

The insulator 550 functions as a gate insulating film. It is preferable that the insulator 550 be provided in contact with the inside (the upper surface and the side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator from which oxygen is released by heating. For example, in TDS analysis, the amount of desorbed oxygen in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ¹⁹ atoms / cm ³ or more, and more preferably 2 × 10 ¹⁹ atoms / cm ³ or more. .0 × ¹⁰ 19 atoms / cm ³ or more, or 3.0 is × ¹⁰ 20 atoms / cm ³ or more is an oxide film. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.

Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and holes are included. Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

By providing an insulator from which oxygen is released by heating as the insulator 550 in contact with the upper surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Can be supplied. Further, similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

In order to efficiently supply excess oxygen included in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

Although the conductor 560 functioning as the first gate electrode is illustrated as a two-layer structure in FIGS. 11A and 11B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. .

Conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule _(N 2 O, NO, etc. NO _2), conductive having a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule). When the conductor 560a has a function of suppressing diffusion of oxygen, the conductivity of the conductor 560b can be suppressed from being reduced by oxidation of the conductor 560b due to oxygen contained in the insulator 550. As the conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

It is preferable that the conductor 560b be formed using a conductive material mainly containing tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, a conductor with high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.

The insulator 580 is provided over the conductor 542 with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having holes Or a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 580 preferably has an excess oxygen region. When the insulator 580 from which oxygen is released by heating is provided in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

The opening of the insulator 580 is formed so as to overlap with a region between the conductor 542a and the conductor 542b. Thus, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region between the conductors 542a and 542b.

In miniaturizing a semiconductor device, it is required to reduce a gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, when the thickness of the conductor 560 is increased, the conductor 560 can have a shape with a high aspect ratio. In this embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, the conductor 560 can be formed without being collapsed during a process even when the conductor 560 has a high aspect ratio. Can be.

The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thus, oxygen can be supplied into the oxide 530 from the excess oxygen region.

For example, as the insulator 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium is used. Can be.

In particular, aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film having a thickness of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by a sputtering method can serve as an oxygen supply source and also have a function as a barrier film for impurities such as hydrogen.

Further, the insulator 581 which functions as an interlayer film is preferably provided over the insulator 574. The insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film, similarly to the insulator 524 and the like.

In addition, the conductor 540a and the conductor 540b are provided in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided to face each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same configuration as the conductor 546 and the conductor 548 described later.

An insulator 582 is provided over the insulator 581. It is preferable that the insulator 582 be formed using a substance having a barrier property to oxygen and hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, for the insulator 582, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.

In particular, aluminum oxide has a high blocking effect on both oxygen and impurities such as hydrogen and moisture which cause a change in electric characteristics of a transistor, without passing through the film. Accordingly, the aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. Further, release of oxygen from an oxide included in the transistor 500 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 500.

An insulator 586 is provided over the insulator 582. For the insulator 586, a material similar to that of the insulator 320 can be used. In addition, by using a material having a relatively low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

In addition, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include a conductor 546, a conductor 548, and the like. Is embedded.

The conductor 546 and the conductor 548 each have a function as a plug or a wiring connected to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be provided using the same material as the conductor 328 and the conductor 330.

Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

Further, the conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug connected to the transistor 500 or a wiring. The conductor 610 has a function as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

The conductor 612 and the conductor 610 each include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements as components. (A tantalum nitride film, a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) or the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. Alternatively, a conductive material such as indium tin oxide may be used.

In FIG. 10, the conductor 612 and the conductor 610 are illustrated as having a single-layer structure; however, the structure is not limited to this, and a stacked structure including two or more layers may be employed. For example, a conductor having a barrier property and a conductor having high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.

The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with another structure such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) may be used.

An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. Further, the insulator 650 may function as a flattening film that covers the uneven shape below the insulator 650.

With the use of this structure, in a semiconductor device including a transistor including an oxide semiconductor, change in electric characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, in a semiconductor device including a transistor including an oxide semiconductor, miniaturization or high integration can be achieved.

<Structure Example of Memory Cell 214>
Here, FIG. 12 is a cross-sectional view in the case where the transistor 500 of the semiconductor device described in this embodiment is applied to the memory cell 214 described in the above embodiment. FIG. 12 illustrates transistors 500a to 500f, and FIG. 12 is a cross-sectional view of the transistors 500a to 500f in a channel length direction.

Note that in FIG. 12, components having the same structure, such as the conductor 518 and the conductor 386, are denoted by reference numerals such as the conductor 518a, the conductor 518b, and the conductor 518c. In FIG. 12, dotted lines indicating the transistors 500a to 500f are smaller than those of the transistor 500 illustrated in FIG.

In addition, the conductor 646 and the conductor 648 are embedded in the insulator 650, and the conductor 646 and the conductor 648 have the same structure as the conductor 546 and the conductor 548; A conductor 660 is provided over the insulator 650. The conductor 660 has the same structure as the conductor 612;

A transistor 500a illustrated in FIG. 12 corresponds to the transistor M21 in the memory cell 214. Hereinafter, similarly, the transistor 500b corresponds to the transistor M22, the transistor 500c corresponds to the transistor M23, the transistor 500d corresponds to the transistor M24, the transistor 500e corresponds to the transistor M25, and the transistor 500f corresponds to the transistor M26.

The conductor 518d functions as a back gate of the transistors 500a to 500d. The conductor 518d is electrically connected to the wiring CAL, and a predetermined potential is applied. That is, a capacitor is formed between the conductor 518d and the channel formation region, the source region, and the drain region of the transistors 500a to 500d. Further, since the source region and the drain region of the transistors 500a to 500d can be arranged adjacent to each other, the area for arranging the transistors 500a to 500d can be reduced.

One of a source and a drain of the transistor 500a is electrically connected to one of a source and a drain of the transistor 500f, and is connected to the conductor 546b, the conductor 548b, the conductor 612a, the conductor 548a, and the conductor 546a. It is electrically connected to the gate of the transistor 500e. That is, the conductor 546b, the conductor 548b, the conductor 612a, the conductor 548a, and the conductor 546a correspond to the node SN1.

As illustrated in FIG. 12, by using an OS transistor with a small off-state current as a transistor included in the memory cell 214, the capacitance of the capacitors C11 to C14 can be reduced. Alternatively, it can be used instead of the capacitor C14. The memory cell 214 can be a small area memory cell.

<Example of transistor structure>
Note that the transistor 500 of the semiconductor device described in this embodiment is not limited to the above structure. Hereinafter, structural examples that can be used for the transistor 500 are described.

<Transistor structure example 1>
An example of the structure of the transistor 510A will be described with reference to FIGS. FIG. 13A is a top view of the transistor 510A. FIG. 13B is a cross-sectional view of a part indicated by a dashed-dotted line L1-L2 in FIG. FIG. 13C is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

In FIGS. 13A, 13B, and 13C, the transistor 510A and an insulator 511, an insulator 512, an insulator 514, an insulator 516, an insulator 580, an insulator 580, an insulator 582, and an insulator functioning as an interlayer film. The body 584 is shown. Further, a conductor 546 (a conductor 546a and a conductor 546b) which is electrically connected to the transistor 510A and functions as a contact plug and a conductor 503 which functions as a wiring are illustrated.

The transistor 510A includes a conductor 560 (a conductor 560a and a conductor 560b) functioning as a first gate electrode, a conductor 505 (a conductor 505a and a conductor 505b) functioning as a second gate electrode, An insulator 550 functioning as a first gate insulating film, an insulator 521, an insulator 522, and an insulator 524 functioning as a second gate insulating film, and an oxide 530 including a region where a channel is formed (oxidized An object 530a, an oxide 530b, and an oxide 530c), a conductor 542a functioning as one of a source and a drain, a conductor 542b functioning as the other of the source and the drain, and an insulator 574.

In the transistor 510A illustrated in FIG. 13, the oxide 530c, the insulator 550, and the conductor 560 are provided in an opening provided in the insulator 580 with the insulator 574 interposed therebetween. The oxide 530c, the insulator 550, and the conductor 560 are provided between the conductor 542a and the conductor 542b.

The insulator 511 and the insulator 512 function as an interlayer film.

As the interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) An insulator such as TiO ₃ (BST) can be used in a single layer or a stacked layer. Alternatively, to these insulators, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

For example, the insulator 511 preferably functions as a barrier film for preventing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, it is preferable that the insulator 511 be formed using an insulating material which has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are hardly transmitted). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above-described oxygen is not easily transmitted). Further, for example, aluminum oxide, silicon nitride, or the like may be used for the insulator 511. With such a structure, impurities such as hydrogen and water can be suppressed from being diffused from the substrate side of the insulator 511 to the transistor 510A side.

For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

The conductor 503 is formed so as to be embedded in the insulator 512. Here, the height of the upper surface of the conductor 503 and the height of the upper surface of the insulator 512 can be approximately the same. Note that the conductor 503 has a single-layer structure, but the present invention is not limited to this. For example, the conductor 503 may have a multilayer structure of two or more layers. Note that the conductor 503 is preferably formed using a highly conductive material mainly containing tungsten, copper, or aluminum.

In the transistor 510A, the conductor 560 may function as a first gate (also referred to as a top gate) electrode in some cases. In some cases, the conductor 505 functions as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 510A can be controlled by changing the potential applied to the conductor 505 independently of the potential applied to the conductor 560 without changing the potential. In particular, by applying a negative potential to the conductor 505, the threshold voltage of the transistor 510A can be made higher than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 505, the drain current when the potential applied to the conductor 560 is 0 V can be smaller than when no potential is applied.

For example, when a potential is applied to the conductor 560 and the conductor 505 by providing the conductor 505 and the conductor 560 so as to overlap with each other, an electric field generated from the conductor 560 and an electric field generated from the conductor 505 are provided. And are connected to each other, so that a channel formation region formed in the oxide 530 can be covered.

That is, the channel formation region can be electrically surrounded by the electric field of the conductor 560 having a function as the first gate electrode and the electric field of the conductor 505 having a function of the second gate electrode. In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

The insulator 514 and the insulator 516 each function as an interlayer film, similarly to the insulator 511 or the insulator 512. For example, the insulator 514 preferably functions as a barrier film for preventing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. With such a structure, diffusion of impurities such as hydrogen and water from the substrate to the transistor 510A relative to the insulator 514 can be suppressed. For example, the insulator 516 preferably has a lower dielectric constant than the insulator 514. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

In the conductor 505 functioning as a second gate, a conductor 505a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and a conductor 505b is formed further inside. Here, the heights of the top surfaces of the conductors 505a and 505b and the top surface of the insulator 516 can be approximately the same. Note that although the transistor 510A has a structure in which the conductor 505a and the conductor 505b are stacked, the present invention is not limited to this. For example, the conductor 505 may have a single-layer structure or a stacked structure of three or more layers.

Here, it is preferable that the conductor 505a be formed using a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are difficult to transmit). Alternatively, it is preferable to use a conductive material which has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is hardly permeated). Note that in this specification, the function of suppressing diffusion of an impurity or oxygen refers to a function of suppressing the diffusion of one or all of the impurity or the oxygen.

For example, when the conductor 505a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductor 505b from being oxidized and the conductivity being reduced.

In the case where the conductor 505 also functions as a wiring, the conductor 505b is preferably formed using a conductive material having high conductivity and mainly containing tungsten, copper, or aluminum. In that case, the conductor 503 is not necessarily provided. Although the conductor 505b is illustrated as a single layer, the conductor 505b may have a stacked structure, for example, a stacked layer of titanium or titanium nitride and the above conductive material.

The insulator 521, the insulator 522, and the insulator 524 have a function as a second gate insulating film.

Further, the insulator 522 preferably has a barrier property. When the insulator 522 has a barrier property, the insulator 522 functions as a layer for preventing impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A.

The insulator 522 is formed using, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or ( An insulator containing a so-called high-k material such as Ba, Sr) TiO ₃ (BST) is preferably used in a single layer or a stacked layer. As the size of a transistor is reduced and the degree of integration is increased, a problem such as a leak current may occur due to a reduction in the thickness of a gate insulating film. With the use of a high-k material for an insulator functioning as a gate insulating film, reduction in gate potential at the time of transistor operation can be performed while the physical thickness is maintained.

Further, the insulator 521 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 521 having a stacked structure that is thermally stable and has a high relative dielectric constant can be obtained.

Note that FIG. 13 illustrates a stacked structure of three layers as the second gate insulating film; however, a single layer or a stacked structure of two or more layers may be used. In that case, the structure is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

The oxide 530 including a region functioning as a channel formation region includes an oxide 530a, an oxide 530b over the oxide 530a, and an oxide 530c over the oxide 530b. When the oxide 530a is provided below the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b can be suppressed. In addition, when the oxide 530c is provided over the oxide 530b, diffusion of impurities from a structure formed above the oxide 530c to the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor which is one of the above-described metal oxides can be used.

Note that the oxide 530c is preferably provided in the opening provided in the insulator 580 with the insulator 574 interposed therebetween. In the case where the insulator 574 has a barrier property, diffusion of impurities from the insulator 580 to the oxide 530 can be suppressed.

One of the conductors 542 functions as a source electrode, and the other functions as a drain electrode.

As the conductor 542a and the conductor 542b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing this as a main component can be used. . In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

Although FIG. 13 shows a single-layer structure, a stacked structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be stacked. Further, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and A two-layer structure in which copper films are stacked may be employed.

Further, a titanium film or a titanium nitride film, a three-layer structure in which an aluminum film or a copper film is stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film, an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereover. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

Further, a barrier layer may be provided over the conductor 542. For the barrier layer, a substance having a barrier property to oxygen or hydrogen is preferably used. With this structure, oxidation of the conductor 542 can be suppressed when the insulator 574 is formed.

For example, a metal oxide can be used for the barrier layer. In particular, it is preferable to use an insulating film having a barrier property to oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Alternatively, silicon nitride formed by a CVD method may be used.

With the barrier layer, the range of choice of the material of the conductor 542 can be increased. For example, a material having low oxidation resistance and high conductivity such as tungsten or aluminum can be used for the conductor 542. Alternatively, for example, a conductor which can be easily formed or processed can be used.

The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably provided in the opening provided in the insulator 580 with the oxide 530c and the insulator 574 interposed therebetween.

As the size of a transistor is reduced and the degree of integration is increased, a problem such as a leak current may occur due to a reduction in the thickness of a gate insulating film. In that case, the insulator 550 may have a stacked structure as in the case of the second gate insulating film. By forming the insulator functioning as a gate insulating film into a stacked structure of a high-k material and a thermally stable material, the gate potential during transistor operation can be reduced while maintaining the physical thickness. Becomes Further, a laminated structure which is thermally stable and has a high relative dielectric constant can be obtained.

The conductor 560 functioning as a first gate electrode includes a conductor 560a and a conductor 560b over the conductor 560a. Like the conductor 505a, the conductor 560a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule).

When the conductor 560a has a function of suppressing oxygen diffusion, material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

As the conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Alternatively, an oxide semiconductor that can be used as the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b by a sputtering method, the electric resistance of the conductor 560a can be reduced to be a conductor. This can be called an OC (Oxide Conductor) electrode.

The conductor 560b is preferably formed using a conductive material mainly containing tungsten, copper, or aluminum. In addition, since the conductor 560 functions as a wiring, a conductor with high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.

An insulator 574 is provided between the insulator 580 and the transistor 510A. The insulator 574 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.

With the insulator 574, diffusion of impurities such as water and hydrogen included in the insulator 580 to the oxide 530b through the oxide 530c and the insulator 550 can be suppressed. Further, oxidation of the conductor 560 due to excess oxygen included in the insulator 580 can be suppressed.

The insulator 580, the insulator 582, and the insulator 584 function as an interlayer film.

Like the insulator 514, the insulator 582 preferably functions as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 510A from the outside.

In addition, the insulator 580 and the insulator 584 preferably have a lower dielectric constant than the insulator 582, similarly to the insulator 516. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

Further, the transistor 510A may be electrically connected to another structure through a plug or a wiring such as the conductor 546 embedded in the insulator 580, the insulator 582, and the insulator 584.

As the material of the conductor 546, a single layer or a stacked layer of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as in the case of the conductor 505. . For example, it is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.

For example, by using a stacked structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten with high conductivity as the conductor 546, the conductivity as a wiring is maintained. In addition, diffusion of impurities from the outside can be suppressed.

With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which fluctuation in electric characteristics is suppressed, stable electric characteristics are improved, and reliability is improved.

<Transistor structural example 2>
A structural example of the transistor 510B will be described with reference to FIGS. FIG. 14A is a top view of the transistor 510B. FIG. 14B is a cross-sectional view of a part indicated by a dashed-dotted line L1-L2 in FIG. FIG. 14C is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

The transistor 510B is a modification example of the transistor 510A. Therefore, in order to prevent the description from being repeated, points different from the transistor 510A will be mainly described.

The transistor 510B includes a region where the conductor 542 (the conductor 542a and the conductor 542b) overlaps with the oxide 530c, the insulator 550, and the conductor 560. With such a structure, a transistor with high on-state current can be provided. Further, a transistor with high controllability can be provided.

The conductor 560 functioning as a first gate electrode includes a conductor 560a and a conductor 560b over the conductor 560a. Like the conductor 505a, the conductor 560a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule).

When the conductor 560a has a function of suppressing oxygen diffusion, material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

Further, the insulator 574 is preferably provided so as to cover the top surface and the side surface of the conductor 560, the side surface of the insulator 550, and the side surface of the oxide 530c. Note that the insulator 574 may be formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.

By providing the insulator 574, oxidation of the conductor 560 can be suppressed. Further, with the use of the insulator 574, diffusion of impurities such as water and hydrogen included in the insulator 580 to the transistor 510B can be suppressed.

In addition, an insulator 576 having a barrier property (an insulator 576a and an insulator 576b) may be provided between the conductor 546 and the insulator 580. With the provision of the insulator 576, oxygen in the insulator 580 reacts with the conductor 546 and oxidation of the conductor 546 can be suppressed.

In addition, by providing the insulator 576 having a barrier property, the range of selection of a material of a conductor used for a plug or a wiring can be increased. For example, by using a metal material having high conductivity while absorbing oxygen for the conductor 546, a semiconductor device with low power consumption can be provided. Specifically, a material having high conductivity while having low oxidation resistance, such as tungsten or aluminum, can be used. Alternatively, for example, a conductor which can be easily formed or processed can be used.

<Transistor structural example 3>
An example of the structure of the transistor 510C will be described with reference to FIGS. FIG. 15A is a top view of the transistor 510C. FIG. 15B is a cross-sectional view of a portion indicated by a dashed-dotted line L1-L2 in FIG. FIG. 15C is a cross-sectional view of a part indicated by a dashed-dotted line W1-W2 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

The transistor 510C is a modification example of the transistor 510A. Therefore, in order to prevent the description from being repeated, points different from the transistor 510A will be mainly described.

In the transistor 510C illustrated in FIG. 15, the conductor 547a is provided between the conductor 542a and the oxide 530b, and the conductor 547b is provided between the conductor 542b and the oxide 530b. Here, the conductor 542a (conductor 542b) extends beyond the upper surface of the conductor 547a (conductor 547b) and the side surface on the conductor 560 side, and has a region in contact with the upper surface of the oxide 530b. Here, as the conductor 547, a conductor which can be used for the conductor 542 may be used. Further, the thickness of the conductor 547 is preferably at least larger than that of the conductor 542.

With the above structure, the transistor 510C illustrated in FIG. 15 can have the conductor 542 closer to the conductor 560 than the transistor 510A. Alternatively, the conductor 560 can overlap with an end portion of the conductor 542a and an end portion of the conductor 542b. Thus, the substantial channel length of the transistor 510C can be reduced, and on-state current and frequency characteristics can be improved.

Further, the conductor 547a (the conductor 547b) is preferably provided so as to overlap with the conductor 542a (the conductor 542b). With such a structure, in the etching for forming the opening in which the conductor 546a (the conductor 546b) is formed, the conductor 547a (the conductor 547b) functions as a stopper and the oxide 530b is not over-etched. Can be prevented.

The transistor 510C illustrated in FIG. 15 may have a structure in which the insulator 545 is provided in contact with the insulator 544. It is preferable that the insulator 544 function as a barrier insulating film for preventing impurities such as water or hydrogen and excess oxygen from entering the transistor 510C from the insulator 580 side. As the insulator 545, an insulator that can be used for the insulator 544 can be used. Further, as the insulator 544, a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide may be used, for example.

Further, the transistor 510C illustrated in FIG. 15 may be different from the transistor 510A illustrated in FIG. 13 in that the conductor 505 has a single-layer structure. In this case, an insulating film serving as the insulator 516 is formed over the patterned conductor 505, and the upper portion of the insulating film is removed by a CMP method or the like until the upper surface of the conductor 505 is exposed. Good. Here, it is preferable that the flatness of the upper surface of the conductor 505 be improved. For example, the average surface roughness (Ra) of the upper surface of the conductor 505 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, planarity of the insulating layer formed over the conductor 505 can be improved and crystallinity of the oxides 530b and 530c can be improved.

<Transistor structural example 4>
An example of the structure of the transistor 510D is described with reference to FIGS. 16A, 16B, and 16C. FIG. 16A is a top view of the transistor 510D. FIG. 16B is a cross-sectional view of a part indicated by a dashed-dotted line L1-L2 in FIG. FIG. 16C is a cross-sectional view of a part indicated by a dashed-dotted line W1-W2 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

The transistor 510D is a modification example of the above transistor. Therefore, in order to prevent repetition of the description, points different from the above transistor are mainly described.

In FIGS. 16A to 16C, the conductor 505 having a function as a second gate also functions as a wiring without providing the conductor 503. Further, the insulator 550 is provided over the oxide 530c and the metal oxide 552 is provided over the insulator 550. Further, the conductor 560 is provided over the metal oxide 552 and the insulator 570 is provided over the conductor 560. Further, an insulator 571 is provided over the insulator 570.

The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 for suppressing diffusion of oxygen between the insulator 550 and the conductor 560, diffusion of oxygen to the conductor 560 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductor 560 by oxygen can be suppressed.

Note that the metal oxide 552 may have a function as part of the first gate. For example, an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552. In that case, by forming the conductor 560 by a sputtering method, the electric resistance of the metal oxide 552 can be reduced and the metal oxide 552 can be formed as a conductive layer. This can be called an OC (Oxide Conductor) electrode.

Further, the metal oxide 552 may have a function as part of the gate insulating film in some cases. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 550, the metal oxide 552 is preferably a high-k metal oxide having a high relative dielectric constant. With such a stacked structure, a stacked structure which is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during the operation of the transistor while maintaining the physical film thickness. Further, the equivalent oxide thickness (EOT) of the insulating layer functioning as a gate insulating film can be reduced.

In the transistor 510D, the metal oxide 552 is illustrated as a single layer; however, a stacked structure including two or more layers may be used. For example, a metal oxide functioning as part of a gate electrode and a metal oxide functioning as part of a gate insulating film may be stacked.

When the metal oxide 552 functions as a gate electrode, the on-state current of the transistor 510D can be improved without weakening the influence of an electric field from the conductor 560. Alternatively, in the case of functioning as a gate insulating film, the distance between the conductor 560 and the oxide 530 is maintained by the physical thickness of the insulator 550 and the metal oxide 552, so that Leakage current with the oxide 530 can be suppressed. Therefore, by providing a stacked structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the electric field strength applied from the conductor 560 to the oxide 530 can be reduced. It can be easily adjusted appropriately.

Specifically, an oxide semiconductor that can be used for the oxide 530 is reduced in resistance as the metal oxide 552, so that the oxide semiconductor can be used as the metal oxide 552. Alternatively, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulating layer containing one or both oxides of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later step. Note that the metal oxide 552 is not an essential component. An appropriate design may be made according to the required transistor characteristics.

The insulator 570 may be formed using an insulating material having a function of suppressing transmission of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. Accordingly, oxidation of the conductor 560 by oxygen from above the insulator 570 can be suppressed. In addition, entry of impurities such as water or hydrogen from above the insulator 570 into the oxide 530 through the conductor 560 and the insulator 550 can be suppressed.

The insulator 571 functions as a hard mask. By providing the insulator 571, when processing the conductor 560, the side surface of the conductor 560 is substantially vertical, specifically, the angle formed by the side surface of the conductor 560 and the substrate surface is 75 degrees or more and 100 degrees or less, Preferably, it can be 80 degrees or more and 95 degrees or less.

Note that the insulator 571 may also serve as a barrier layer by using an insulating material having a function of suppressing transmission of impurities such as water or hydrogen and oxygen. In that case, the insulator 570 may not be provided.

The insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and part of the oxide 530c are selectively removed with the use of the insulator 571 as a hard mask so that their side surfaces are substantially aligned with each other. In addition, part of the surface of the oxide 530b can be exposed.

Further, the transistor 510D includes a region 531a and a region 531b in part of the surface of the oxide 530b which is exposed. One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region.

The regions 531a and 531b are formed by, for example, introducing an impurity element such as phosphorus or boron into the exposed surface of the oxide 530b by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like. This can be achieved by: Note that in this embodiment and the like, the “impurity element” refers to an element other than the main component element.

In addition, a metal film is formed after part of the surface of the oxide 530b is exposed, and heat treatment is performed thereon, so that an element included in the metal film is diffused into the oxide 530b to form a region 531a and a region 531b. You can also.

In a region where the impurity element of the oxide 530b is introduced, electric resistivity is reduced. Therefore, the region 531a and the region 531b may be referred to as an "impurity region" or a "low resistance region".

With the use of the insulator 571 and / or the conductor 560 as a mask, the region 531a and the region 531b can be formed in a self-aligned manner. Therefore, the conductor 560 does not overlap with the region 531a and / or the region 531b, so that parasitic capacitance can be reduced. Further, no offset region is formed between the channel formation region and the source / drain region (the region 531a or the region 531b). By forming the regions 531a and 531b in a self-aligned manner (self-alignment), an increase in on-state current, a reduction in threshold voltage, an increase in operation frequency, and the like can be realized.

Note that an offset region may be provided between the channel formation region and the source / drain region in order to further reduce the off-state current. The offset region is a region where the electrical resistivity is high, and is a region where the above-described impurity element is not introduced. The offset region can be formed by introducing the above-described impurity element after the formation of the insulator 575. In this case, the insulator 575 also functions as a mask similarly to the insulator 571 and the like. Therefore, an impurity element is not introduced into a region of the oxide 530b which overlaps with the insulator 575, so that the region can have high electrical resistivity.

The transistor 510D includes an insulator 570, a conductor 560, a metal oxide 552, an insulator 550, and an insulator 575 on a side surface of the oxide 530c. The insulator 575 is preferably an insulator having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or resin. Preferably, there is. In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes for the insulator 575 because an excess oxygen region can be easily formed in the insulator 575 in a later step. Further, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Further, the insulator 575 preferably has a function of diffusing oxygen.

Further, the transistor 510D includes an insulator 574 over the insulator 575 and the oxide 530. The insulator 574 is preferably formed by a sputtering method. By using a sputtering method, an insulator with little impurities such as water or hydrogen can be formed. For example, aluminum oxide may be used for the insulator 574.

Note that an oxide film formed by a sputtering method may extract hydrogen from a structure to be formed. Therefore, when the insulator 574 absorbs hydrogen and water from the oxide 530 and the insulator 575, the hydrogen concentration in the oxide 530 and the insulator 575 can be reduced.

<Transistor structural example 5>
17A to 17C, a structural example of the transistor 510E is described. FIG. 17A is a top view of the transistor 510E. FIG. 17B is a cross-sectional view of a part indicated by a dashed-dotted line L1-L2 in FIG. FIG. 17C is a cross-sectional view of a part indicated by a dashed-dotted line W1-W2 in FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

The transistor 510E is a modification of the above transistor. Therefore, in order to prevent repetition of the description, points different from the above transistor are mainly described.

In FIGS. 17A to 17C, a region 531a and a region 531b are provided over part of an exposed surface of the oxide 530b without providing the conductor 542. One of the region 531a and the region 531b functions as a source region, and the other functions as a drain region. In addition, an insulator 573 is provided between the oxide 530b and the insulator 574.

A region 531 (a region 531a and a region 531b) illustrated in FIG. 17 is a region in which the following element is added to the oxide 530b. The region 531 can be formed by using, for example, a dummy gate.

Specifically, a dummy gate may be provided over the oxide 530b, and an element which reduces the resistance of the oxide 530b may be added using the dummy gate as a mask. That is, the element is added to a region where the oxide 530 does not overlap with the dummy gate, so that a region 531 is formed. As the method for adding the element, an ion implantation method in which an ionized source gas is added by mass separation, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like. Can be used.

Note that as an element for reducing the resistance of the oxide 530, boron or phosphorus is typically given. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas, or the like may be used. Representative examples of the rare gas include helium, neon, argon, krypton, and xenon. The concentration of the element may be measured by using secondary ion mass spectrometry (SIMS) or the like.

In particular, boron and phosphorus are preferable because an apparatus of a production line of amorphous silicon or low-temperature polysilicon can be used. Existing equipment can be diverted and equipment investment can be reduced.

Subsequently, an insulating film to be the insulator 573 and an insulating film to be the insulator 574 may be formed over the oxide 530b and the dummy gate. By stacking and providing the insulating film to be the insulator 573 and the insulating film to be the insulator 574, a region where the region 531 overlaps with the oxide 530c and the insulator 550 can be provided.

Specifically, after providing an insulating film to be the insulator 580 over the insulating film to be the insulator 574, the insulating film to be the insulator 580 is subjected to a CMP (Chemical Mechanical Polishing) process, so that the insulator 580 and the insulator 580 are formed. A part of the insulating film is removed to expose the dummy gate. Subsequently, when removing the dummy gate, a part of the insulator 573 which is in contact with the dummy gate may be removed. Therefore, the insulator 574 and the insulator 573 are exposed on the side surface of the opening provided in the insulator 580, and part of the region 531 provided in the oxide 530b is exposed on the bottom surface of the opening. I do. Next, after an oxide film to be the oxide 530c, an insulating film to be the insulator 550, and a conductive film to be the conductor 560 are sequentially formed in the opening, a CMP process or the like is performed until the insulator 580 is exposed. By removing part of the oxide film to be the oxide 530c, the insulating film to be the insulator 550, and part of the conductive film to be the conductor 560, the transistor illustrated in FIGS.

Note that the insulator 573 and the insulator 574 are not essential components. An appropriate design may be made according to the required transistor characteristics.

In the transistor illustrated in FIGS. 17A and 17B, an existing device can be used and the conductor 542 is not provided; thus, cost can be reduced.

<Structural example 6 of transistor>
10 and 11 illustrate an example in which the conductor 560 having a function as a gate is formed inside the opening of the insulator 580; for example, the conductor 560 is provided above the conductor. A structure provided with a body can also be used. FIGS. 18 and 19 show structural examples of such a transistor.

FIG. 18A is a top view of a transistor, and FIG. 18B is a perspective view of the transistor. A cross-sectional view taken along line X1-X2 in FIG. 18A is shown in FIG. 19A, and a cross-sectional view taken along Y1-Y2 is shown in FIG.

The transistors illustrated in FIGS. 18 and 19 include a conductor BGE having a function as a back gate, an insulator BGI having a function as a gate insulating film, an oxide semiconductor S, and an insulating material having a function as a gate insulating film. A body FGI, a conductor FGE having a function as a front gate, and a conductor WE having a function as a wiring. In addition, the conductor PE has a function as a plug for connecting the conductor WE to the oxide S, the conductor BGE, or the conductor FGE. Note that here, an example is shown in which the oxide semiconductor S includes three layers of oxides S1, S2, and S3.

<Electrical characteristics of transistor>
Next, electric characteristics of the OS transistor are described. Hereinafter, a transistor having a first gate and a second gate will be described as an example. The threshold voltage of the transistor including the first gate and the second gate can be controlled by applying different potentials to the first gate and the second gate. For example, by applying a negative potential to the second gate, the threshold voltage of the transistor can be higher than 0 V and the off-state current can be reduced. That is, by applying a negative potential to the second gate, the drain current when the potential applied to the first electrode is 0 V can be reduced.

In addition, when an impurity such as hydrogen is added to an oxide semiconductor, carrier density may increase. For example, in some cases, when hydrogen is added, an oxide semiconductor reacts with oxygen that is bonded to a metal atom to become water and forms oxygen vacancies. When hydrogen enters the oxygen vacancy, the carrier density increases. Further, part of hydrogen may bond with oxygen which is bonded to a metal atom to generate an electron serving as a carrier. That is, the oxide semiconductor to which impurities such as hydrogen are added becomes n-type and has low resistance.

Therefore, the resistance of the oxide semiconductor can be reduced selectively. That is, an oxide semiconductor includes a region having a low carrier density and functioning as a semiconductor functioning as a channel formation region and a region having a high carrier density and a low-resistance region functioning as a source region or a drain region. it can.

Here, in the case where different potentials are applied to the first gate and the second gate, the influence of the structure of the low-resistance region and the high-resistance region provided in the oxide semiconductor on the electrical characteristics of the transistor is evaluated.

[Transistor structure]
FIGS. 20A and 20C are cross-sectional views of a transistor used for evaluation of electric characteristics. Note that FIGS. 20A and 20C do not illustrate some components for clarity.

The transistors illustrated in FIGS. 20A and 20C each include a conductor FGE functioning as a first gate, an insulator TGI functioning as a first gate insulating film (denoted as FGI in the drawing), An insulator SW functioning as a sidewall provided on a side surface of the first gate; an oxide semiconductor S; a conductor BGE functioning as a second gate; and an insulator BGI functioning as a second gate insulating film And The insulator BGI has a three-layer structure including a first layer in contact with the conductor BGE, a second layer on the first layer, and a third layer on the second layer. Note that the third layer is in contact with the oxide semiconductor S.

Here, the oxide semiconductor S included in the transistor illustrated in FIG. 20A includes an n + region and an i region that overlaps with the conductor FGE. On the other hand, the oxide semiconductor S included in the transistor illustrated in FIG. 20C includes an n + region, an i region overlapping with the conductor FGE, and an n − region between the n + region and the i region.

Note that the n + region functions as a source region or a drain region, and has a high carrier density and a low resistance. Further, the i region is a high resistance region that functions as a channel formation region and has a lower carrier density than the n + region. The n− region is a region having a lower carrier density than the n + region and a higher carrier density than the i region.

Although not illustrated, the n + region of the oxide semiconductor S has a structure in contact with an S / D electrode functioning as a source or a drain.

[Evaluation results of electrical characteristics]
In the transistor illustrated in FIG. 20A and the transistor illustrated in FIG. 20C, Id-Vg characteristics were calculated and electric characteristics of the transistors were evaluated.

Here, a change amount (hereinafter, also referred to as ΔVsh) of a threshold voltage (hereinafter, also referred to as Vsh) of the transistor was used as an index of the electrical characteristics of the transistor. Note that Vsh is defined as the value of Vg when Id = 1.0 × 10 ⁻¹² [A] in the Id-Vg characteristics.

Note that the Id-Vg characteristics are obtained by changing a potential (hereinafter, also referred to as a gate potential (Vg)) applied to a conductor FGE functioning as a first gate of a transistor from a first value to a second value. Of the current (hereinafter, also referred to as drain current (Id)) between the source and the drain when the current flows.

Here, the potential between the source and the drain (hereinafter, also referred to as drain potential Vd) is +0.1 V, and the potential between the source and the conductor FGE functioning as the first gate is from -1 V to +4 V. The change of the drain current (Id) when it was changed was evaluated.

The calculation was performed using a device simulator ATLAS manufactured by Silvaco. The table below shows the parameters used in the calculations. Eg is an energy gap, Nc is an effective state density of a conduction band, and Nv is an effective state density of a valence band.

In the transistor illustrated in FIG. 20A, the n + region on one side is set to 700 nm and the n− region on one side is set to 0 nm. In the transistor illustrated in FIG. 20C, the n + region on one side is set to 655 nm and the n− region on one side is set to 45 nm. In the transistor illustrated in FIG. 20A and the transistor illustrated in FIG. 20C, the second gate has a structure larger than the i-region. Note that in this evaluation, the potential of the conductor BGE functioning as a second gate (hereinafter, also referred to as a back gate potential (Vbg)) was set to 0.00 V, -3.00 V, or -6.00 V. .

FIG. 20B illustrates the results of the Id-Vg characteristics obtained by calculation of the transistor illustrated in FIG. When the back gate potential was −3.00 V, the amount of change in the threshold voltage of the transistor (ΔVsh) was +1.2 V, as compared to when the back gate potential was set to 0.00 V. In addition, when the back gate potential was −6.00 V, the amount of change in the threshold voltage of the transistor (ΔVsh) was +2.3 V, as compared to when the back gate potential was 0.00 V. That is, when the back gate potential was set to −6.00 V, the amount of change in the threshold voltage of the transistor (ΔVsh) was +1.1 V, as compared with the case where the back gate potential was set to −3.00 V. Therefore, even when the potential of the conductor BGE functioning as the second gate was increased, the amount of change in the threshold voltage of the transistor hardly changed. Even when the back gate potential (absolute value) was increased, no change was observed in the rising characteristics.

FIG. 20D illustrates the results of the Id-Vg characteristics obtained by calculation of the transistor illustrated in FIG. When the back gate potential was −3.00 V, the amount of change in the threshold voltage of the transistor (ΔVsh) was +1.2 V, as compared to when the back gate potential was set to 0.00 V. In addition, when the back gate potential was −6.00 V, the amount of change in the threshold voltage of the transistor (ΔVsh) was +3.5 V, as compared to when the back gate potential was 0.00 V. That is, when the back gate potential was −6.00 V, the amount of change in the threshold voltage of the transistor (ΔVsh) was +2.3 V, as compared with the case where the back gate potential was −3.00 V. Therefore, as the potential (absolute value) of the conductor BGE functioning as the second gate was increased, the amount of change in the threshold voltage of the transistor was increased. On the other hand, as the back gate potential (absolute value) increases, the rising characteristics deteriorate.

From the above, it was found that in the transistor illustrated in FIG. 20C, as the potential (absolute value) of the conductor BGE functioning as the second gate was increased, the amount of change in the threshold voltage of the transistor was increased. On the other hand, in the transistor illustrated in FIG. 20A, even when the potential (absolute value) of the conductor BGE functioning as the second gate is increased, a change in the amount of change in the threshold voltage of the transistor is hardly observed. Was.

Note that this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 4)
In this embodiment, a structure of a metal oxide that can be used for the OS transistor described in the above embodiment will be described.

<Structure of metal oxide>
In this specification and the like, CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be used. Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or structure of a material.

The CAC-OS or CAC-metal oxide has a conductive function in part of a material, an insulating function in part of the material, and a semiconductor function as a whole of the material. Note that in the case where the CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a carrier. This function does not allow electrons to flow. A switching function (on / off function) can be given to the CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In the CAC-OS or CAC-metal oxide, by separating the respective functions, both functions can be maximized.

Further, the CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In some cases, a conductive region and an insulating region are separated at a nanoparticle level in a material. Further, the conductive region and the insulating region may be unevenly distributed in the material. In some cases, the conductive region is observed with its periphery blurred and connected in a cloud shape.

In the CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material in a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

Further, CAC-OS or CAC-metal oxide includes components having different band gaps. For example, a CAC-OS or a CAC-metal oxide includes a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, in the case where the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained when the transistor is on.

That is, the CAC-OS or the CAC-metal oxide may be referred to as a matrix composite or a metal matrix composite.

<Structure of metal oxide>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As a non-single-crystal oxide semiconductor, for example, a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), or a pseudo-amorphous oxide semiconductor (a-like) OS includes amorphous-like oxide semiconductor (OS) and an amorphous oxide semiconductor.

It is preferable to use a thin film with high crystallinity as an oxide semiconductor used for a semiconductor of the transistor. With the use of the thin film, stability or reliability of the transistor can be improved. Examples of the thin film include a single crystal oxide semiconductor thin film and a polycrystalline oxide semiconductor thin film. However, forming a thin film of a single crystal oxide semiconductor or a thin film of a polycrystalline oxide semiconductor over a substrate requires a high-temperature or laser heating step. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

It was reported in Non-Patent Documents 1 and 2 that an In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, crystal grain boundaries are not clearly observed, and can be formed on a substrate at a low temperature. Further, it is reported that a transistor using CAAC-IGZO has excellent electric characteristics and reliability.

In 2013, an In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it has been reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and that there is no regularity in the crystal orientation between different regions. I have.

Non-Patent Documents 4 and 5 show changes in the average crystal size due to the irradiation of electron beams to the thin films of the above-described CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity. In an IGZO thin film having low crystallinity, crystalline IGZO of about 1 nm has been observed even before irradiation with an electron beam. Therefore, it is reported here that the existence of a completely amorphous structure in IGZO could not be confirmed. Furthermore, it is shown that the CAAC-IGZO thin film and the nc-IGZO thin film have higher stability to electron beam irradiation than the IGZO thin film having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.

The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in an ab plane direction and has a strain. Note that the strain refers to a region where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and a region where another lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.

The nanocrystal is basically a hexagon, but is not limited to a regular hexagon and may be a non-regular hexagon. In addition, distortion may have a lattice arrangement such as a pentagon and a heptagon. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be found even in the vicinity of a strain. That is, it is understood that the formation of the crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction, or the bonding distance between atoms changes by substitution with a metal element. It is thought to be.

The CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be referred to as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced with the element M, it can be referred to as an (In, M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, in the CAAC-OS, a crystal grain boundary cannot be clearly observed, so that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, the crystallinity of the oxide semiconductor may be reduced due to entry of impurities, generation of defects, or the like; thus, the CAAC-OS can be regarded as an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor including a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. Further, the CAAC-OS is stable even at a high temperature (so-called thermal budget) in a manufacturing process. Therefore, when a CAAC-OS is used for an OS transistor, the degree of freedom in a manufacturing process can be increased.

The nc-OS has a periodic atomic arrangement in a minute region (for example, a region with a thickness of 1 nm to 10 nm, particularly, a region with a size of 1 nm to 3 nm). In the nc-OS, there is no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors have a variety of structures, each having different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<Transistor including oxide semiconductor>
Next, the case where the above oxide semiconductor is used for a transistor is described.

Note that by using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

In addition, a transistor including the above oxide semiconductor has extremely low leakage current in a non-conduction state; specifically, the off-state current per 1 μm of channel width of the transistor is in the order of yA / μm (10 ⁻²⁴ A / μm). Is shown in Non-Patent Document 6. For example, a low-power-consumption CPU utilizing the characteristic of a transistor including an oxide semiconductor with low leakage current is disclosed (see Non-Patent Document 7).

In addition, application of a transistor including an oxide semiconductor to a display device, which utilizes the characteristic of a transistor with low leakage current, has been reported (see Non-Patent Document 8). In the display device, the displayed image switches several tens of times per second. The number of times the image is switched per second is called a refresh rate. Also, the refresh rate may be called a drive frequency. Such high-speed switching of the screen, which is difficult for the human eyes to perceive, is considered as a cause of eye fatigue. Therefore, it has been proposed to decrease the refresh rate of the display device to reduce the number of times of rewriting of the image. Further, power consumption of the display device can be reduced by driving with a reduced refresh rate. Such a driving method is called idling stop (IDS) driving.

It is preferable to use an oxide semiconductor with a low carrier density for the transistor. In the case where the carrier density of the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect states may be reduced. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. cm ³ or more.

In addition, since the oxide semiconductor film having high purity intrinsic or substantially high purity intrinsic has a low density of defect states, the density of trap states may be low in some cases.

Further, the charge trapped in the trap level of the oxide semiconductor takes a long time to be lost, and may behave as a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electric characteristics in some cases.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in an adjacent film. Examples of the impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

<Impurities>
Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon which is one of Group 14 elements is included in the oxide semiconductor, a defect level is formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density is increased, and the oxide semiconductor is easily made n-type. As a result, a transistor including an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Therefore, it is preferable that nitrogen in the oxide semiconductor be reduced as much as possible. For example, the concentration of nitrogen in an oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less in SIMS. Preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancy, an electron serving as a carrier may be generated. Further, part of hydrogen may bond with oxygen which is bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is lower than 1 × 10 ²⁰ atoms / cm ³ , preferably lower than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably lower than 5 × 10 ¹⁸ atoms / cm 3. ^{It is set to} less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor with sufficiently reduced impurities for a channel formation region of a transistor, stable electric characteristics can be provided.

The discovery of the CAAC structure and the nc structure contributes to improvement in electrical characteristics and reliability of a transistor including an oxide semiconductor having the CAAC structure or the nc structure, reduction in manufacturing process cost, and improvement in throughput. In addition, research on application of the transistor to a display device and an LSI utilizing the characteristic of the transistor having a low leakage current has been advanced.

Note that this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 5)
In this embodiment, an example of an electronic device in which the storage device described in the above embodiment can be used will be described. 21 to 24 illustrate examples of electronic devices each including the storage device according to one embodiment of the present invention.

<Electronic equipment>
The storage device according to one embodiment of the present invention can be used for various electronic devices. In particular, the storage device according to one embodiment of the present invention can be used as a memory built in an electronic device. Hereinafter, a system including an information terminal, a game machine, an electric appliance, a mobile object, a parallel computer, a server, and the like will be described as examples of electronic devices that can use the storage device according to one embodiment of the present invention.

For example, an information terminal 5500 is illustrated in FIG. 21A as an electronic device in which a storage device according to one embodiment of the present invention can be used. Information terminal 5500 is a mobile phone (smartphone). The information terminal 5500 includes a housing 5510 and a display portion 5511. As the input interface, a touch panel is provided in the display portion 5511, and buttons are provided in the housing 5510.

For example, a desktop information terminal 5300 is illustrated in FIG. 21B as an electronic device in which a storage device according to one embodiment of the present invention can be used. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

FIGS. 21A and 21B illustrate a smartphone and a desktop information terminal as examples, but other information terminals include, for example, a PDA (Personal Digital Assistant), a notebook information terminal, a workstation, and the like. Alternatively, a storage device according to one embodiment of the present invention may be used.

For example, a portable game machine 5200 is illustrated in FIG. 21C as an electronic device in which the storage device according to one embodiment of the present invention can be used. The portable game machine 5200 includes a housing 5201, a display portion 5202, a button 5203, and the like.

FIG. 21C illustrates a portable game machine as an example, but other game machines include, for example, home-use stationary game machines and arcade games installed in entertainment facilities (game centers, amusement parks, and the like). The storage device according to one embodiment of the present invention may be used for a batting machine and a pitching machine for batting practice installed in a sports facility.

For example, an electric refrigerator-freezer 5800 is illustrated in FIG. 21D as an electronic device which can use the memory device according to one embodiment of the present invention. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a refrigerator door 5803, and the like.

FIG. 21D illustrates an electric refrigerator-freezer as an example, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. The storage device according to one embodiment of the present invention may be used for a cooling / heating appliance, a washing machine, a dryer, an audiovisual device, a digital camera, a digital video camera, and the like.

For example, FIG. 21E1 illustrates an automobile 5700 as an electronic device in which a memory device according to one embodiment of the present invention can be used. FIG. 21 (E2) is a diagram showing the vicinity of a windshield in a vehicle. FIG. 21E2 illustrates a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard, and a display panel 5704 attached to a pillar.

The display panels 5701 to 5703 can provide various kinds of information such as a speedometer, a tachometer, a traveling distance, a refueling amount, a gear state, and setting of an air conditioner. Further, display items, layouts, and the like displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

By displaying an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, the field of view (blind spot) blocked by the pillar can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated for and safety can be improved. In addition, by displaying an image that complements an invisible part, it is possible to more naturally confirm safety without a sense of incongruity. The display panel 5704 can be used as a lighting device.

In FIG. 21 (E1) and FIG. 21 (E2), a car and a display panel attached around a windshield of the car are illustrated as examples, but other moving objects are, for example, trains, monorails, ships, and flying objects. (Helicopter, unmanned aerial vehicle (drone), airplane, rocket, etc.) may use the storage device according to one embodiment of the present invention.

For example, an information terminal 7000 is illustrated in FIGS. 22A and 22B as an electronic device in which a storage device according to one embodiment of the present invention can be used. The information terminal 7000 includes a housing 7010, a monitor 7012, a keyboard 7013, a port 7015, and the like.

The keyboard 7013 and the port 7015 are provided in the housing 7010. The port 7015 includes, for example, a USB port, a LAN port, and an HDMI (High-Definition Multimedia Interface; HDMI is a registered trademark) port.

A monitor 7012 attached to the housing 7010 can be opened and closed. FIG. 22A illustrates a state where the monitor unit 7012 is open, and FIG. 22B illustrates a state where the monitor unit 7012 is closed. For example, the maximum angle at which the monitor 7012 opens is about 135 ° (see FIG. 22A).

The housing 7010 is provided with a cover 7011 that can be opened and closed (see FIG. 22B). The storage device 100 according to one embodiment of the present invention is incorporated in the housing 7010, and the storage device 100 is detachable. A device for cooling the storage device 100 or a device for radiating heat may be provided inside the housing 7010. Since the storage device 100 can be attached and detached by opening the cover 7011, the expandability of the information terminal 7000 is high. By incorporating a plurality of storage devices 100 into the information terminal 7000, it is possible to perform advanced graphic processing, scientific and technical calculations, artificial intelligence calculations, and the like.

For example, a large-sized parallel computer 5400 is illustrated in FIG. 23A as an electronic device in which the storage device according to one embodiment of the present invention can be used. The parallel computer 5400 has a plurality of rack-mounted computers 5420 in a rack 5410.

FIG. 23B is a schematic perspective view showing a configuration example of the computer 5420. The calculator 5420 has a motherboard 5430, and the motherboard has a plurality of slots 5431. A PC card 5421 is inserted into the slot 5431. The PC card 5421 has a connection terminal 5423, a connection terminal 5424, and a connection terminal 5425, and is connected to the motherboard 5430, respectively.

FIG. 23C is a schematic perspective view illustrating a configuration example of the PC card 5421. The PC card 5421 has a board 5422, and has a connection terminal 5423, a connection terminal 5424, a connection terminal 5425, a chip 5426, a chip 5427, and the like on the board 5422.

As the chip 5426, the chip 5427, and the like, a storage device, a CPU, a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), or the like according to one embodiment of the present invention is mounted. The chip 5426, the chip 5427, and the like have a plurality of terminals (not shown) for inputting and outputting signals, and the terminals are inserted into sockets (not shown) provided in the PC card 5421 to connect with the PC card 5421. The electrical connection may be performed, or the terminal may be connected to the wiring included in the PC card 5421 by, for example, reflow soldering to perform the electrical connection.

The connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 can be, for example, interfaces for supplying power to the PC card 5421, inputting / outputting signals, and the like. As a standard of the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), and HDMI (registered trademark) when outputting a video signal ) And the like.

The PC card 5421 has a connection terminal 5428 on the board 5422. The connection terminal 5428 has a shape that can be inserted into the slot 5431 of the motherboard 5430, and the connection terminal 5428 functions as an interface for connecting the PC card 5421 to the motherboard 5430. As a standard of the connection terminal 5428, for example, PCI Express (also referred to as PCIe; PCI Express and PCIe are registered trademarks) is exemplified.

The parallel computer 5400 can perform, for example, large-scale operations required for large-scale scientific and technological calculations, learning and inference of artificial intelligence.

For example, FIG. 24A illustrates a system including a server 5100 as an electronic device in which a storage device according to one embodiment of the present invention can be used. FIG. 24A schematically illustrates a state in which communication 5110 is performed between the server 5100, the information terminal 5500, and the desktop information terminal 5300.

The user can access the server 5100 from the information terminal 5500, the desktop information terminal 5300, or the like. Then, the user can receive the service provided by the administrator of the server 5100 through the communication 5110 via the Internet. Such services include, for example, e-mail, SNS (Social Networking Service), online software, cloud storage, navigation systems, translation systems, Internet games, online shopping, financial transactions such as stocks, exchanges, receivables, public facilities, commercial facilities, Reservation systems for accommodation facilities and hospitals, and viewing of Internet programs, lectures, lectures, and the like.

If the information terminal 5500 or the desktop information terminal 5300 at hand is short of processing capacity, such as calculations required for science and technology calculations, learning of artificial intelligence, and inference, the user accesses the server 5100 through communication 5110. Then, the calculation or the operation can be performed on the server 5100.

For example, in a service provided on the server 5100, artificial intelligence can be used. For example, by introducing artificial intelligence into a navigation system, the system may be able to provide flexible guidance according to road congestion conditions, train operation information, and the like. For example, by introducing artificial intelligence into a translation system, the system may be able to appropriately translate unique expressions such as dialects and slang. For example, by using artificial intelligence in a reservation system for a hospital or the like, the system may determine a user's symptom / degree of injuries and the like, and may be able to introduce an appropriate hospital / clinic or the like.

FIG. 24A shows a state in which communication 5110 is performed between server 5100, information terminal 5500, and desktop information terminal 5300. However, between server 5100 and an electronic device other than the information terminal, , Communication 5110 may be performed. For example, it may be in the form of IoT (Internet of Things) in which an electronic device is connected to the Internet.

FIG. 24B schematically illustrates, as an example, a state in which communication 5110 is performed between the server 5100 and electronic devices (an electric refrigerator-freezer 5800, a portable game machine 5200, a car 5700, and a television device 5600). ing.

In FIG. 24B, each electronic device may use artificial intelligence. Operations required for learning and inference of artificial intelligence can be performed on the server 5100. For example, data necessary for the calculation is transmitted from one of the electronic devices to the server 5100 by the communication 5110, the calculation of the artificial intelligence is performed on the server 5100, and the output data is transmitted from the server 5100 by the communication 5110 to the electronic device. Sent to one of Thus, the electronic device can use the data output by the artificial intelligence operation.

Note that the electronic device illustrated in FIG. 24B is an example, and communication 5110 may be performed between the server 5100 and an electronic device not illustrated in FIG.

As described above, the storage device according to one embodiment of the present invention can be used for various electronic devices. The storage device according to one embodiment of the present invention can be operated with a small number of power supplies, and cost of an electronic device using the storage device can be reduced. Further, the memory device according to one embodiment of the present invention has a small chip area and can reduce the size of an electronic device. Alternatively, more storage devices can be mounted on the electronic device. Further, in the storage device according to one embodiment of the present invention, loss of data hardly occurs even in a high-temperature environment and high-speed operation can be performed. With the use of the memory device according to one embodiment of the present invention, a highly reliable electronic device which operates reliably even in a high-temperature environment can be provided.

Note that this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

C11 capacitance element, C12 capacitance element, C13 capacitance element, C14 capacitance element, M11 transistor, M12 transistor, M13 transistor, M14 transistor, M15 transistor, M16 transistor, M21 transistor, M22 transistor, M23 transistor, M24 transistor Transistor, M31 transistor, M32 transistor, M33 transistor, M34 transistor, M36 transistor, S1 oxide, SN1 node, SN2 node, SN3 node, SN4 node, VBG1 wiring, VBG2 wiring, wl1 word line , Wl2 word line, wl3 word line, wl4 word line, 30 circuits, 31 sense amplifier circuit, 32 AND circuit, 33 analog switch, 34 analog switch, 100 storage device, 101 layer, 105 storage device, 110 peripheral circuit, 115 peripheral Circuit, 121 row decoder, 122 word line driver circuit, 123 predecoder, 131 column decoder, 132 bit line driver circuit, 133 precharge circuit, 134 sense amplifier circuit, 135 output MUX circuit, 136 driver circuit, 138 page buffer, 140 Output circuit, 150 potential generation circuit, 151 regulator, 152 regulator, 153 regulator, 154 power switch, 160 control logic circuit, 161 SPI controller, 162 serial / parallel converter, 163 instruction decoder circuit, 164 page address generation circuit, 165 command generation circuit, 166 byte address generation circuit, 167 parallel / serial converter, 168 status register, 201 layer, 210 memory cell array, 211 memory cell, 212 memory cell, 213 memory cell, 214 memory cell, 300 transistor, 311 substrate, 313 semiconductor region, 314a low resistance region, 314b low resistance region, 315 insulator , 316 conductor, 320 Insulator, 322 insulator, 324 insulator, 326 insulator, 328 conductor, 330 conductor, 350 insulator, 352 insulator, 354 insulator, 356 conductor, 360 insulator, 362 insulator, 364 insulator 366 conductor, 370 insulator, 372 insulator, 374 insulator, 376 conductor, 380 insulator, 382 insulator, 384 insulator, 386 conductor, 500 transistor, 500a transistor, 500b transistor, 500c transistor Transistor, 500e transistor, 500f transistor, 503 conductor, 503a conductor, 503b conductor 505 conductors, 505a conductors, 505b conductors, 510 insulators, 510A transistors, 510B transistors, 510C transistors, 510D transistors, 510E transistors, 511 insulators, 512 insulators, 514 insulators, 516 insulators , 518a conductor, 518b conductor, 518c conductor, 518d conductor, 520 insulator, 521 insulator, 522 insulator, 524 insulator, 530 oxide, 530a oxide, 530b oxide, 530c Region, 531a region, 531b region, 540a conductor, 540b conductor, 54 Conductor, 542a conductor, 542b conductor, 543 region, 543a region, 543b region, 544 insulator, 545 insulator, 546 conductor, 546a conductor, 546b conductor, 547 conductor, 547 conductor Body, 548 conductor, 548a conductor, 548b conductor, 550 insulator, 552 metal oxide, 560 conductor, 560a conductor, 560b conductor, 570 insulator, 571 insulator, 573 insulator, 574 insulator 575 insulators, 576 insulators, 576a insulators, 576b insulators, 580 insulators, 581 insulators, 582 insulators, 584 Insulator, 586 Insulator, 600 Capacitance Element, 610 Conductor, 612 Conductor, 612a Conductor, 620 Conductor, 630 Insulator, 646 Conductor, 648 Conductor, 650 Insulator, 660 Conductor, 5100 Server 5110 communication, 5200 portable game machine, 5201 housing, 5202 display unit, 5203 button, 5300 desktop information terminal, 5301 body, 5302 display, 5303 keyboard, 5400 parallel computer, 5410 rack, 5420 computer, 5421 PC card, 5421 PC card , 5423 connection terminal, 5424 connection terminal, 5425 connection terminal, 5426 , 5427 chip, 5428 connection terminal, 5430 motherboard, 5431 slot, 5500 information terminal, 5510 housing, 5511 display portion, 5600 television device, 5700 car, 5701 display panel, 5702 display panel, 5703 display panel, 5704 display panel , 5800 electric refrigerator-freezer, 5801 housing, 5802 refrigerator compartment door, 5803 freezer compartment door, 7000 information terminal, 7010 housing, 7011 cover, 7012 monitor unit, 7013 keyboard, 7015 port

Claims (8)

First to k-th write word lines (k is an integer of 2 or more);
A read word line;
A precharge line,
A write bit line;
A read bit line;
k write transistors,
A read transistor;
A precharge transistor;
One of a source and a drain of the first write transistor is electrically connected to a gate of the read transistor and one of a source and a drain of the precharge transistor,
One of a source and a drain of the l-th (1 is an integer of 2 or more and k or less) write transistor is electrically connected to the other of the source or the drain of the 1-1 write transistor;
The other of the source or the drain of the k-th write transistor is electrically connected to the write bit line,
A gate of the first write transistor is electrically connected to the first write word line;
A gate of the first write transistor is electrically connected to the first write word line;
One of a source and a drain of the read transistor is electrically connected to the read word line,
The other of the source and the drain of the read transistor is electrically connected to the read bit line,
A gate of the precharge transistor is electrically connected to the precharge line;
The other of the source and the drain of the precharge transistor is electrically connected to a wiring to which a predetermined potential is supplied. In claim 1,
The semiconductor device, wherein each of the first to k-th write transistors and the precharge transistor includes a metal oxide in a channel formation region. In claim 1,
The semiconductor device, wherein the first to k-th write transistors, the precharge transistor, and the read transistor each include a metal oxide in a channel formation region. A memory cell array;
And a peripheral circuit,
The memory cell array includes m × n memory cells (m and n are integers of 1 or more), m first to k-th write word lines (k is an integer of 2 or more), and m read lines, respectively. A word line, m precharge lines, n write bit lines, and n read bit lines;
The m × n memory cells are arranged in a matrix,
Each of the memory cells is electrically connected to the first to k-th write word lines, the read word line, the precharge line, the write bit line, and the read bit line,
Each of the memory cells has k write transistors, a read transistor, and a precharge transistor,
One of a source and a drain of the first write transistor is electrically connected to a gate of the read transistor and one of a source and a drain of the precharge transistor,
One of a source and a drain of the l-th (1 is an integer of 2 or more and k or less) write transistor is electrically connected to the other of the source or the drain of the 1-1 write transistor;
The other of the source or the drain of the k-th write transistor is electrically connected to the write bit line,
A gate of the first write transistor is electrically connected to the first write word line;
A gate of the first write transistor is electrically connected to the first write word line;
One of a source and a drain of the read transistor is electrically connected to the read word line,
The other of the source and the drain of the read transistor is electrically connected to the read bit line,
A gate of the precharge transistor is electrically connected to the precharge line;
The other of the source and the drain of the precharge transistor is electrically connected to a wiring to which a predetermined potential is supplied,
The peripheral circuit has a first circuit, a second circuit, and a controller,
The first circuit is electrically connected to the write bit line and the read bit line,
The first circuit has a function of writing data to the memory cell and a function of reading data from the memory cell.
The second circuit is electrically connected to the first to k-th write word lines, the read word line, and the precharge line,
The second circuit has a function of driving the first to k-th write word lines, the read word lines, and the precharge lines,
The storage device, wherein the controller has a function of controlling the first circuit and the second circuit. In claim 4,
The memory device, wherein each of the first to k-th write transistors and the precharge transistor includes a metal oxide in a channel formation region. In claim 4,
The memory device, wherein the first to k-th write transistors, the precharge transistor, and the read transistor each include a metal oxide in a channel formation region. In claim 5,
The first circuit, the second circuit, and the controller include a transistor formed on a semiconductor substrate,
The memory device, wherein the first to k-th write transistors and the precharge transistor are formed by being stacked on the semiconductor substrate, respectively. In claim 6,
The first circuit, the second circuit, and the controller include a transistor formed on a semiconductor substrate,
The memory device, wherein the first to k-th write transistors, the precharge transistor, and the read transistor are formed by being stacked above the semiconductor substrate, respectively.