CN116209244A - Dynamic memory and memory device - Google Patents
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- CN116209244A CN116209244A CN202210095782.6A CN202210095782A CN116209244A CN 116209244 A CN116209244 A CN 116209244A CN 202210095782 A CN202210095782 A CN 202210095782A CN 116209244 A CN116209244 A CN 116209244A
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- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
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- 229910007667 ZnOx Inorganic materials 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
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- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
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Abstract
The application provides a dynamic memory and storage device, the memory cell in the dynamic memory is including the first layer MOS pipe subassembly and the second floor MOS pipe subassembly of range upon range of setting. Through setting up first MOS pipe and second MOS pipe in first layer MOS pipe subassembly, the grid electric capacity of first MOS pipe and second MOS pipe can be regarded as the storage capacity of memory cell, has improved dynamic memory's storage capacity from this. The first MOS tube and the second MOS tube share the source electrode, and the third MOS tube and the fourth MOS tube share the source electrode, so that the occupied area of the first-layer MOS tube assembly and the second-layer MOS tube assembly can be reduced. Therefore, the number of MOS transistors is increased, the capacity of the dynamic memory is improved, and meanwhile, the excessive occupied area is not increased, so that the integration of devices is facilitated. In addition, the read bit line is arranged on one side of the first-layer MOS tube assembly far away from the second-layer MOS tube assembly, and the write bit line is arranged on one side of the second-layer MOS tube assembly far away from the first-layer MOS tube assembly, so that wiring is facilitated.
Description
Technical Field
The present application relates to the field of semiconductor device technologies, and in particular, to a dynamic memory and a memory device.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and compared with the static memory, the DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density, and along with the development of technology, the DRAM memory is more and more widely applied to electronic devices such as servers, smart phones, personal computers and the like.
DRAM memory typically includes a plurality of memory cells, and in order to increase the capacity of the DRAM memory, the number of memory cells needs to be increased. However, increasing the number of memory cells occupies a larger area, which makes the structure less compact and is disadvantageous for device integration.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a dynamic memory and a memory device, which are used for solving the problems of large occupied area and insufficient compactness of the structure of a DRAM memory in the prior art.
1. A dynamic memory comprising a plurality of memory cells, wherein the memory cells comprise:
the first-layer MOS tube assembly comprises a first MOS tube and a second MOS tube, wherein the first MOS tube and the second MOS tube are metal oxide thin film transistors, and share a source electrode;
the second-layer MOS tube assembly is positioned on one side of the first-layer MOS tube assembly and comprises a third MOS tube and a fourth MOS tube, the third MOS tube and the fourth MOS tube are metal oxide thin film transistors, and the third MOS tube and the fourth MOS tube share a source electrode;
the read bit line is positioned on one side of the first layer of MOS tube assembly far away from the second layer of MOS tube assembly and is electrically connected with the sources of the first MOS tube and the second MOS tube;
the write bit line is positioned on one side of the second-layer MOS tube assembly, which is far away from the first-layer MOS tube assembly, and is electrically connected with the sources of the third MOS tube and the fourth MOS tube;
the two read word lines are positioned on one side of the first-layer MOS tube assembly far away from the second-layer MOS tube assembly and are respectively and electrically connected with the drains of the first MOS tube and the second MOS tube;
the two writing lines are respectively and electrically connected with the grid electrodes of the third MOS tube and the fourth MOS tube;
the grid electrode of the first MOS tube is electrically connected with the drain electrode of the third MOS tube, and the grid electrode of the second MOS tube is electrically connected with the drain electrode of the fourth MOS tube.
Optionally, the active layer materials of the first MOS transistor and the second MOS transistor include ITO, IWO, or IGZO, and the active layer materials of the third MOS transistor and the fourth MOS transistor include ITO, IWO, or IGZO.
Optionally, the read bit line is electrically connected to the sources of the first MOS transistor and the second MOS transistor through a contact point.
Optionally, the gate of the first MOS transistor is parallel to the gate of the second MOS transistor, and the read bit line is perpendicular to the gates of the first MOS transistor and the second MOS transistor.
Optionally, the read word line is parallel to the gates of the first MOS transistor and the second MOS transistor.
Optionally, the gate of the first MOS transistor is electrically connected to the drain of the third MOS transistor through a through hole, and the gate of the second MOS transistor is electrically connected to the drain of the fourth MOS transistor through a through hole.
Optionally, the first MOS transistor includes a first drain, the second MOS transistor includes a second drain, and the read word line includes a first read word line and a second read word line;
the first read word line is electrically connected with the first drain electrode through a contact point; and/or, the second read word line is electrically connected with the second drain electrode through a contact point.
Optionally, the third MOS transistor includes a third gate, the fourth MOS transistor includes a fourth gate, and the write word line includes a first write word line and a second write word line;
the first write word line is electrically connected with the third gate through a contact point; and/or, the second write word line is electrically connected with the fourth gate through a contact point.
Optionally, the dynamic memory includes a plurality of array modules disposed in a stacked manner, and the array modules include a plurality of memory cells arranged in an array.
Optionally, the first MOS transistor includes a first gate insulating layer, the second MOS transistor includes a second gate insulating layer, and the first gate insulating layer is connected to the second gate insulating layer.
In a second aspect, embodiments of the present application provide a storage device including a dynamic memory in embodiments of the present application.
The beneficial technical effects that technical scheme that this application embodiment provided brought include:
the dynamic memory in the embodiment of the application comprises a plurality of memory units, wherein the memory units comprise a first layer of MOS tube assembly and a second layer of MOS tube assembly which are arranged in a stacked mode. Through setting up first MOS pipe and second MOS pipe in first layer MOS pipe subassembly, the grid electric capacity of first MOS pipe and second MOS pipe has all improved dynamic memory's storage capacity from this. The first MOS tube and the second MOS tube share the source electrode, and the third MOS tube and the fourth MOS tube share the source electrode, so that the occupied area of the first-layer MOS tube assembly and the second-layer MOS tube assembly can be reduced. Therefore, the number of MOS tubes is increased, the capacity of the dynamic memory is improved, and meanwhile, too much occupied area is not increased, so that the structural layout of the memory unit is more compact, the area utilization rate of the memory unit is improved, and the integration of devices is facilitated. In addition, the read bit line is arranged on one side of the first-layer MOS tube assembly far away from the second-layer MOS tube assembly, and the write bit line is arranged on one side of the second-layer MOS tube assembly far away from the first-layer MOS tube assembly, so that wiring is facilitated.
Advantages of embodiments of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic cross-sectional structure of a memory cell of a dynamic memory according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional structure of a memory cell of another dynamic memory according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional structure of a memory cell of the dynamic memory according to the embodiment of the present application;
fig. 4 is a schematic top view of the second MOS transistor assembly of fig. 1;
fig. 5 is a schematic top view of the first MOS transistor assembly of fig. 1;
fig. 6 is a schematic structural diagram of a stacked arrangement of a plurality of memory cells in an embodiment of the present application.
In the figure:
10-dynamic memory; a 100-memory cell; 11-a first layer MOS tube assembly; 12-a second-layer MOS tube assembly; 111-a first MOS tube; 112-a second MOS tube; 121-a third MOS tube; 122-a fourth MOS tube; 1110-a first active layer; 1210-a second active layer; 1111-a first layer MOS tube source; 1211-a second layer MOS tube source; 1112-a first gate; 1113-a first drain; 1212-a second gate; 1213-a second drain; 1312-third gate; 1313-a third drain; 1412-fourth gate; 1413-fourth drain; 1501-a first gate insulating layer; 1502-a second gate insulating layer; 1503-a third gate insulating layer; 1504-a fourth gate insulating layer; 16-other film layers;
20-word line read; 20 a-a first read word line; 20 b-a second read wordline; 21-a read bit line;
30-write word lines; 30 a-a first write word line; 30 b-a second write word line; 31-write bit lines;
41-contact points; 42-through holes; 43-metal block; 50-array module.
Detailed Description
Examples of embodiments of the present application are illustrated in the accompanying drawings, in which like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
The memory cells in DRAM memory generally include MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFETs) and a capacitor, which has a simple structure and a high capacity per unit volume. The main working principle of the DRAM memory is to store charges by using a capacitor, and determine whether a binary bit is 1 or 0 according to the quantity of the charges stored in the capacitor. The DRAM memory can also adopt a design without capacitance, namely, a reading MOS tube and a writing MOS tube are arranged in the memory unit, and the grid electrode of the reading MOS tube is electrically connected with the source electrode and the drain electrode of the writing MOS tube. Therefore, no capacitor device is needed to be additionally arranged, and the structure of the memory is further simplified.
The inventor in the art considers that in the existing 2T0C memory (i.e. 2 MOS transistors are arranged in the memory, and no capacitor is arranged), two MOS transistors in the memory generally adopt a planar layout, i.e. the two MOS transistors are arranged on the same plane, and the area utilization rate is low. When the memory is designed in a large capacity, the number of memory cells needs to be increased, which causes a large area occupation, and the structure is not compact enough, which is not beneficial to the integration of devices.
The application provides a dynamic memory and a storage device, which aim to solve the technical problems in the prior art.
The dynamic memory 10 and the memory device according to the embodiments of the present application are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, fig. 2, fig. 3, fig. 4, and fig. 5, a dynamic memory 10 provided in an embodiment of the present application includes:
the first-layer MOS tube assembly 11 comprises a first MOS tube 111 and a second MOS tube 112, wherein the first MOS tube 111 and the second MOS tube 112 are metal oxide thin film transistors, and the first MOS tube 111 and the second MOS tube 112 share a source electrode;
the second-layer MOS tube assembly 12 is positioned at one side of the first-layer MOS tube assembly 11 and comprises a third MOS tube 121 and a fourth MOS tube 122, the third MOS tube 121 and the fourth MOS tube 122 are metal oxide thin film transistors, and the third MOS tube 121 and the fourth MOS tube 122 share a source electrode;
the read bit line 21 is positioned on one side of the first-layer MOS tube assembly 11, which is far away from the second-layer MOS tube assembly 12, and is electrically connected with the sources of the first MOS tube 111 and the second MOS tube 112;
the write bit line 31 is positioned on one side of the second-layer MOS tube assembly 12 far away from the first-layer MOS tube assembly 11 and is electrically connected with the sources of the third MOS tube 121 and the fourth MOS tube 122;
two read word lines 20, which are located at one side of the first layer MOS tube assembly 11 far away from the second layer MOS tube assembly 12 and are respectively electrically connected with the drains of the first MOS tube 111 and the second MOS tube 112;
two writing lines 30 electrically connected to the gates of the third MOS transistor 121 and the fourth MOS transistor 122, respectively;
the gate of the first MOS transistor 111 is electrically connected to the drain of the third MOS transistor 121, and the gate of the second MOS transistor 112 is electrically connected to the drain of the fourth MOS transistor 122.
Specifically, the dynamic memory 10 includes a plurality of memory units 100 arranged in an array, and each memory unit 100 includes a first layer of MOS transistor assembly 11 and a second layer of MOS transistor assembly 12 that are stacked. The first-layer MOS tube assembly 11 includes a first MOS tube 111 and a second MOS tube 112, active layers of the first MOS tube 111 and the second MOS tube 112 (i.e., the first active layer 1110 in fig. 1) are located on the same layer, and materials of the active layers of the first MOS tube 111 and the second MOS tube 112 include metal oxides such as indium gallium zinc oxide (Indium Gallium Zinc Oxide). In other embodiments, the metal oxide material may be ITO, IWO, or other materials, such as ZnOx, inOx, in O3, inWO, snO2, tiOx, inSnOx, znxOyNz, mgxZnyOz, inxZnyOz, inxGayZnzOa, zrxInyZnzOa, hfxInyZnzOa, snxInyZnzOa, alxSnyInzZnaOd, sixInyZnzOa, znxSnyOz, alxZnySnzOa, gaxZnySnzOa, zrxZnySnzOa, inGaSiO, or other materials.
In this embodiment, the first MOS transistor 111 includes a first gate 1112 and a first drain 1113, the first gate 1112 and the first drain 1113 are respectively located on opposite sides of the first active layer 1110 (as shown in fig. 1, the first gate 1112 is located above the first active layer 1110, the first drain 1113 is located below the first active layer 1110), and a first gate insulating layer 1501 is disposed between the first gate 1112 and the first active layer 1110. The second MOS transistor 112 includes a second gate electrode 1212 and a second drain electrode 1213, the second gate electrode 1212 and the second drain electrode 1213 are respectively located at opposite sides of the first active layer 1110 (as shown in fig. 1, the second gate electrode 1212 is located above the first active layer 1110, the second drain electrode 1213 is located below the first active layer 1110), and a second gate insulating layer 1502 is disposed between the second gate electrode 1212 and the first active layer 1110. The first MOS transistor 111 and the second MOS transistor 112 share a source, that is, the first layer MOS transistor source 1111 is both the source of the first MOS transistor 111 and the source of the second MOS transistor 112. The first MOS transistor source 1111 and the first drain 1113 and the second drain 1213 are located on the same side of the first active layer 1110 (as shown in fig. 1, the first MOS transistor source 1111 is located below the first active layer 1110).
Note that the arrangement of the first gate insulating layer 1501 and the second gate insulating layer 1502 can be adjusted according to actual situations. As shown in fig. 1, the first gate insulating layer 1501 and the second gate insulating layer 1502 are separated from each other. As shown in fig. 3, the first gate insulating layer 1501 and the second gate insulating layer 1502 are connected to each other, and thus, a manufacturing process of the first gate insulating layer 1501 and the second gate insulating layer 1502 can be simplified (when the first gate insulating layer 1501 and the second gate insulating layer 1502 are manufactured, it is not necessary to remove a portion between the first gate insulating layer 1501 and the second gate insulating layer 1502 by an etching process).
As shown in fig. 1, the second layer MOS transistor assembly 12 is disposed above the first layer MOS transistor assembly 11, where the second layer MOS transistor assembly 12 includes a third MOS transistor 121 and a fourth MOS transistor 122, active layers (i.e., a second active layer 1210 in fig. 1) of the third MOS transistor 121 and the fourth MOS transistor 122 are located on the same layer, and materials of the active layers of the third MOS transistor 121 and the fourth MOS transistor 122 include metal oxides such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), which can be specifically determined according to practical situations, and are not limited herein.
It should be noted that, the second layer MOS transistor assembly 12 and the first layer MOS transistor assembly 11 are disposed opposite to each other, that is, the second layer MOS transistor assembly 12 is disposed at one side of the first layer MOS transistor assembly 11, and the second layer MOS transistor assembly 12 is not limited to be disposed above the first layer MOS transistor assembly 11. As shown in fig. 2, the second layer MOS transistor assembly 12 is disposed below the first layer MOS transistor assembly 11. The relative positions of the first layer of MOS tube assembly 11 and the second layer of MOS tube assembly 12 can be adjusted according to actual conditions.
Specifically, the third MOS transistor 121 includes a third gate electrode 1312 and a third drain electrode 1313, the third gate electrode 1312 and the third drain electrode 1313 are respectively located on opposite sides of the second active layer 1210 (as shown in fig. 1, the third gate electrode 1312 is located above the second active layer 1210, the third drain electrode 1313 is located below the second active layer 1210), and a third gate insulating layer 1503 is disposed between the third gate electrode 1312 and the second active layer 1210. The fourth MOS transistor 122 includes a fourth gate electrode 1412 and a fourth drain electrode 1413, the fourth gate electrode 1412 and the fourth drain electrode 1413 are respectively located on opposite sides of the second active layer 1210 (as shown in fig. 1, the fourth gate electrode 1412 is located above the second active layer 1210, the fourth drain electrode 1413 is located below the second active layer 1210), and a fourth gate insulating layer 1504 is disposed between the fourth gate electrode 1412 and the second active layer 1210.
In this embodiment, the third MOS transistor 121 and the fourth MOS transistor 122 share a source, that is, the second layer MOS transistor source 1211 is both the source of the third MOS transistor 121 and the source of the fourth MOS transistor 122. In the second MOS transistor, the source 1211, the third drain 1313, and the fourth drain 1413 are located on opposite sides of the second active layer 1210 (as shown in fig. 1, the second MOS transistor source 1211 is located on a side of the second active layer 1210 away from the first MOS transistor assembly 11). The first gate 1112 is electrically connected to the third drain 1313, so that the first MOS transistor 111 and the third MOS transistor 121 are electrically connected. The second gate 1212 is electrically connected to the fourth drain 1413 to electrically connect the second MOS transistor 112 and the fourth MOS transistor 122. The gate parasitic capacitances of the third MOS transistor 121 and the fourth MOS transistor 122 constitute a storage capacitance (data is stored on the gate parasitic capacitance) of the memory cell 100.
Referring to fig. 1, 2, 3, 4 and 5, the memory cell 100 further includes a read word line 20, a read bit line 21, a write word line 30 and a write bit line 31. The read word line 20 is located at a side of the first active layer 1110 remote from the first gate 1112 (as shown in fig. 1, the read word line 20 is located under the first active layer 1110). The read word line 20 includes a first read word line 20a and a second read word line 20b, the first read word line 20a is electrically connected to the first drain 1113 of the first MOS transistor 111, and the second read word line 20b is electrically connected to the second drain 1213 of the second MOS transistor 112. Optionally, the first read word line 20a, the second read word line 20b, the first gate 1112 and the second gate 1212 are disposed parallel to each other, so as to facilitate manufacturing of the dynamic memory 10. The read bit line 21 is located on a side of the first active layer 1110 remote from the first gate 1112 (as shown in fig. 1, the read bit line 21 is located below the first active layer 1110). The read bit line 21 is electrically connected to the first MOS transistor source 1111, and the read bit line 21 is disposed across the first read word line 20a, the second read word line 20b, the first gate 1112 and the second gate 1212, and optionally, the read bit line 21 is perpendicular to the first read word line 20a, the second read word line 20b, the first gate 1112 and the second gate 1212.
As shown in fig. 1, 2, 3, 4, and 5, the write bit line 31 is located at a side of the second active layer 1210 remote from the third drain electrode 1313 and the fourth drain electrode 1413 (as shown in fig. 1, the write bit line 31 is located above the second active layer 1210). The write bit line 31 is electrically connected to the second MOS transistor source 1211, and the write bit line 31 is disposed to cross the third gate 1312 and the fourth gate 1412, and optionally, the third gate 1312 is parallel to the fourth gate 1412, and the write bit line 31 is perpendicular to the third gate 1312 and the fourth gate 1412. The write word line 30 is located at a side of the second active layer 1210 remote from the third drain electrode 1313 and the fourth drain electrode 1413 (as shown in fig. 1, the write word line 30 is located above the second active layer 1210), the write word line 30 includes a first write word line 30a and a second write word line 30b, the first write word line 30a is electrically connected to the third gate electrode 1312, and the second write word line 30b is electrically connected to the fourth gate electrode 1412. In the writing operation, a high voltage is applied to the third gate 1312 and the fourth gate 1412 through the first write word line 30a and the second write word line 30b, the third MOS transistor 121 and the fourth MOS transistor 122 are turned on, and an external data signal is transmitted to the second layer MOS transistor source 1211 through the write bit line 31 and is transmitted to the gate capacitances (storage capacitances) of the first gate 1112 and the second gate 1212 through the turned-on third MOS transistor 121 and the fourth MOS transistor 122, respectively. In performing a read operation, a specific voltage is applied to the first drain 1113 through the first read word line 20a, and a specific voltage is applied to the second drain 1213 through the second read word line 20b, while the read bit line 21 is turned on to a readout circuit (not shown) to read out data.
By providing the first MOS transistor 111 and the second MOS transistor 112 in the first layer MOS transistor assembly 11, the gate capacitances of the first MOS transistor 111 and the second MOS transistor 112 can be used as the storage capacitance of the memory cell 100, and the storage capacity is improved compared with the case where only one MOS transistor is provided. The first MOS tube 111 and the second MOS tube 112 share the source electrode, and the third MOS tube 121 and the fourth MOS tube share the source electrode, so that the occupied area of the first-layer MOS tube assembly 11 and the second-layer MOS tube assembly 12 is reduced, the structural layout of the memory unit 100 is more compact, the area utilization rate of the memory unit 100 is improved, and the integration of devices is facilitated.
Alternatively, in the embodiment of the present application, as shown in fig. 1 and 2, the sources of the first MOS transistor 111 and the second MOS transistor 112 (i.e., the first layer MOS transistor source 1111) are electrically connected to the read bit line 21 through the contact point 41, i.e., the first layer MOS transistor source 1111 is electrically connected to the read bit line 21 through the contact point 41. In the process of manufacturing the dynamic memory 10, the read bit line 21 may be manufactured first, then the contact 41 and the first layer of MOS transistor source 1111 are manufactured on the read bit line 21, and the first layer of MOS transistor source 1111 is electrically connected to the read bit line 21 through the contact 41. The contact point 41 may be formed by dropping a metal conductive paste, and may be specifically determined according to practical circumstances. By arranging the contact point 41, the sources of the first MOS tube 111 and the second MOS tube 112 are electrically connected with the read bit line 21 through the contact point 41, so that the connection is more convenient and the process is easy to realize.
Note that, the sources of the first MOS transistor 111 and the second MOS transistor 112 may be electrically connected to the read bit line 21 through a via hole. Specifically, in the process of manufacturing the dynamic memory 10, vias are formed in other film layers 16 (including interlayer dielectric layers, passivation layers, etc.), metal layers are deposited on walls of the vias, and then the read bit lines 21 are electrically connected to sources of the first MOS transistor 111 and the second MOS transistor 112 (i.e., the first MOS transistor source 1111) through the metal layers on walls of the vias. The specific connection manner between the sources of the first MOS transistor 111 and the second MOS transistor 112 and the read bit line 21 may be adjusted according to the actual situation, which is not limited herein.
In the embodiment of the present application, as shown in fig. 1, 2, 3, 4 and 5, the first MOS transistor 111 includes a first gate 1112, the second MOS transistor 112 includes a second gate 1212, the third MOS transistor 121 includes a third drain 1313, and the fourth MOS transistor 122 includes a fourth drain 1413. The third drain 1313 of the third MOS transistor 121 is electrically connected to the first gate 1112 of the first MOS transistor 111 through the via hole 42, and the fourth drain 1413 of the fourth MOS transistor 122 is electrically connected to the second gate 1212 of the second MOS transistor 112 through the via hole 42. Specifically, after the first-layer MOS transistor assembly 11 is fabricated, other film layers 16 (passivation layers or interlayer dielectric layers, etc.) are fabricated above the first-layer MOS transistor assembly 11 (on the side of the first-layer MOS transistor away from the read bit line 21); then, forming a through hole 42 on the other film 16, depositing a metal layer on the wall of the through hole 42, then forming a third drain 1313 and a fourth drain 1413 on the other film 16, and electrically connecting the third drain 1313 and the fourth drain 1413 with the first gate 1112 and the second gate 1212 respectively through the metal layer on the wall of the through hole 42.
It should be noted that the first gate 1112 may be connected to the third drain 1313, the second gate 1212, and the fourth drain 1413 in other manners. For example, in the process of manufacturing the dynamic memory 10, the metal block 43 may be formed by opening the through hole 42 in the other film layer 16 between the first layer MOS transistor assembly 11 and the second layer MOS transistor assembly 12, and then depositing metal in the entire through hole 42. As shown in fig. 1 and 2, the first gate electrode 1112 is electrically connected to the third drain electrode 1313 through one metal block 43 and two through holes 42, and the second gate electrode 1212 is electrically connected to the fourth drain electrode 1413 through one metal block 43 and two through holes 42. By disposing the metal block 43 between the first gate 1112 and the third drain 1313, and between the second gate 1212 and the fourth drain 1413, the gate capacitance of the first MOS transistor 111 and the gate capacitance of the second MOS transistor 112 can be increased, which is beneficial to prolonging the data retention time of the dynamic memory 10 and reducing the refresh frequency and power consumption of the dynamic memory 10. The dimensions (e.g., area size, thickness, etc.) of the metal block 43 may be adjusted according to actual conditions, and are not limited herein.
It should be noted that, to further simplify the structure and the manufacturing process of the dynamic memory 10, the first MOS transistor 111 may optionally include a first drain 1113, the second MOS transistor 112 may include a second drain 1213, and the read word line 20 may include a first read word line 20a and a second read word line 20b; the first read word line 20a is electrically connected to the first drain 1113 through a contact (not shown); and/or the second read wordline 20b is electrically connected to the second drain 1213 through a contact (not shown). Specifically, in the process of manufacturing the dynamic memory 10, the contact point on the first drain electrode 1113 may be extended to form the first read word line 20a, that is, the contact point is directly manufactured on the first drain electrode 1113 after the first drain electrode 1113 is manufactured, and then the contact point is extended to form the first read word line 20a. The second drain 1213 and the second read wordline 20b may be integrated in the same manner, i.e., a contact is directly made on the second drain 1213 after the second drain 1213 is made, and then the contact is extended to form the second read wordline 20b. The first drain 1113, the second drain 1213, the first gate 1112 and the second gate 1212 may be parallel to each other, so as to facilitate fabrication of the dynamic memory 10, which may be determined according to practical situations.
As shown in conjunction with fig. 1, 4, and 5, in an embodiment of the present application, the third MOS transistor 121 includes a third gate 1312, the fourth MOS transistor 122 includes a fourth gate 1412, and the write word line 30 includes a first write word line 30a and a second write word line 30b; the first write word line 30a is electrically connected to the third gate electrode 1312 through a contact point (not shown in the drawing); and/or, the second write word line 30b is electrically connected to the fourth gate 1412 through a contact (not shown). Specifically, the contact on the third gate 1312 may be extended to be the first write word line 30a; the contact on the fourth gate 1412 can be extended to be the same as the second write word line 30b. Thereby, the structure of the dynamic memory 10 is further simplified, and the manufacturing process of the dynamic memory 10 is simplified. The third gate 1312 and the fourth gate 1412 may be parallel to each other to facilitate fabrication of the dynamic memory 10, which may be determined according to practical situations.
Alternatively, as shown in fig. 6, in the embodiment of the present application, the dynamic memory 10 includes a plurality of array modules 50 stacked, and the array modules 50 include a plurality of memory cells 100 arranged in an array. Specifically, as shown in fig. 1, 4, 5 and 6, word lines (including read word line 20 and write word line 30) of a plurality of memory cells 100 are connected to each other, and bit lines (including read bit line 21 and write bit line 31) are connected to each other, forming a layer of array module 50. The multi-layer array module 50 is stacked to form the dynamic memory 10 with a three-dimensional structure, so that the memory capacity of the dynamic memory 10 can be increased, the occupied area of the dynamic memory 10 can be reduced, and the integration of devices is facilitated.
Based on the same inventive concept, the embodiment of the present application also provides a storage device, which includes the above-mentioned dynamic memory 10 provided in the embodiment of the present application. Since the memory device includes the dynamic memory 10 provided in the embodiments of the present application, the memory device has the same advantages as the dynamic memory 10, and will not be described herein.
Specifically, the storage device in the embodiment of the application may include a solid state disk, or a usb disk, and may specifically be determined according to an actual situation.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
1. the application provides a dynamic memory and storage device, the memory cell in the dynamic memory is including the first layer MOS pipe subassembly and the second floor MOS pipe subassembly of range upon range of setting. Through setting up first MOS pipe and second MOS pipe in first layer MOS pipe subassembly, the grid electric capacity of first MOS pipe and second MOS pipe all can be regarded as the storage capacity of memory cell, has improved dynamic memory's storage capacity from this. The first MOS tube and the second MOS tube share the source electrode, and the third MOS tube and the fourth MOS tube share the source electrode, so that the occupied area of the first-layer MOS tube assembly and the second-layer MOS tube assembly can be reduced. Therefore, the number of MOS tubes is increased, the capacity of the dynamic memory is improved, and meanwhile, too much occupied area is not increased, so that the structural layout of the memory unit is more compact, the area utilization rate of the memory unit is improved, and the integration of devices is facilitated. In addition, the read bit line is arranged on one side of the first-layer MOS tube assembly far away from the second-layer MOS tube assembly, and the write bit line is arranged on one side of the second-layer MOS tube assembly far away from the first-layer MOS tube assembly, so that wiring is facilitated.
2. In the process of manufacturing the dynamic memory 10, the read bit line 21 may be manufactured first, then the contact 41 and the first layer of MOS transistor source 1111 are manufactured on the read bit line 21, and the first layer of MOS transistor source 1111 is electrically connected to the read bit line 21 through the contact 41. The contact point 41 may be formed by dropping a metal conductive paste, and may be specifically determined according to practical circumstances. By arranging the contact point 41, the sources of the first MOS tube 111 and the second MOS tube 112 are electrically connected with the read bit line 21 through the contact point 41, so that the connection is more convenient and the process is easy to realize.
3. In the embodiment of the present application, the first gate electrode 1112 is electrically connected to the third drain electrode 1313 through one metal block 43 and two through holes 42, and the second gate electrode 1212 is electrically connected to the fourth drain electrode 1413 through one metal block 43 and two through holes 42. By disposing the metal block 43 between the first gate 1112 and the third drain 1313, and between the second gate 1212 and the fourth drain 1413, the gate capacitance of the first MOS transistor 111 and the gate capacitance of the second MOS transistor 112 can be increased, which is beneficial to prolonging the data retention time of the dynamic memory 10 and reducing the refresh frequency and power consumption of the dynamic memory 10.
4. In the embodiment of the present application, the array arrangement of the plurality of memory cells 100 may form a layer of array modules 50, and the plurality of layers of array modules 50 are stacked, so that the dynamic memory 10 having a three-dimensional structure may be formed, and thus the storage capacity of the dynamic memory 10 may be increased while the area occupied by the dynamic memory 10 may be reduced.
In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for a person skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (11)
1. A dynamic memory comprising a plurality of memory cells, wherein the memory cells comprise:
the first-layer MOS tube assembly comprises a first MOS tube and a second MOS tube, wherein the first MOS tube and the second MOS tube are metal oxide thin film transistors, and share a source electrode;
the second-layer MOS tube assembly is positioned on one side of the first-layer MOS tube assembly and comprises a third MOS tube and a fourth MOS tube, the third MOS tube and the fourth MOS tube are metal oxide thin film transistors, and the third MOS tube and the fourth MOS tube share a source electrode;
the read bit line is positioned on one side of the first layer of MOS tube assembly far away from the second layer of MOS tube assembly and is electrically connected with the sources of the first MOS tube and the second MOS tube;
the write bit line is positioned on one side of the second-layer MOS tube assembly, which is far away from the first-layer MOS tube assembly, and is electrically connected with the sources of the third MOS tube and the fourth MOS tube;
the two read word lines are positioned on one side of the first-layer MOS tube assembly far away from the second-layer MOS tube assembly and are respectively and electrically connected with the drains of the first MOS tube and the second MOS tube;
the two writing lines are respectively and electrically connected with the grid electrodes of the third MOS tube and the fourth MOS tube;
the grid electrode of the first MOS tube is electrically connected with the drain electrode of the third MOS tube, and the grid electrode of the second MOS tube is electrically connected with the drain electrode of the fourth MOS tube.
2. The dynamic memory of claim 1, wherein the active layer material of the first MOS transistor and the second MOS transistor comprises ITO, IWO, or IGZO, and the active layer material of the third MOS transistor and the fourth MOS transistor comprises ITO, IWO, or IGZO.
3. The dynamic memory of claim 2, wherein the read bit line is electrically connected to sources of the first MOS transistor and the second MOS transistor through contact points.
4. The dynamic memory of claim 3, wherein the gate of the first MOS transistor is parallel to the gate of the second MOS transistor, and the read bit line is perpendicular to the gates of the first MOS transistor and the second MOS transistor.
5. The dynamic memory of claim 4, wherein the read word line is parallel to gates of the first MOS transistor and the second MOS transistor.
6. The dynamic memory of claim 2, wherein the gate of the first MOS transistor is electrically connected to the drain of the third MOS transistor through a via, and the gate of the second MOS transistor is electrically connected to the drain of the fourth MOS transistor through a via.
7. The dynamic memory of claim 1, wherein the first MOS transistor comprises a first drain, the second MOS transistor comprises a second drain, and the read wordline comprises a first read wordline and a second read wordline;
the first read word line is electrically connected with the first drain electrode through a contact point; and/or, the second read word line is electrically connected with the second drain electrode through a contact point.
8. The dynamic memory of claim 1, wherein the third MOS transistor comprises a third gate, the fourth MOS transistor comprises a fourth gate, and the write word line comprises a first write word line and a second write word line;
the first write word line is electrically connected with the third gate through a contact point; and/or, the second write word line is electrically connected with the fourth gate through a contact point.
9. The dynamic memory of claim 1, wherein the dynamic memory comprises a plurality of array modules arranged in a stack, the array modules comprising a plurality of the memory cells arranged in an array.
10. The dynamic memory of claim 1, wherein the first MOS transistor comprises a first gate insulating layer and the second MOS transistor comprises a second gate insulating layer, the first gate insulating layer and the second gate insulating layer being connected.
11. A memory device comprising the dynamic memory of any one of claims 1 to 10.
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