CN116133405A - Dynamic memory, manufacturing method thereof and memory device - Google Patents
Dynamic memory, manufacturing method thereof and memory device Download PDFInfo
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- CN116133405A CN116133405A CN202210465087.4A CN202210465087A CN116133405A CN 116133405 A CN116133405 A CN 116133405A CN 202210465087 A CN202210465087 A CN 202210465087A CN 116133405 A CN116133405 A CN 116133405A
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Abstract
The application provides a dynamic memory, a manufacturing method thereof and a memory device. The word line of the dynamic memory is positioned at the grid electrode of the transistor and connected with the transistor, the bit line penetrates through a plurality of memory cells, and the transistors in the memory cells are connected through the bit line. By stacking a memory array including a plurality of memory cells, a dynamic memory having a three-dimensional structure is formed, and the memory capacity of the dynamic memory is increased while the structural layout of the memory cells is made more compact. On the other hand, by making the bit line penetrate through a plurality of memory cells, a plurality of transistors arranged in a stacked manner can be connected by one bit line, thereby simplifying the structure and manufacturing process of the dynamic memory.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a dynamic memory, a manufacturing method thereof and a storage device.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and compared with the static memory, the DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density, and along with the development of technology, the DRAM memory is more and more widely applied to electronic devices such as servers, smart phones, personal computers and the like.
DRAM memory generally includes a plurality of memory cells, and in order to increase the storage capacity of the DRAM memory, the number of memory cells needs to be increased. However, increasing the number of memory cells occupies a larger area, which makes the structure less compact and is disadvantageous for device integration.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a dynamic memory and a manufacturing method thereof, which are used for solving the problem of larger occupied area of a DRAM memory in the prior art.
In a first aspect, an embodiment of the present application provides a dynamic memory, including a substrate and a plurality of stacked memory arrays disposed on the substrate, where the memory arrays include a plurality of memory cells arranged in arrays, and the memory cells include:
a transistor comprising a semiconductor layer, the semiconductor layer comprising a source, a drain, and a channel between the source and the drain, the transistor further comprising a gate;
a capacitor electrically connected to the transistor, the capacitor being located at the drain of the transistor;
a word line at the gate, the word line electrically connected to the transistor;
the dynamic memory further includes a bit line extending through the semiconductor layer of the transistors in the plurality of memory cells, the bit line being located at the source, the transistors in the plurality of memory cells being electrically connected through the bit line.
Optionally, the capacitor includes an inner electrode, a dielectric layer and an outer electrode located at the drain electrode, where the inner electrode, the dielectric layer and the outer electrode all surround the drain electrode of the semiconductor layer, and the inner electrode, the dielectric layer and the outer electrode are sequentially distributed along a direction away from the semiconductor layer.
Optionally, the capacitors of the memory cells in the adjacent two layers of the memory array share the external electrode.
Optionally, the transistor includes a gate and a gate insulating layer, the gate and the gate insulating layer surround the semiconductor layer, and the gate insulating layer are sequentially distributed along a direction away from the semiconductor layer.
Optionally, at least two of the transistors share a bit line in the same layer of memory array.
Optionally, the material of the semiconductor layer comprises epitaxial monocrystalline silicon or other group IV semiconductor material; and/or the material of the bit line comprises tungsten.
In a second aspect, embodiments of the present application provide a storage device including a dynamic memory in embodiments of the present application.
In a third aspect, an embodiment of the present application provides a method for manufacturing a dynamic memory, including:
providing a substrate;
fabricating a plurality of transistors on one side of the substrate, the transistors including a semiconductor layer including a source and a drain, and a channel between the source and the drain;
forming a word line at a gate of the semiconductor layer, the word line being electrically connected to the transistor;
sequentially manufacturing an inner electrode layer, a dielectric layer and an outer electrode layer which surround the semiconductor layer at the drain electrode of the semiconductor layer to form a capacitor;
and manufacturing bit lines at the source electrodes of the semiconductor layers, enabling the bit lines to penetrate through a plurality of semiconductor layers, and enabling the transistors to be electrically connected through the bit lines.
Optionally, the fabricating a plurality of transistors on one side of the substrate includes:
manufacturing a plurality of semiconductor layers on one side of the substrate, wherein the semiconductor layers comprise oppositely arranged source electrodes and drain electrodes;
and sequentially manufacturing a gate insulating layer, a gate electrode and an interlayer insulating layer which surround the semiconductor layer, wherein the gate insulating layer, the gate electrode, the interlayer insulating layer and the semiconductor layer form a transistor.
Optionally, the fabricating a plurality of semiconductor layers on one side of the substrate includes:
manufacturing a plurality of layers of superlattice films on one side of a substrate in a lamination manner through an epitaxial growth process, wherein each layer of superlattice film comprises a sacrificial layer and a semiconductor layer which are sequentially laminated;
etching the sacrificial layers and the semiconductor layers to form a plurality of semiconductor layers arranged at intervals;
etching the portions of the sacrificial layer, which are positioned at the two ends of the semiconductor layer, so as to form grooves;
manufacturing supporting layers at two ends of the semiconductor layer through a deposition process, and enabling the supporting layers to fill the grooves;
and removing the sacrificial layer between the semiconductor layers.
The beneficial technical effects that technical scheme that this application embodiment provided brought include:
the dynamic memory in the embodiment of the application comprises a substrate and a plurality of memory arrays which are arranged on the substrate in a stacked mode, wherein the memory arrays comprise a plurality of memory cells which are arranged in an array mode. The memory cell includes a transistor and a capacitor electrically connected to the transistor, the capacitor being located at a drain of the transistor. The dynamic memory further includes a word line at a gate of the transistor and electrically connected to the transistor, and a bit line penetrating through semiconductor layers of the transistors in the plurality of memory cells, the bit line at a source, the transistors in the plurality of memory cells being electrically connected through the bit line. Through the stacked arrangement of the storage arrays comprising a plurality of storage units, the dynamic memory with a three-dimensional structure is formed, the storage capacity of the dynamic memory is improved, meanwhile, the overlarge area of the dynamic memory caused by the arrangement of the storage units on the same plane is avoided, the structural layout of the storage units is more compact, and the integration of devices is facilitated while the storage density is improved. On the other hand, by making the bit line penetrate through the semiconductor layers of the transistors in the plurality of memory cells, the plurality of transistors arranged in a stacked manner can be electrically connected by one bit line, thereby simplifying the structure and manufacturing process of the dynamic memory.
Advantages of embodiments of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic top view of a dynamic memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic view of the structure of FIG. 1 at section AA;
FIG. 3 is a schematic view of the structure at section BB in FIG. 1;
fig. 4 is a schematic structural view of the section CC in fig. 3;
FIG. 5 is a schematic view of the structure of FIG. 3 at section DD;
FIG. 6 is a schematic diagram of a manufacturing process of a dynamic memory according to an embodiment of the present disclosure;
fig. 7a to fig. 7j are schematic structural diagrams illustrating different processes of fabricating a dynamic memory according to an embodiment of the present application.
In the figure:
10-dynamic memory; 11-a substrate; 12-a storage array; 120-memory cell;
a 121-transistor; 123-word lines; 124-bit line; 125-grid; 126-gate insulation layer; 127-capacitance; 1271-inner electrode; 1272-dielectric layer; 1273-external electrode; 128-an interlayer insulating layer;
20-superlattice thin film; 21-a sacrificial layer; a 22-semiconductor layer; 23-grooves; 24-a support layer; 25-through holes;
31-channel; 32-source; 33-drain.
Detailed Description
Examples of embodiments of the present application are illustrated in the accompanying drawings, in which like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
The memory cells in DRAM memory generally include MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFETs) and a capacitor, which has a simple structure and a high capacity per unit volume. The main working principle of the DRAM memory is to store charges by using a capacitor, and determine whether a binary bit is 1 or 0 according to the quantity of the charges stored in the capacitor. The DRAM memory can also adopt a design without capacitance, namely, a reading MOS tube and a writing MOS tube are arranged in the memory unit, and the grid electrode of the reading MOS tube is electrically connected with the source electrode and the drain electrode of the writing MOS tube. Therefore, no capacitor device is needed to be additionally arranged, and the structure of the memory is further simplified.
The inventor in the art considers that in the existing 1T1C memory (i.e. a MOS transistor and a capacitor are disposed in a memory cell), the memory cell generally adopts a planar layout, and when the memory adopts a large-capacity design, the number of memory cells needs to be increased, which results in occupying a larger area, so that the structure is not compact enough, and the integration of devices is not facilitated.
The embodiment of the application provides a dynamic memory and a storage device, which aim to solve the technical problems in the prior art.
The dynamic memory and the storage device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, 2 and 3, the dynamic memory 10 in the embodiment of the present application includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11, the memory arrays 12 include a plurality of memory cells 120 arranged in an array, and the memory cells 120 include:
a transistor 121 including a semiconductor layer 22, the semiconductor layer 22 including a source electrode 32, a drain electrode 33, and a channel 31 disposed between the source electrode 32 and the drain electrode 33; transistor 121 also includes gate 125;
a capacitor 127 electrically connected to the transistor 121, the capacitor 127 being located at the drain 33 of the transistor 121;
a word line 123 located at the gate 125, the word line 123 being electrically connected to the transistor 121;
the dynamic memory 10 further includes a bit line 124, the bit line 124 extending through the semiconductor layer 22 of the transistors 121 in the plurality of memory cells 120, the bit line 124 being located at the source 32, the transistors 121 in the plurality of memory cells 120 being electrically connected by the bit line 124.
Specifically, the material of the substrate 11 includes silicon, and a plurality of memory arrays 12 are disposed on the substrate 11, and each memory array 12 includes a plurality of memory cells 120 arranged in an array. It should be noted that the number of layers of the memory array 12, and the number of memory cells 120 in each layer of the memory array 12 may be adjusted according to practical situations. Each memory cell 120 includes 1 transistor 121 and 1 capacitor 127. As shown in fig. 1, the transistor 121 includes a semiconductor layer 22, and the material of the semiconductor layer 22 may be epitaxial monocrystalline silicon or other group iv semiconductor materials, which may be specifically determined according to practical situations. The semiconductor layer 22 includes a source electrode 32, a drain electrode 33, and a channel disposed between the source electrode 32 and the drain electrode 33. In the fabrication process of the dynamic memory 10, in fabricating the semiconductor layer 22, the source electrode 32, the channel 31 and the drain electrode 33 are formed on the semiconductor layer 22 through an in-situ doping process. The memory cell 120 includes a capacitor 127, the capacitor 127 being disposed at the drain 33 of the transistor 121. The dynamic memory 10 includes a plurality of word lines 123, and each layer of memory array 12 has a plurality of memory cells 120 (memory cells 120 arranged in the same direction) sharing one word line 123, i.e., the transistors 121 of the plurality of memory cells 120 in each layer of memory array 12 are electrically connected by the word line 123 (the word line 123 is connected to the gate 125 of the transistor 121), and the extending direction of the word line 123 is perpendicular to the extending direction of the semiconductor layer 22. The dynamic memory 10 further includes a plurality of bit lines 124, as shown in fig. 1, 2 and 3, the bit lines 124 are located at the source 32 of the semiconductor layer 22, each bit line 124 penetrates through the transistors 121 in the multi-layer memory array 12, and the plurality of transistors 121 penetrated by the bit lines 124 are electrically connected through the bit lines 124. The material of the bit line 124 includes tungsten or other material with good conductivity, and may be specifically determined according to practical situations.
As shown in fig. 1, 2 and 3, when the dynamic memory 10 is in the writing mode, a high voltage is applied to the gate 125 of the transistor 121 through the word line 123, the channel 31 between the source 32 and the drain 33 of the semiconductor layer 22 is turned on, so that the transistor 121 is in an on state, and a data signal is transmitted to the transistor 121 through the bit line 124 and then transmitted to the capacitor 127 through the transistor 121, so that writing of data into the memory cell 120 is achieved. The level of the data signal voltage determines how much charge is on capacitor 127, which in turn determines whether the binary value of the written data signal is a 0 or a 1. When the dynamic memory 10 is in the read mode, a high voltage is applied to the gate 125 of the transistor 121 through the word line 123, so that the transistor 121 is in an on state, and an electric signal in the capacitor 127 is transmitted to an external read/write circuit (not shown in fig. 1 to 3) through the bit line 124, that is, the read/write circuit reads out data in the memory cell 120 through the bit line 124. It should be noted that, by directly connecting the semiconductor layer 22 to the capacitor 127 and the bit line 124 in contact, the drain 33 of the semiconductor layer 22 is electrically connected to the capacitor 127, and the source 32 of the semiconductor layer 22 is electrically connected to the bit line 124, so that it is not necessary to provide a metal electrode (source or drain) on the semiconductor layer 22.
In the embodiment of the application, the memory array 12 including the plurality of memory cells 120 is stacked to form the dynamic memory 10 with a three-dimensional structure, so that the memory capacity of the dynamic memory 10 is improved, and meanwhile, the overlarge area of the dynamic memory 10 caused by arranging the memory cells 120 on the same plane is avoided, so that the structural layout of the memory cells 120 is more compact, and the integration of devices is more facilitated while the memory density is improved. On the other hand, by penetrating the bit line 124 through the semiconductor layers of the transistors 121 in the plurality of memory cells 120, the plurality of transistors 121 stacked together can be electrically connected by one bit line 124, i.e., the plurality of transistors 121 stacked together share one bit line 124, which is advantageous in simplifying the structure and manufacturing process of the dynamic memory.
Alternatively, in the embodiment of the present application, as shown in fig. 1, 3 and 4, the capacitor 127 includes the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 located at the drain electrode 33, the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 all surround the drain electrode 33 of the semiconductor layer 22, and the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 are sequentially distributed in a direction away from the semiconductor layer 22.
Specifically, in the process of manufacturing the dynamic memory 10, the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 are sequentially grown at the drain electrode 33 of the semiconductor layer 22, and the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 are all disposed around the semiconductor layer 22 and are sequentially distributed along the direction away from the semiconductor layer 22. The outer electrode 1273, the inner electrode 1271, and the dielectric layer 1272 overlap each other to form the capacitor 127. By disposing the outer electrode 1273, the inner electrode 1271, and the dielectric layer 1272 around the semiconductor layer 22, the area where the outer electrode 1273 and the inner electrode 1271 overlap each other can be increased, which is advantageous for improving the capacity of the capacitor 127. In addition, the thickness of the dielectric layer 1272 does not need to be very thin (the smaller the thickness of the dielectric layer 1272 is, the larger the capacity of the capacitor 127 is, and the thickness of the dielectric layer 1272 can be reduced to increase the capacity of the capacitor 127), so that the manufacturing difficulty of the dynamic memory 10 is reduced. The materials of the inner electrode 1271 and the outer electrode 1273 include materials with good conductivity such as titanium nitride, and the material of the dielectric layer 1272 is a material with high dielectric constant, which can be specifically determined according to practical situations.
Alternatively, in the embodiment of the present application, the capacitors 127 of the memory cells 120 in the adjacent two-layer memory array 12 share the external electrode 1273. Specifically, as shown in fig. 3, the external electrode 1273 located between the two memory cells 120 is the external electrode 1273 of the capacitor 127 in the memory cell 120 of the upper layer, and is the external electrode 1273 of the capacitor 127 in the memory cell 120 of the lower layer, so that the structure of the dynamic memory 10 is simplified, and the thickness of the dynamic memory 10 in the first direction in fig. 3 is advantageously reduced. On the other hand, in the process of manufacturing the dynamic memory 10, only one external electrode 1273 needs to be manufactured between two adjacent layers of memory cells 120, thereby simplifying the manufacturing process of the dynamic memory 10.
In the embodiment of the present application, the transistor 121 includes the gate electrode 125 and the gate insulating layer 126, the gate electrode 125 and the gate insulating layer 126 surround the semiconductor layer 22, and the gate electrode 125 and the gate insulating layer 126 are sequentially distributed in a direction away from the semiconductor layer 22. Specifically, as shown in fig. 1, 2, 3, and 5, the gate electrode 125 and the gate insulating layer 126 surround the semiconductor layer 22, and the gate electrode 125 and the gate insulating layer 126 are sequentially distributed in a direction away from the semiconductor layer 22. The gates 125 of the transistors 121 located at different layers are insulated from each other by an interlayer insulating layer 128. By providing the gate insulating layer 126 and the gate electrode 125 around the semiconductor layer 22, the area where the gate electrode 125 overlaps with the semiconductor layer 22 can be increased, and thus control of the on/off of the transistor 121 can be made easier.
Alternatively, in embodiments of the present application, at least two transistors 121 share a bit line 124 in the same layer of memory array 12. Specifically, as shown in fig. 1 and 3, in the same layer of memory array 12, the transistors 121 in two adjacent memory cells 120 (the transistors 121 in the same line in fig. 1) share the bit line 124, so that the number of memory cells 120 is increased, the memory density is improved, and meanwhile, the occupation of excessive area is avoided, which is beneficial to improving the integration level of the device. It should be noted that, in the same layer of memory array 12, the number of transistors 121 of the common bit line 124 may be adjusted according to practical situations, and the larger the number of transistors 121 of the common bit line 124, the more beneficial is to reduce the area of the dynamic memory 10 and improve the integration level of the dynamic memory 10.
Based on the same inventive concept, the embodiments of the present application further provide a storage device, where the storage device includes the dynamic memory 10 in the foregoing embodiments, and has the beneficial effects of the dynamic memory 10 in the foregoing embodiments, which are not described herein again. Specifically, the storage device in the embodiments of the present application may be a main memory of a computer, etc., and may be specifically determined according to actual situations, which is not limited herein.
Based on the same inventive concept, the embodiment of the present application further provides a method for manufacturing the dynamic memory 10, as shown in fig. 6, including:
s101, providing a substrate;
s102, manufacturing a plurality of transistors on one side of a substrate, wherein the transistors comprise a semiconductor layer, and the semiconductor layer comprises a source electrode and a drain electrode which are oppositely arranged, and a channel positioned between the source electrode and the drain electrode;
s103, manufacturing a word line at the grid electrode of the semiconductor layer, wherein the word line is electrically connected with the transistor;
s104, sequentially manufacturing an inner electrode layer, a dielectric layer and an outer electrode layer which surround the semiconductor layer at the drain electrode of the semiconductor layer to form a capacitor;
s105, a bit line is manufactured at the source electrode of the semiconductor layer, the bit line penetrates through the semiconductor layers, and the transistors are electrically connected through the bit line.
In the manufacturing method provided in the embodiment of the present application, the dynamic memory 10 includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11, the memory arrays 12 include a plurality of memory cells 120 arranged in an array, and the memory cells 120 include transistors 121 and capacitors 127. The dynamic memory 10 further includes a word line 123 and a bit line 124, the word line 123 being located at a gate 125 of the transistor 121 and electrically connected to the transistor 121, the bit line 124 extending through the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120, the bit line 124 being located at the source 32, the transistor 121 in the plurality of memory cells 120 being electrically connected through the bit line 124. By stacking the memory array 12 including the plurality of memory cells 120, the dynamic memory 10 having a three-dimensional structure is formed, and the memory capacity of the dynamic memory 10 is improved, and meanwhile, the excessive area of the dynamic memory 10 caused when the memory cells 120 are arranged on the same plane is avoided, so that the structural layout of the memory cells 120 is more compact, and the integration of devices is more facilitated while the memory density is improved.
In the process of manufacturing the dynamic memory 10, the word lines 123 may be etched by a modification etching process, so that the word lines 123 located in different layers are not uniform, even if the word lines 123 in different layers are stepped. As shown in fig. 1 and 2, the length of the word line 123 in the second direction (gradually away from the substrate 1111) in fig. 2 is gradually reduced along the first direction in fig. 2, so that the word lines 123 located at different layers can be conveniently routed through routing and read-write circuits (not shown in fig. 1 and 2).
Optionally, in a specific embodiment of the present application, fabricating the plurality of transistors 121 on one side of the substrate 11 includes:
manufacturing a plurality of semiconductor layers on one side of a substrate, wherein the semiconductor layers comprise a source electrode and a drain electrode which are oppositely arranged;
and sequentially manufacturing a gate insulating layer, a gate electrode and an interlayer insulating layer which surround the semiconductor layer, wherein the gate insulating layer, the gate electrode, the interlayer insulating layer and the semiconductor layer form a transistor.
Optionally, in a specific embodiment of the present application, fabricating the plurality of semiconductor layers 22 on one side of the substrate 11 includes:
manufacturing a plurality of layers of superlattice films on one side of a substrate through an epitaxial growth process, wherein each layer of superlattice film comprises a sacrificial layer and a semiconductor layer 22 which are sequentially stacked;
etching the multi-layer sacrificial layer and the multi-layer semiconductor layer to form a plurality of semiconductor layers arranged at intervals;
etching the portions of the sacrificial layer at two ends of the semiconductor layer to form grooves;
manufacturing supporting layers at two ends of the semiconductor layer through a deposition process, and filling the supporting layers into the grooves;
and removing the sacrificial layer between the semiconductor layers.
The following describes the method for manufacturing the dynamic memory 10 in the embodiment of the present application in detail with reference to the accompanying drawings.
As shown in fig. 7a, first, a substrate 11 is provided, and the material of the substrate 11 includes silicon.
As shown in fig. 7b, next, a plurality of superlattice films 20 are stacked on one side of the substrate 11 by an epitaxial growth process, each of the superlattice films 20 including a sacrificial layer 21 and a semiconductor layer 22 distributed along the first direction in fig. 7b, the material of the sacrificial layer 21 including silicon germanium (SiGe), and the material of the semiconductor layer 22 including single crystal silicon. The source 32 and drain 33, and the channel 31 of the source 32 and drain 33 are formed by a semiconductor oxide in-situ doping process while the semiconductor layer 22 is being fabricated. The number of layers of the superlattice film 20 may be determined according to practical situations, and may be 8 layers, 16 layers, or 32 layers, for example. Note that, as shown in fig. 7b, only three sacrificial layers 21 are shown as an illustration, and do not represent an actual situation.
As shown in fig. 7c, next, the multi-layered sacrificial layer 21 and the semiconductor layer 22 are etched to remove a part of the materials of the sacrificial layer 21 and the semiconductor layer 22 so that the semiconductor layer 22 forms a structure in which the layers are disposed at intervals. The number of semiconductor layers 22 and the distance d between the semiconductor layers 22 can be adjusted according to practical situations.
As shown in fig. 7d, next, portions of the sacrificial layer 21 located at both ends of the semiconductor layer 22 are etched to form trenches 23. The width w of the groove 23 in the third direction in fig. 7d can be adjusted according to the actual situation.
As shown in fig. 7e, the support layer 24 is then deposited by an atomic deposition process or a chemical vapor deposition process (the support layer 24 is located at both ends of the semiconductor layer 22), and the support layer 24 is made to fill the trench 23. The material of the support layer 24 includes materials having good insulating properties such as silicon nitride and silicon oxide, and may be specifically determined according to practical situations. The purpose of the trench 23 and the support layer 24 is to support the multi-layered semiconductor layer 22 by the support layer 24 after the sacrificial layer 21 is removed later, so as to prevent the collapse of the structure. The material of the support layer 24 includes oxide, nitride, etc. (e.g., silicon oxide and silicon nitride), and may be specifically adjusted according to the actual situation.
As shown in fig. 7f, next, the sacrificial layer 21 between the semiconductor layers 22 is etched and removed by adjusting the etching selectivity ratio of the sacrificial layer 21 and the semiconductor layers 22 (such that the rate at which the sacrificial layer 21 is etched is greater than the rate at which the semiconductor layers 22 are etched), leaving the semiconductor layers 22 as a plurality of semiconductor layers 22. The support layers 24 at both ends of the semiconductor layer 22 may support the semiconductor layer 22.
As shown in fig. 7g, next, a gate insulating layer 126, a gate electrode 125, and an interlayer insulating layer 128 are sequentially grown on the semiconductor layer 22 around the semiconductor layer 22, and a conductive material is continuously grown between the gate electrodes 125 located at the same layer to form a connection word line 123. The word lines 123 are etched by a trim etching process so that the lengths of the word lines 123 located at different layers are not uniform even though the word lines 123 at different layers are stepped.
As shown in fig. 7h, next, an inner electrode 1271, a dielectric layer 1272 and an outer electrode 1273 surrounding the semiconductor layer 22 are sequentially grown on the semiconductor layer 22 in the region where the capacitor 127 is to be fabricated (i.e., at the drain electrode 33 of the semiconductor layer 22), the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 constituting the capacitor 127. The external electrode 1273 between the two semiconductor layers 22 is the external electrode 1273 of the capacitor 127 corresponding to the semiconductor layer 22 of the upper layer, and is the external electrode 1273 of the capacitor 127 corresponding to the semiconductor layer 22 of the lower layer, thereby simplifying the structure of the dynamic memory and the manufacturing process of the dynamic memory. The materials of the inner electrode 1271 and the outer electrode 1273 include titanium nitride, and may be specifically determined according to practical situations.
As shown in fig. 7i, next, a via hole 25 is opened at the source electrode 32 of the semiconductor layer 22 by an etching process, and the via hole 25 penetrates through the multi-layered semiconductor layer 22.
As shown in fig. 7j, then, a metal material is filled in the via holes 25 to form bit lines 124. The sources 32 of the transistors 121 located in the different layers are electrically connected by bit lines 124. It should be noted that the blank area between the word line 123 and the bit line 124 may be filled with an isolation material (not shown in fig. 7 j) having good insulation performance, so as to avoid voids in the structure of the dynamic memory 10.
By adopting the manufacturing method in the embodiment of the application, the manufacturing of the dynamic memory 10 with the laminated structure is easier in process, so that large-scale mass production of the dynamic memory 10 with the laminated structure is possible.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
1. in the embodiment of the present application, the dynamic memory 10 includes a substrate 11 and a plurality of memory arrays 12 stacked on the substrate 11, the memory arrays 12 include a plurality of memory cells 120 arranged in an array, and the memory cells 120 include transistors 121 and capacitors 127. The dynamic memory 10 further includes a word line 123 and a bit line 124, the word line 123 being located at a gate 125 of the transistor 121 and electrically connected to the transistor 121, the bit line 124 extending through the semiconductor layer 22 of the transistor 121 in the plurality of memory cells 120, the bit line 124 being located at the source 32, the transistor 121 in the plurality of memory cells 120 being electrically connected through the bit line 124. By stacking the memory array 12 including the plurality of memory cells 120, the dynamic memory 10 having a three-dimensional structure is formed, and the memory capacity of the dynamic memory 10 is improved, and meanwhile, the excessive area of the dynamic memory 10 caused when the memory cells 120 are arranged on the same plane is avoided, so that the structural layout of the memory cells 120 is more compact, and the integration of devices is more facilitated while the memory density is improved. On the other hand, by making the bit line penetrate through the semiconductor layer 22 of the transistor in the plurality of memory cells, the plurality of transistors arranged in a stacked state can be electrically connected by one bit line, thereby simplifying the structure and manufacturing process of the dynamic memory.
2. In an embodiment of the present application, the capacitor 127 includes an inner electrode 1271, a dielectric layer 1272 and an outer electrode 1273 at the drain electrode 33, the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 all surrounding the drain electrode 33 of the semiconductor layer 22, the inner electrode 1271, the dielectric layer 1272 and the outer electrode 1273 being distributed in sequence in a direction away from the semiconductor layer 22. By disposing the outer electrode 1273, the inner electrode 1271, and the dielectric layer 1272 around the semiconductor layer 22, the area of the outer electrode 1273 and the inner electrode 1271 can be increased, which is advantageous for improving the capacity of the capacitor 127.
3. In the embodiment of the present application, the capacitors 127 of the memory cells 120 in the adjacent two layers of the memory array 12 share the external electrode 1273, i.e., the external electrode 1273 located between the two layers of the memory cells 120 is the external electrode 1273 of the capacitor 127 in the memory cell 120 of the previous layer or the external electrode 1273 of the capacitor 127 in the memory cell 120 of the next layer, so that the structure and the manufacturing process of the dynamic memory 10 can be simplified.
4. In the embodiment of the present application, at least two transistors 121 share the bit line 124 in the same layer of the memory array 12, so that the number of the memory cells 120 is increased, the memory density is improved, and meanwhile, the occupation of excessive area is avoided, which is beneficial to improving the integration level of the device.
In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for a person skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (10)
1. A dynamic memory comprising a substrate and a plurality of memory arrays disposed on the substrate in a stacked configuration, the memory arrays comprising a plurality of memory cells arranged in an array, the memory cells comprising:
a transistor comprising a semiconductor layer, the semiconductor layer comprising a source, a drain, and a channel between the source and the drain, the transistor further comprising a gate;
a capacitor electrically connected to the transistor, the capacitor being located at the drain of the transistor;
a word line at the gate, the word line electrically connected to the transistor;
the dynamic memory further includes a bit line extending through the semiconductor layer of the transistors in the plurality of memory cells, the bit line being located at the source, the transistors in the plurality of memory cells being electrically connected through the bit line.
2. The dynamic memory of claim 1, wherein the capacitor comprises an inner electrode, a dielectric layer, and an outer electrode at the drain electrode, the inner electrode, the dielectric layer, and the outer electrode all surrounding the drain electrode of the semiconductor layer, the inner electrode, the dielectric layer, and the outer electrode being sequentially distributed in a direction away from the semiconductor layer.
3. The dynamic memory of claim 2, wherein the external electrode is shared by capacitances of the memory cells in adjacent two layers of the memory array.
4. The dynamic memory of claim 1, wherein the transistor comprises a gate and a gate insulating layer, the gate and the gate insulating layer surrounding the semiconductor layer, the gate and the gate insulating layer being sequentially distributed in a direction away from the semiconductor layer.
5. The dynamic memory of claim 1, wherein at least two of said transistors share a bit line in a same layer of memory array.
6. The dynamic memory of any one of claims 1 to 5, wherein the material of the semiconductor layer comprises epitaxial monocrystalline silicon or other group iv semiconductor material; and/or the material of the bit line comprises tungsten.
7. A memory device comprising the dynamic memory of any one of claims 1 to 6.
8. A method for manufacturing a dynamic memory, comprising:
providing a substrate;
fabricating a plurality of transistors on one side of the substrate, the transistors including a semiconductor layer including a source and a drain, and a channel between the source and the drain;
forming a word line at a gate of the semiconductor layer, the word line being electrically connected to the transistor;
sequentially manufacturing an inner electrode layer, a dielectric layer and an outer electrode layer which surround the semiconductor layer at the drain electrode of the semiconductor layer to form a capacitor;
and manufacturing bit lines at the source electrodes of the semiconductor layers, enabling the bit lines to penetrate through a plurality of semiconductor layers, and enabling the transistors to be electrically connected through the bit lines.
9. The method of fabricating of claim 8, wherein fabricating a plurality of transistors on one side of the substrate comprises:
manufacturing a plurality of semiconductor layers on one side of the substrate, wherein the semiconductor layers comprise oppositely arranged source electrodes and drain electrodes;
and sequentially manufacturing a gate insulating layer, a gate electrode and an interlayer insulating layer which surround the semiconductor layer, wherein the gate insulating layer, the gate electrode, the interlayer insulating layer and the semiconductor layer form a transistor.
10. The method of fabricating of claim 9, wherein fabricating a plurality of semiconductor layers on one side of the substrate comprises:
manufacturing a plurality of superlattice thin film layers on one side of a substrate in a lamination manner through an epitaxial growth process, wherein each superlattice thin film layer comprises a sacrificial layer and a semiconductor channel layer which are sequentially laminated;
etching the sacrificial layers and the semiconductor layers to form a plurality of semiconductor layers arranged at intervals;
etching the portions of the sacrificial layer, which are positioned at the two ends of the semiconductor layer, so as to form grooves;
manufacturing supporting layers at two ends of the semiconductor layer through a deposition process, and enabling the supporting layers to fill the grooves;
and removing the sacrificial layer between the semiconductor layers.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210465087.4A CN116133405A (en) | 2022-04-25 | 2022-04-25 | Dynamic memory, manufacturing method thereof and memory device |
| PCT/CN2022/121034 WO2023206948A1 (en) | 2022-04-25 | 2022-09-23 | Dynamic memory and manufacturing method therefor and storage device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210465087.4A CN116133405A (en) | 2022-04-25 | 2022-04-25 | Dynamic memory, manufacturing method thereof and memory device |
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| CN116133405A true CN116133405A (en) | 2023-05-16 |
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| CN202210465087.4A Pending CN116133405A (en) | 2022-04-25 | 2022-04-25 | Dynamic memory, manufacturing method thereof and memory device |
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| CN118317601A (en) * | 2024-04-07 | 2024-07-09 | 北京超弦存储器研究院 | Semiconductor device, manufacturing method thereof and electronic equipment |
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| US5977580A (en) * | 1995-12-29 | 1999-11-02 | Lg Semicon Co., Ltd. | Memory device and fabrication method thereof |
| US20090108316A1 (en) * | 2007-10-26 | 2009-04-30 | Weize Xiong | Memory device with memory cell including mugfet and fin capacitor |
| CN109616474A (en) * | 2017-09-29 | 2019-04-12 | 三星电子株式会社 | Semiconductor storage unit |
| CN114121958A (en) * | 2020-08-25 | 2022-03-01 | 南亚科技股份有限公司 | Memory element and forming method thereof |
| CN114171520A (en) * | 2020-09-11 | 2022-03-11 | 三星电子株式会社 | Semiconductor memory device with a plurality of memory cells |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110875315A (en) * | 2018-08-31 | 2020-03-10 | 长鑫存储技术有限公司 | Memory and semiconductor device |
| KR102634614B1 (en) * | 2019-07-12 | 2024-02-08 | 에스케이하이닉스 주식회사 | Vertical memory device |
| JP7341810B2 (en) * | 2019-09-13 | 2023-09-11 | キオクシア株式会社 | semiconductor storage device |
| KR20220019498A (en) * | 2020-08-10 | 2022-02-17 | 에스케이하이닉스 주식회사 | Stacked Memory Device |
| KR20220049866A (en) * | 2020-10-15 | 2022-04-22 | 에스케이하이닉스 주식회사 | Memory cell and semiconductor dedvice with the same |
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2022
- 2022-04-25 CN CN202210465087.4A patent/CN116133405A/en active Pending
- 2022-09-23 WO PCT/CN2022/121034 patent/WO2023206948A1/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5977580A (en) * | 1995-12-29 | 1999-11-02 | Lg Semicon Co., Ltd. | Memory device and fabrication method thereof |
| US20090108316A1 (en) * | 2007-10-26 | 2009-04-30 | Weize Xiong | Memory device with memory cell including mugfet and fin capacitor |
| CN109616474A (en) * | 2017-09-29 | 2019-04-12 | 三星电子株式会社 | Semiconductor storage unit |
| CN114121958A (en) * | 2020-08-25 | 2022-03-01 | 南亚科技股份有限公司 | Memory element and forming method thereof |
| CN114171520A (en) * | 2020-09-11 | 2022-03-11 | 三星电子株式会社 | Semiconductor memory device with a plurality of memory cells |
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