WO2021053473A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2021053473A1
WO2021053473A1 PCT/IB2020/058438 IB2020058438W WO2021053473A1 WO 2021053473 A1 WO2021053473 A1 WO 2021053473A1 IB 2020058438 W IB2020058438 W IB 2020058438W WO 2021053473 A1 WO2021053473 A1 WO 2021053473A1
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Prior art keywords
oxide
insulator
transistor
conductor
layer
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PCT/IB2020/058438
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French (fr)
Japanese (ja)
Inventor
太田将志
安藤善範
長塚修平
越田樹
大下智
方堂涼太
津田一樹
鈴木陽夫
Original Assignee
株式会社半導体エネルギー研究所
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Application filed by 株式会社半導体エネルギー研究所 filed Critical 株式会社半導体エネルギー研究所
Priority to JP2021546062A priority Critical patent/JPWO2021053473A5/en
Priority to KR1020227008487A priority patent/KR20220062524A/en
Priority to DE112020004415.7T priority patent/DE112020004415T5/en
Priority to CN202080065554.3A priority patent/CN114424339A/en
Priority to US17/760,836 priority patent/US20220352384A1/en
Publication of WO2021053473A1 publication Critical patent/WO2021053473A1/en

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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
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    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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Definitions

  • One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Further, one aspect of the present invention relates to semiconductor wafers, modules, and electronic devices.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • a semiconductor device such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of the semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.
  • One aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Also, one aspect of the present invention relates to a process, machine, manufacture, or composition (composition of matter).
  • transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • Non-Patent Document 1 In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystal nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).
  • Non-Patent Document 1 and Non-Patent Document 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
  • One aspect of the present invention is to provide a semiconductor device having good reliability. Another object of one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Another object of one aspect of the present invention is to provide a semiconductor device having a large on-current. Another object of one aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Another object of one aspect of the present invention is to provide a semiconductor device having low power consumption.
  • One aspect of the present invention is to oxidize a first layer in which a first transistor having an oxide semiconductor is provided on a substrate, a second layer on the first layer, and an oxidation on the second layer. It has a third layer provided with a second transistor having a physical semiconductor, and the total internal stress of the first layer and the total internal stress of the third layer act in the first direction. The total internal stress of the second layer acts in the direction opposite to the first direction.
  • One aspect of the present invention is to oxidize a first layer in which a first transistor having an oxide semiconductor is provided on a substrate, a second layer on the first layer, and an oxidation on the second layer.
  • a first transistor having an oxide semiconductor is provided on a substrate
  • a second layer on the first layer between the third layer provided with the second transistor having a physical semiconductor
  • between the first layer and the second layer between the fourth layer, and between the second layer and the third layer.
  • the fifth layer, the total internal stress of the first layer and the total internal stress of the third layer act in the first direction
  • the total internal stress of the second layer is Acting in the direction opposite to the first direction
  • the fourth layer and the fifth layer contain a film having a barrier property.
  • the total internal stress of the fourth layer and the total internal stress of the fifth layer act in the first direction.
  • the film having a barrier property suppresses the diffusion of hydrogen and impurities.
  • the fourth layer seals the first layer
  • the fifth layer seals the third layer
  • the second layer has a conductor that functions as wiring.
  • the oxide semiconductor is an In-Ga-Zn oxide.
  • a semiconductor device having good reliability it is possible to provide a semiconductor device having good electrical characteristics. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Further, according to one aspect of the present invention, a semiconductor device having low power consumption can be provided.
  • 1A and 1B are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • 2A, 2B, 2C, and 2D are a cross-sectional view and a top view of the semiconductor device according to one aspect of the present invention.
  • 3A, 3B, 3C, and 3D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
  • 4A, 4B, 4C, and 4D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
  • 5A, 5B, 5C, and 5D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
  • 6A, 6B, 6C, and 6D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
  • 7A, 7B, 7C, and 7D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
  • 8A, 8B, 8C, and 8D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
  • 9A, 9B, 9C, and 9D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
  • 10A, 10B, and 10C are a cross-sectional view and a top view of the semiconductor device according to one aspect of the present invention.
  • 11A, 11B, 11C, and 11D are cross-sectional views and top views of the semiconductor device according to one aspect of the present invention.
  • FIG. 12 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
  • FIG. 13 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
  • FIG. 14 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention.
  • 15A and 15B are a block diagram and a perspective view showing a configuration example of a storage device according to one aspect of the present invention.
  • 16A, 16B, 16C, 16D, 16E, 16F, 16G, and 16H are circuit diagrams showing a configuration example of a storage device according to one aspect of the present invention.
  • 17A and 17B are schematic views of a semiconductor device according to one aspect of the present invention.
  • 18A, 18B, 18C, 18D, and 18E are schematic views of a storage device according to an aspect of the present invention.
  • 19A, 19B, 19C, 19D, 19E, 19F, 19G, 19H are diagrams showing an electronic device according to an aspect of the present invention.
  • 20A and 20B are views for explaining the cross-sectional STEM observation results of the sample in this example.
  • FIG. 21 is a diagram for explaining the cross-sectional STEM observation results of the sample in this example.
  • FIG. 22A, FIG. 22B is a diagram for explaining the I d -V g measurements of the transistor included in the sample in the present embodiment.
  • 23A and 23B are diagrams for explaining the influence of the fluctuation of the threshold value of the transistor of the sample in this embodiment on the field effect mobility ( ⁇ FEs) of each transistor 200.
  • FIG. 24B is a diagram illustrating a measurement result of I d -V g measured results and the mobility of the transistor having the sample in this embodiment.
  • FIG. 25 is a diagram for explaining the measurement result of the off-leakage current of the transistor included in the sample in this embodiment.
  • 26A and 26B are diagrams for explaining the writing speed of the transistor included in the sample in this embodiment.
  • FIG. 27 is a diagram illustrating the results of the writing operation and the holding test when the sample functions as the multi-valued memory of the transistor in this embodiment.
  • FIG. 28 is a diagram illustrating a writing time and an erasing time in the multi-valued operation of the transistor included in the sample in this embodiment.
  • FIG. 29 is a diagram for explaining the result of the rewrite resistance test in the binary operation of the transistor included in the sample in this embodiment.
  • Figure 30 is a diagram for explaining the evaluation of the cut-off frequency f T of the transistor included in the sample in the present embodiment.
  • the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may not be reflected in the figure for the sake of easy understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular sign may be added.
  • a top view also referred to as a "plan view”
  • a perspective view the description of some components may be omitted.
  • some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first” can be appropriately replaced with the “second” or “third” for explanation.
  • the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or a sentence, and a connection relationship other than the connection relationship shown in the figure or the sentence is also disclosed in the figure or the sentence.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. It also has a region (hereinafter, also referred to as a channel forming region) in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode). A current can flow between the source and the drain through the channel formation region.
  • the channel forming region means a region in which a current mainly flows.
  • source and drain functions may be interchanged when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.
  • the channel length is, for example, the source in the top view of the transistor, the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the channel formation region.
  • the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width is, for example, the channel length direction in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other in the top view of the transistor, or the channel formation region. Refers to the length of the channel formation region in the vertical direction with reference to. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor (hereinafter, also referred to as “effective channel width”).
  • effective channel width when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible.
  • the proportion of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width when simply described as a channel width, it may refer to an apparent channel width.
  • channel width may refer to an effective channel width.
  • the values of the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the semiconductor impurities refer to, for example, other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors.
  • transition metals other than the main component such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water may also function as an impurity.
  • oxygen deficiency may be formed in the oxide semiconductor due to the mixing of impurities.
  • silicon oxide nitride has a higher oxygen content than nitrogen as its composition. Further, silicon nitride has a higher nitrogen content than oxygen in its composition.
  • the term “insulator” can be paraphrased as an insulating film or an insulating layer.
  • the term “conductor” can be rephrased as a conductive film or a conductive layer.
  • semiconductor can be paraphrased as a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of ⁇ 5 ° or more and 5 ° or less is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° or more and 30 ° or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the drain current per 1 ⁇ m of the channel width flowing through the transistor is 1 ⁇ 10 ⁇ at room temperature. It means that it is 20 A or less, 1 ⁇ 10 -18 A or less at 85 ° C, or 1 ⁇ 10 -16 A or less at 125 ° C.
  • FIG. 1 is a cross-sectional view of a semiconductor device having a transistor 200 according to an aspect of the present invention. In the semiconductor device shown in FIG. 1, some elements are omitted for the purpose of clarifying the figure.
  • the semiconductor device 10 of one aspect of the present invention includes a substrate 11, an adjusting layer 12 on the substrate, a layer 14 including a transistor, an adjusting layer 16, and a layer 18 containing a transistor.
  • Each layer constitutes a laminated structure.
  • at least one or more transistors 200_1 are provided on the layer 14 including the transistors, and at least one or more transistors 200_1 are provided on the layer 18 including the transistors.
  • the transistor 200_1 and the transistor 200_2 may be a transistor having a different structure or a transistor having the same structure. Further, in the following specification, the transistor 200_1 and the transistor 200_2 may be collectively referred to as a transistor 200.
  • the transistor 200 uses a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor as a semiconductor that includes a region in which a channel is formed (hereinafter, also referred to as a channel formation region). Is preferable.
  • an oxide semiconductor that functions as an oxide semiconductor as a semiconductor that includes a region in which a channel is formed (hereinafter, also referred to as a channel formation region). Is preferable.
  • oxide semiconductors for example, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium). , Hafnium, tantalum, tungsten, gallium, etc. (one or more) and the like may be used. Further, as the oxide semiconductor, In-Ga-Zn oxide, In-Ga oxide, or In-Zn oxide may be used.
  • the transistor 200 using an oxide semiconductor in the channel forming region has an extremely small leakage current in a non-conducting state, it is possible to provide a semiconductor device with low power consumption.
  • oxide semiconductor various elements can be laminated and integrated three-dimensionally. That is, since the oxide semiconductor can be deposited by using a sputtering method or the like, it should be a three-dimensional integrated circuit (three-dimensional integrated circuit) in which the circuit is developed not only on the plane of the substrate but also in the vertical direction. Can be done.
  • the internal stress generated from the thin film formed on the substrate also increases in the case of high integration.
  • the substrate and the semiconductor device provided on the substrate are distorted, and the focus shift occurs in the exposure process, and as a result, the focus blur may occur.
  • the substrate is distorted, when it is put into the apparatus, the substrate cannot be adsorbed, or even if it is adsorbed, the substrate becomes unstable. In addition, misalignment may occur.
  • the internal stress has two directions, tensile stress and compressive stress.
  • the tensile stress acts on the film in the direction of expansion at the interface between the substrate and the thin film, and acts on the substrate in the direction of contraction. Therefore, when the substrate is thin and the mechanical strength is not sufficiently strong, the substrate is deformed so that the surface to be filmed becomes a concave surface.
  • the substrate is thick or the mechanical strength is sufficiently strong and the thin film cannot withstand the tensile stress, cracks may occur on the film surface.
  • the compressive stress acts on the film in the direction of compression at the interface between the substrate and the thin film, and acts on the substrate in the direction of expansion. Therefore, when the substrate is thin and the mechanical strength is not sufficiently strong, the substrate is deformed so that the surface to be filmed becomes a convex surface. On the other hand, if the substrate is thick or the mechanical strength is sufficiently strong and the thin film cannot withstand the tensile stress, the film may be lifted from the substrate surface, cracked on the entire surface and peeled off, and the peeled films may overlap each other. ..
  • the internal stress of the layered structure of the repeating unit that is, the combined stress of the internal stresses of all the films constituting the layered structure of the repeating unit (also referred to as total internal stress) is , In the same direction. Therefore, the more the layered structure of the repeating unit is laminated, the larger the total internal stress applied in one direction.
  • n is a natural number of 2 or more layers
  • the adjusting layer has the total internal stress of the layer structure of the repeating unit and the internal stress in the opposite direction.
  • the layer structure of the repeating unit when the total internal stress acts in the compression direction, the layer structure may be such that the total internal stress of the adjusting layer acts in the tensile direction.
  • an adjusting layer 16 between the layer 14 including the transistor and the layer 18 containing the transistor.
  • the total internal stress acts in the same direction in the layer 14 containing the transistor and the layer 18 containing the transistor.
  • the total internal stress of the adjusting layer 16 acts in the opposite direction to the layer 14 including the transistor or the layer 18 containing the transistor.
  • the adjustment layer 16 may have a total internal stress in the opposite direction to the total internal stress of the layer 14 including the transistor and the layer 18 including the transistor. That is, when the adjusting layer 16 has a laminated structure, it is not necessary for all the layers of the adjusting layer 16 to act in the opposite directions to the layer 14 including the transistor and the layer 18 containing the transistor.
  • the internal stress when the adjusting layer 16 is regarded as one layer may act in the opposite direction to the layer 14 including the transistor and the layer 18 containing the transistor. Therefore, as a film in contact with the layer including the transistor of the adjustment layer 16, a film that functions as a buffer may be included.
  • the internal stress of the buffer film may act in the same direction as the layer 14 containing the transistor and the layer 18 containing the transistor.
  • the adjustment layer 16 can also serve as a wiring layer. Therefore, the adjusting layer 16 may include a conductor. Specifically, it may have a conductor that electrically connects the transistor 200_1 and the transistor 200_2. Further, the wiring electrically connected to the transistor 200_1 or the transistor 200_2 may be routed.
  • the adjustment layer 12 may be arranged as needed, and is not necessarily an essential configuration. Further, although not shown, an adjustment layer may be provided on the layer 18 including the transistor.
  • the substrate is not distorted, so that the alignment margin can be reduced and the degree of freedom in design is increased. be able to.
  • the semiconductor device 20 includes a substrate 21, an insulator 23 having a barrier property, a layer 24 including a transistor, an adjusting layer 26, and an insulator 27 having a barrier property. And a layer 28 including a transistor, and each layer constitutes a laminated structure. Further, at least one or more transistors 200_1 are provided on the layer 24 including the transistors, and at least one or more transistors 200_1 are provided on the layer 28 including the transistors.
  • an oxide semiconductor that can be easily laminated is used as the semiconductor including the region where the channel is formed.
  • the oxide semiconductor of the transistor 200 is more likely to have its electrical characteristics fluctuated due to impurities such as hydrogen, water, and metal oxides, so it is preferable to block the intrusion of impurities from the outside.
  • an insulator 23 having a barrier property or an insulator 27 having a barrier property to seal the layer 24 containing the transistor and the layer 28 containing the transistor.
  • the function of suppressing impurities is a function of suppressing the diffusion of any one or all of the impurities.
  • a membrane having a function of suppressing the diffusion of impurities may be referred to as a membrane in which impurities are difficult to permeate, a membrane having low impurity permeability, a membrane having a barrier property against impurities, a barrier film against impurities, and the like.
  • the barrier film may be referred to as a conductive barrier film.
  • the insulator 23 having a barrier property is provided in contact with the lower surface, the upper surface, and the side surface of the layer 24 having the transistor.
  • the insulator 23 having a barrier property can be formed by forming a film of the insulator having a barrier property a plurality of times.
  • the insulator 23 can be formed by a film having at least three layers. Specifically, after forming the first insulating film having a barrier property, a layer having a transistor is formed. An insulating film having a second barrier property is formed on the layer having the transistor. Subsequently, the layer having the transistor and a part of the insulating film having the second barrier property are removed to expose the insulating film having the first barrier property. Next, it has a third barrier property so as to be in contact with the exposed surface of the insulating film having the first barrier property, the side surface of the layer having the transistor, and the upper surface and the side surface of the insulating film having the second barrier property. It is advisable to form a film.
  • the transistor 200_1 can be sealed by the insulator 23 having a barrier property.
  • a metal oxide such as aluminum oxide or a nitride such as silicon nitride may have a function of suppressing the diffusion of oxygen (hereinafter, also referred to as a barrier property). ..
  • a barrier property when compared with silicon oxide, aluminum oxide and silicon nitride have a function of suppressing the diffusion of oxygen or impurities such as water and hydrogen.
  • silicon nitride can be used as the insulator 23 having a barrier property or the insulator 27 having a barrier property.
  • silicon nitride can be used as the insulator 23 having a barrier property or the insulator 27 having a barrier property.
  • aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, metal oxides such as neodymium oxide or tantalum oxide, and nitrides such as silicon nitride. can be used.
  • the distortion of the substrate 21 can be reduced by providing the adjusting layer 26. it can. Therefore, the alignment margin can be reduced in the step of creating the laminated structure of the insulator 23 having a barrier property provided on the adjusting layer 26 and the layer 28 having the transistor.
  • the shift of focus can be suppressed, and as a result, the occurrence of focus blur can be reduced. Further, when it is put into the apparatus, the substrate can be adsorbed in a stable state. Further, the deviation with respect to the alignment can be suppressed.
  • the substrate is not distorted, so that the degree of freedom in design can be increased. Further, when a laminated structure having n or more layers is provided, film breakage is unlikely to occur even when the uppermost layer is provided, and a semiconductor device with a high yield can be manufactured.
  • a semiconductor device having a transistor 200 according to one aspect of the present invention is a transistor having an oxide semiconductor in a channel forming region.
  • FIG. 2 is a top view and a cross-sectional view of a semiconductor device having the transistor 200 according to one aspect of the present invention.
  • FIG. 2A is a top view of the semiconductor device.
  • 2B and 2C are cross-sectional views of the semiconductor device.
  • FIG. 2B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 2A.
  • FIG. 2C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 2A.
  • FIG. 2D is a cross-sectional view of the portion shown by the alternate long and short dash line of A5-A6 in FIG. 2A.
  • FIG. 2A some elements are omitted for the purpose of clarifying the figure.
  • the semiconductor device includes a transistor 200 and an insulator 214, an insulator 216, an insulator 280, an insulator 282, and an insulator 284 that function as interlayer films.
  • the insulator 280 is provided in contact with at least the oxide 230.
  • the transistor 200 is arranged on a substrate (not shown) and on the conductor 205 arranged so as to be embedded in the insulator 216, and on the insulator 216 and on the conductor 205.
  • An insulator 222 arranged above, an insulator 224 arranged on the insulator 222, and an oxide 230 arranged on the insulator 224 (oxide 230a, oxide 230b, and oxide 230c).
  • the conductor 250 arranged on the oxide 230, the conductor 260 (conductor 260a and the conductor 260b) arranged on the insulator 250, and the conductivity in contact with a part of the upper surface of the oxide 230b. It has a body 240a and a conductor 240b, an insulator 245a on the conductor 240a, and an insulator 245b on the conductor 240b.
  • the transistor 200 is a metal that functions as an oxide semiconductor in an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) including a region in which a channel is formed (hereinafter, also referred to as a channel formation region).
  • An oxide hereinafter, also referred to as an oxide semiconductor is used.
  • the oxide semiconductor that functions as the channel formation region preferably has a bandgap of 2 eV or more, preferably 2.5 eV or more. As described above, by using an oxide semiconductor having a large bandgap, the off-current of the transistor can be reduced.
  • the oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
  • oxide 230c a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • the oxide 230b is an In-Ga-Zn oxide
  • In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 230a and the oxide 230c.
  • the oxide 230b and the oxide 230c are preferably crystalline.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. Further, even if heat treatment is performed, oxygen can be reduced from being extracted from the oxide 230b, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
  • the transistor 200 shows a configuration in which the oxide 230 is laminated with three layers of the oxide 230a, the oxide 230b, and the oxide 230c
  • the present invention is not limited to this.
  • a single layer of oxide 230b, a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, or a laminated structure of four or more layers may be provided, or oxidation may be provided.
  • Each of the object 230a, the oxide 230b, and the oxide 230c may have a laminated structure.
  • the side surface of the oxide 230b and the side surface of the conductor 240 are substantially perpendicular to the surface where the insulator 224 and the oxide 230a are in contact with each other. It is preferable to have.
  • the side surface of the oxide 230b and the side surface of the conductor 240 are 60 degrees or more and 95 degrees or less, preferably 88 degrees or more and 92 degrees with respect to the surface where the insulator 224 and the oxide 230a are in contact with each other. It should be less than or equal to the degree.
  • the upper end portion of the oxide 230 in the channel forming region has a shape having a curvature. That is, in the channel forming region, the upper surface and the side surface of the oxide 230 may have a shape that is gently connected by a curved surface without forming a corner portion. Since there are no corners in the channel formation region, electric field concentration due to the electric field of either one or both of the conductor 260 that functions as the first gate electrode and the conductor 205 that functions as the second gate electrode does not occur. , Deterioration of the oxide 230 can be suppressed.
  • the upper end portion of the oxide 230 in the region overlapping with the conductor 240 has a shape having a smaller curvature than the upper end portion of the oxide 230 in the channel forming region.
  • the above structure can be formed by processing the oxide 230b and the conductor 240 using the same mask. Therefore, since the conductor 240 is superimposed on the projected area of the oxide 230b, a fine transistor can be produced.
  • the conductor 260 functions as a first gate (also referred to as a top gate) electrode.
  • the transistor 200 is provided by burying the conductor 260 in an opening formed in an insulator 280 or the like. Further, in the step of providing the opening, a part of the conductive layer to be the conductor 240 is exposed at the bottom of the opening provided in the insulator 280. In the conductive layer to be the conductor 240, the conductor 240a and the conductor 240b are formed by removing the region overlapping with the bottom of the opening provided in the insulator 280.
  • the end portion of the conductor 240a and the end portion of the conductor 240b are on the same surface as the side surface of the opening.
  • the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250 and the upper surface of the oxide 230c.
  • the shortest distance between the surface where the conductor 260 and the insulator 250 contact and the upper surface of the insulator 222 is the oxide 230b and the oxide. It is preferably shorter than the shortest distance between the surface in contact with the object 230a and the upper surface of the insulator 222. That is, in the channel width direction of the transistor 200, the side surface of the oxide 230b is covered with the conductor 260 at least via the insulator 250.
  • the conductor 260 that functions as a gate electrode covers the side surface and the upper surface of the channel forming region of the oxide 230b via an insulator 250 or the like, so that the electric field of the conductor 260 covers the channel forming region of the oxide 230b. It acts on the whole. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a.
  • the conductor 260a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 260b.
  • the conductor 260a it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity.
  • a conductor having high conductivity for example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
  • the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b, but it may be a single-layer structure or a laminated structure of three or more layers.
  • the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 200 is changed by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260. (Vth) can be controlled. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when it is not applied.
  • the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Further, the conductor 205 is preferably provided by being embedded in the insulator 214 or the insulator 216.
  • the conductor 205 is provided larger than the channel forming region in the oxide 230 in the channel width direction. In particular, as shown in FIG. 2C, it is preferable that the conductor 205 is stretched so as to intersect the channel width direction of the oxide 230.
  • the conductor 205 and the conductor 260 are superimposed via an insulator on the outside of the side surface of the oxide 230 in the channel width direction.
  • the channel forming region of the oxide 230 is electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. Can be done.
  • the conductor 205 is shown as a configuration in which the first conductor and the second conductor are laminated, but the present invention is not limited to this.
  • the conductor 205 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
  • first conductor of the conductor 205 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), impurities such as copper atoms It is preferable to use a conductive material having a function of suppressing diffusion. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the first conductor of the conductor 205, the conductive material may be a single layer or a laminated material.
  • the first conductor of the conductor 205 may be a laminate of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.
  • the second conductor of the conductor 205 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • a conductive material containing tungsten, copper, or aluminum as a main component.
  • the second conductor of the conductor 205 is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the conductor 205 is stretched to function as wiring.
  • the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 205. Further, it is not always necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.
  • the conductor 240 (conductor 240a and conductor 240b) functions as a source electrode or a drain electrode.
  • the conductor 240 for example, it is preferable to use a TaN x O y.
  • TaN x O y may comprise aluminum.
  • titanium nitride, a nitride containing titanium and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
  • an insulator 245 that functions as a barrier layer on the conductor 240.
  • the insulator 245 is preferably in contact with the upper surface of the conductor 240. With this configuration, it is possible to suppress the absorption of excess oxygen contained in the insulator 280 by the conductor 240. Further, by suppressing the oxidation of the conductor 240, it is possible to suppress an increase in the contact resistance between the transistor 200 and the wiring. Therefore, good electrical characteristics and reliability can be given to the transistor 200.
  • the insulator 245 has a function of suppressing the diffusion of oxygen.
  • the insulator 245 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.
  • the insulator 245 for example, it is preferable to form an insulator containing oxides of one or both of aluminum and hafnium. Further, as the insulator 245, for example, an insulator containing aluminum nitride may be used.
  • the insulator 250 functions as a first gate insulator.
  • the insulator 250 is preferably arranged in contact with the oxide 230c.
  • the insulator 250 includes silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and the like. Can be used. In particular, silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
  • microwave excitation plasma treatment may be performed in an atmosphere containing oxygen. Hydrogen, water, or impurities in the insulator 250 can be removed by performing the microwave excitation plasma treatment. Further, by modifying the film quality of the insulator 250 by performing the microwave excitation plasma treatment, it is possible to suppress the diffusion of hydrogen, water, impurities and the like. Therefore, it is possible to prevent hydrogen, water, or impurities from diffusing into the oxide 230 through the insulator 250 by a post-process such as film formation of a conductive film to be a conductor 260 or a post-treatment such as heat treatment. be able to.
  • a post-process such as film formation of a conductive film to be a conductor 260 or a post-treatment such as heat treatment.
  • the bond energy between a hydrogen atom and a silicon atom in solid silicon oxide is 3.3 eV
  • the bond energy between a carbon atom and a silicon atom is 3.4 eV
  • the bond energy between a nitrogen atom and a silicon atom is 3.5 eV. Therefore, in order to remove the hydrogen atom bonded to the silicon atom, a radical or ion having an energy of at least 3.3 eV or more is made to collide with the bond portion between the hydrogen atom and the silicon atom, so that the hydrogen atom and silicon are removed. It can break the bond with an atom.
  • radicals or ions having at least an energy equal to or higher than the binding energy are made to collide with the bond portion between the impurity atom and the silicon atom to form the impurity atom. It can break the bond with the silicon atom.
  • the ground state O ( 3 P) of the oxygen atomic radical As radicals and ions generated by plasma excited by microwaves, the ground state O ( 3 P) of the oxygen atomic radical, the first excited state O ( 1 D) of the oxygen atomic radical, and the monovalent oxygen molecule. there is a cationic O 2 + and the like.
  • the energy of O ( 3 P) is 2.42 eV
  • the energy of O (1 D) is 4.6 eV.
  • O 2 + is to have a charge, potential distribution in the plasma, and to be accelerated by the bias, but the energy is not uniquely determined, at least, even only within the energy, a higher energy than the O (1 D) Have.
  • impurities such as hydrogen, nitrogen, and carbon can be reduced by the thermal energy applied to the substrate when the microwave excitation plasma treatment is performed.
  • O ( 3 P) since O ( 3 P) has low reactivity, it does not react with the insulator 250 and diffuses deep into the membrane. Alternatively, O ( 3 P) reaches the oxide 230 via the insulator 250 and diffuses into the oxide 230.
  • O ( 3 P) diffused in the oxide 230 approaches the oxygen deficiency containing hydrogen, the hydrogen in the oxygen deficiency is released from the oxygen deficiency, and instead O ( 3 P) enters the oxygen deficiency. , Oxygen deficiency is compensated. Therefore, it is possible to suppress the generation of electrons as carriers in the oxide 230.
  • the ratio of O (3 P) to the total radicals and ionic species is increased by performing microwave excitation plasma treatment under high pressure conditions.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • the oxygen flow rate ratio (O 2 / O 2 + Ar) is 50% or less, preferably 10% or more and 30% or less.
  • an oxide material for the insulator 250 in which a part of oxygen is desorbed by heating.
  • Oxides that desorb oxygen by heating are those in which the amount of desorbed oxygen molecules is 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1.0 ⁇ 10 19 molecules, as determined by TDS (Thermal Desortion Spectropy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • oxygen is effectively supplied to the channel forming region of the oxide 230b, and the channel of the oxide 230b is formed. Oxygen deficiency in the region can be reduced. Therefore, it is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced.
  • a metal oxide may be provided between the insulator 250 and the conductor 260.
  • the metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260.
  • the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
  • the oxidation of the conductor 260 by oxygen of the insulator 250 can be suppressed.
  • the metal oxide may have a function as a part of a gate insulator. Therefore, when silicon oxide, silicon oxide nitride, or the like is used for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity as the metal oxide.
  • a metal oxide which is a high-k material having a high relative permittivity as the metal oxide.
  • a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used.
  • an insulator containing an oxide of one or both of aluminum and hafnium it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.
  • the metal oxide may have a function as a part of the first gate electrode.
  • an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260 into a film by a sputtering method, the electric resistance value of the metal oxide can be lowered to form a conductor.
  • the above metal oxide it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Further, by keeping the distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, the leakage current between the conductor 260 and the oxide 230 is maintained. Can be suppressed. Further, by providing the insulator 250 and the laminated structure with the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be determined. It can be easily adjusted as appropriate.
  • the insulator 222 and the insulator 224 function as a second gate insulator.
  • the insulator 222 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.
  • the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials.
  • the insulator it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 222 releases oxygen from the oxide 230 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Functions as a layer that suppresses.
  • the insulator 222 impurities such as hydrogen can be suppressed from diffusing into the inside of the transistor 200, and the generation of oxygen deficiency in the oxide 230 can be suppressed. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • the insulator 222 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
  • the insulator 222 includes, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr) TiO 3 (BST) and the like. Insulators containing so-called high-k materials may be used in single layers or in layers. As transistors become finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • the insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating.
  • the insulator 224 silicon oxide, silicon oxide nitride, or the like may be appropriately used.
  • the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the insulator 214, the insulator 216, the insulator 280, the insulator 282, and the insulator 284 function as an interlayer film.
  • the insulator 214 preferably functions as an insulating barrier film that prevents impurities such as water and hydrogen from diffusing from the substrate side into the transistor 200.
  • the insulator 214 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), has a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use an insulating material. Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
  • the insulator 214 it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This makes it possible to prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side of the insulator 214. Alternatively, it is possible to prevent oxygen contained in the insulator 224 or the like from diffusing toward the substrate side of the insulator 214.
  • the insulator 214 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials. For example, it may be a laminate of aluminum oxide and silicon nitride.
  • the insulator 214 it is preferable to use silicon nitride formed by a sputtering method as the insulator 214.
  • the hydrogen concentration in the insulator 214 can be lowered, and impurities such as water and hydrogen can be further suppressed from diffusing from the substrate side to the transistor 200 side as compared with the insulator 214.
  • the insulator 216 that functions as an interlayer film preferably has a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores. Etc. may be used as appropriate.
  • the insulator 216 has a low hydrogen concentration and a region in which oxygen is excessively present in excess of the stoichiometric composition (hereinafter, also referred to as an excess oxygen region) or oxygen released by heating (hereinafter, also referred to as excess oxygen). ) Is preferable.
  • the insulator 216 may have a laminated structure.
  • an insulator similar to the insulator 214 may be provided at least in a portion in contact with the side surface of the conductor 205.
  • the conductor 205 can suppress a decrease in the amount of oxygen contained in the insulator 216.
  • the insulator 280 is provided on the insulator 224, the oxide 230, and the conductor 240. Further, the upper surface of the insulator 280 may be flattened.
  • the insulator 280 that functions as an interlayer film preferably has a low dielectric constant.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the insulator 280 is provided, for example, by using the same material as the insulator 216.
  • silicon oxide and silicon oxide nitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxide nitride, and silicon oxide having pores are preferable because a region containing oxygen desorbed by heating can be easily formed.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
  • the insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or an excess oxygen, and may be provided by using the same material as the insulator 216, for example.
  • the insulator 280 may have a laminated structure of two or more layers.
  • the insulator 282 preferably functions as an insulating barrier film that suppresses impurities such as water and hydrogen from diffusing into the insulator 280 from above. Further, it is preferable that the insulator 282 has a low hydrogen concentration and has a function of suppressing the diffusion of hydrogen, like the insulator 214 and the like.
  • the insulator 282 is in contact with the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively.
  • impurities such as hydrogen contained in the insulator 284 and the like can be suppressed from being mixed into the insulator 250. Therefore, it is possible to suppress adverse effects on the electrical characteristics of the transistor and the reliability of the transistor.
  • the insulator 284 preferably has a low dielectric constant, like the insulator 216 and the like. Further, it is preferable that the insulator 284 has a reduced concentration of impurities such as water and hydrogen in the film, similarly to the insulator 224 and the like.
  • an insulator substrate for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like.
  • the semiconductor substrate include a semiconductor substrate made of silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • the conductor substrate includes a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided in an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • those on which an element is provided may be used.
  • Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
  • Insulator examples include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like having insulating properties.
  • the material may be selected according to the function of the insulator.
  • Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.
  • Examples of insulators having a low specific dielectric constant include silicon oxide, silicon oxide, silicon oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and empty. There are silicon oxide having holes, resin, and the like.
  • the transistor using the oxide semiconductor is surrounded by an insulator (insulator 214, insulator 222, insulator 245, insulator 282, etc.) having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • the electrical characteristics of the transistor can be stabilized.
  • the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulations containing, lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen
  • Metal oxides such as tantalum oxide and metal nitrides such as aluminum nitride, silicon nitride and silicon nitride can be used.
  • the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
  • the oxygen deficiency of the oxide 230 can be compensated.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a plurality of conductive layers formed of the above materials may be laminated and used.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • the conductor functioning as the gate electrode shall have a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Is preferable.
  • a conductive material containing oxygen may be provided on the channel forming region side.
  • a conductor that functions as a gate electrode it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed.
  • the above-mentioned conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal Oxide As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, gallium, yttrium, tin and the like are preferably contained. Further, one kind or a plurality of kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.
  • the metal oxide is an In-M-Zn oxide having indium, the element M, and zinc.
  • the element M is aluminum, gallium, yttrium, or tin.
  • elements applicable to the other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M a plurality of the above-mentioned elements may be combined in some cases.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
  • Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • Examples of the non-monocrystalline oxide semiconductor include CAAC-OS, polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), and the like. And amorphous oxide semiconductors.
  • CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction.
  • the strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.
  • Nanocrystals are basically hexagons, but they are not limited to regular hexagons and may be non-regular hexagons. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. Because.
  • CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as the (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can be expressed as the (In, M) layer.
  • CAAC-OS is a highly crystalline metal oxide.
  • CAAC-OS it is difficult to confirm a clear grain boundary, so it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur.
  • CAAC-OS since the crystallinity of the metal oxide may be lowered due to the mixing of impurities or the formation of defects, CAAC-OS can be said to be a metal oxide having few impurities and defects (oxygen deficiency, etc.). Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors depending on the analysis method.
  • In-Ga-Zn oxide which is a kind of metal oxide having indium, gallium, and zinc, may have a stable structure by forming the above-mentioned nanocrystals. is there.
  • IGZO tends to have difficulty in crystal growth in the atmosphere, it is preferable to use smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, a few mm crystal or a few cm crystal). However, it may be structurally stable.
  • the a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.
  • Impurities mixed in oxide semiconductors may form defect levels or oxygen deficiencies. Therefore, when impurities are mixed in the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are liable to fluctuate, and the reliability may be deteriorated. Further, when the channel formation region contains oxygen deficiency, the transistor tends to have a normally-on characteristic.
  • the above defect level may include a trap level.
  • the charge captured at the trap level of the metal oxide takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor having a metal oxide having a high trap level density in the channel forming region may have unstable electrical characteristics.
  • the crystallinity of the channel forming region may be lowered, or the crystallinity of the oxide provided in contact with the channel forming region may be lowered. Poor crystallinity in the channel formation region tends to reduce the stability or reliability of the transistor. Further, if the crystallinity of the oxide provided in contact with the channel forming region is low, an interface state may be formed and the stability or reliability of the transistor may be deteriorated.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of the above-mentioned impurities obtained by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the concentration of the impurities obtained by elemental analysis using EDX in the channel formation region of the oxide semiconductor and its vicinity is set to 1.0 atomic% or less.
  • the concentration ratio of the impurities to the element M in the channel forming region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably 0.05. To less than.
  • the concentration of the element M used in calculating the concentration ratio may be the concentration in the same region as the region in which the concentration of the impurities is calculated, or may be the concentration in the oxide semiconductor.
  • the metal oxide with reduced impurity concentration has a low defect level density, so the trap level density may also be low.
  • a in each figure shows a top view.
  • B in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in A, and is also a cross-sectional view in the channel length direction of the transistor 200.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line in A3-A4, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • D in each figure is a cross-sectional view of a portion shown by a alternate long and short dash line in A5 to A6 in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • some elements are omitted for the purpose of clarifying the figure.
  • a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate.
  • the film formation of the insulator 214 is performed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, and a pulse laser deposition method (PLD). It can be done by using.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organometallic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage during film formation does not occur, so that a film having few defects can be obtained.
  • the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, and pins. It has the effects of being able to form a film with few defects such as holes, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
  • the ALD method also includes a PEALD (Plasma Enhanced ALD) method using plasma. By using plasma, it is possible to form a film at a lower temperature, which may be preferable.
  • Some precursors used in the ALD method contain impurities such as carbon.
  • the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
  • the quantification of impurities can be performed by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage.
  • the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas.
  • a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film.
  • aluminum oxide is formed as the insulator 214 by a sputtering method. Further, the insulator 214 may have a multi-layer structure.
  • the insulator 216 is formed on the insulator 214.
  • the film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide nitriding film is formed by the CVD method as an insulating film to be the insulator 216.
  • an opening is formed in the insulator 216 to reach the insulator 214.
  • the opening also includes, for example, a groove or a slit. Further, the region where the opening is formed may be referred to as an opening. Although wet etching may be used to form the openings, it is preferable to use dry etching for microfabrication.
  • the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxide is used for the insulator 216 forming the groove, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.
  • a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate type electrodes can be used.
  • the capacitively coupled plasma etching apparatus having the parallel plate type electrodes may be configured to apply a high frequency voltage to one of the parallel plate type electrodes.
  • a plurality of different high frequency voltages may be applied to one of the parallel plate type electrodes.
  • a high frequency voltage having the same frequency may be applied to each of the parallel plate type electrodes.
  • a high frequency voltage having a different frequency may be applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like can be used.
  • a conductive film to be the first conductor of the conductor 205 is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen.
  • a conductor having a function of suppressing the permeation of oxygen For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film of a conductor having a function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper or molybdenum tungsten alloy.
  • the film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a tantalum nitride film or a film in which titanium nitride is laminated on the tantalum nitride is formed by a sputtering method.
  • a conductive film to be the second conductor of the conductor 205 is formed on the conductive film to be the first conductor of the conductor 205.
  • the film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • tungsten is formed as the conductive film.
  • a part of the conductive film that becomes the first conductor of the conductor 205 and a part of the conductive film that becomes the second conductor of the conductor 205 are removed.
  • the insulator 216 is exposed.
  • the conductive film that becomes the first conductor of the conductor 205 and the conductive film that becomes the second conductor of the conductor 205 remain only in the opening.
  • a part of the second conductor of the conductor 205 is removed to form a groove in the second conductor of the conductor 205, and the conductor is embedded so as to embed the groove.
  • a step of forming a conductive film on the 205 and the insulator 216 and performing a CMP treatment may be performed. By the CMP treatment, a part of the conductive film is removed to expose the insulator 216.
  • a part of the second conductor of the conductor 205 may be removed by a dry etching method or the like.
  • a conductor 205 having a flat upper surface and containing the above conductive film can be formed.
  • the crystallinity of the oxide 230a, the oxide 230b, and the oxide 230c can be improved.
  • the conductive film it is preferable to use the same material as the first conductor of the conductor 205 or the second conductor of the conductor 205.
  • a conductive film to be a conductor 205 is formed on the insulator 214.
  • the film formation of the conductive film to be the conductor 205 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205 can be a multilayer film. For example, tungsten is formed as a conductive film to be the conductor 205.
  • the conductive film to be the conductor 205 is processed to form the conductor 205.
  • the resist is first exposed through a mask. Next, the exposed region is removed or left with a developing solution to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film to be a hard mask material is formed on a conductive film to be a conductor 205, a resist mask is formed on the conductive film, and the hard mask material is etched to obtain a desired shape.
  • a hard mask can be formed.
  • the etching of the conductive film to be the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the conductive film to be the conductor 205.
  • the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.
  • an insulating film to be the insulator 216 is formed on the insulator 214 and the conductor 205.
  • the insulating film is formed so as to be in contact with the upper surface and the side surface of the conductor 205.
  • the insulating film can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the film thickness of the insulating film to be the insulator 216 is preferably equal to or greater than the film thickness of the conductor 205.
  • the film thickness of the conductor 205 is 1, the film thickness of the insulating film that becomes the insulator 216 is 1 or more and 3 or less.
  • the conductor 205 and the insulator 216 having a flat upper surface can be formed.
  • the above is a different method for forming the conductor 205.
  • the insulator 222 is formed on the insulator 216 and the conductor 205.
  • the film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • hafnium oxide or aluminum oxide is formed as the insulator 222 by the ALD method.
  • the heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
  • the insulator 222 is treated in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, and then continuously in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour. Perform processing.
  • impurities such as water and hydrogen contained in the insulator 222 can be removed.
  • the heat treatment can be performed at a timing such as after the film formation of the insulator 224 is performed.
  • the insulator 224 is formed on the insulator 222.
  • the film formation of the insulator 224 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film is formed as the insulator 224 by the CVD method.
  • plasma treatment containing oxygen may be performed in a reduced pressure state.
  • plasma treatment containing oxygen for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves.
  • a power source for applying RF Radio Frequency
  • high-density plasma high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can.
  • the plasma treatment containing an inert gas may be performed using this device, and then the plasma treatment containing oxygen may be performed to supplement the desorbed oxygen.
  • impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, the heat treatment does not have to be performed.
  • CMP treatment may be performed until the insulator 224 is reached.
  • the surface of the insulator 224 can be flattened and smoothed.
  • the CMP treatment may polish a part of the insulator 224 to reduce the film thickness of the insulator 224, but the film thickness may be adjusted when the insulator 224 is formed.
  • oxygen can be added to the insulator 224 by forming aluminum oxide on the insulator 224 by a sputtering method.
  • the oxide film 230A and the oxide film 230B are formed on the insulator 224 in this order (see FIG. 3). It is preferable that the oxide film 230A and the oxide film 230B are continuously formed without being exposed to the atmospheric environment. By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas.
  • excess oxygen in the oxide film formed can be increased.
  • the above oxide film is formed by a sputtering method
  • the above In—M—Zn oxide target or the like can be used.
  • the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen excess type oxidation A physical semiconductor is formed. Transistors using oxygen-rich oxide semiconductors in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this.
  • the oxide film 230B is formed by a sputtering method and the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. To. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can obtain relatively high field-effect mobilities. Further, the crystallinity of the oxide film can be improved by forming a film while heating the substrate.
  • Each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film forming conditions and the atomic number ratio.
  • the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are formed without being exposed to the atmosphere.
  • a multi-chamber type film forming apparatus may be used.
  • heat treatment may be performed.
  • the above-mentioned heat treatment conditions can be used.
  • impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed.
  • the treatment is continuously carried out in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.
  • a conductive film 240A is formed on the oxide film 230B.
  • the film formation of the conductive film 240A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 3).
  • the heat treatment may be performed before the film formation of the conductive film 240A.
  • the heat treatment may be performed under reduced pressure to continuously form the conductive film 240A without exposing it to the atmosphere. By performing such a treatment, the water and hydrogen adsorbed on the surface of the oxide film 230B and the like can be removed, and the water concentration and the hydrogen concentration in the oxide film 230A and the oxide film 230B can be further reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200 ° C.
  • an insulating film 245A that functions as a barrier layer is formed (see FIG. 3).
  • aluminum oxide may be formed as the insulating film 245A by the ALD method.
  • ALD method it is possible to form a film having a dense, reduced defects such as cracks and pinholes, or a uniform thickness.
  • a film 290A to be a hard mask is formed on the insulating film 245A (see FIG. 3).
  • tungsten or tantalum nitride may be formed by a sputtering method as the film 290A to be a hard mask.
  • a resist mask 292 is formed on the film 290A, which is a hard mask, by a photolithography method.
  • the hard mask 290B and the insulating layer 245B are formed by selectively removing a part of the hard mask film 290A and the insulating film 245A using the resist mask 292 (FIG. 4).
  • a part of the conductive film 240A is selectively removed to form an island-shaped conductive layer 240B (FIG. 5). At this time, a part or all of the hard mask 290B may be removed.
  • a part of the oxide film 230A and the oxide film 230B is selectively removed using the island-shaped conductive layer 240B, the insulating layer 245B, and the hard mask 290B as masks (FIG. 6).
  • a part of the insulator 224 may be removed at the same time.
  • a laminated structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B can be formed (FIG. 6). ).
  • this step by processing the conductive film 240A using the hard mask 290, it is possible to suppress the formation of etching (also referred to as CD loss) unnecessary for the shape of the conductor 240.
  • the mask when a resist mask is used, the mask may be side-etched at the time of etching, the end surface of the workpiece may be exposed, and the corners may be rounded.
  • the conductor 240 when the defect is large, the volume of the conductor 240 may be smaller than the design value, and the on-current may be smaller.
  • the shape of the hard mask is maintained at the time of etching, and it is possible to prevent the workpiece from becoming defective in shape. it can.
  • the etch rate of the material used for the hard mask is 1, it is preferable to use a material having an etch rate of 5 or more, preferably 10 or more as the mask.
  • an insulating film 280A is formed on the laminated structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B.
  • the insulating film 280A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film is formed as the insulating film 280A by a CVD method or a sputtering method.
  • the heat treatment may be performed before the insulating film 280A is formed.
  • the heat treatment may be performed under reduced pressure to continuously form the insulating film without exposing it to the atmosphere.
  • the water and hydrogen adsorbed on the surface of the insulator 224 and the like are removed, and the water concentration and the hydrogen concentration in the oxide 230a, the oxide 230b, and the insulator 224 are further reduced. be able to.
  • the above-mentioned heat treatment conditions can be used.
  • the insulating film 280A may have a multilayer structure.
  • the structure may be such that a silicon oxide film is formed by a sputtering method and a silicon oxide film is formed on the silicon oxide film by a CVD method.
  • the insulating film 280A is subjected to CMP treatment to form an insulator 280 having a flat upper surface (see FIG. 6).
  • a part of the insulator 280 and a part of the conductive layer 240B are processed to form an opening reaching the oxide 230b.
  • the opening is preferably formed so as to overlap the conductor 205.
  • the conductor 240a, the conductive layer 240B, the insulator 245a, and the insulating layer 245B are formed.
  • the film thickness of the region overlapping the opening of the oxide 230b may be reduced (see FIG. 7).
  • a part of the insulator 280, a part of the insulating layer 245B, and a part of the conductive layer 240B may be processed under different conditions.
  • a part of the insulator 280 may be processed by a dry etching method
  • a part of the insulating layer 245B may be processed by a wet etching method
  • a part of the conductive layer 240B may be processed by a dry etching method.
  • impurities adhering to or diffused inside the surface such as oxide 230a and oxide 230b.
  • the impurities include components contained in the insulator 280, the insulating layer 245B, and the conductive layer 240B, components contained in the member used in the apparatus used for forming the opening, and gas or liquid used for etching. Examples include those caused by the components contained in.
  • the impurities include aluminum, silicon, tantalum, fluorine, chlorine and the like.
  • a cleaning treatment may be performed to remove the above impurities and the like.
  • the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.
  • the cleaning treatment may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water, pure water, carbonated water or the like. Further, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Moreover, you may perform these washings in combination as appropriate.
  • heat treatment may be performed. It is preferable that the heat treatment is performed in an atmosphere containing oxygen. Further, the heat treatment may be carried out under reduced pressure to continuously form the oxide film 230C without exposing it to the atmosphere (see FIG. 8). By performing such a treatment, the water and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and the water concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200 ° C.
  • the oxide film 230C can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C.
  • a film is formed using a Zn oxide target.
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure to continuously form the insulating film 250A without exposing it to the atmosphere.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower.
  • the insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 8).
  • silicon oxide nitride is formed as the insulating film 250A by the CVD method.
  • the film forming temperature at the time of forming the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly around 400 ° C. By forming the insulating film 250A at 400 ° C., an insulating film having few impurities can be formed.
  • the conductive film 260A and the conductive film 260B are formed in this order.
  • the film formation of the conductive film 260A and the conductive film 260B can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 260A is formed by using the ALD method
  • the conductive film 260B is formed by using the CVD method (see FIG. 8).
  • the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed, whereby the oxide 230c, the insulator 250, and the conductor 260 (conductive).
  • the body 260a and the conductor 260b) are formed (see FIG. 9).
  • the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the opening reaching the oxide 230b.
  • the insulator 250 is arranged so as to cover the inner wall of the opening via the oxide 230c.
  • the conductor 260 is arranged so as to embed the opening via the oxide 230c and the insulator 250.
  • heat treatment may be performed.
  • the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.
  • the heat treatment the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
  • the insulator 282 is formed on the oxide 230c, the insulator 250, the conductor 260, and the insulator 280.
  • the film formation of the insulator 282 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 282 for example, it is preferable to form an aluminum oxide film or a silicon nitride film by a sputtering method.
  • a sputtering method By forming an aluminum oxide film or a silicon nitride film by a sputtering method, it is possible to suppress the diffusion of hydrogen contained in the insulator 284 to the oxide 230. Further, by forming the insulator 282 so as to be in contact with the conductor 260, oxidation of the conductor 260 can be suppressed, which is preferable.
  • oxygen can be supplied to the insulator 280 by forming an aluminum oxide film by a sputtering method.
  • the oxygen supplied to the insulator 280 may be supplied to the channel forming region of the oxide 230b via the oxide 230c.
  • oxygen contained in the insulator 280 before the formation of the insulator 282 is supplied to the channel forming region of the oxide 230b via the oxide 230c. In some cases.
  • the insulator 282 may have a multi-layer structure.
  • the structure may be such that an aluminum oxide film is formed by a sputtering method and silicon nitride is formed on the aluminum oxide film by a sputtering method.
  • heat treatment may be performed.
  • the above-mentioned heat treatment conditions can be used.
  • the heat treatment the water concentration and the hydrogen concentration of the insulator 280 can be reduced. Further, the oxygen contained in the insulator 282 can be injected into the insulator 280.
  • an aluminum oxide film is formed on the insulator 280 or the like by a sputtering method, and then heat treatment is performed using the above-mentioned heat treatment conditions.
  • a step of removing the aluminum oxide film by CMP treatment may be performed. By this step, more excess oxygen regions can be formed in the insulator 280.
  • a part of the insulator 280, a part of the conductor 260, a part of the insulator 250, and a part of the oxide 230c may be removed.
  • an insulator may be provided between the insulator 280 and the insulator 282.
  • the insulator for example, silicon oxide formed by a sputtering method may be used. By providing the insulator, an excess oxygen region can be formed in the insulator 280.
  • the insulator 284 may be formed on the insulator 282.
  • the film formation of the insulator 284 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 1).
  • the semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured.
  • an opening may be formed so as to surround the transistor 200, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening.
  • the plurality of transistors 200 may be put together and wrapped with an insulator having a high barrier property against hydrogen or water.
  • an opening is formed so as to surround the transistor 200, for example, an opening reaching the insulator 214 or the insulator 222 is formed, and the above-mentioned insulator having a high barrier property is provided so as to be in contact with the insulator 214 or the insulator 222.
  • the insulator having a high barrier property to hydrogen or water for example, the same material as the insulator 222 may be used.
  • a semiconductor device having good reliability it is possible to provide a semiconductor device having good electrical characteristics. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Further, according to one aspect of the present invention, a semiconductor device having low power consumption can be provided.
  • FIG. 10A shows a top view.
  • FIG. 10B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 10A.
  • FIG. 10C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A3-A4 in FIG. 10A.
  • some elements are omitted for the sake of clarity.
  • the semiconductor device shown in FIG. 10 is different from the semiconductor device shown in FIG. 2 in that the oxide 230b has a laminated structure. Another difference is that the oxide 230c has a laminated structure. It is also different from having an insulator 273 and an insulator 274.
  • the oxide 230c may have a laminated structure of two or more layers.
  • FIG. 10 has a first oxide of oxide 230c and a second oxide of oxide 230c disposed on top of the first oxide of oxide 230c.
  • the first oxide of the oxide 230c preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230b, and more preferably contains all the metal elements. ..
  • In-Ga-Zn oxide is used as the first oxide of the oxide 230c
  • In-Ga-Zn oxide, Ga-Zn oxide, or oxidation is used as the second oxide of the oxide 230c.
  • Gallium should be used. With this structure, the defect level density at the interface between the oxide 230b and the first oxide of the oxide 230c can be lowered.
  • the second oxide of the oxide 230c is preferably a metal oxide that suppresses the diffusion or permeation of oxygen, rather than the first oxide of the oxide 230c.
  • oxygen contained in the insulator 280 is suppressed from diffusing into the insulator 250. be able to. Therefore, the oxygen is likely to be supplied to the oxide 230b via the first oxide of the oxide 230c.
  • the atomic number ratio of In to the metal element as the main component is the main component in the metal oxide used for the first oxide of the oxide 230c.
  • In can be suppressed from diffusing to the insulator 250 side. Since the insulator 250 functions as a gate insulator, if In is mixed in the insulator 250 or the like, the characteristics of the transistor become poor. Therefore, by forming the oxide 230c in a laminated structure, it is possible to provide a highly reliable semiconductor device.
  • the oxide 230b may have a laminated structure of two or more layers.
  • FIG. 10 has a first oxide of oxide 230b and a second oxide of oxide 230b disposed on top of the first oxide of oxide 230b.
  • the second oxide of the oxide 230b is composed of the first oxide of the oxide 230b and the conductor 240 (conductor 240a and conductor 240b) that functions as a source electrode or a drain electrode. It is good to provide it in between.
  • the second oxide of the oxide 230b preferably has a function of suppressing the permeation of oxygen.
  • the second oxide of the oxide 230b having the function of suppressing the permeation of oxygen between the conductor 240 functioning as the source electrode or the drain electrode and the first oxide of the oxide 230b. It is preferable because the electric resistance between the conductor 240 and the first oxide of the oxide 230b is reduced. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved.
  • the conductor 240 and the first oxide of the oxide 230b do not come into contact with each other, it is possible to suppress the conductor 240 from absorbing the oxygen of the first oxide of the oxide 230b. By preventing the conductor 240 from being oxidized, it is possible to suppress a decrease in the conductivity of the conductor 240.
  • a metal oxide having an element M may be used as the second oxide of the oxide 230b.
  • the element M aluminum, gallium, yttrium, or tin may be used.
  • the second oxide of the oxide 230b preferably has a higher concentration of element M than the first oxide of the oxide 230b.
  • gallium oxide may be used as the second oxide of the oxide 230b.
  • a metal oxide such as In—M—Zn oxide may be used as the second oxide of the oxide 230b.
  • the atomic number ratio of the element M to In is the element to In in the metal oxide used for the first oxide of the oxide 230b. It is preferably larger than the number of atoms ratio of M.
  • the film thickness of the second oxide of the oxide 230b is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less.
  • the second oxide of the oxide 230b has crystalline property.
  • the release of oxygen in the first oxide of the oxide 230b can be reduced.
  • the second oxide of the oxide 230b has a crystal structure such as a hexagonal crystal, the release of oxygen in the first oxide of the oxide 230b may be suppressed.
  • oxygen in the oxide 230 may diffuse to the conductor 240 and the conductor 240 may be oxidized. It is highly probable that the conductivity of the conductor 240 will decrease due to the oxidation of the conductor 240.
  • the diffusion of oxygen in the oxide 230 to the conductor 240 can be rephrased as the conductor 240 absorbing the oxygen in the oxide 230.
  • oxygen in the oxide 230 may diffuse to the conductor 240 to form a different layer between the conductor 240 and the oxide 230. Since the different layer contains more oxygen than the conductor 240, it is presumed that the different layer has insulating properties.
  • the three-layer structure of the conductor 240, the different layer, and the oxide 230 can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and has a MIS (Metal-Insulator-Semiconductor) structure. It may be called, or it may be called a diode junction structure mainly composed of a MIS structure.
  • an insulator 273 having a barrier property may be provided so as to cover the upper surface of the conductor 240 and the side surfaces of the oxide 230a, the oxide 230b, and the conductor 240.
  • the insulator 245 does not necessarily have to be provided.
  • the oxide 230 overlaps with the conductor 240
  • a metal element of the conductor 240 is added, or oxygen is absorbed by the conductor 240, causing oxygen deficiency. That is, the resistance of the oxide 230 in the vicinity of the surface in contact with the conductor 240 may be locally reduced.
  • the on-current of the transistor 200 can be improved.
  • the excess oxygen contained in the insulator 280 diffuses from the side surface of the oxide 230 in the region overlapping the conductor 240 to the oxide 230, so that the station generated in the oxide 230 in the region overlapping the conductor 240 is generated.
  • the geologically low resistance region may decrease, and the on-current of the transistor 200 may decrease.
  • the insulator 273 it is possible to suppress the supply of excess oxygen contained in the insulator 280 from the side surface of the oxide 230 in the region overlapping with the conductor 240.
  • the excess oxygen contained in the insulator 280 can be supplied to the channel forming region of the oxide 230b via the oxide 230c. Therefore, the oxygen deficiency generated in the channel forming region of the oxide 230 can be efficiently compensated without reducing the resistance-reducing region generated in the vicinity of the surface of the oxide 230 in contact with the conductor 240.
  • the excess oxygen of the insulator 224 diffuses into the oxide 230b via the oxide 230a. That is, excess oxygen can be supplied from the oxide 230a side. Therefore, it is possible to compensate for the oxygen deficiency generated in the channel formation region of the oxide 230 while suppressing the decrease of the low resistance region generated in the vicinity of the surface of the oxide 230 in contact with the conductor 240.
  • the insulator 273 it is preferable to use an aluminum oxide film formed by using a sputtering apparatus. By forming an aluminum oxide film as the insulator 273 in an oxygen gas atmosphere, excess oxygen can be introduced into the insulator 224 while forming the insulator 273.
  • the insulator 274 may be provided on the insulator 273.
  • the insulator 273 formed by the sputtering method has a low film property. Therefore, it is preferable that the insulator 274 is formed into a film by using the ALD method. This is because the ALD method can form a film having excellent step covering property and thickness uniformity, so that it is not easily affected by the shape of the object to be treated and has good step covering property.
  • FIG. 11A shows a top view.
  • FIG. 11B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 11A.
  • 11C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in A3-A4 in FIG. 11A.
  • FIG. 11D is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 11A.
  • some elements are omitted for the sake of clarity.
  • the insulator 280, the insulator 282, the insulator 283, and the insulator 284 have an opening for exposing the transistor 200. Further, in the opening, there is a conductor 246 (conductor 246a, conductor 246b) that functions as a plug for connecting to the transistor 200. In addition, an insulator 247 is provided on the side surface of the opening.
  • the conductor 246 has a function as a plug or wiring that electrically connects to the transistor 200.
  • the semiconductor device shown in FIG. 11 has an insulator 212 and an insulator 283 that function as a barrier layer above and below the transistor 200. Further, the insulator 212 and the insulator 283 are in contact with each other in a side surface of the transistor 200 or a region serving as an end portion of the substrate. That is, the semiconductor device shown in FIG. 11 has a structure in which the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.
  • the region where the insulator 212 and the insulator 283 are in contact with each other may be provided along the scribe line. Further, for example, when a plurality of transistors 200 are arranged in a matrix, a region in which the insulator 212 and the insulator 283 are in contact with each other may be provided so as to follow a matrix in which the plurality of transistors are arranged.
  • the region may be provided so as to overlap with the scribe line.
  • the insulator 283 is provided on the insulator 282.
  • the insulator 284 uses a material having a large etch rate selection ratio with respect to the conductor 248. Therefore, the insulator 284 may be provided on the insulator 283 as needed.
  • the insulator 247 is in contact with the insulator 283.
  • the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.
  • the insulator 247 is provided in contact with the side wall of the opening of the insulator 283, the insulator 282, and the insulator 280, and the conductor 246 is formed in contact with the side surface thereof.
  • the transistor 200 is located at least a part of the bottom of the opening, and the conductor 246 is in contact with the transistor 200.
  • FIG. 12 shows an example of a semiconductor device (storage device) using a capacitive element which is one aspect of the present invention.
  • the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 200. It is preferable that at least a part of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. As a result, the occupied area of the capacitive element 100, the transistor 200, and the transistor 300 in the top view can be reduced, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated.
  • the semiconductor device is, for example, a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a DRAM (Dynamic Random Access Memory) or NVM (Non-Volatile Memory). It can be applied to a memory circuit represented by.
  • a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a DRAM (Dynamic Random Access Memory) or NVM (Non-Volatile Memory). It can be applied to a memory circuit represented by.
  • the transistor 200 As the transistor 200, the transistor 200 described in the previous embodiment can be used. Therefore, for the transistor 200 and the layer including the transistor 200, the description of the previous embodiment can be taken into consideration.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced. Further, the transistor 200 has better electrical characteristics at high temperatures than a transistor using silicon for the semiconductor layer. For example, the transistor 200 exhibits good electrical characteristics even in the temperature range of 125 ° C to 150 ° C. Further, in the temperature range of 125 ° C. to 150 ° C., the transistor 200 has a transistor on / off ratio of 10 digits or more. In other words, the transistor 200 has better characteristics as the on-current, frequency characteristics, and the like, which are examples of transistor characteristics, become higher than those of a transistor using silicon for the semiconductor layer.
  • the wiring 1001 is electrically connected to the source of the transistor 300
  • the wiring 1002 is electrically connected to the drain of the transistor 300
  • the wiring 1007 is electrically connected to the gate of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and drain of the transistor 200
  • the wiring 1004 is electrically connected to the first gate of the transistor 200
  • the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the other of the source and drain of the transistor 200 is electrically connected to one of the electrodes of the capacitance element 100
  • the wiring 1005 is electrically connected to the other of the electrodes of the capacitance element 100.
  • the semiconductor device shown in FIG. 12 has a characteristic that the charged charge can be held in one of the electrodes of the capacitive element 100 by switching the transistor 200, so that information can be written, held, and read out.
  • the transistor 200 is an element provided with a back gate in addition to a source, a gate (top gate), and a drain. That is, since it is a 4-terminal element, MRAM (Magnetoresistive Random Access Memory) utilizing MTJ (Magnetic Tunnel Junction) characteristics, ReRAM (Resistive Random Access Memory), ReRAM (Resistive Random Access Memory), etc.
  • MRAM Magneticoresistive Random Access Memory
  • MTJ Magnetic Tunnel Junction
  • ReRAM Resistive Random Access Memory
  • ReRAM Resistive Random Access Memory
  • the MRAM, the ReRAM, and the phase change memory may undergo a structural change at the atomic level when the information is rewritten.
  • the semiconductor device shown in FIG. 12 operates by charging or discharging electrons using a transistor and a capacitive element when rewriting information, so that it has excellent resistance to repeated rewriting and has few structural changes.
  • the semiconductor devices shown in FIG. 12 can form a memory cell array by arranging them in a matrix.
  • the transistor 300 can be used as a read circuit, a drive circuit, or the like connected to the memory cell array.
  • the semiconductor device shown in FIG. 12 constitutes a memory cell array as described above.
  • an operating frequency of 200 MHz or more can be realized in a range of a drive voltage of 2.5 V and an evaluation environment temperature of ⁇ 40 ° C. to 85 ° C.
  • the transistor 300 is provided on the substrate 311 and functions as a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b.
  • the insulator 315 is arranged on the semiconductor region 313, and the conductor 316 is arranged on the insulator 315. Further, the transistors 300 formed in the same layer are electrically separated by an insulator 312 that functions as an element separation insulating layer. As the insulator 312, the same insulator as the insulator 326 described later can be used.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the substrate 311 includes a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 300 may be a HEMT (High Electro
  • an element that imparts n-type conductivity such as arsenic and phosphorus, or a p-type conductivity such as boron is imparted.
  • the conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a material or a conductive material such as a metal oxide material can be used.
  • the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • transistor 300 shown in FIG. 12 is an example, and the transistor 300 is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.
  • the semiconductor device is provided by stacking the transistor 300 and the transistor 200.
  • the transistor 300 can be made of a silicon-based semiconductor material
  • the transistor 200 can be made of an oxide semiconductor.
  • the silicon-based semiconductor material and the oxide semiconductor can be mixedly mounted on different layers to form the semiconductor device.
  • the semiconductor device shown in FIG. 12 can be manufactured by the same process as the manufacturing device used for the silicon-based semiconductor material, and can be highly integrated.
  • the capacitive element 100 includes an insulator 114 on the insulator 160, an insulator 140 on the insulator 114, a conductor 110 arranged in the insulator 114 and an opening formed in the insulator 140, and a conductor. It has an insulator 130 on the 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130.
  • at least a part of the conductor 110, the insulator 130, and the conductor 120 is arranged in the openings formed in the insulator 114 and the insulator 140.
  • the conductor 110 functions as a lower electrode of the capacitance element 100
  • the conductor 120 functions as an upper electrode of the capacitance element 100
  • the insulator 130 functions as a dielectric of the capacitance element 100.
  • the capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched not only on the bottom surface but also on the side surface at the openings of the insulator 114 and the insulator 140, and the capacitance per unit area is electrostatic.
  • the capacity can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitance element 100 can be.
  • an insulator that can be used for the insulator 280 may be used.
  • the insulator 140 preferably functions as an etching stopper when forming an opening of the insulator 114, and an insulator that can be used for the insulator 214 may be used.
  • the shape of the openings formed in the insulator 114 and the insulator 140 when viewed from above may be a quadrangle, a polygonal shape other than the quadrangle, or a polygonal shape with curved corners. , It may be a circular shape including an ellipse.
  • it is preferable that the area where the opening and the transistor 200 overlap is large. With such a configuration, the occupied area of the semiconductor device having the capacitance element 100 and the transistor 200 can be reduced.
  • the conductor 110 is arranged in contact with the insulator 140 and the opening formed in the insulator 114. It is preferable that the upper surface of the conductor 110 substantially coincides with the upper surface of the insulator 140. Further, the conductor 152 provided on the insulator 160 is in contact with the lower surface of the conductor 110.
  • the conductor 110 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the insulator 130 is arranged so as to cover the conductor 110 and the insulator 140.
  • the insulator 130 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium oxide, and nitride.
  • Hafnium or the like may be used, and it can be provided in a laminated or single layer.
  • an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • a material having a large dielectric strength such as silicon oxide or a material having a high dielectric constant (high-k) for the insulator 130.
  • a laminated structure of a material having a large dielectric strength and a high dielectric constant (high-k) material may be used.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and vacancies are used as materials having high insulation strength.
  • silicon oxide, resin, etc. laminated in the order of silicon nitride was deposited using ALD (SiN x), silicon oxide was deposited using PEALD method (SiO x), silicon nitride was deposited using ALD (SiN x)
  • An insulating film that has been formed can be used. By using such an insulator having a large dielectric strength, the dielectric strength can be improved and electrostatic breakdown of the capacitive element 100 can be suppressed.
  • the conductor 120 is arranged so as to fill the openings formed in the insulator 140 and the insulator 114. Further, the conductor 120 is electrically connected to the wiring 1005 via the conductor 112 and the conductor 153.
  • the conductor 120 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the transistor 200 is configured to use an oxide semiconductor, the compatibility with the capacitive element 100 is excellent. Specifically, since the transistor 200 using an oxide semiconductor has a small off-current, it is possible to retain the stored contents for a long period of time by using it in combination with the capacitive element 100.
  • a wiring layer provided with an interlayer film, wiring, a plug, or the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design.
  • the conductor that functions as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order on the transistor 300 as an interlayer film.
  • the insulator 322, the insulator 324, and the insulator 326 may have a function as an adjusting layer described in the previous embodiment.
  • a conductor 328 and a conductor 330 that are electrically connected to the conductor 153 that functions as a terminal are embedded.
  • the conductor 328 and the conductor 330 function as plugs or wirings.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • the insulator 350, the insulator 352, and the insulator 354 may have a function as an adjusting layer described in the previous embodiment.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or wiring.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are laminated in this order.
  • the insulator 210, the insulator 212, and the insulator 214 can function as the adjusting layer described in the previous embodiment.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like.
  • the conductor 218 functions as a plug or wiring that electrically connects to the transistor 300.
  • the conductor 112 the conductors constituting the capacitive element 100 (conductor 120, conductor 110) and the like are embedded in the insulator 114, the insulator 140, the insulator 130, the insulator 150, and the insulator 154. It has been.
  • the conductor 112 functions as a plug or wiring that electrically connects the capacitive element 100, the transistor 200, or the transistor 300 and the conductor 153 that functions as a terminal.
  • the conductor 153 is provided on the insulator 154, and the conductor 153 is covered with the insulator 156.
  • the conductor 153 is in contact with the upper surface of the conductor 112, and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.
  • Examples of the insulator that can be used as the interlayer film include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties.
  • the material may be selected according to the function of the insulator.
  • the insulator 320, the insulator 322, the insulator 326, the insulator 352, the insulator 354, the insulator 212, the insulator 114, the insulator 150, the insulator 156, and the like have an insulator having a low relative dielectric constant.
  • the insulator includes silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores. , Resin and the like are preferable.
  • the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores.
  • resin it is preferable to have a laminated structure. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 is 1.0 ⁇ 10 12 ⁇ cm or more and 1.0 ⁇ 10 15 ⁇ cm or less, preferably 5.0 ⁇ 10 12 ⁇ cm or more 1 It is preferably 0.0 ⁇ 10 14 ⁇ cm or less, more preferably 1.0 ⁇ 10 13 ⁇ cm or more and 5.0 ⁇ 10 13 ⁇ cm or less.
  • Silicon nitride or silicon nitride oxide can be used as such an insulator.
  • the resistivity of the insulator 160 or the insulator 154 may be set within the above range.
  • a transistor using an oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 324, the insulator 350, the insulator 210, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
  • Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulations containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and SiO such as nickel silicide may be used.
  • the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, the conductor 152, the conductor 153, and the like include a metal material, an alloy material, and a metal nitride material formed of the above materials.
  • a conductive material such as a metal oxide material can be used as a single layer or laminated. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • an insulator 247 between the insulator 280 having excess oxygen and the conductor 248.
  • the conductor 248 and the transistor 200 can be sealed by the insulator having a barrier property.
  • the insulator 247 it is possible to suppress the excess oxygen contained in the insulator 280 from being absorbed by the conductor 248. Further, by having the insulator 247, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 248.
  • the conductor 248 has a function as a transistor 200 or a plug or wiring that electrically connects to the transistor 300.
  • the insulator 247 is provided in contact with the side wall of the opening of the insulator 284, the insulator 282, and the insulator 280, and the conductor 248 is formed in contact with the side surface thereof.
  • the conductor 240 is located at least a part of the bottom of the opening, and the conductor 248 is in contact with the conductor 240.
  • the conductor 248 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 248 may have a laminated structure.
  • the transistor 200 shows a configuration in which the conductor 248 is provided as a two-layer laminated structure, but the present invention is not limited to this.
  • the conductor 248 may be provided as a single layer or a laminated structure having three or more layers.
  • the conductors in contact with the conductor 240 and in contact with the insulator 280, the insulator 282, and the insulator 284 via the insulator 247 include water, hydrogen, and the like. It is preferable to use a conductive material having a function of suppressing the permeation of impurities.
  • a conductive material having a function of suppressing the permeation of impurities For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated state.
  • the conductive material By using the conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 248. Further, it is possible to prevent impurities such as water and hydrogen contained in the layer above the insulator 284 from diffusing into the oxide 230 through the conductor 248.
  • the insulator 247 for example, an insulator that can be used for the insulator 214 or the like may be used.
  • the insulator 247 can suppress impurities such as water and hydrogen contained in the insulator 280 and the like from diffusing into the oxide 230 through the conductor 248. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 248.
  • a conductor 152 that is in contact with the upper surface of the conductor 248 and functions as wiring may be arranged.
  • the conductor that functions as wiring it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • a semiconductor device using a transistor having an oxide semiconductor can be miniaturized or highly integrated. Further, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Further, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Further, it is possible to provide a transistor having an oxide semiconductor having a small off-current. Further, it is possible to provide a semiconductor device having reduced power consumption.
  • FIG. 13 shows an example of a semiconductor device (storage device) using the semiconductor device according to one aspect of the present invention.
  • the semiconductor device shown in FIG. 13 has a transistor 200, a transistor 300, and a capacitive element 100, similarly to the semiconductor device shown in FIG.
  • the semiconductor device shown in FIG. 13 is different from the semiconductor device shown in FIG. 12 in that the capacitive element 100 is a planar type and the transistor 200 and the transistor 300 are electrically connected.
  • the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. It is preferable that at least a part of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. As a result, the occupied area of the capacitive element 100, the transistor 200, and the transistor 300 in the top view can be reduced, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated.
  • the above-mentioned transistor 200 and transistor 300 can be used as the transistor 200 and the transistor 300. Therefore, the above description can be taken into consideration for the transistor 200, the transistor 300, and the layer including these.
  • the wiring 2001 is electrically connected to the source of the transistor 300, and the wiring 2002 is electrically connected to the drain of the transistor 300.
  • the wiring 2003 is electrically connected to one of the source and drain of the transistor 200
  • the wiring 2004 is electrically connected to the first gate of the transistor 200
  • the wiring 2006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitance element 100
  • the wiring 2005 is electrically connected to the other of the electrodes of the capacitance element 100. ..
  • a node in which the gate of the transistor 300, the other of the source and drain of the transistor 200, and one of the electrodes of the capacitive element 100 are connected may be referred to as a node FG.
  • the semiconductor device shown in FIG. 13 has a characteristic that the potential of the gate (node FG) of the transistor 300 can be held by switching the transistor 200, so that information can be written, held, and read out.
  • the semiconductor devices shown in FIG. 13 can form a memory cell array by arranging them in a matrix.
  • the layer containing the transistor 300 has the same structure as the semiconductor device shown in FIG. 12, the structure below the insulator 354 can take the above description into consideration.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are arranged on the insulator 354.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used, similarly to the insulator 350 and the like.
  • a conductor 218 is embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
  • the conductor 218 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300.
  • the conductor 218 is electrically connected to the conductor 316 which functions as a gate electrode of the transistor 300.
  • the conductor 248 functions as a plug or wiring that electrically connects to the transistor 200 or the transistor 300.
  • the conductor 240b that functions as the other of the source and drain of the transistor 200 and the conductor 110 that functions as one of the electrodes of the capacitive element 100 are electrically connected via the conductor 248. There is.
  • the capacitive element 100 is provided above the transistor 200.
  • the capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
  • the conductor 153 and the conductor 110 are provided in contact with the upper surface of the conductor 248.
  • the conductor 153 is in contact with the upper surface of the conductor 248 and functions as a terminal of the transistor 200 or the transistor 300.
  • the conductor 153 and the conductor 110 are covered with an insulator 130, and the conductor 120 is arranged so as to overlap the conductor 110 via the insulator 130. Further, an insulator 114 is arranged on the conductor 120 and the insulator 130.
  • FIG. 13 an example in which a planar type capacitive element is used as the capacitive element 100 is shown, but the semiconductor device shown in the present embodiment is not limited to this.
  • a cylinder-type capacitance element 100 as shown in FIG. 12 may be used as the capacitance element 100.
  • FIG. 14 shows an example of a storage device using the semiconductor device which is one aspect of the present invention.
  • the storage device shown in FIG. 14 includes a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitive element 100 shown in FIG.
  • the transistor 400 can control the second gate voltage of the transistor 200.
  • the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the second gate of the transistor 200 are connected.
  • the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source become 0V.
  • the second gate of the transistor 200 since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the second gate of the transistor 200 does not need to be supplied with power to the transistor 200 and the transistor 400.
  • the negative potential can be maintained for a long time.
  • the storage device having the transistor 200 and the transistor 400 can retain the stored contents for a long period of time.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate (back gate) of the transistor 200. Is connected. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitance element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitance element 100. ..
  • the wiring 1007 is electrically connected to the source of the transistor 400
  • the wiring 1008 is electrically connected to the gate of the transistor 400
  • the wiring 1009 is electrically connected to the second gate (back gate) of the transistor 400.
  • the 1010 is electrically connected to the drain of the transistor 400.
  • the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
  • the storage devices shown in FIG. 14 can form a memory cell array by arranging them in a matrix like the storage devices shown in FIGS. 12 and 13.
  • One transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, it is preferable to provide a smaller number of transistors 400 than the transistors 200.
  • the transistor 400 is a transistor formed in the same layer as the transistor 200 and can be manufactured in parallel with the transistor 200.
  • the transistor 400 includes a conductor 460 (conductor 460a and a conductor 460b) that functions as a first gate electrode, a conductor 405 that functions as a second gate electrode, and an insulator 222 that functions as a gate insulating layer.
  • the conductor 405 is the same layer as the conductor 205.
  • Oxide 431a, oxide 432a, and oxide 230a are in the same layer, and oxide 431b, oxide 432b, and oxide 230b are in the same layer.
  • the conductor 440 (conductor 440a and conductor 440b) is the same layer as the conductor 240.
  • the insulator 445 (insulator 445a and insulator 445b) is the same layer as the insulator 245.
  • Oxide 430c is the same layer as oxide 230c.
  • the insulator 450 is the same layer as the insulator 250.
  • the conductor 460 is the same layer as the conductor 260.
  • the structures formed in the same layer can be formed at the same time.
  • the oxide 430c can be formed by processing an oxide film that becomes the oxide 230c.
  • Oxide 430c which functions as an active layer of the transistor 400, has reduced oxygen deficiency and impurities such as hydrogen and water, similarly to oxide 230 and the like.
  • the threshold voltage of the transistor 400 can be made larger than 0V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small.
  • an OS transistor a transistor using an oxide as a semiconductor
  • a capacitive element according to one aspect of the present invention
  • a storage device hereinafter, may be referred to as an OS memory device
  • the OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.
  • FIG. 15A shows an example of the configuration of the OS memory device.
  • the storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a writing circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell.
  • the wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and the row to be accessed can be selected.
  • a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400 from the outside as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
  • the control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for row decoders and column decoders.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
  • the memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in a row, and the like.
  • the number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
  • FIG. 15A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap under the memory cell array 1470.
  • FIG. 16 describes an example of a memory cell configuration applicable to the above-mentioned memory cell MC.
  • [DOSRAM] 16A to 16C show an example of a circuit configuration of a DRAM memory cell.
  • a DRAM using a memory cell of a 1OS transistor and 1 capacitance element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • the memory cell 1471 shown in FIG. 16A includes a transistor M1 and a capacitive element CA.
  • the transistor M1 has a gate (sometimes called a top gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1. Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring LL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring LL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, the wiring LL may have a ground potential or a low level potential.
  • the wiring BGL functions as wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell 1471 shown in FIG. 16A corresponds to the storage device shown in FIG. That is, the transistor M1 corresponds to the transistor 200, the capacitive element CA corresponds to the capacitive element 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring LL corresponds to the wiring 1005.
  • the transistor 300 shown in FIG. 12 corresponds to a transistor provided in the peripheral circuit 1411 of the storage device 1400 shown in FIGS. 15A and 15B.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 16B.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 having no back gate, as in the memory cell 1473 shown in FIG. 16C.
  • a transistor 200 can be used as the transistor M1 and a capacitance element 100 can be used as the capacitance element CA.
  • an OS transistor as the transistor M1
  • the leakage current of the transistor M1 can be made very low. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cells can be reduced. Alternatively, the memory cell refresh operation can be eliminated. Further, since the leak current is very low, it is possible to hold multi-valued data or analog data for the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.
  • [NOSRAM] 16D to 16G show an example of a circuit configuration of a gain cell type memory cell having a 2-transistor and 1-capacity element.
  • the memory cell 1474 shown in FIG. 16D includes a transistor M2, a transistor M3, and a capacitance element CB.
  • the transistor M2 has a top gate (sometimes referred to simply as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2. Is connected to the wiring BGL.
  • the second terminal of the capacitive element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitance element CB.
  • the wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M2.
  • the threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell 1474 shown in FIG. 16D corresponds to the storage device shown in FIG. That is, the transistor M2 is connected to the transistor 200, the capacitive element CB is connected to the capacitive element 100, the transistor M3 is connected to the transistor 300, the wiring WBL is connected to the wiring 2003, the wiring WOL is connected to the wiring 2004, the wiring BGL is connected to the wiring 2006, and the wiring CAL is connected to the wiring 2006.
  • the wiring RBL corresponds to the wiring 2002
  • the wiring SL corresponds to the wiring 2001.
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 16E.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 16F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL, as in the memory cell 1477 shown in FIG. 16G.
  • a transistor 200 can be used as the transistor M2
  • a transistor 300 can be used as the transistor M3
  • a capacitance element 100 can be used as the capacitance element CB.
  • OS transistor an OS transistor
  • the leakage current of the transistor M2 can be made very low.
  • the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cells can be reduced.
  • the memory cell refresh operation can be eliminated.
  • the leak current is very low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in the channel forming region (hereinafter, may be referred to as a Si transistor).
  • the conductive type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a readout transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by stacking the transistor M3 on the transistor M3, so that the occupied area of the memory cell can be reduced and the storage device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • an OS transistor is used for the transistor M2 and the transistor M3, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.
  • FIG. 16H shows an example of a gain cell type memory cell having a 3-transistor and 1-capacity element.
  • the memory cell 1478 shown in FIG. 16H includes transistors M4 to M6 and a capacitive element CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL.
  • Wiring GNDL is a wiring that gives a low level potential.
  • the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL.
  • the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not have to have a back gate.
  • the transistor M5 and the transistor M6 may be an n-channel Si transistor or a p-channel Si transistor, respectively.
  • the transistor M4 to the transistor M6 may be an OS transistor.
  • the circuit can be configured by using only the n-type transistor in the memory cell array 1470.
  • the transistor 200 can be used as the transistor M4
  • the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitance element 100 can be used as the capacitance element CC.
  • the leakage current of the transistor M4 can be made very low.
  • the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above.
  • the arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
  • FIG. 5 An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIG.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a CPU 1211, GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with a bump (not shown) and is connected to the first surface of a printed circuit board (Printed Circuit Board: PCB) 1201 as shown in FIG. 17B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • a bump not shown
  • PCB printed circuit Board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM shown in the previous embodiment can be used for the DRAM 1221.
  • the NO SRAM shown in the previous embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200.
  • the above-mentioned NOSRAM or DOSRAM can be used.
  • GPU1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, it becomes possible to execute image processing and product-sum calculation with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memory of the CPU 1211 and the GPU 1212, And after the calculation on the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.
  • the memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
  • the interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface High-Definition Multimedia Interface
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201, the DRAM 1221 provided with the chip 1200 having the GPU 1212, and the motherboard 1203 provided with the flash memory 1222 can be referred to as the GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines.
  • a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DEM) by a product-sum calculation circuit using GPU1212 Since a method such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recurrent neural network
  • DBM deep Boltzmann machine
  • DEM deep belief network
  • the semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 18 schematically shows some configuration examples of the removable storage device.
  • the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 18A is a schematic diagram of a USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like of the substrate 1104.
  • FIG. 18B is a schematic view of the appearance of the SD card
  • FIG. 18C is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111 and a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 1113.
  • data on the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like of the substrate 1113.
  • FIG. 18D is a schematic view of the appearance of the SSD
  • FIG. 18E is a schematic view of the internal structure of the SSD.
  • the SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like of the substrate 1153.
  • the semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip.
  • FIG. 19 shows a specific example of an electronic device provided with a processor such as a CPU or GPU or a chip according to one aspect of the present invention.
  • the GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signage), and large game machines such as pachinko machines.
  • digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be mentioned.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one aspect of the present invention may have an antenna.
  • the display unit can display images, information, and the like.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
  • the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • FIG. 19 shows an example of an electronic device.
  • FIG. 19A illustrates a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5100 has a housing 5101 and a display unit 5102, and as an input interface, a touch panel is provided in the display unit 5102 and buttons are provided in the housing 5101.
  • the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102.
  • Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
  • FIG. 19B illustrates a notebook type information terminal 5200.
  • the notebook type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
  • the notebook-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
  • a smartphone and a notebook-type information terminal are taken as examples of electronic devices, which are shown in FIGS. 19A and 19B, respectively, but information terminals other than the smartphone and the notebook-type information terminal can be applied.
  • information terminals other than smartphones and notebook-type information terminals include PDA (Personal Digital Assistant), desktop-type information terminals, workstations, and the like.
  • FIG. 19C shows a portable game machine 5300, which is an example of a game machine.
  • the portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like.
  • the housing 5302 and the housing 5303 can be removed from the housing 5301.
  • the connection unit 5305 provided in the housing 5301 to another housing (not shown)
  • the image output to the display unit 5304 can be output to another video device (not shown). it can.
  • the housing 5302 and the housing 5303 can each function as operation units.
  • a plurality of players can play the game at the same time.
  • the chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
  • FIG. 19D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
  • a low power consumption game machine By applying the GPU or chip of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400, a low power consumption game machine can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are defined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5300.
  • Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
  • the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one person can play the game. You can play the game.
  • 19C and 19D show a portable game machine and a stationary game machine as examples of the game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like. Can be mentioned.
  • the GPU or chip of one aspect of the present invention can be applied to a large computer.
  • FIG. 19E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 19F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
  • the supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502.
  • the plurality of calculators 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or chip described in the above embodiment can be mounted on the substrate.
  • the supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the chip generates a lot of heat.
  • the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • a supercomputer is illustrated as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the large computer to which the GPU or chip of one aspect of the present invention is applied include a computer (server) that provides a service, a large general-purpose computer (mainframe), and the like.
  • the GPU or chip of one aspect of the present invention can be applied to a moving vehicle and around the driver's seat of the vehicle.
  • FIG. 19G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body.
  • the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are shown.
  • the display panel 5701 to the display panel 5703 can provide various other information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like.
  • the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
  • the display panel 5701 to 5703 can also be used as a lighting device.
  • the display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an image pickup device (not shown) provided in the automobile. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
  • the chip can be used, for example, in an automatic driving system of an automobile.
  • the chip can be used in a system for road guidance, danger prediction, and the like.
  • the display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, a system using artificial intelligence can be provided.
  • FIG. 19H shows an electric refrigerator / freezer 5800, which is an example of an electric appliance.
  • the electric refrigerator / freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric refrigerator / freezer 5800 having artificial intelligence can be realized.
  • the electric freezer / refrigerator 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800, the expiration date of the foodstuffs, etc., and is stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the food.
  • electric refrigerators and freezers have been described as an example of electric appliances
  • other electric appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
  • sample 1A a semiconductor device having a first transistor and a second transistor stacked on top of each other was manufactured. After that, the cross section of the semiconductor device was observed.
  • the transistor 200 shown in FIG. 2 was manufactured as the first transistor and the second transistor.
  • sample preparation method The method for producing sample 1A will be described below.
  • a first layer (1st layer) having a first transistor 200 on the base was created.
  • a film was formed using a target of [number ratio].
  • a tungsten film to be a conductor 240 was formed on the second oxide.
  • the conductor, the second oxide, and the first oxide are processed using a hard mask to form an insulating layer to be the oxide 230a, the oxide 230b, the conductive layer 240B, and the insulating layer 245. did.
  • a silicon oxide film serving as an insulator 280 was formed. Subsequently, CMP treatment was performed, the silicon oxide film was polished, and the surface of the silicon oxide film was flattened to form an insulator 280.
  • sample 1A an opening was formed in the silicon oxide nitride film to be the insulator 280. Subsequently, the conductive layer 240B exposed on the bottom surface of the opening was removed to form the conductor 240a and the conductor 240b.
  • sample 1A a silicon oxide film (insulating film 250A) to be an insulator 250 was formed.
  • a titanium nitride film was formed as a conductive film (conductive film 260A) to be a conductor 260a on a silicon oxide film to be an insulator 250.
  • a tungsten film was formed as a conductive film (conductive film 260B) to be the conductor 260b.
  • the titanium nitride film and the tungsten film were formed by continuous film formation.
  • sample 1A a part of the conductive film 260A, the conductive film 260B, the insulating film 250A, and the oxide film 230C was removed to form the conductor 260, the insulator 250, and the oxide 230c.
  • the first layer having the first transistor 200 was prepared. Subsequently, an interlayer film was formed between the first transistor and the second transistor.
  • an interlayer film a film having a stress opposite to the warping direction of the first layer was formed. That is, when the total stress of all the films constituting the first layer (also referred to as the total stress of the first layer) is compressive stress, the interlayer film uses a layer having tensile stress. When the total stress of the first layer is tensile stress, a layer having compressive stress is used as the interlayer film.
  • the total stress of the first layer was the compressive stress. Therefore, as the interlayer film, a layer having a tensile stress was used as the total stress. Specifically, a silicon oxide film having a compressive stress and a silicon oxide film having a tensile stress are laminated, and the film thickness of the silicon oxide film having a tensile stress is set to be larger than the film thickness of the silicon oxide film having a compressive stress. A thick film was formed.
  • a second layer (2nd layer) having a second transistor 200 on the interlayer film was prepared.
  • the second layer was prepared in the same process as the first layer.
  • Sample 1A was prepared from the above steps.
  • the length in the L length direction in the channel portion of sample 1A was 72 nm.
  • the length in the W length direction in the channel portion of sample 1A was 51 nm.
  • the first transistor and the second transistor could be laminated and manufactured.
  • the threshold value was changed by changing the voltage (Vbg) applied to the conductor 205 in the transistor 200 of the first layer and the transistor 200 of the second layer. Specifically, do condition the first time the voltage (Vbg) is applied to the conductor 205 of each transistor 200, it was confirmed by performing I d -V g Measurement of transistor 200.
  • FIG 22A shows the I d -V g measurement results in transistor 200 of the first layer. Further, in the FIG. 22B, the shows the I d -V g measurement results in transistor 200 of the second layer.
  • the amount of change in the threshold value with respect to the voltage (Vbg) applied to the conductor 205 of the transistor 200 provided in each layer was determined.
  • the result is shown in FIG. 23A. As shown in FIG. 23A, it was found that the transistor 200 can control the threshold value according to the circuit application by appropriately adjusting the voltage (V bg) applied to the conductor 205.
  • the influence of the fluctuation of the threshold value of each transistor 200 on the field effect mobility ( ⁇ FEs ) of each transistor 200 was investigated.
  • the result is shown in FIG. 23B.
  • the threshold fluctuation amount ⁇ V th / ⁇ V bg is 0.13 V / V.
  • FIG 24A shows the I d -V g measurement results in transistor 200 of the first layer.
  • FIG. 24B shows the I d -V g measurement results in transistor 200 of the second layer.
  • the off-leakage current of the transistors 200 provided in the first layer and the second layer is always below the detection limit (1 ⁇ 10-13 A) in the temperature range of ⁇ 40 to 85 ° C. It turned out to be. Further, the temperature dependence of the field effect mobility of each transistor 200 is shown in the figure. It was confirmed that the field effect mobility was almost unchanged with respect to the temperature change. This is a feature not found in Si transistors whose field-effect mobility decreases at high temperatures.
  • the vertical axis represents Leakage current and the horizontal axis represents 1000 / T.
  • the white circles indicate the results of Drain
  • the squares indicate the results of D-TG
  • the triangles indicate the results of D-BG
  • the diamonds indicate the results of Si FET [5].
  • the off-leakage value between the conductors was 5.0 ⁇ 10 -20 A / ⁇ m or less. Therefore, it was found that the refresh power of the transistor 200 can be significantly reduced because the off-leakage current is extremely low.
  • FIG. 26 the vertical axis represents the Write Time and the Erase Time, and the horizontal axis represents the Retension Time.
  • FIG. 26A shows the result when DOSRAM is assumed
  • FIG. 26B shows the result when NOSRAM is assumed.
  • the holding time is assumed to only the sub-threshold leakage as leakage caused was calculated by extrapolating the I d -V g curve by subthreshold swing.
  • the data retention time at 85 ° C is adjusted by applying a voltage (V pg voltage) to the conductor 205. ..
  • V pg voltage a voltage (V pg voltage) to the conductor 205. ..
  • the power supply voltage used for holding and writing was ⁇ 0.8V / 2.5V, the allowable voltage fluctuation amount was 0.2V, the writing determination voltage was 0.52V, and the operating speed of the drive circuit was 2.5GHz.
  • the write speed under the assumption of DOSRAM drive (holding capacity 3.5 fF, data holding time 1 hr at 85 ° C.) is about 1.0 to 3.0 nsec. I was able to estimate. This corresponds to an operating speed of 100 MHz or more for the DOS RAM.
  • the write time under the NO SRAM drive assumption (holding capacity 1.2 fF, data holding time assumed to be 5 years at 85 ° C.) could be estimated to be 10.0 nsec or less.
  • the load on wiring such as bit lines can be reduced by using the laminated structure, so that the influence of the read speed is small and the write speed can determine the overall operating speed. Therefore, when the writing time is 10.0 nsec or less, the operating speed corresponds to 40 MHz or more.
  • FIG. 26B also shows the estimation result of the time required to erase the written data.
  • the holding capacity was 3.5 fF, and the voltage fluctuation allowed for holding multiple values (3 bits / cell) was 0.02 V. Assuming that it is used for NO SRAM, analog voltage can be written directly to the holding node, so unlike flash memory, verify operation is not required. Therefore, it was confirmed that both the writing time and the data erasing time were sufficiently shorter than the writing time of the drive circuit of 100 nsec in the range of the holding time of 1 year or less.
  • FIG. 28 shows the holding characteristics obtained from the evaluation results. From FIG. 28, it was shown that even when driven as a multi-valued memory, writing equivalent to 8 values is possible in 100 nsec, and data can be retained for 1 hr or more at 27 ° C.
  • FIG. 29 shows the rewrite resistance based on the evaluation result.
  • the horizontal axis represents Write cycles. From FIG. 29, it was confirmed that the data could be retained without any problem even if the rewriting operation was performed 10 or 12 times or more.
  • the cut-off frequency f T of the transistor 200 was evaluated for the cut-off frequency f T of the transistor 200.
  • the result is shown in FIG. In FIG. 30, the horizontal axis represents Input Frequency.
  • a sample prepared only for the first layer was used. The evaluation was performed by setting the voltage (V g ) applied to the conductor 205 and the voltage (V d ) applied to the conductor 240 a to 2.5 V.
  • the cut-off frequency f T could be estimated to be about 43 GHz.
  • the result shows that the transistor 200 can be applied not only to a memory but also to an analog circuit such as a high frequency circuit.
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.

Abstract

Provided is a semiconductor device suited to high integration. The present invention has: a first layer on a substrate and provided with a first transistor having an oxide semiconductor; a second layer on the first layer; a third layer on the second layer and provided with a second transistor having an oxide semiconductor; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.

Description

半導体装置、および半導体装置の作製方法Semiconductor devices and methods for manufacturing semiconductor devices
　本発明の一態様は、半導体装置、および半導体装置の作製方法に関する。また、本発明の一態様は、半導体ウエハ、モジュール、および電子機器に関する。 One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Further, one aspect of the present invention relates to semiconductor wafers, modules, and electronic devices.
　なお、本明細書等において半導体装置とは、半導体特性を利用することで機能し得る装置全般を指す。トランジスタなどの半導体素子をはじめ、半導体回路、演算装置、記憶装置は、半導体装置の一態様である。表示装置（液晶表示装置、発光表示装置など）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置、電子機器などは、半導体装置を有すると言える場合がある。 In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor device such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of the semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.
　なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様は、物、方法、または、製造方法に関するものである。また、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物（コンポジション・オブ・マター）に関するものである。 Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Also, one aspect of the present invention relates to a process, machine, manufacture, or composition (composition of matter).
　絶縁表面を有する基板上に形成された半導体薄膜を用いてトランジスタを構成する技術が注目されている。当該トランジスタは集積回路（ＩＣ）や画像表示装置（単に表示装置とも表記する。）のような電子デバイスに広く応用されている。トランジスタに適用可能な半導体薄膜としてシリコン系半導体材料が広く知られているが、その他の材料として酸化物半導体が注目されている。 Attention is being paid to a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
　酸化物半導体において、単結晶でも非晶質でもない、ＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ）構造およびｎｃ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ）構造が見出されている（非特許文献１及び非特許文献２参照）。 In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystal nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).
　非特許文献１および非特許文献２では、ＣＡＡＣ構造を有する酸化物半導体を用いてトランジスタを作製する技術が開示されている。 Non-Patent Document 1 and Non-Patent Document 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
　本発明の一態様は、信頼性が良好な半導体装置を提供することを課題の一つとする。また、本発明の一態様は、良好な電気特性を有する半導体装置を提供することを課題の一つとする。また、本発明の一態様は、オン電流が大きい半導体装置を提供することを課題の一つとする。また、本発明の一態様は、微細化または高集積化が可能な半導体装置を提供することを課題の一つとする。また、本発明の一態様は、低消費電力の半導体装置を提供することを課題の一つとする。 One aspect of the present invention is to provide a semiconductor device having good reliability. Another object of one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Another object of one aspect of the present invention is to provide a semiconductor device having a large on-current. Another object of one aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Another object of one aspect of the present invention is to provide a semiconductor device having low power consumption.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。 The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. It should be noted that the problems other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the problems other than these from the description of the description, drawings, claims, etc. Is.
　本発明の一態様は、基板上に、酸化物半導体を有する第１のトランジスタを設けた第１の層と、第１の層上に、第２の層と、第２の層上に、酸化物半導体を有する第２のトランジスタを設けた第３の層と、を有し、第１の層の総内部応力と、第３の層の総内部応力とは、第１の方向に作用し、第２の層の総内部応力は、第１の方向と逆方向に作用する。 One aspect of the present invention is to oxidize a first layer in which a first transistor having an oxide semiconductor is provided on a substrate, a second layer on the first layer, and an oxidation on the second layer. It has a third layer provided with a second transistor having a physical semiconductor, and the total internal stress of the first layer and the total internal stress of the third layer act in the first direction. The total internal stress of the second layer acts in the direction opposite to the first direction.
　本発明の一態様は、基板上に、酸化物半導体を有する第１のトランジスタを設けた第１の層と、第１の層上に、第２の層と、第２の層上に、酸化物半導体を有する第２のトランジスタを設けた第３の層と、第１の層と第２の層との間に、第４の層と、第２の層と第３の層との間に、第５の層と、を有し、第１の層の総内部応力と、第３の層の総内部応力とは、第１の方向に作用し、第２の層の総内部応力は、第１の方向と逆方向に作用し、第４の層と、第５の層は、バリア性を有する膜を含む。 One aspect of the present invention is to oxidize a first layer in which a first transistor having an oxide semiconductor is provided on a substrate, a second layer on the first layer, and an oxidation on the second layer. Between the third layer provided with the second transistor having a physical semiconductor, between the first layer and the second layer, between the fourth layer, and between the second layer and the third layer. , The fifth layer, the total internal stress of the first layer and the total internal stress of the third layer act in the first direction, and the total internal stress of the second layer is Acting in the direction opposite to the first direction, the fourth layer and the fifth layer contain a film having a barrier property.
　上記において、第４の層の総内部応力と、第５の層の総内部応力とは、第１の方向に作用する。 In the above, the total internal stress of the fourth layer and the total internal stress of the fifth layer act in the first direction.
　上記において、バリア性を有する膜は、水素、および不純物の拡散を抑制する。 In the above, the film having a barrier property suppresses the diffusion of hydrogen and impurities.
　上記において、第４の層は、第１の層を封止し、第５の層は、第３の層を封止する。 In the above, the fourth layer seals the first layer, and the fifth layer seals the third layer.
　上記において、第２の層は配線として機能する導電体を有する。 In the above, the second layer has a conductor that functions as wiring.
　上記において、酸化物半導体は、Ｉｎ−Ｇａ−Ｚｎ酸化物である。 In the above, the oxide semiconductor is an In-Ga-Zn oxide.
　本発明の一態様により、信頼性が良好な半導体装置を提供することができる。また、本発明の一態様により、良好な電気特性を有する半導体装置を提供することができる。また、本発明の一態様により、オン電流が大きい半導体装置を提供することができる。また、本発明の一態様により、微細化または高集積化が可能な半導体装置を提供することができる。また、本発明の一態様により、低消費電力の半導体装置を提供することができる。 According to one aspect of the present invention, it is possible to provide a semiconductor device having good reliability. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having good electrical characteristics. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Further, according to one aspect of the present invention, a semiconductor device having low power consumption can be provided.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 The description of these effects does not prevent the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.
図１Ａ、図１Ｂは本発明の一態様に係る半導体装置の断面図である。
図２Ａ、図２Ｂ、図２Ｃ、図２Ｄは本発明の一態様に係る半導体装置の断面図および上面図である。
図３Ａ、図３Ｂ、図３Ｃ、図３Ｄは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図４Ａ、図４Ｂ、図４Ｃ、図４Ｄは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図５Ａ、図５Ｂ、図５Ｃ、図５Ｄは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図６Ａ、図６Ｂ、図６Ｃ、図６Ｄは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図７Ａ、図７Ｂ、図７Ｃ、図７Ｄは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図８Ａ、図８Ｂ、図８Ｃ、図８Ｄは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図９Ａ、図９Ｂ、図９Ｃ、図９Ｄは本発明の一態様に係る半導体装置の作製方法を示す上面図、および断面図である。
図１０Ａ、図１０Ｂ、図１０Ｃは本発明の一態様に係る半導体装置の断面図および上面図である。
図１１Ａ、図１１Ｂ、図１１Ｃ、図１１Ｄは本発明の一態様に係る半導体装置の断面図および上面図である。
図１２は本発明の一態様に係る記憶装置の構成を示す断面図である。
図１３は本発明の一態様に係る記憶装置の構成を示す断面図である。
図１４は本発明の一態様に係る記憶装置の構成を示す断面図である。
図１５Ａ、図１５Ｂは本発明の一態様に係る記憶装置の構成例を示すブロック図および斜視図である。
図１６Ａ、図１６Ｂ、図１６Ｃ、図１６Ｄ、図１６Ｅ、図１６Ｆ、図１６Ｇ、図１６Ｈは本発明の一態様に係る記憶装置の構成例を示す回路図である。
図１７Ａ、図１７Ｂは本発明の一態様に係る半導体装置の模式図である。
図１８Ａ、図１８Ｂ、図１８Ｃ、図１８Ｄ、図１８Ｅは本発明の一態様に係る記憶装置の模式図である。
図１９Ａ、図１９Ｂ、図１９Ｃ、図１９Ｄ、図１９Ｅ、図１９Ｆ、図１９Ｇ、図１９Ｈは本発明の一態様に係る電子機器を示す図である。
図２０Ａ、図２０Ｂは本実施例における試料の断面ＳＴＥＭ観察結果を説明する図である。
図２１は本実施例における試料の断面ＳＴＥＭ観察結果を説明する図である。
図２２Ａ、図２２Ｂは本実施例における試料が有するトランジスタのＩｄ−Ｖｇ測定結果を説明する図である。
図２３Ａ、図２３Ｂは本実施例における試料が有するトランジスタの閾値の変動が、各トランジスタ２００の電界効果移動度（μＦＥｓ）に与える影響を説明する図である。
図２４Ａ、図２４Ｂは本実施例における試料が有するトランジスタのＩｄ−Ｖｇ測定結果および移動度の測定結果を説明する図である。
図２５は本実施例における試料が有するトランジスタのオフリーク電流の測定結果を説明する図である。
図２６Ａ、図２６Ｂは本実施例における試料が有するトランジスタの書き込み速度を説明する図である。
図２７は本実施例における試料が有するトランジスタの多値メモリとして機能した場合の書き込み動作と保持試験の結果を説明する図である。
図２８は本実施例における試料が有するトランジスタの多値動作での書き込み時間、および消去時間を説明する図である。
図２９は本実施例における試料が有するトランジスタの２値動作における書き換え耐性試験の結果を説明する図である。
図３０は本実施例における試料が有するトランジスタの遮断周波数ｆＴの評価を説明する図である。 1A and 1B are cross-sectional views of a semiconductor device according to an aspect of the present invention.
2A, 2B, 2C, and 2D are a cross-sectional view and a top view of the semiconductor device according to one aspect of the present invention.
3A, 3B, 3C, and 3D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
4A, 4B, 4C, and 4D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
5A, 5B, 5C, and 5D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
6A, 6B, 6C, and 6D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
7A, 7B, 7C, and 7D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
8A, 8B, 8C, and 8D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
9A, 9B, 9C, and 9D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.
10A, 10B, and 10C are a cross-sectional view and a top view of the semiconductor device according to one aspect of the present invention.
11A, 11B, 11C, and 11D are cross-sectional views and top views of the semiconductor device according to one aspect of the present invention.
FIG. 12 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
FIG. 13 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
FIG. 14 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention.
15A and 15B are a block diagram and a perspective view showing a configuration example of a storage device according to one aspect of the present invention.
16A, 16B, 16C, 16D, 16E, 16F, 16G, and 16H are circuit diagrams showing a configuration example of a storage device according to one aspect of the present invention.
17A and 17B are schematic views of a semiconductor device according to one aspect of the present invention.
18A, 18B, 18C, 18D, and 18E are schematic views of a storage device according to an aspect of the present invention.
19A, 19B, 19C, 19D, 19E, 19F, 19G, 19H are diagrams showing an electronic device according to an aspect of the present invention.
20A and 20B are views for explaining the cross-sectional STEM observation results of the sample in this example.
FIG. 21 is a diagram for explaining the cross-sectional STEM observation results of the sample in this example.
FIG. 22A, FIG. 22B is a diagram for explaining the I d -V g measurements of the transistor included in the sample in the present embodiment.
23A and 23B are diagrams for explaining the influence of the fluctuation of the threshold value of the transistor of the sample in this embodiment on the field effect mobility ( μFEs) of each transistor 200.
FIG. 24A, FIG. 24B is a diagram illustrating a measurement result of I d -V g measured results and the mobility of the transistor having the sample in this embodiment.
FIG. 25 is a diagram for explaining the measurement result of the off-leakage current of the transistor included in the sample in this embodiment.
26A and 26B are diagrams for explaining the writing speed of the transistor included in the sample in this embodiment.
FIG. 27 is a diagram illustrating the results of the writing operation and the holding test when the sample functions as the multi-valued memory of the transistor in this embodiment.
FIG. 28 is a diagram illustrating a writing time and an erasing time in the multi-valued operation of the transistor included in the sample in this embodiment.
FIG. 29 is a diagram for explaining the result of the rewrite resistance test in the binary operation of the transistor included in the sample in this embodiment.
Figure 30 is a diagram for explaining the evaluation of the cut-off frequency f T of the transistor included in the sample in the present embodiment.
　以下、実施の形態について図面を参照しながら説明する。ただし、実施の形態は多くの異なる態様で実施することが可能であり、趣旨およびその範囲から逸脱することなくその形態および詳細を様々に変更し得ることは、当業者であれば容易に理解される。したがって、本発明は、以下の実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments and that the embodiments and details can be variously modified without departing from the spirit and scope thereof. To. Therefore, the present invention is not construed as being limited to the description of the following embodiments.
　また、図面において、大きさ、層の厚さ、または領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。なお、図面は、理想的な例を模式的に示したものであり、図面に示す形状または値などに限定されない。例えば、実際の製造工程において、エッチングなどの処理により層やレジストマスクなどが意図せずに目減りすることがあるが、理解を容易とするため、図に反映しないことがある。また、図面において、同一部分または同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する場合がある。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。 Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may not be reflected in the figure for the sake of easy understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular sign may be added.
　また、特に上面図（「平面図」ともいう。）や斜視図などにおいて、発明の理解を容易とするため、一部の構成要素の記載を省略する場合がある。また、一部の隠れ線などの記載を省略する場合がある。 Further, in order to facilitate understanding of the invention, in particular, in a top view (also referred to as a "plan view") or a perspective view, the description of some components may be omitted. In addition, some hidden lines may be omitted.
　また、本明細書等において、第１、第２等として付される序数詞は便宜上用いるものであり、工程順または積層順を示すものではない。そのため、例えば、「第１の」を「第２の」または「第３の」などと適宜置き換えて説明することができる。また、本明細書等に記載されている序数詞と、本発明の一態様を特定するために用いられる序数詞は一致しない場合がある。 Further, in the present specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
　また、本明細書等において、「上に」、「下に」などの配置を示す語旬は、構成同士の位置関係を、図面を参照して説明するために、便宜上用いている。また、構成同士の位置関係は、各構成を描写する方向に応じて適宜変化するものである。したがって、明細書で説明した語句に限定されず、状況に応じて適切に言い換えることができる。 Further, in the present specification and the like, the word seasons indicating the arrangements such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes as appropriate according to the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.
　例えば、本明細書等において、ＸとＹとが接続されている、と明示的に記載されている場合は、ＸとＹとが電気的に接続されている場合と、ＸとＹとが機能的に接続されている場合と、ＸとＹとが直接的に接続されている場合とが、本明細書等に開示されているものとする。したがって、所定の接続関係、例えば、図または文章に示された接続関係に限定されず、図または文章に示された接続関係以外のものも、図または文章に開示されているものとする。ここで、Ｘ、Ｙは、対象物（例えば、装置、素子、回路、配線、電極、端子、導電膜、層、など）であるとする。 For example, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or a sentence, and a connection relationship other than the connection relationship shown in the figure or the sentence is also disclosed in the figure or the sentence. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
　また、本明細書等において、トランジスタとは、ゲートと、ドレインと、ソースとを含む少なくとも三つの端子を有する素子である。そして、ドレイン（ドレイン端子、ドレイン領域またはドレイン電極）とソース（ソース端子、ソース領域またはソース電極）の間にチャネルが形成される領域（以下、チャネル形成領域ともいう。）を有しており、チャネル形成領域を介して、ソースとドレインとの間に電流を流すことができるものである。なお、本明細書等において、チャネル形成領域とは、電流が主として流れる領域をいう。 Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. It also has a region (hereinafter, also referred to as a channel forming region) in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode). A current can flow between the source and the drain through the channel formation region. In the present specification and the like, the channel forming region means a region in which a current mainly flows.
　また、ソースやドレインの機能は、異なる極性のトランジスタを採用する場合や、回路動作において電流の方向が変化する場合などには入れ替わることがある。このため、本明細書等においては、ソースやドレインの用語は、入れ替えて用いることができる場合がある。 In addition, the source and drain functions may be interchanged when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.
　なお、チャネル長とは、例えば、トランジスタの上面図において、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネル形成領域における、ソース（ソース領域またはソース電極）とドレイン（ドレイン領域またはドレイン電極）との間の距離をいう。なお、一つのトランジスタにおいて、チャネル長が全ての領域で同じ値をとるとは限らない。すなわち、一つのトランジスタのチャネル長は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル長は、チャネル形成領域における、いずれか一の値、最大値、最小値または平均値とする。 The channel length is, for example, the source in the top view of the transistor, the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the channel formation region. The distance between (source region or source electrode) and drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
　チャネル幅とは、例えば、トランジスタの上面図において、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネル形成領域における、チャネル長方向を基準として垂直方向のチャネル形成領域の長さをいう。なお、一つのトランジスタにおいて、チャネル幅がすべての領域で同じ値をとるとは限らない。すなわち、一つのトランジスタのチャネル幅は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル幅は、チャネル形成領域における、いずれか一の値、最大値、最小値または平均値とする。 The channel width is, for example, the channel length direction in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other in the top view of the transistor, or the channel formation region. Refers to the length of the channel formation region in the vertical direction with reference to. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
　なお、本明細書等において、トランジスタの構造によっては、実際にチャネルの形成される領域におけるチャネル幅（以下、「実効的なチャネル幅」ともいう）と、トランジスタの上面図において示されるチャネル幅（以下、「見かけ上のチャネル幅」ともいう。）と、が異なる場合がある。例えば、ゲート電極が半導体の側面を覆う場合、実効的なチャネル幅が、見かけ上のチャネル幅よりも大きくなり、その影響が無視できなくなる場合がある。例えば、微細かつゲート電極が半導体の側面を覆うトランジスタでは、半導体の側面に形成されるチャネル形成領域の割合が大きくなる場合がある。その場合は、見かけ上のチャネル幅よりも、実効的なチャネル幅の方が大きくなる。 In the present specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor (hereinafter, also referred to as “effective channel width”). Hereinafter, it may also be referred to as “apparent channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the proportion of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
　このような場合、実効的なチャネル幅の、実測による見積もりが困難となる場合がある。例えば、設計値から実効的なチャネル幅を見積もるためには、半導体の形状が既知という仮定が必要である。したがって、半導体の形状が正確にわからない場合には、実効的なチャネル幅を正確に測定することは困難である。 In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.
　本明細書では、単にチャネル幅と記載した場合には、見かけ上のチャネル幅を指す場合がある。または、本明細書では、単にチャネル幅と記載した場合には、実効的なチャネル幅を指す場合がある。なお、チャネル長、チャネル幅、実効的なチャネル幅、見かけ上のチャネル幅などは、断面ＴＥＭ像などを解析することなどによって、値を決定することができる。 In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
　なお、半導体の不純物とは、例えば、半導体を構成する主成分以外をいう。例えば、濃度が０．１原子％未満の元素は不純物と言える。不純物が含まれることにより、例えば、半導体の欠陥準位密度が高くなることや、結晶性が低下することなどが起こる場合がある。半導体が酸化物半導体である場合、半導体の特性を変化させる不純物としては、例えば、第１族元素、第２族元素、第１３族元素、第１４族元素、第１５族元素、酸化物半導体の主成分以外の遷移金属などがあり、例えば、水素、リチウム、ナトリウム、シリコン、ホウ素、リン、炭素、窒素などがある。なお、水も不純物として機能する場合がある。また、例えば不純物の混入によって、酸化物半導体に酸素欠損が形成される場合がある。 Note that the semiconductor impurities refer to, for example, other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may result in, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors. There are transition metals other than the main component, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water may also function as an impurity. Further, for example, oxygen deficiency may be formed in the oxide semiconductor due to the mixing of impurities.
　なお、本明細書等において、酸化窒化シリコンとは、その組成として、窒素よりも酸素の含有量が多いものである。また、窒化酸化シリコンとは、その組成として、酸素よりも窒素の含有量が多いものである。 In the present specification and the like, silicon oxide nitride has a higher oxygen content than nitrogen as its composition. Further, silicon nitride has a higher nitrogen content than oxygen in its composition.
　また、本明細書等において、「絶縁体」という用語を、絶縁膜または絶縁層と言い換えることができる。また、「導電体」という用語を、導電膜または導電層と言い換えることができる。また、「半導体」という用語を、半導体膜または半導体層と言い換えることができる。 Further, in the present specification and the like, the term "insulator" can be paraphrased as an insulating film or an insulating layer. Further, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be paraphrased as a semiconductor film or a semiconductor layer.
　また、本明細書等において、「平行」とは、二つの直線が−１０°以上１０°以下の角度で配置されている状態をいう。したがって、−５°以上５°以下の場合も含まれる。また、「略平行」とは、二つの直線が−３０°以上３０°以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０°以上１００°以下の角度で配置されている状態をいう。したがって、８５°以上９５°以下の場合も含まれる。また、「略垂直」とは、二つの直線が６０°以上１２０°以下の角度で配置されている状態をいう。 Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
　本明細書等において、金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）とは、広い意味での金属の酸化物である。金属酸化物は、酸化物絶縁体、酸化物導電体（透明酸化物導電体を含む。）、酸化物半導体（Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒまたは単にＯＳともいう。）などに分類される。例えば、トランジスタの半導体層に金属酸化物を用いた場合、当該金属酸化物を酸化物半導体と呼称する場合がある。つまり、ＯＳトランジスタと記載する場合においては、金属酸化物または酸化物半導体を有するトランジスタと換言することができる。 In the present specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
　また、本明細書等において、ノーマリーオフとは、ゲートに電位を印加しない、またはゲートに接地電位を与えたときに、トランジスタに流れるチャネル幅１μｍあたりのドレイン電流が、室温において１×１０−２０Ａ以下、８５℃において１×１０−１８Ａ以下、または１２５℃において１×１０−１６Ａ以下であることをいう。 Further, in the present specification and the like, normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the drain current per 1 μm of the channel width flowing through the transistor is 1 × 10 − at room temperature. It means that it is 20 A or less, 1 × 10 -18 A or less at 85 ° C, or 1 × 10 -16 A or less at 125 ° C.
（実施の形態１）
　本実施の形態では、本発明の一態様に係るトランジスタ２００を有する半導体装置の一例について説明する。 (Embodiment 1)
In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described.
＜半導体装置の構成例＞
　図１は、本発明の一態様に係るトランジスタ２００を有する半導体装置の断面図である。なお、図１に示す半導体装置では、図の明瞭化のために一部の要素を省いている。 <Semiconductor device configuration example>
FIG. 1 is a cross-sectional view of a semiconductor device having a transistor 200 according to an aspect of the present invention. In the semiconductor device shown in FIG. 1, some elements are omitted for the purpose of clarifying the figure.
　図１Ａに示すように、本発明の一態様の半導体装置１０は、基板１１と、基板上の調整層１２と、トランジスタを含む層１４と、調整層１６と、トランジスタを含む層１８と、を有し、各層が積層構造を構成している。また、トランジスタを含む層１４には、少なくとも１個以上のトランジスタ２００＿１が設けられ、トランジスタを含む層１８には、少なくとも１個以上のトランジスタ２００＿２が設けられる。 As shown in FIG. 1A, the semiconductor device 10 of one aspect of the present invention includes a substrate 11, an adjusting layer 12 on the substrate, a layer 14 including a transistor, an adjusting layer 16, and a layer 18 containing a transistor. Each layer constitutes a laminated structure. Further, at least one or more transistors 200_1 are provided on the layer 14 including the transistors, and at least one or more transistors 200_1 are provided on the layer 18 including the transistors.
　なお、トランジスタ２００＿１、およびトランジスタ２００＿２は、異なる構造のトランジスタとしても、同じ構造のトランジスタとしてもよい。また、以下の明細書では、トランジスタ２００＿１、およびトランジスタ２００＿２をまとめてトランジスタ２００と記載する場合がある。 The transistor 200_1 and the transistor 200_2 may be a transistor having a different structure or a transistor having the same structure. Further, in the following specification, the transistor 200_1 and the transistor 200_2 may be collectively referred to as a transistor 200.
　ここで、トランジスタ２００は、チャネルが形成される領域（以下、チャネル形成領域ともいう。）を含む半導体に、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう。）を用いることが好ましい。 Here, the transistor 200 uses a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor as a semiconductor that includes a region in which a channel is formed (hereinafter, also referred to as a channel formation region). Is preferable.
　酸化物半導体として、例えば、Ｉｎ−Ｍ−Ｚｎ酸化物（元素Ｍは、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種）等の金属酸化物を用いるとよい。また、酸化物半導体として、Ｉｎ−Ｇａ−Ｚｎ酸化物、Ｉｎ−Ｇａ酸化物、Ｉｎ−Ｚｎ酸化物を用いてもよい。 As oxide semiconductors, for example, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium). , Hafnium, tantalum, tungsten, gallium, etc. (one or more) and the like may be used. Further, as the oxide semiconductor, In-Ga-Zn oxide, In-Ga oxide, or In-Zn oxide may be used.
　チャネル形成領域に酸化物半導体を用いたトランジスタ２００は、非導通状態において極めてリーク電流が小さいため、低消費電力の半導体装置を提供できる。 Since the transistor 200 using an oxide semiconductor in the channel forming region has an extremely small leakage current in a non-conducting state, it is possible to provide a semiconductor device with low power consumption.
　また、酸化物半導体を用いることで、様々な素子を積層して立体的に集積化することができる。つまり、酸化物半導体は、スパッタリング法などを用いて成膜できるため、基板の平面に回路を展開するだけでなく、垂直方向にも回路を展開した立体集積回路（３次元集積回路）とすることができる。 Further, by using an oxide semiconductor, various elements can be laminated and integrated three-dimensionally. That is, since the oxide semiconductor can be deposited by using a sputtering method or the like, it should be a three-dimensional integrated circuit (three-dimensional integrated circuit) in which the circuit is developed not only on the plane of the substrate but also in the vertical direction. Can be done.
　一方、半導体装置の高集積化に伴い、露光工程において、必要なマスク合わせ（アライメント）の精度も高くなる。また、設計におけるアライメントのマージンが小さくなる傾向がある。 On the other hand, as semiconductor devices become more integrated, the accuracy of mask alignment required in the exposure process also increases. Also, the alignment margin in the design tends to be small.
　また、高集積化に際し、積層構造を形成する総膜数の増加に伴い、基板上に成膜された薄膜から生じる内部応力も増加する。基板内に平行な成分の内部応力が作用すると、基板、および基板上に設けた半導体装置に歪みが生じ、露光工程において、フォーカスのずれが起こり、結果、フォーカスボケが発生する場合がある。また、基板に歪みが生じた場合、装置に投入した場合、基板の吸着ができない、または吸着したとしても基板が不安定な状態になる。さらに、アライメントに対するずれが生じる場合がある。 In addition, as the total number of films forming the laminated structure increases, the internal stress generated from the thin film formed on the substrate also increases in the case of high integration. When the internal stress of parallel components acts in the substrate, the substrate and the semiconductor device provided on the substrate are distorted, and the focus shift occurs in the exposure process, and as a result, the focus blur may occur. Further, when the substrate is distorted, when it is put into the apparatus, the substrate cannot be adsorbed, or even if it is adsorbed, the substrate becomes unstable. In addition, misalignment may occur.
　ここで、内部応力は、引張応力と圧縮応力の２方向がある。例えば、引張応力は、基板と薄膜との界面で膜に対して拡張する方向に作用し、基板に対しては収縮する方向に作用する。従って、基板が薄く、機械的強度が十分に強くない場合、基板は被成膜面が凹面となるように変形する。一方、基板が厚い、または機械的強度が十分に強く、薄膜が引張応力に耐えられなかった場合、膜面に亀裂が生じる場合がある。 Here, the internal stress has two directions, tensile stress and compressive stress. For example, the tensile stress acts on the film in the direction of expansion at the interface between the substrate and the thin film, and acts on the substrate in the direction of contraction. Therefore, when the substrate is thin and the mechanical strength is not sufficiently strong, the substrate is deformed so that the surface to be filmed becomes a concave surface. On the other hand, if the substrate is thick or the mechanical strength is sufficiently strong and the thin film cannot withstand the tensile stress, cracks may occur on the film surface.
　また、圧縮応力は、基板と薄膜との界面で膜に対して圧縮する方向に作用し、基板に対しては拡張する方向に作用する。従って、基板が薄く、機械的強度が十分に強くない場合、基板は被成膜面が凸面となるように変形する。一方、基板が厚い、または機械的強度が十分に強く、薄膜が引張応力に耐えられなかった場合、膜が基板面から浮き上がり、全面に亀裂が生じ剥離し、剥離した膜同士が重なり合う場合がある。 In addition, the compressive stress acts on the film in the direction of compression at the interface between the substrate and the thin film, and acts on the substrate in the direction of expansion. Therefore, when the substrate is thin and the mechanical strength is not sufficiently strong, the substrate is deformed so that the surface to be filmed becomes a convex surface. On the other hand, if the substrate is thick or the mechanical strength is sufficiently strong and the thin film cannot withstand the tensile stress, the film may be lifted from the substrate surface, cracked on the entire surface and peeled off, and the peeled films may overlap each other. ..
　従って、高集積化は、設計におけるアライメントに厳密さが求められる一方で、基板の歪みにより、アライメントのずれが生じやすくなる。 Therefore, while high integration requires strict alignment in the design, misalignment is likely to occur due to distortion of the substrate.
　特に、半導体装置が、繰り返しの積層構造を有する場合、繰り返し単位の層構造の内部応力、つまり、繰り返し単位の層構造を構成する全膜の内部応力を合わせた応力（総内部応力ともいう）は、同一方向である。従って、繰り返し単位の層構造を積層すればするほど、一方向にかかる総内部応力は大きくなる。 In particular, when the semiconductor device has a repeating laminated structure, the internal stress of the layered structure of the repeating unit, that is, the combined stress of the internal stresses of all the films constituting the layered structure of the repeating unit (also referred to as total internal stress) is , In the same direction. Therefore, the more the layered structure of the repeating unit is laminated, the larger the total internal stress applied in one direction.
　そこで、ｎ（ｎは２以上の自然数）層の繰り返し層構造を有する積層構造において、ｎ−１層目の構造と、ｎ層目の層構造との間に、調整層を設けるとよい。調整層は、繰り返し単位の層構造の総内部応力と、反対方向の内部応力を有する。具体的には、繰り返し単位の層構造において、総内部応力が圧縮方向に作用する場合、調整層の総内部応力が引張方向に作用するような層構造とするとよい。 Therefore, in a laminated structure having a repeating layer structure of n (n is a natural number of 2 or more) layers, it is preferable to provide an adjusting layer between the structure of the n-1st layer and the layer structure of the nth layer. The adjusting layer has the total internal stress of the layer structure of the repeating unit and the internal stress in the opposite direction. Specifically, in the layer structure of the repeating unit, when the total internal stress acts in the compression direction, the layer structure may be such that the total internal stress of the adjusting layer acts in the tensile direction.
　従って、図１Ａに示す半導体装置１０に示すように、トランジスタを含む層１４と、トランジスタを含む層１８との間には、調整層１６を設けるとよい。 Therefore, as shown in the semiconductor device 10 shown in FIG. 1A, it is preferable to provide an adjusting layer 16 between the layer 14 including the transistor and the layer 18 containing the transistor.
　具体的には、トランジスタを含む層１４と、トランジスタを含む層１８において、総内部応力は同方向に作用する。一方、調整層１６の総内部応力は、トランジスタを含む層１４、またはトランジスタを含む層１８と逆方向に作用する。 Specifically, the total internal stress acts in the same direction in the layer 14 containing the transistor and the layer 18 containing the transistor. On the other hand, the total internal stress of the adjusting layer 16 acts in the opposite direction to the layer 14 including the transistor or the layer 18 containing the transistor.
　ここで、調整層１６は、総内部応力が、トランジスタを含む層１４およびトランジスタを含む層１８の総内部応力と逆方向であればよい。つまり、調整層１６が積層構造を有する場合、調整層１６が有する層すべてが、トランジスタを含む層１４およびトランジスタを含む層１８と逆方向に作用する必要はない。調整層１６を１層としてみなした場合の内部応力が、トランジスタを含む層１４およびトランジスタを含む層１８と逆方向に作用すればよい。従って、調整層１６のトランジスタを含む層と接する膜として、バッファとして機能する膜を含んでいてもよい。当該バッファ膜の内部応力は、トランジスタを含む層１４およびトランジスタを含む層１８と同方向に作用する場合がある。 Here, the adjustment layer 16 may have a total internal stress in the opposite direction to the total internal stress of the layer 14 including the transistor and the layer 18 including the transistor. That is, when the adjusting layer 16 has a laminated structure, it is not necessary for all the layers of the adjusting layer 16 to act in the opposite directions to the layer 14 including the transistor and the layer 18 containing the transistor. The internal stress when the adjusting layer 16 is regarded as one layer may act in the opposite direction to the layer 14 including the transistor and the layer 18 containing the transistor. Therefore, as a film in contact with the layer including the transistor of the adjustment layer 16, a film that functions as a buffer may be included. The internal stress of the buffer film may act in the same direction as the layer 14 containing the transistor and the layer 18 containing the transistor.
　また、調整層１６は、配線層を兼ねることができる。従って、調整層１６は導電体を含む場合がある。具体的には、トランジスタ２００＿１とトランジスタ２００＿２とを電気的に接続する導電体を有していてもよい。また、トランジスタ２００＿１、またはトランジスタ２００＿２と電気的に接続する配線が引き回されていてもよい。 Further, the adjustment layer 16 can also serve as a wiring layer. Therefore, the adjusting layer 16 may include a conductor. Specifically, it may have a conductor that electrically connects the transistor 200_1 and the transistor 200_2. Further, the wiring electrically connected to the transistor 200_1 or the transistor 200_2 may be routed.
　なお、調整層１２は、必要に応じて配置すればよく、必ずしも必須の構成ではない。また、図示しないが、トランジスタを含む層１８上にも、調整層を設けてもよい。 The adjustment layer 12 may be arranged as needed, and is not necessarily an essential configuration. Further, although not shown, an adjustment layer may be provided on the layer 18 including the transistor.
　上記構造を有することで、垂直方向にも回路を展開した立体集積回路（３次元集積回路）において、基板がゆがむことがないため、アライメントマージンを小さくすることができ、設計の自由度を高くすることができる。 By having the above structure, in a three-dimensional integrated circuit (three-dimensional integrated circuit) in which the circuit is expanded in the vertical direction, the substrate is not distorted, so that the alignment margin can be reduced and the degree of freedom in design is increased. be able to.
＜半導体装置の応用例＞
　以下では、図１Ｂを用いて、本発明の一態様に係るトランジスタ２００を有する半導体装置の一例について説明する。 <Application example of semiconductor device>
Hereinafter, an example of a semiconductor device having the transistor 200 according to one aspect of the present invention will be described with reference to FIG. 1B.
　図１Ｂに示すように、本発明の一態様の半導体装置２０は、基板２１と、バリア性を有する絶縁体２３と、トランジスタを含む層２４と、調整層２６と、バリア性を有する絶縁体２７と、トランジスタを含む層２８と、を有し、各層が積層構造を構成している。また、トランジスタを含む層２４には、少なくとも１個以上のトランジスタ２００＿１が設けられ、トランジスタを含む層２８には、少なくとも１個以上のトランジスタ２００＿２が設けられる。 As shown in FIG. 1B, the semiconductor device 20 according to one aspect of the present invention includes a substrate 21, an insulator 23 having a barrier property, a layer 24 including a transistor, an adjusting layer 26, and an insulator 27 having a barrier property. And a layer 28 including a transistor, and each layer constitutes a laminated structure. Further, at least one or more transistors 200_1 are provided on the layer 24 including the transistors, and at least one or more transistors 200_1 are provided on the layer 28 including the transistors.
　トランジスタ２００は、チャネルが形成される領域を含む半導体に、積層が容易な酸化物半導体を用いる。 For the transistor 200, an oxide semiconductor that can be easily laminated is used as the semiconductor including the region where the channel is formed.
　一方、トランジスタ２００が有する酸化物半導体は、水素、水、または金属酸化物などの不純物により電気特性が変動する蓋然性が高くなるため、外部から不純物の侵入を遮断することが好ましい。 On the other hand, the oxide semiconductor of the transistor 200 is more likely to have its electrical characteristics fluctuated due to impurities such as hydrogen, water, and metal oxides, so it is preferable to block the intrusion of impurities from the outside.
　そこで、バリア性を有する絶縁体２３、またはバリア性を有する絶縁体２７を用いて、トランジスタを含む層２４、およびトランジスタを含む層２８を封止することが好ましい。 Therefore, it is preferable to use an insulator 23 having a barrier property or an insulator 27 having a barrier property to seal the layer 24 containing the transistor and the layer 28 containing the transistor.
　なお、本明細書において、不純物を抑制する機能とは、当該不純物のいずれか一またはすべての拡散を抑制する機能とする。また、不純物の拡散を抑制する機能を有する膜を、不純物が透過しにくい膜、不純物の透過性が低い膜、不純物に対してバリア性を有する膜、不純物に対するバリア膜などと呼ぶ場合がある。また、バリア膜に導電性を有する場合、当該バリア膜を導電性バリア膜と呼ぶことがある。 In the present specification, the function of suppressing impurities is a function of suppressing the diffusion of any one or all of the impurities. Further, a membrane having a function of suppressing the diffusion of impurities may be referred to as a membrane in which impurities are difficult to permeate, a membrane having low impurity permeability, a membrane having a barrier property against impurities, a barrier film against impurities, and the like. When the barrier film has conductivity, the barrier film may be referred to as a conductive barrier film.
　バリア性を有する絶縁体２３は、トランジスタを有する層２４の下面、上面、側面に接して設けられる。バリア性を有する絶縁体２３は、バリア性を有する絶縁体を、複数回成膜することにより、形成することができる。 The insulator 23 having a barrier property is provided in contact with the lower surface, the upper surface, and the side surface of the layer 24 having the transistor. The insulator 23 having a barrier property can be formed by forming a film of the insulator having a barrier property a plurality of times.
　例えば、絶縁体２３は、少なくとも３層の膜により成膜することができる。具体的には、第１のバリア性を有する絶縁膜を成膜した後、トランジスタを有する層を形成する。トランジスタを有する層上に第２のバリア性を有する絶縁膜を成膜する。続いて、トランジスタを有する層、および第２のバリア性を有する絶縁膜の一部を除去し、第１のバリア性を有する絶縁膜を露出する。次に、第１のバリア性を有する絶縁膜の露出した面、トランジスタを有する層の側面、および第２のバリア性を有する絶縁膜の上面および側面に接するように、第３のバリア性を有する膜を成膜するとよい。 For example, the insulator 23 can be formed by a film having at least three layers. Specifically, after forming the first insulating film having a barrier property, a layer having a transistor is formed. An insulating film having a second barrier property is formed on the layer having the transistor. Subsequently, the layer having the transistor and a part of the insulating film having the second barrier property are removed to expose the insulating film having the first barrier property. Next, it has a third barrier property so as to be in contact with the exposed surface of the insulating film having the first barrier property, the side surface of the layer having the transistor, and the upper surface and the side surface of the insulating film having the second barrier property. It is advisable to form a film.
　上記構成により、トランジスタ２００＿１を、バリア性を有する絶縁体２３により、封止することが可能である。 With the above configuration, the transistor 200_1 can be sealed by the insulator 23 having a barrier property.
　バリア性を有する絶縁体として、具体的には、酸化アルミニウムなどの金属酸化物や、窒化シリコンなどの窒化物は、酸素の拡散を抑制する機能（以下、バリア性ともいう）を有する場合がある。特に、酸化シリコンと比較した場合、酸化アルミニウム、および窒化シリコンは、酸素、または、水、水素などの不純物の拡散を抑制する機能を有する。 Specifically, as an insulator having a barrier property, a metal oxide such as aluminum oxide or a nitride such as silicon nitride may have a function of suppressing the diffusion of oxygen (hereinafter, also referred to as a barrier property). .. In particular, when compared with silicon oxide, aluminum oxide and silicon nitride have a function of suppressing the diffusion of oxygen or impurities such as water and hydrogen.
　従って、バリア性を有する絶縁体２３、またはバリア性を有する絶縁体２７として、例えば、窒化シリコンを用いることができる。また、他にも、例えば、酸化アルミニウム、酸化ハフニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジムまたは酸化タンタルなどの金属酸化物、窒化酸化シリコンなど窒化物を用いることができる。 Therefore, for example, silicon nitride can be used as the insulator 23 having a barrier property or the insulator 27 having a barrier property. In addition, for example, aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, metal oxides such as neodymium oxide or tantalum oxide, and nitrides such as silicon nitride. Can be used.
　なお、上述したバリア性を有する膜は、一般的に、内部応力が高い傾向がある。 Note that the above-mentioned film having a barrier property generally tends to have a high internal stress.
　従って、バリア性を有する絶縁体２３の総内部応力が、トランジスタを有する層２４の総内部応力と、同方向に作用する場合、調整層２６を設けることで、基板２１の歪みを低減することができる。従って、調整層２６上に設けるバリア性を有する絶縁体２３、およびトランジスタを有する層２８の積層構造を作成する工程において、アライメントマージンを小さくすることができる。 Therefore, when the total internal stress of the insulator 23 having a barrier property acts in the same direction as the total internal stress of the layer 24 having the transistor, the distortion of the substrate 21 can be reduced by providing the adjusting layer 26. it can. Therefore, the alignment margin can be reduced in the step of creating the laminated structure of the insulator 23 having a barrier property provided on the adjusting layer 26 and the layer 28 having the transistor.
　つまり、露光工程において、フォーカスのずれを抑制し、結果、フォーカスボケの発生を低減することができる。また、装置に投入した場合、基板を安定な状態で吸着することができる。さらに、アライメントに対するずれを抑制することができる。 That is, in the exposure process, the shift of focus can be suppressed, and as a result, the occurrence of focus blur can be reduced. Further, when it is put into the apparatus, the substrate can be adsorbed in a stable state. Further, the deviation with respect to the alignment can be suppressed.
　また、垂直方向にも回路を展開した立体集積回路（３次元集積回路）において、基板がゆがむことがないため、設計の自由度を高くすることができる。また、ｎ層以上の積層構造を設けた場合、最上層を設ける場合でも、膜破壊などが生じにくく、歩留まり高く半導体装置を作製することができる。 Further, in a three-dimensional integrated circuit (three-dimensional integrated circuit) in which the circuit is expanded in the vertical direction, the substrate is not distorted, so that the degree of freedom in design can be increased. Further, when a laminated structure having n or more layers is provided, film breakage is unlikely to occur even when the uppermost layer is provided, and a semiconductor device with a high yield can be manufactured.
　以上、本実施の形態に示す構成、方法などは、他の実施の形態や実施例に示す構成、方法などと適宜組み合わせて用いることができる。 As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments and examples.
（実施の形態２）
　本実施の形態では、本発明の一態様に係るトランジスタ２００を有する半導体装置の一例について説明する。本発明の一態様に係るトランジスタを有する半導体装置は、チャネル形成領域に酸化物半導体を有するトランジスタである。 (Embodiment 2)
In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described. A semiconductor device having a transistor according to one aspect of the present invention is a transistor having an oxide semiconductor in a channel forming region.
　ここで、本発明の一態様に係るトランジスタを有する半導体装置の一例について、図面を用いて詳細な説明を以下で行う。 Here, an example of a semiconductor device having a transistor according to one aspect of the present invention will be described in detail below with reference to the drawings.
＜半導体装置の構成例＞
　図２は、本発明の一態様に係るトランジスタ２００を有する半導体装置の上面図および断面図である。図２Ａは、当該半導体装置の上面図である。また、図２Ｂ、および図２Ｃは、当該半導体装置の断面図である。ここで、図２Ｂは、図２ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。また、図２Ｃは、図２ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。また、図２Ｄは、図２ＡにＡ５−Ａ６の一点鎖線で示す部位の断面図である。なお、図２Ａの上面図では、図の明瞭化のために一部の要素を省いている。 <Semiconductor device configuration example>
FIG. 2 is a top view and a cross-sectional view of a semiconductor device having the transistor 200 according to one aspect of the present invention. FIG. 2A is a top view of the semiconductor device. 2B and 2C are cross-sectional views of the semiconductor device. Here, FIG. 2B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 2A. Further, FIG. 2C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 2A. Further, FIG. 2D is a cross-sectional view of the portion shown by the alternate long and short dash line of A5-A6 in FIG. 2A. In the top view of FIG. 2A, some elements are omitted for the purpose of clarifying the figure.
　本発明の一態様の半導体装置は、トランジスタ２００と、層間膜として機能する絶縁体２１４、絶縁体２１６、絶縁体２８０、絶縁体２８２、および絶縁体２８４と、を有する。なお、絶縁体２８０は、少なくとも、酸化物２３０と接して設けられる。 The semiconductor device according to one aspect of the present invention includes a transistor 200 and an insulator 214, an insulator 216, an insulator 280, an insulator 282, and an insulator 284 that function as interlayer films. The insulator 280 is provided in contact with at least the oxide 230.
［トランジスタ２００］
　図２に示すように、トランジスタ２００は、基板（図示せず。）の上に配置され、絶縁体２１６に埋め込まれるように配置された導電体２０５と、絶縁体２１６の上および導電体２０５の上に配置された絶縁体２２２と、絶縁体２２２の上に配置された絶縁体２２４と、絶縁体２２４の上に配置された酸化物２３０（酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃ）と、酸化物２３０の上に配置された絶縁体２５０と、絶縁体２５０上に配置された導電体２６０（導電体２６０ａ、および導電体２６０ｂ）と、酸化物２３０ｂの上面の一部と接する導電体２４０ａおよび導電体２４０ｂと、導電体２４０ａ上の絶縁体２４５ａと、導電体２４０ｂ上の絶縁体２４５ｂと、を有する。 [Transistor 200]
As shown in FIG. 2, the transistor 200 is arranged on a substrate (not shown) and on the conductor 205 arranged so as to be embedded in the insulator 216, and on the insulator 216 and on the conductor 205. An insulator 222 arranged above, an insulator 224 arranged on the insulator 222, and an oxide 230 arranged on the insulator 224 (oxide 230a, oxide 230b, and oxide 230c). And the conductor 250 arranged on the oxide 230, the conductor 260 (conductor 260a and the conductor 260b) arranged on the insulator 250, and the conductivity in contact with a part of the upper surface of the oxide 230b. It has a body 240a and a conductor 240b, an insulator 245a on the conductor 240a, and an insulator 245b on the conductor 240b.
　また、トランジスタ２００は、チャネルが形成される領域（以下、チャネル形成領域ともいう。）を含む酸化物２３０（酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃ）に、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう。）を用いる。 Further, the transistor 200 is a metal that functions as an oxide semiconductor in an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) including a region in which a channel is formed (hereinafter, also referred to as a channel formation region). An oxide (hereinafter, also referred to as an oxide semiconductor) is used.
　なお、チャネル形成領域として機能する酸化物半導体は、バンドギャップが２ｅＶ以上、好ましくは２．５ｅＶ以上のものを用いることが好ましい。このように、バンドギャップの大きい酸化物半導体を用いることで、トランジスタのオフ電流を低減することができる。 The oxide semiconductor that functions as the channel formation region preferably has a bandgap of 2 eV or more, preferably 2.5 eV or more. As described above, by using an oxide semiconductor having a large bandgap, the off-current of the transistor can be reduced.
　なお、酸化物２３０は、化学組成が異なる複数の酸化物層の積層構造を有することが好ましい。具体的には、酸化物２３０ａに用いる金属酸化物において、Ｉｎに対する元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、Ｉｎに対する元素Ｍの原子数比より大きいことが好ましい。 The oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
　また、酸化物２３０ｃは、酸化物２３０ａまたは酸化物２３０ｂに用いることができる金属酸化物を、用いることができる。 Further, as the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
　例えば、酸化物２３０ｂがＩｎ−Ｇａ−Ｚｎ酸化物の場合、酸化物２３０ａおよび酸化物２３０ｃとして、Ｉｎ−Ｇａ−Ｚｎ酸化物、Ｇａ−Ｚｎ酸化物、酸化ガリウムなどを用いてもよい。 For example, when the oxide 230b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 230a and the oxide 230c.
　また、酸化物２３０ｂおよび酸化物２３０ｃは、結晶性を有することが好ましい。例えば、後述するＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）を用いることが好ましい。ＣＡＡＣ−ＯＳなどの結晶性を有する酸化物は、不純物や欠陥（酸素欠損など）が少なく、結晶性の高い、緻密な構造を有している。従って、ソース電極またはドレイン電極による、酸化物２３０ｂからの酸素の引き抜きを抑制することができる。また、熱処理を行っても、酸化物２３０ｂから酸素が引き抜かれることを低減できるため、トランジスタ２００は、製造工程における高い温度（所謂サーマルバジェット）に対して安定する。 Further, the oxide 230b and the oxide 230c are preferably crystalline. For example, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor), which will be described later. Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. Further, even if heat treatment is performed, oxygen can be reduced from being extracted from the oxide 230b, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
　なお、トランジスタ２００では、酸化物２３０が、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃの３層を積層する構成について示しているが、本発明はこれに限られるものではない。例えば、酸化物２３０ｂの単層、酸化物２３０ａと酸化物２３０ｂの２層構造、酸化物２３０ｂと酸化物２３０ｃの２層構造、または４層以上の積層構造を設ける構成にしてもよいし、酸化物２３０ａ、酸化物２３０ｂ、酸化物２３０ｃのそれぞれが積層構造を有していてもよい。 Although the transistor 200 shows a configuration in which the oxide 230 is laminated with three layers of the oxide 230a, the oxide 230b, and the oxide 230c, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, or a laminated structure of four or more layers may be provided, or oxidation may be provided. Each of the object 230a, the oxide 230b, and the oxide 230c may have a laminated structure.
　また、図２Ｄに示すように、少なくとも酸化物２３０ｂの側面、および導電体２４０（導電体２４０ａ、導電体２４０ｂ）の側面は、絶縁体２２４と酸化物２３０ａとが接する面に対し、概略垂直であることが好ましい。具体的には、図２Ｄにおいて、酸化物２３０ｂの側面および導電体２４０の側面は、絶縁体２２４と酸化物２３０ａとが接する面に対し、６０度以上９５度以下、好ましくは、８８度以上９２度以下とするとよい。 Further, as shown in FIG. 2D, at least the side surface of the oxide 230b and the side surface of the conductor 240 (conductor 240a, conductor 240b) are substantially perpendicular to the surface where the insulator 224 and the oxide 230a are in contact with each other. It is preferable to have. Specifically, in FIG. 2D, the side surface of the oxide 230b and the side surface of the conductor 240 are 60 degrees or more and 95 degrees or less, preferably 88 degrees or more and 92 degrees with respect to the surface where the insulator 224 and the oxide 230a are in contact with each other. It should be less than or equal to the degree.
　また、図２Ｃに示すように、チャネル形成領域における酸化物２３０の上端部は、曲率を有する形状とすることが好ましい。つまり、チャネル形成領域において、酸化物２３０の上面と側面とは、角部を形成することなく、曲面によりなだらかに繋がる形状とするとよい。チャネル形成領域に、角部を有さないため、第１のゲート電極として機能する導電体２６０、または第２のゲート電極として機能する導電体２０５いずれか一方または双方の電界による電界集中が生じず、酸化物２３０の劣化を抑制することができる。 Further, as shown in FIG. 2C, it is preferable that the upper end portion of the oxide 230 in the channel forming region has a shape having a curvature. That is, in the channel forming region, the upper surface and the side surface of the oxide 230 may have a shape that is gently connected by a curved surface without forming a corner portion. Since there are no corners in the channel formation region, electric field concentration due to the electric field of either one or both of the conductor 260 that functions as the first gate electrode and the conductor 205 that functions as the second gate electrode does not occur. , Deterioration of the oxide 230 can be suppressed.
　一方、図２Ｄに示すように、導電体２４０と重畳する領域の酸化物２３０の上端部は、チャネル形成領域における酸化物２３０の上端部よりも、曲率が小さい形状とすることが好ましい。上記構造は、酸化物２３０ｂと、導電体２４０とを、同じマスクを用いて加工することで形成することができる。従って、酸化物２３０ｂの投影面積内に導電体２４０が重畳するため、微細なトランジスタを作成することができる。 On the other hand, as shown in FIG. 2D, it is preferable that the upper end portion of the oxide 230 in the region overlapping with the conductor 240 has a shape having a smaller curvature than the upper end portion of the oxide 230 in the channel forming region. The above structure can be formed by processing the oxide 230b and the conductor 240 using the same mask. Therefore, since the conductor 240 is superimposed on the projected area of the oxide 230b, a fine transistor can be produced.
　導電体２６０は、第１のゲート（トップゲートともいう。）電極として機能する。 The conductor 260 functions as a first gate (also referred to as a top gate) electrode.
　ここで、トランジスタ２００は、導電体２６０を、絶縁体２８０などに形成されている開口に埋めることで設ける。また、当該開口を設ける工程において、絶縁体２８０に設ける開口の底部に、導電体２４０となる導電層の一部が露出する。導電体２４０となる導電層において、絶縁体２８０に設けた開口の底部と重畳する領域を除去することで、導電体２４０ａ、および導電体２４０ｂが形成される。 Here, the transistor 200 is provided by burying the conductor 260 in an opening formed in an insulator 280 or the like. Further, in the step of providing the opening, a part of the conductive layer to be the conductor 240 is exposed at the bottom of the opening provided in the insulator 280. In the conductive layer to be the conductor 240, the conductor 240a and the conductor 240b are formed by removing the region overlapping with the bottom of the opening provided in the insulator 280.
　従って、導電体２４０ａの端部と、導電体２４０ｂの端部は、開口部の側面と同一面上となる。導電体２６０を、絶縁体２８０に設けた開口に、絶縁体２５０などを介して埋め込むことで、導電体２４０ａと導電体２４０ｂとの間の領域に、導電体２６０を位置合わせすることなく自己整合的に配置することができる。 Therefore, the end portion of the conductor 240a and the end portion of the conductor 240b are on the same surface as the side surface of the opening. By embedding the conductor 260 in the opening provided in the insulator 280 via the insulator 250 or the like, the conductor 260 is self-aligned in the region between the conductor 240a and the conductor 240b without aligning the conductor 260. Can be arranged as a target.
　また、図２Ｂ、または図２Ｃに示すように、導電体２６０の上面は、絶縁体２５０の上面および酸化物２３０ｃの上面と略一致している。 Further, as shown in FIG. 2B or FIG. 2C, the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250 and the upper surface of the oxide 230c.
　また、図２Ｃに示すように、導電体２６０と酸化物２３０とが重畳しない領域において、導電体２６０と絶縁体２５０とが接する面と絶縁体２２２の上面に対する最短距離は、酸化物２３０ｂと酸化物２３０ａとが接する面と絶縁体２２２の上面に対する最短距離よりも、短いことが好ましい。つまり、トランジスタ２００のチャネル幅方向において、酸化物２３０ｂの側面が、少なくとも絶縁体２５０を介して、導電体２６０により、覆われている構造を有する。 Further, as shown in FIG. 2C, in the region where the conductor 260 and the oxide 230 do not overlap, the shortest distance between the surface where the conductor 260 and the insulator 250 contact and the upper surface of the insulator 222 is the oxide 230b and the oxide. It is preferably shorter than the shortest distance between the surface in contact with the object 230a and the upper surface of the insulator 222. That is, in the channel width direction of the transistor 200, the side surface of the oxide 230b is covered with the conductor 260 at least via the insulator 250.
　ゲート電極として機能する導電体２６０が、絶縁体２５０などを介して、酸化物２３０ｂのチャネル形成領域の側面および上面を覆う構成とすることで、導電体２６０の電界が酸化物２３０ｂのチャネル形成領域全体に作用する。従って、トランジスタ２００のオン電流を増大させ、周波数特性を向上させることができる。 The conductor 260 that functions as a gate electrode covers the side surface and the upper surface of the channel forming region of the oxide 230b via an insulator 250 or the like, so that the electric field of the conductor 260 covers the channel forming region of the oxide 230b. It acts on the whole. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.
　なお、導電体２６０は、導電体２６０ａと、導電体２６０ａの上に配置された導電体２６０ｂと、を有することが好ましい。例えば、導電体２６０ａは、導電体２６０ｂの底面および側面を包むように配置されることが好ましい。 The conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 260b.
　導電体２６０ａは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子、銅原子などの不純物の拡散を抑制する機能を有する導電性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する導電性材料を用いることが好ましい。 As the conductor 260a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
　また、導電体２６０ａが酸素の拡散を抑制する機能を持つことにより、絶縁体２５０に含まれる酸素により、導電体２６０ｂが酸化して導電率が低下することを抑制することができる。酸素の拡散を抑制する機能を有する導電性材料としては、例えば、タンタル、窒化タンタル、ルテニウム、酸化ルテニウムなどを用いることが好ましい。 Further, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
　また、導電体２６０は、配線としても機能するため、導電性が高い導電体を用いることが好ましい。例えば、導電体２６０ｂは、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることができる。また、導電体２６０ｂは積層構造としてもよく、例えば、チタン、または窒化チタンと上記導電性材料との積層構造としてもよい。 Further, since the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity. For example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 260b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
　図２では、導電体２６０は、導電体２６０ａと導電体２６０ｂの２層構造として示しているが、単層構造でもよいし、３層以上の積層構造であってもよい。 In FIG. 2, the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b, but it may be a single-layer structure or a laminated structure of three or more layers.
　導電体２０５は、第２のゲート（ボトムゲートともいう。）電極として機能する。 The conductor 205 functions as a second gate (also referred to as a bottom gate) electrode.
　また、導電体２０５がゲート電極として機能する場合、導電体２０５に印加する電位を、導電体２６０に印加する電位と、連動させず、独立して変化させることで、トランジスタ２００のしきい値電圧（Ｖｔｈ）を制御することができる。特に、導電体２０５に負の電位を印加することにより、トランジスタ２００のＶｔｈをより大きくし、オフ電流を低減することが可能となる。したがって、導電体２０５に負の電位を印加したほうが、印加しない場合よりも、導電体２６０に印加する電位が０Ｖのときのドレイン電流を小さくすることができる。 Further, when the conductor 205 functions as a gate electrode, the threshold voltage of the transistor 200 is changed by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260. (Vth) can be controlled. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when it is not applied.
　導電体２０５は、酸化物２３０、および導電体２６０と、重なるように配置する。また、導電体２０５は、絶縁体２１４または絶縁体２１６に埋め込まれて設けることが好ましい。 The conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Further, the conductor 205 is preferably provided by being embedded in the insulator 214 or the insulator 216.
　なお、チャネル幅方向において、導電体２０５は、酸化物２３０におけるチャネル形成領域よりも、大きく設けるとよい。特に、図２Ｃに示すように、導電体２０５は、酸化物２３０のチャネル幅方向と交差して、延伸していることが好ましい。 It is preferable that the conductor 205 is provided larger than the channel forming region in the oxide 230 in the channel width direction. In particular, as shown in FIG. 2C, it is preferable that the conductor 205 is stretched so as to intersect the channel width direction of the oxide 230.
　ここで、酸化物２３０のチャネル幅方向における側面の外側において、導電体２０５と、導電体２６０とは、絶縁体を介して重畳していることが好ましい。当該構成を有することで、第１のゲート電極として機能する導電体２６０の電界と、第２のゲート電極として機能する導電体２０５の電界によって、酸化物２３０のチャネル形成領域を電気的に取り囲むことができる。 Here, it is preferable that the conductor 205 and the conductor 260 are superimposed via an insulator on the outside of the side surface of the oxide 230 in the channel width direction. By having this configuration, the channel forming region of the oxide 230 is electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. Can be done.
　また、図２では、導電体２０５を第１の導電体と第２の導電体とを積層する構成として示しているが、本発明はこれに限られるものではない。例えば、導電体２０５は、単層、または３層以上の積層構造として設ける構成にしてもよい。構造体が積層構造を有する場合、形成順に序数を付与し、区別する場合がある。 Further, in FIG. 2, the conductor 205 is shown as a configuration in which the first conductor and the second conductor are laminated, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
　ここで、導電体２０５の第１の導電体は、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する導電性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する導電性材料を用いることが好ましい。 Here, first conductor of the conductor 205 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), impurities such as copper atoms It is preferable to use a conductive material having a function of suppressing diffusion. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
　導電体２０５の第１の導電体に、酸素の拡散を抑制する機能を有する導電性材料を用いることにより、導電体２０５の第２の導電体が酸化して導電率が低下することを抑制することができる。酸素の拡散を抑制する機能を有する導電性材料としては、例えば、タンタル、窒化タンタル、ルテニウム、酸化ルテニウムなどを用いることが好ましい。したがって、導電体２０５の第１の導電体としては、上記導電性材料を単層または積層とすればよい。例えば、導電体２０５の第１の導電体は、タンタル、窒化タンタル、ルテニウム、または酸化ルテニウムと、チタンまたは窒化チタンとの積層としてもよい。 By using a conductive material having a function of suppressing the diffusion of oxygen as the first conductor of the conductor 205, it is possible to prevent the second conductor of the conductor 205 from being oxidized and the conductivity from being lowered. be able to. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the first conductor of the conductor 205, the conductive material may be a single layer or a laminated material. For example, the first conductor of the conductor 205 may be a laminate of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.
　また、導電体２０５の第２の導電体は、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。なお、導電体２０５の第２の導電体を単層で図示したが、積層構造としてもよく、例えば、チタンまたは窒化チタンと、当該導電性材料との積層としてもよい。 Further, as the second conductor of the conductor 205, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Although the second conductor of the conductor 205 is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
　また、図２Ｃに示すように、導電体２０５は延伸させて、配線としても機能させている。ただし、これに限られることなく、導電体２０５の下に、配線として機能する導電体を設ける構成にしてもよい。また、導電体２０５は、必ずしも各トランジスタに一個ずつ設ける必要はない。例えば、導電体２０５を複数のトランジスタで共有する構成にしてもよい。 Further, as shown in FIG. 2C, the conductor 205 is stretched to function as wiring. However, the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 205. Further, it is not always necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.
　導電体２４０（導電体２４０ａ、および導電体２４０ｂ）は、ソース電極またはドレイン電極として機能する。 The conductor 240 (conductor 240a and conductor 240b) functions as a source electrode or a drain electrode.
　導電体２４０としては、例えば、ＴａＮｘＯｙを用いることが好ましい。なお、ＴａＮｘＯｙはアルミニウムを含んでもよい。また、例えば、窒化チタン、チタンとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いてもよい。これらの材料は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。 The conductor 240, for example, it is preferable to use a TaN x O y. Incidentally, TaN x O y may comprise aluminum. Further, for example, titanium nitride, a nitride containing titanium and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
　また、導電体２４０上に、バリア層として機能する絶縁体２４５を設けるとよい。 Further, it is preferable to provide an insulator 245 that functions as a barrier layer on the conductor 240.
　絶縁体２４５は、図２Ｂに示すように、導電体２４０の上面に接することが好ましい。当該構成にすることで、導電体２４０による、絶縁体２８０が有する過剰酸素の吸収を抑制することができる。また、導電体２４０の酸化を抑制することで、トランジスタ２００と配線とのコンタクト抵抗の増加を抑制することができる。よって、トランジスタ２００に良好な電気特性および信頼性を与えることができる。 As shown in FIG. 2B, the insulator 245 is preferably in contact with the upper surface of the conductor 240. With this configuration, it is possible to suppress the absorption of excess oxygen contained in the insulator 280 by the conductor 240. Further, by suppressing the oxidation of the conductor 240, it is possible to suppress an increase in the contact resistance between the transistor 200 and the wiring. Therefore, good electrical characteristics and reliability can be given to the transistor 200.
　従って、絶縁体２４５は、酸素の拡散を抑制する機能を有することが好ましい。例えば、絶縁体２４５は、絶縁体２８０よりも酸素の拡散を抑制する機能を有することが好ましい。 Therefore, it is preferable that the insulator 245 has a function of suppressing the diffusion of oxygen. For example, the insulator 245 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.
　絶縁体２４５としては、例えば、アルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体を成膜するとよい。また、絶縁体２４５としては、例えば、窒化アルミニウムを含む絶縁体を用いればよい。 As the insulator 245, for example, it is preferable to form an insulator containing oxides of one or both of aluminum and hafnium. Further, as the insulator 245, for example, an insulator containing aluminum nitride may be used.
　絶縁体２５０は、第１のゲート絶縁体として機能する。 The insulator 250 functions as a first gate insulator.
　絶縁体２５０は、酸化物２３０ｃに接して配置することが好ましい。絶縁体２５０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコンなどを用いることができる。特に、酸化シリコン、および酸化窒化シリコンは熱に対し安定であるため好ましい。 The insulator 250 is preferably arranged in contact with the oxide 230c. The insulator 250 includes silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and the like. Can be used. In particular, silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
　なお、絶縁体２５０を成膜した後に、酸素を含む雰囲気下にて、マイクロ波励起プラズマ処理を行ってもよい。マイクロ波励起プラズマ処理を行うことにより、絶縁体２５０中の、水素、水、または不純物を除去することができる。さらに、マイクロ波励起プラズマ処理を行うことにより、絶縁体２５０の膜質を改質することで、水素、水、または不純物等の拡散を抑制することができる。従って、導電体２６０となる導電膜の成膜などの後工程、または熱処理などの後処理により、絶縁体２５０を介して、水素、水、または不純物が、酸化物２３０へ拡散することを抑制することができる。 After forming the insulator 250, microwave excitation plasma treatment may be performed in an atmosphere containing oxygen. Hydrogen, water, or impurities in the insulator 250 can be removed by performing the microwave excitation plasma treatment. Further, by modifying the film quality of the insulator 250 by performing the microwave excitation plasma treatment, it is possible to suppress the diffusion of hydrogen, water, impurities and the like. Therefore, it is possible to prevent hydrogen, water, or impurities from diffusing into the oxide 230 through the insulator 250 by a post-process such as film formation of a conductive film to be a conductor 260 or a post-treatment such as heat treatment. be able to.
　例えば、固体の酸化シリコンにおける水素原子とシリコン原子の結合エネルギーは３．３ｅＶ、炭素原子とシリコン原子の結合エネルギーは３．４ｅＶ、窒素原子とシリコン原子の結合エネルギーは３．５ｅＶ、である。従って、シリコン原子と結合した水素原子を取り除くには、少なくとも、３．３ｅＶ以上のエネルギーを持つラジカル、またはイオンを、水素原子とシリコン原子との結合部に衝突させることで、水素原子と、シリコン原子との結合を切断することができる。 For example, the bond energy between a hydrogen atom and a silicon atom in solid silicon oxide is 3.3 eV, the bond energy between a carbon atom and a silicon atom is 3.4 eV, and the bond energy between a nitrogen atom and a silicon atom is 3.5 eV. Therefore, in order to remove the hydrogen atom bonded to the silicon atom, a radical or ion having an energy of at least 3.3 eV or more is made to collide with the bond portion between the hydrogen atom and the silicon atom, so that the hydrogen atom and silicon are removed. It can break the bond with an atom.
　なお、窒素、および炭素などの他の不純物についても、同様に、少なくとも、結合エネルギー以上のエネルギーを持つラジカル、またはイオンを、不純物原子とシリコン原子との結合部に衝突させることで、不純物原子とシリコン原子との結合を切断することができる。 Similarly, for other impurities such as nitrogen and carbon, radicals or ions having at least an energy equal to or higher than the binding energy are made to collide with the bond portion between the impurity atom and the silicon atom to form the impurity atom. It can break the bond with the silicon atom.
　ここで、マイクロ波で励起したプラズマにより発生するラジカル、およびイオンとして、酸素原子ラジカルの基底状態Ｏ（３Ｐ）、酸素原子ラジカルの第一励起状態Ｏ（１Ｄ）、および酸素分子の一価のカチオンＯ２ ＋等がある。Ｏ（３Ｐ）のエネルギーは、２．４２ｅＶ、Ｏ（１Ｄ）のエネルギーは、４．６ｅＶ、である。また、Ｏ２ ＋は電荷をもつために、プラズマ中の電位分布、およびバイアスにより加速されるため、エネルギーは一意に定まらないが、少なくとも、内部エネルギーのみでも、Ｏ（１Ｄ）より高いエネルギーを持つ。 Here, as radicals and ions generated by plasma excited by microwaves, the ground state O ( 3 P) of the oxygen atomic radical, the first excited state O ( 1 D) of the oxygen atomic radical, and the monovalent oxygen molecule. there is a cationic O 2 + and the like. The energy of O ( 3 P) is 2.42 eV, and the energy of O (1 D) is 4.6 eV. Also, O 2 + is to have a charge, potential distribution in the plasma, and to be accelerated by the bias, but the energy is not uniquely determined, at least, even only within the energy, a higher energy than the O (1 D) Have.
　つまり、Ｏ（１Ｄ）、およびＯ２ ＋等のラジカル、およびイオンは、絶縁体２５０中の水素、窒素、および炭素原子と、シリコン原子との結合を切断し、シリコン原子と結合した水素、窒素、および炭素を除去することができる。また、マイクロ波励起プラズマ処理を行う際に、基板に加わる熱エネルギー等によっても、水素、窒素、および炭素などの不純物を低減することができる。 That, O (1 D), and O 2 + etc. radicals, and ions, hydrogen hydrogen in the insulator 250, and nitrogen, and carbon atoms, to cut the bond of silicon atoms bound to silicon atoms, Nitrogen and carbon can be removed. In addition, impurities such as hydrogen, nitrogen, and carbon can be reduced by the thermal energy applied to the substrate when the microwave excitation plasma treatment is performed.
　一方、Ｏ（３Ｐ）は、反応性が低いため、絶縁体２５０では反応せず、膜中深くまで拡散する。または、Ｏ（３Ｐ）は絶縁体２５０を介して、酸化物２３０へと到達し、酸化物２３０中に拡散する。酸化物２３０中に拡散したＯ（３Ｐ）が、水素が入った酸素欠損に近接すると、酸素欠損中の水素は酸素欠損から放出され、代わりにＯ（３Ｐ）が酸素欠損に入ることで、酸素欠損は補償される。従って、酸化物２３０中で、キャリアである電子の生成を抑制することができる。 On the other hand, since O ( 3 P) has low reactivity, it does not react with the insulator 250 and diffuses deep into the membrane. Alternatively, O ( 3 P) reaches the oxide 230 via the insulator 250 and diffuses into the oxide 230. When the O (3 P) diffused in the oxide 230 approaches the oxygen deficiency containing hydrogen, the hydrogen in the oxygen deficiency is released from the oxygen deficiency, and instead O ( 3 P) enters the oxygen deficiency. , Oxygen deficiency is compensated. Therefore, it is possible to suppress the generation of electrons as carriers in the oxide 230.
　なお、全体のラジカル、およびイオン種に対するＯ（３Ｐ）の割合は、マイクロ波励起プラズマ処理を、圧力が高い条件で行うことにより、増加する。酸化物２３０中の酸素欠損を補償するためには、Ｏ（３Ｐ）の割合が多い方が好ましい。従って、マイクロ波励起プラズマ処理は、圧力を１３３Ｐａ以上、好ましくは２００Ｐａ以上、さらに好ましくは４００Ｐａ以上とすればよい。また、酸素流量比（Ｏ２／Ｏ２＋Ａｒ）が５０％以下、好ましくは１０％以上３０％以下で行うとよい。 The ratio of O (3 P) to the total radicals and ionic species is increased by performing microwave excitation plasma treatment under high pressure conditions. In order to compensate for the oxygen deficiency in the oxide 230, it is preferable that the proportion of O (3 P) is large. Therefore, in the microwave excitation plasma treatment, the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. Further, the oxygen flow rate ratio (O 2 / O 2 + Ar) is 50% or less, preferably 10% or more and 30% or less.
　また、絶縁体２５０は、加熱により一部の酸素が脱離する酸化物材料を用いることが好ましい。加熱により酸素を脱離する酸化物とは、ＴＤＳ（Ｔｈｅｒｍａｌ　Ｄｅｓｏｒｐｔｉｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）分析にて、酸素分子の脱離量が１．０×１０１８ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上、好ましくは１．０×１０１９ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上、さらに好ましくは２．０×１０１９ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上、または３．０×１０２０ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上である酸化膜である。なお、上記ＴＤＳ分析時における膜の表面温度としては１００℃以上７００℃以下、または１００℃以上４００℃以下の範囲が好ましい。 Further, it is preferable to use an oxide material for the insulator 250, in which a part of oxygen is desorbed by heating. Oxides that desorb oxygen by heating are those in which the amount of desorbed oxygen molecules is 1.0 × 10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules, as determined by TDS (Thermal Desortion Spectropy) analysis. An oxide film of / cm 3 or more, more preferably 2.0 × 10 19 molecules / cm 3 or more, or 3.0 × 10 20 molecules / cm 3 or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
　加熱により酸素が放出される絶縁体を、絶縁体２５０として、酸化物２３０ｃの上面に接して設けることにより、酸化物２３０ｂのチャネル形成領域に効果的に酸素を供給し、酸化物２３０ｂのチャネル形成領域の酸素欠損を低減することができる。したがって、電気特性の変動を抑制し、安定した電気特性を有するとともに、信頼性を向上させたトランジスタを提供することができる。また、絶縁体２５０中の水、水素などの不純物濃度は、低減されていることが好ましい。 By providing an insulator that releases oxygen by heating as an insulator 250 in contact with the upper surface of the oxide 230c, oxygen is effectively supplied to the channel forming region of the oxide 230b, and the channel of the oxide 230b is formed. Oxygen deficiency in the region can be reduced. Therefore, it is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced.
　また、絶縁体２５０と導電体２６０との間に金属酸化物を設けてもよい。当該金属酸化物は、絶縁体２５０から導電体２６０への酸素の拡散を抑制することが好ましい。酸素の拡散を抑制する金属酸化物を設けることで、絶縁体２５０から導電体２６０への酸素の拡散が抑制される。つまり、酸化物２３０へ供給する酸素量の減少を抑制することができる。また、絶縁体２５０の酸素による導電体２６０の酸化を抑制することができる。 Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing the metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. In addition, the oxidation of the conductor 260 by oxygen of the insulator 250 can be suppressed.
　なお、上記金属酸化物は、ゲート絶縁体の一部としての機能を有する場合がある。したがって、絶縁体２５０に酸化シリコンや酸化窒化シリコンなどを用いる場合、上記金属酸化物は、比誘電率が高いｈｉｇｈ−ｋ材料である金属酸化物を用いることが好ましい。ゲート絶縁体を、絶縁体２５０と上記金属酸化物との積層構造とすることで、熱に対して安定、かつ比誘電率の高い積層構造とすることができる。したがって、ゲート絶縁体の物理膜厚を保持したまま、トランジスタ動作時に印加するゲート電位の低減化が可能となる。また、ゲート絶縁体として機能する絶縁体の等価酸化膜厚（ＥＯＴ）の薄膜化が可能となる。 The metal oxide may have a function as a part of a gate insulator. Therefore, when silicon oxide, silicon oxide nitride, or the like is used for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, the equivalent oxide film thickness (EOT) of an insulator that functions as a gate insulator can be thinned.
　具体的には、ハフニウム、アルミニウム、ガリウム、イットリウム、ジルコニウム、タングステン、チタン、タンタル、ニッケル、ゲルマニウム、マグネシウムなどから選ばれた一種、または二種以上が含まれた金属酸化物を用いることができる。特に、アルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体を用いることが好ましい。 Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.
　また、上記金属酸化物は、第１のゲート電極の一部としての機能を有してもよい。例えば、酸化物２３０として用いることができる酸化物半導体を、上記金属酸化物として用いることができる。その場合、導電体２６０をスパッタリング法で成膜することで、上記金属酸化物の電気抵抗値を低下させて導電体とすることができる。 Further, the metal oxide may have a function as a part of the first gate electrode. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260 into a film by a sputtering method, the electric resistance value of the metal oxide can be lowered to form a conductor.
　上記金属酸化物を有することで、導電体２６０からの電界の影響を弱めることなく、トランジスタ２００のオン電流の向上を図ることができる。また、絶縁体２５０と、上記金属酸化物との物理的な厚みにより、導電体２６０と、酸化物２３０との間の距離を保つことで、導電体２６０と酸化物２３０との間のリーク電流を抑制することができる。また、絶縁体２５０、および上記金属酸化物との積層構造を設けることで、導電体２６０と酸化物２３０との間の物理的な距離、および導電体２６０から酸化物２３０へかかる電界強度を、容易に適宜調整することができる。 By having the above metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Further, by keeping the distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, the leakage current between the conductor 260 and the oxide 230 is maintained. Can be suppressed. Further, by providing the insulator 250 and the laminated structure with the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be determined. It can be easily adjusted as appropriate.
　絶縁体２２２、および絶縁体２２４は、第２のゲート絶縁体として機能する。 The insulator 222 and the insulator 224 function as a second gate insulator.
　絶縁体２２２は、水素（例えば、水素原子、水素分子などの少なくとも一）の拡散を抑制する機能を有することが好ましい。また、絶縁体２２２は、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有することが好ましい。例えば、絶縁体２２２は、絶縁体２２４よりも水素および酸素の一方または双方の拡散を抑制する機能を有することが好ましい。 The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.
　絶縁体２２２は、絶縁性材料であるアルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体を用いるとよい。当該絶縁体として、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。このような材料を用いて絶縁体２２２を形成した場合、絶縁体２２２は、酸化物２３０から基板側への酸素の放出や、トランジスタ２００の周辺部から酸化物２３０への水素等の不純物の拡散を抑制する層として機能する。よって、絶縁体２２２を設けることで、水素等の不純物が、トランジスタ２００の内側へ拡散することを抑制し、酸化物２３０中の酸素欠損の生成を抑制することができる。また、導電体２０５が、絶縁体２２４や、酸化物２３０が有する酸素と反応することを抑制することができる。 As the insulator 222, it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator 222 is formed by using such a material, the insulator 222 releases oxygen from the oxide 230 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Functions as a layer that suppresses. Therefore, by providing the insulator 222, impurities such as hydrogen can be suppressed from diffusing into the inside of the transistor 200, and the generation of oxygen deficiency in the oxide 230 can be suppressed. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.
　または、上記絶縁体に、例えば、酸化アルミニウム、酸化ビスマス、酸化ゲルマニウム、酸化ニオブ、酸化シリコン、酸化チタン、酸化タングステン、酸化イットリウム、酸化ジルコニウムを添加してもよい。または、これらの絶縁体を窒化処理してもよい。また、絶縁体２２２は、これらの絶縁体に酸化シリコン、酸化窒化シリコンまたは窒化シリコンを積層して用いてもよい。 Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Further, the insulator 222 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
　また、絶縁体２２２は、例えば、酸化アルミニウム、酸化ハフニウム、酸化タンタル、酸化ジルコニウム、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）、（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などのいわゆるｈｉｇｈ−ｋ材料を含む絶縁体を単層または積層で用いてもよい。トランジスタの微細化、および高集積化が進むと、ゲート絶縁体の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁体として機能する絶縁体にｈｉｇｈ−ｋ材料を用いることで、物理膜厚を保ちながら、トランジスタ動作時のゲート電位の低減が可能となる。 Further, the insulator 222 includes, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba, Sr) TiO 3 (BST) and the like. Insulators containing so-called high-k materials may be used in single layers or in layers. As transistors become finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
　酸化物２３０と接する絶縁体２２４は、絶縁体２５０と同様に、加熱により酸素を脱離することが好ましい。例えば、絶縁体２２４は、酸化シリコン、酸化窒化シリコンなどを適宜用いればよい。酸素を含む絶縁体を酸化物２３０に接して設けることにより、酸化物２３０中の酸素欠損を低減し、トランジスタ２００の信頼性を向上させることができる。 Like the insulator 250, the insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating. For example, as the insulator 224, silicon oxide, silicon oxide nitride, or the like may be appropriately used. By providing an insulator containing oxygen in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.
　なお、絶縁体２２２、および絶縁体２２４が、２層以上の積層構造を有していてもよい。その場合、同じ材料からなる積層構造に限定されず、異なる材料からなる積層構造でもよい。 Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
　絶縁体２１４、絶縁体２１６、絶縁体２８０、絶縁体２８２、絶縁体２８４は層間膜として機能する。 The insulator 214, the insulator 216, the insulator 280, the insulator 282, and the insulator 284 function as an interlayer film.
　絶縁体２１４は、水、水素などの不純物が、基板側からトランジスタ２００に拡散するのを抑制する絶縁性バリア膜として機能することが好ましい。したがって、絶縁体２１４は、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する絶縁性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する絶縁性材料を用いることが好ましい。 The insulator 214 preferably functions as an insulating barrier film that prevents impurities such as water and hydrogen from diffusing from the substrate side into the transistor 200. Thus, the insulator 214 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), has a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use an insulating material. Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
　例えば、絶縁体２１４として、酸化アルミニウム、窒化シリコンなどを用いることが好ましい。これにより、水、水素などの不純物が、絶縁体２１４よりも基板側からトランジスタ２００側に拡散するのを抑制することができる。または、絶縁体２２４などに含まれる酸素が、絶縁体２１４よりも基板側に、拡散するのを抑制することができる。なお、絶縁体２１４は、２層以上の積層構造を有していてもよい。その場合、同じ材料からなる積層構造に限定されず、異なる材料からなる積層構造でもよい。例えば、酸化アルミニウムと窒化シリコンとの積層としてもよい。 For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This makes it possible to prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side of the insulator 214. Alternatively, it is possible to prevent oxygen contained in the insulator 224 or the like from diffusing toward the substrate side of the insulator 214. The insulator 214 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials. For example, it may be a laminate of aluminum oxide and silicon nitride.
　また、例えば、絶縁体２１４として、スパッタリング法を用いて成膜した、窒化シリコンを用いることが好ましい。これにより、絶縁体２１４中の水素濃度を低くことができ、水、水素などの不純物が、絶縁体２１４よりも基板側からトランジスタ２００側に拡散するのをより抑制することができる。 Further, for example, it is preferable to use silicon nitride formed by a sputtering method as the insulator 214. As a result, the hydrogen concentration in the insulator 214 can be lowered, and impurities such as water and hydrogen can be further suppressed from diffusing from the substrate side to the transistor 200 side as compared with the insulator 214.
　層間膜として機能する絶縁体２１６は、絶縁体２１４よりも誘電率が低いことが好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。例えば、絶縁体２１６として、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコンなどを適宜用いればよい。 The insulator 216 that functions as an interlayer film preferably has a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 216, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores. Etc. may be used as appropriate.
　また、絶縁体２１６は、水素濃度が低く、化学量論的組成よりも酸素が過剰に存在する領域（以下、過剰酸素領域ともいう。）または加熱により離脱する酸素（以下、過剰酸素ともいう。）を有することが好ましい。例えば、絶縁体２１６として、スパッタリング法を用いて成膜した酸化シリコンを用いることが好ましい。これにより、酸化物２３０への水素の混入を抑制することができる、または、酸化物２３０に酸素を供給し、酸化物２３０中の酸素欠損を低減することができる。したがって、電気特性の変動を抑制し、安定した電気特性を有するとともに、信頼性を向上させたトランジスタを提供することができる。 Further, the insulator 216 has a low hydrogen concentration and a region in which oxygen is excessively present in excess of the stoichiometric composition (hereinafter, also referred to as an excess oxygen region) or oxygen released by heating (hereinafter, also referred to as excess oxygen). ) Is preferable. For example, it is preferable to use silicon oxide formed by a sputtering method as the insulator 216. Thereby, it is possible to suppress the mixing of hydrogen into the oxide 230, or to supply oxygen to the oxide 230 and reduce the oxygen deficiency in the oxide 230. Therefore, it is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.
　なお、絶縁体２１６を積層構造にしてもよい。例えば、絶縁体２１６において、少なくとも導電体２０５の側面と接する部分に、絶縁体２１４と同様の絶縁体を設ける構成にしてもよい。このような構成にすることで、絶縁体２１６に含まれる酸素によって、導電体２０５が酸化するのを抑制することができる。または、導電体２０５により、絶縁体２１６に含まれる酸素量が減少するのを抑制することができる。 The insulator 216 may have a laminated structure. For example, in the insulator 216, an insulator similar to the insulator 214 may be provided at least in a portion in contact with the side surface of the conductor 205. With such a configuration, it is possible to suppress the oxidation of the conductor 205 by the oxygen contained in the insulator 216. Alternatively, the conductor 205 can suppress a decrease in the amount of oxygen contained in the insulator 216.
　絶縁体２８０は、絶縁体２２４、酸化物２３０、および導電体２４０上に設けられる。また、絶縁体２８０の上面は、平坦化されていてもよい。 The insulator 280 is provided on the insulator 224, the oxide 230, and the conductor 240. Further, the upper surface of the insulator 280 may be flattened.
　層間膜として機能する絶縁体２８０は、誘電率が低いことが好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。絶縁体２８０は、例えば、絶縁体２１６と同様の材料を用いて設けることが好ましい。特に、酸化シリコンおよび酸化窒化シリコンは、熱的に安定であるため好ましい。特に、酸化シリコン、酸化窒化シリコン、空孔を有する酸化シリコンなどの材料は、加熱により脱離する酸素を含む領域を容易に形成することができるため好ましい。 The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. It is preferable that the insulator 280 is provided, for example, by using the same material as the insulator 216. In particular, silicon oxide and silicon oxide nitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxide nitride, and silicon oxide having pores are preferable because a region containing oxygen desorbed by heating can be easily formed.
　絶縁体２８０中の水、水素などの不純物濃度は低減されていることが好ましい。また、絶縁体２８０は、水素濃度が低く、過剰酸素領域または過剰酸素を有することが好ましく、例えば、絶縁体２１６と同様の材料を用いて設けてもよい。なお、絶縁体２８０は、２層以上の積層構造を有していてもよい。 It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. Further, the insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or an excess oxygen, and may be provided by using the same material as the insulator 216, for example. The insulator 280 may have a laminated structure of two or more layers.
　絶縁体２８２は、絶縁体２１４などと同様に、水、水素などの不純物が、上方から絶縁体２８０に拡散するのを抑制する絶縁性バリア膜として機能することが好ましい。また、絶縁体２８２は、絶縁体２１４などと同様に、水素濃度が低く、水素の拡散を抑制する機能を有することが好ましい。 Like the insulator 214, the insulator 282 preferably functions as an insulating barrier film that suppresses impurities such as water and hydrogen from diffusing into the insulator 280 from above. Further, it is preferable that the insulator 282 has a low hydrogen concentration and has a function of suppressing the diffusion of hydrogen, like the insulator 214 and the like.
　また、図２Ｂに示すように、絶縁体２８２は、導電体２６０、絶縁体２５０、および酸化物２３０ｃのそれぞれの上面と接することが好ましい。これにより、絶縁体２８４などに含まれる水素などの不純物が、絶縁体２５０へ混入することを抑えることができる。したがって、トランジスタの電気特性およびトランジスタの信頼性への悪影響を抑制することができる。 Further, as shown in FIG. 2B, it is preferable that the insulator 282 is in contact with the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively. As a result, impurities such as hydrogen contained in the insulator 284 and the like can be suppressed from being mixed into the insulator 250. Therefore, it is possible to suppress adverse effects on the electrical characteristics of the transistor and the reliability of the transistor.
　絶縁体２８２の上に、層間膜として機能する絶縁体２８４を設けることが好ましい。絶縁体２８４は、絶縁体２１６などと同様に、誘電率が低いことが好ましい。また、絶縁体２８４は、絶縁体２２４などと同様に、膜中の水、水素などの不純物濃度が低減されていることが好ましい。 It is preferable to provide an insulator 284 that functions as an interlayer film on the insulator 282. The insulator 284 preferably has a low dielectric constant, like the insulator 216 and the like. Further, it is preferable that the insulator 284 has a reduced concentration of impurities such as water and hydrogen in the film, similarly to the insulator 224 and the like.
＜半導体装置の構成材料＞
　以下では、半導体装置に用いることができる構成材料について説明する。 <Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used in semiconductor devices will be described.
＜＜基板＞＞
　トランジスタ２００を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 << Board >>
As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like. Further, examples of the semiconductor substrate include a semiconductor substrate made of silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
＜＜絶縁体＞＞
　絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 << Insulator >>
Examples of the insulator include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like having insulating properties.
　例えば、トランジスタの微細化、および高集積化が進むと、ゲート絶縁体の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁体として機能する絶縁体に、ｈｉｇｈ−ｋ材料を用いることで物理膜厚を保ちながら、トランジスタ動作時の低電圧化が可能となる。一方、層間膜として機能する絶縁体には、比誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。したがって、絶縁体の機能に応じて、材料を選択するとよい。 For example, as transistors become finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material having a low relative permittivity for the insulator that functions as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. Therefore, the material may be selected according to the function of the insulator.
　また、比誘電率の高い絶縁体としては、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウムおよびハフニウムを有する酸化物、アルミニウムおよびハフニウムを有する酸化窒化物、シリコンおよびハフニウムを有する酸化物、シリコンおよびハフニウムを有する酸化窒化物、またはシリコンおよびハフニウムを有する窒化物などがある。 Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.
　また、比誘電率が低い絶縁体としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコン、または樹脂などがある。 Examples of insulators having a low specific dielectric constant include silicon oxide, silicon oxide, silicon oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and empty. There are silicon oxide having holes, resin, and the like.
　また、酸化物半導体を用いたトランジスタは、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体（絶縁体２１４、絶縁体２２２、絶縁体２４５、および絶縁体２８２など）で囲うことによって、トランジスタの電気特性を安定にすることができる。水素などの不純物および酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム、またはタンタルを含む絶縁体を、単層で、または積層で用いればよい。具体的には、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体として、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、酸化タンタルなどの金属酸化物、窒化アルミニウム、窒化酸化シリコン、窒化シリコンなどの金属窒化物を用いることができる。 Further, the transistor using the oxide semiconductor is surrounded by an insulator (insulator 214, insulator 222, insulator 245, insulator 282, etc.) having a function of suppressing the permeation of impurities such as hydrogen and oxygen. , The electrical characteristics of the transistor can be stabilized. Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulations containing, lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in layers. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, etc. Metal oxides such as tantalum oxide and metal nitrides such as aluminum nitride, silicon nitride and silicon nitride can be used.
　また、ゲート絶縁体として機能する絶縁体は、加熱により脱離する酸素を含む領域を有する絶縁体であることが好ましい。例えば、加熱により脱離する酸素を含む領域を有する酸化シリコンまたは酸化窒化シリコンを酸化物２３０と接する構造とすることで、酸化物２３０が有する酸素欠損を補償することができる。 Further, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by adopting a structure in which silicon oxide or silicon oxide nitride having a region containing oxygen desorbed by heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated.
＜＜導電体＞＞
　導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。例えば、窒化タンタル、窒化チタン、窒化タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 << Conductor >>
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like. For example, tantalum nitride, titanium nitride, tungsten nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. It is preferable to use it. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.
　また、上記の材料で形成される導電層を複数積層して用いてもよい。例えば、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、酸素を含む導電性材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。 Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
　なお、トランジスタのチャネル形成領域に酸化物を用いる場合において、ゲート電極として機能する導電体には、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造を用いることが好ましい。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から離脱した酸素がチャネル形成領域に供給されやすくなる。 When an oxide is used in the channel forming region of the transistor, the conductor functioning as the gate electrode shall have a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Is preferable. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.
　特に、ゲート電極として機能する導電体として、チャネルが形成される金属酸化物に含まれる金属元素および酸素を含む導電性材料を用いることが好ましい。また、前述した金属元素および窒素を含む導電性材料を用いてもよい。例えば、窒化チタン、窒化タンタルなどの窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、チャネルが形成される金属酸化物に含まれる水素を捕獲することができる場合がある。または、外方の絶縁体などから混入する水素を捕獲することができる場合がある。 In particular, as a conductor that functions as a gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which channels are formed. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.
＜＜金属酸化物＞＞
　酸化物２３０として、酸化物半導体として機能する金属酸化物を用いることが好ましい。以下では、本発明に係る酸化物２３０に適用可能な金属酸化物について説明する。 << Metal Oxide >>
As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.
　金属酸化物は、少なくともインジウムまたは亜鉛を含むことが好ましい。特に、インジウムおよび亜鉛を含むことが好ましい。また、それらに加えて、ガリウム、イットリウム、錫などが含まれていることが好ましい。また、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどから選ばれた一種、または複数種が含まれていてもよい。 The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, gallium, yttrium, tin and the like are preferably contained. Further, one kind or a plurality of kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.
　ここでは、金属酸化物が、インジウム、元素Ｍおよび亜鉛を有するＩｎ−Ｍ−Ｚｎ酸化物である場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウム、または錫とする。そのほかの元素Ｍに適用可能な元素としては、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどがある。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。 Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Examples of elements applicable to the other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.
　なお、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 In addition, in this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
［金属酸化物の構造］
　酸化物半導体（金属酸化物）は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、ＣＡＡＣ−ＯＳ、多結晶酸化物半導体、ｎｃ−ＯＳ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、および非晶質酸化物半導体などがある。 [Structure of metal oxide]
Oxide semiconductors (metal oxides) are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-monocrystalline oxide semiconductor include CAAC-OS, polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), and the like. And amorphous oxide semiconductors.
　ＣＡＡＣ−ＯＳは、ｃ軸配向性を有し、かつａ−ｂ面方向において複数のナノ結晶が連結し、歪みを有した結晶構造となっている。なお、歪みとは、複数のナノ結晶が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。 CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.
　ナノ結晶は、六角形を基本とするが、正六角形状とは限らず、非正六角形状である場合がある。また、歪みにおいて、五角形、および七角形などの格子配列を有する場合がある。なお、ＣＡＡＣ−ＯＳにおいて、歪み近傍においても、明確な結晶粒界（グレインバウンダリーともいう。）を確認することは難しい。すなわち、格子配列の歪みによって、結晶粒界の形成が抑制されていることがわかる。これは、ＣＡＡＣ−ＯＳが、ａ−ｂ面方向において酸素原子の配列が稠密でないことや、金属元素が置換することで原子間の結合距離が変化することなどによって、歪みを許容することができるためである。 Nanocrystals are basically hexagons, but they are not limited to regular hexagons and may be non-regular hexagons. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. Because.
　また、ＣＡＡＣ−ＯＳは、インジウム、および酸素を有する層（以下、Ｉｎ層）と、元素Ｍ、亜鉛、および酸素を有する層（以下、（Ｍ，Ｚｎ）層）とが積層した、層状の結晶構造（層状構造ともいう）を有する傾向がある。なお、インジウムと元素Ｍは、互いに置換可能であり、（Ｍ，Ｚｎ）層の元素Ｍがインジウムと置換した場合、（Ｉｎ，Ｍ，Ｚｎ）層と表すこともできる。また、Ｉｎ層のインジウムが元素Ｍと置換した場合、（Ｉｎ，Ｍ）層と表すこともできる。 Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as the (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can be expressed as the (In, M) layer.
　ＣＡＡＣ−ＯＳは結晶性の高い金属酸化物である。一方、ＣＡＡＣ−ＯＳは、明確な結晶粒界を確認することが難しいため、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。また、金属酸化物の結晶性は不純物の混入や欠陥の生成などによって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物や欠陥（酸素欠損など）の少ない金属酸化物ともいえる。したがって、ＣＡＡＣ−ＯＳを有する金属酸化物は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する金属酸化物は熱に強く、信頼性が高い。 CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, it is difficult to confirm a clear grain boundary, so it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the metal oxide may be lowered due to the mixing of impurities or the formation of defects, CAAC-OS can be said to be a metal oxide having few impurities and defects (oxygen deficiency, etc.). Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
　ｎｃ−ＯＳは、微小な領域（例えば、１ｎｍ以上１０ｎｍ以下の領域、特に１ｎｍ以上３ｎｍ以下の領域）において原子配列に周期性を有する。また、ｎｃ−ＯＳは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、ｎｃ−ＯＳは、分析方法によっては、ａ−ｌｉｋｅ　ＯＳや非晶質酸化物半導体と区別が付かない場合がある。 The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors depending on the analysis method.
　なお、インジウムと、ガリウムと、亜鉛と、を有する金属酸化物の一種である、Ｉｎ−Ｇａ−Ｚｎ酸化物（以下、ＩＧＺＯ）は、上述のナノ結晶とすることで安定な構造をとる場合がある。特に、ＩＧＺＯは、大気中では結晶成長がし難い傾向があるため、大きな結晶（ここでは、数ｍｍの結晶、または数ｃｍの結晶）よりも小さな結晶（例えば、上述のナノ結晶）とする方が、構造的に安定となる場合がある。 In-Ga-Zn oxide (hereinafter, IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may have a stable structure by forming the above-mentioned nanocrystals. is there. In particular, since IGZO tends to have difficulty in crystal growth in the atmosphere, it is preferable to use smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, a few mm crystal or a few cm crystal). However, it may be structurally stable.
　ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳと非晶質酸化物半導体との間の構造を有する金属酸化物である。ａ−ｌｉｋｅ　ＯＳは、鬆または低密度領域を有する。すなわち、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて、結晶性が低い。 The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
　酸化物半導体（金属酸化物）は、多様な構造をとり、それぞれが異なる特性を有する。本発明の一態様の酸化物半導体は、非晶質酸化物半導体、多結晶酸化物半導体、ａ−ｌｉｋｅ　ＯＳ、ｎｃ−ＯＳ、ＣＡＡＣ−ＯＳのうち、二種以上を有していてもよい。 Oxide semiconductors (metal oxides) have various structures, and each has different characteristics. The oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.
［不純物］
　ここで、金属酸化物中における各不純物の影響について説明する。 [impurities]
Here, the influence of each impurity in the metal oxide will be described.
　酸化物半導体に不純物が混入すると、欠陥準位または酸素欠損が形成される場合がある。よって、酸化物半導体のチャネル形成領域に不純物が混入することで、酸化物半導体を用いたトランジスタの電気特性が変動しやすく、信頼性が悪くなる場合がある。また、チャネル形成領域に酸素欠損が含まれていると、トランジスタはノーマリーオン特性となりやすい。 Impurities mixed in oxide semiconductors may form defect levels or oxygen deficiencies. Therefore, when impurities are mixed in the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are liable to fluctuate, and the reliability may be deteriorated. Further, when the channel formation region contains oxygen deficiency, the transistor tends to have a normally-on characteristic.
　また、上記欠陥準位には、トラップ準位が含まれる場合がある。金属酸化物のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い金属酸化物をチャネル形成領域に有するトランジスタは、電気特性が不安定となる場合がある。 In addition, the above defect level may include a trap level. The charge captured at the trap level of the metal oxide takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor having a metal oxide having a high trap level density in the channel forming region may have unstable electrical characteristics.
　また、酸化物半導体のチャネル形成領域に不純物が存在すると、チャネル形成領域の結晶性が低くなる場合がある、また、チャネル形成領域に接して設けられる酸化物の結晶性が低くなる場合がある。チャネル形成領域の結晶性が低いと、トランジスタの安定性または信頼性が悪化する傾向がある。また、チャネル形成領域に接して設けられる酸化物の結晶性が低いと、界面準位が形成され、トランジスタの安定性または信頼性が悪化する場合がある。 Further, if impurities are present in the channel forming region of the oxide semiconductor, the crystallinity of the channel forming region may be lowered, or the crystallinity of the oxide provided in contact with the channel forming region may be lowered. Poor crystallinity in the channel formation region tends to reduce the stability or reliability of the transistor. Further, if the crystallinity of the oxide provided in contact with the channel forming region is low, an interface state may be formed and the stability or reliability of the transistor may be deteriorated.
　したがって、トランジスタの安定性または信頼性を向上させるには、酸化物半導体のチャネル形成領域およびその近傍の不純物濃度を低減することが有効である。不純物としては、水素、窒素、アルカリ金属、アルカリ土類金属、鉄、ニッケル、シリコン等がある。 Therefore, in order to improve the stability or reliability of the transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
　具体的には、当該酸化物半導体のチャネル形成領域およびその近傍において、ＳＩＭＳにより得られる上記不純物の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。または、当該酸化物半導体のチャネル形成領域およびその近傍において、ＥＤＸを用いた元素分析により得られる上記不純物の濃度を、１．０ａｔｏｍｉｃ％以下にする。なお、当該酸化物半導体として元素Ｍを含む酸化物を用いる場合、当該酸化物半導体のチャネル形成領域およびその近傍において、元素Ｍに対する上記不純物の濃度比を、０．１０未満、好ましくは０．０５未満にする。ここで、上記濃度比を算出する際に用いる元素Ｍの濃度は、上記不純物の濃度を算出した領域と同じ領域の濃度でもよいし、当該酸化物半導体中の濃度でもよい。 Specifically, the concentration of the above-mentioned impurities obtained by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less. To do. Alternatively, the concentration of the impurities obtained by elemental analysis using EDX in the channel formation region of the oxide semiconductor and its vicinity is set to 1.0 atomic% or less. When an oxide containing an element M is used as the oxide semiconductor, the concentration ratio of the impurities to the element M in the channel forming region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably 0.05. To less than. Here, the concentration of the element M used in calculating the concentration ratio may be the concentration in the same region as the region in which the concentration of the impurities is calculated, or may be the concentration in the oxide semiconductor.
　また、不純物濃度を低減した金属酸化物は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。 In addition, the metal oxide with reduced impurity concentration has a low defect level density, so the trap level density may also be low.
＜半導体装置の作製方法＞
　次に、図２に示す、本発明の一態様に係るトランジスタ２００を有する半導体装置の作製方法を、図３乃至図９を用いて説明する。 <Method of manufacturing semiconductor devices>
Next, a method of manufacturing a semiconductor device having the transistor 200 according to one aspect of the present invention shown in FIG. 2 will be described with reference to FIGS. 3 to 9.
　図３乃至図９において、各図のＡは上面図を示す。また、各図のＢは、Ａに示すＡ１−Ａ２の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、各図のＣは、ＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、各図のＤは、各図のＡにＡ５−Ａ６の一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。なお、各図のＡの上面図では、図の明瞭化のために一部の要素を省いている。 In FIGS. 3 to 9, A in each figure shows a top view. Further, B in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in A, and is also a cross-sectional view in the channel length direction of the transistor 200. Further, C in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line in A3-A4, and is also a cross-sectional view in the channel width direction of the transistor 200. Further, D in each figure is a cross-sectional view of a portion shown by a alternate long and short dash line in A5 to A6 in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of A in each figure, some elements are omitted for the purpose of clarifying the figure.
　まず、基板（図示しない。）を準備し、当該基板上に絶縁体２１４を成膜する。絶縁体２１４の成膜は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法、パルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ法などを用いて行うことができる。 First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The film formation of the insulator 214 is performed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, and a pulse laser deposition method (PLD). It can be done by using.
　なお、ＣＶＤ法は、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＣＶＤ）法、熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ　ＣＶＤ）法、光を利用する光ＣＶＤ（Ｐｈｏｔｏ　ＣＶＤ）法などに分類できる。さらに用いる原料ガスによって金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ　ＣＶＤ）法、有機金属ＣＶＤ（ＭＯＣＶＤ：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　ＣＶＤ）法に分けることができる。 The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organometallic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.
　プラズマＣＶＤ法は、比較的低温で高品質の膜が得られる。また、熱ＣＶＤ法は、プラズマを用いないため、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。例えば、半導体装置に含まれる配線、電極、素子（トランジスタ、容量素子など）などは、プラズマから電荷を受け取ることでチャージアップする場合がある。このとき、蓄積した電荷によって、半導体装置に含まれる配線、電極、素子などが破壊される場合がある。一方、プラズマを用いない熱ＣＶＤ法の場合、こういったプラズマダメージが生じないため、半導体装置の歩留まりを高くすることができる。また、熱ＣＶＤ法では、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。 The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage during film formation does not occur, so that a film having few defects can be obtained.
　また、ＡＬＤ法は、原子の性質である自己制御性を利用し、一層ずつ原子を堆積することができるので、極薄の成膜が可能、アスペクト比の高い構造への成膜が可能、ピンホールなどの欠陥の少ない成膜が可能、被覆性に優れた成膜が可能、低温での成膜が可能、などの効果がある。また、ＡＬＤ法には、プラズマを利用するＰＥＡＬＤ（Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＡＬＤ）法も含まれる。プラズマを利用することで、より低温での成膜が可能となり好ましい場合がある。なお、ＡＬＤ法で用いるプリカーサには炭素などの不純物を含むものがある。このため、ＡＬＤ法により設けられた膜は、他の成膜法により設けられた膜と比較して、炭素などの不純物を多く含む場合がある。なお、不純物の定量は、Ｘ線光電子分光法（ＸＰＳ：Ｘ−ｒａｙ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて行うことができる。 In addition, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, and pins. It has the effects of being able to form a film with few defects such as holes, being able to form a film with excellent coverage, and being able to form a film at a low temperature. The ALD method also includes a PEALD (Plasma Enhanced ALD) method using plasma. By using plasma, it is possible to form a film at a lower temperature, which may be preferable. Some precursors used in the ALD method contain impurities such as carbon. Therefore, the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods. The quantification of impurities can be performed by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
　ＣＶＤ法およびＡＬＤ法は、ターゲットなどから放出される粒子が堆積する成膜方法とは異なり、被処理物の表面における反応により膜が形成される成膜方法である。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。 The CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage. In particular, the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.
　ＣＶＤ法およびＡＬＤ法は、原料ガスの流量比によって、得られる膜の組成を制御することができる。例えば、ＣＶＤ法およびＡＬＤ法では、原料ガスの流量比によって、任意の組成の膜を成膜することができる。また、例えば、ＣＶＤ法およびＡＬＤ法では、成膜しながら原料ガスの流量比を変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスの流量比を変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送や圧力調整に掛かる時間を要さない分、成膜に掛かる時間を短くすることができる。したがって、半導体装置の生産性を高めることができる場合がある。 In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas. Further, for example, in the CVD method and the ALD method, a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film. When film formation is performed while changing the flow rate ratio of the raw material gas, the time required for film formation is shortened because it does not require time for transportation and pressure adjustment as compared with the case where film formation is performed using a plurality of film forming chambers. can do. Therefore, it may be possible to increase the productivity of the semiconductor device.
　本実施の形態では、絶縁体２１４として、スパッタリング法によって酸化アルミニウムを成膜する。また、絶縁体２１４は、多層構造としてもよい。 In the present embodiment, aluminum oxide is formed as the insulator 214 by a sputtering method. Further, the insulator 214 may have a multi-layer structure.
　次に、絶縁体２１４上に絶縁体２１６を成膜する。絶縁体２１６の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２１６となる絶縁膜として、ＣＶＤ法によって酸化窒化シリコンを成膜する。 Next, the insulator 216 is formed on the insulator 214. The film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide nitriding film is formed by the CVD method as an insulating film to be the insulator 216.
　次に、絶縁体２１６に絶縁体２１４に達する開口を形成する。開口とは、例えば、溝やスリットなども含まれる。また、開口が形成された領域を指して開口部とする場合がある。開口の形成はウェットエッチングを用いてもよいが、ドライエッチングを用いるほうが微細加工には好ましい。また、絶縁体２１４は、絶縁体２１６をエッチングして溝を形成する際のエッチングストッパ膜として機能する絶縁体を選択することが好ましい。例えば、溝を形成する絶縁体２１６に酸化窒化シリコンを用いた場合は、絶縁体２１４は窒化シリコン、酸化アルミニウム、酸化ハフニウムを用いるとよい。 Next, an opening is formed in the insulator 216 to reach the insulator 214. The opening also includes, for example, a groove or a slit. Further, the region where the opening is formed may be referred to as an opening. Although wet etching may be used to form the openings, it is preferable to use dry etching for microfabrication. Further, as the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxide is used for the insulator 216 forming the groove, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.
　ドライエッチング装置としては、平行平板型電極を有する容量結合型プラズマ（ＣＣＰ：Ｃａｐａｃｉｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置を用いることができる。平行平板型電極を有する容量結合型プラズマエッチング装置は、平行平板型電極の一方の電極に高周波電圧を印加する構成でもよい。または平行平板型電極の一方の電極に複数の異なった高周波電圧を印加する構成でもよい。または平行平板型電極それぞれに同じ周波数の高周波電圧を印加する構成でもよい。または平行平板型電極それぞれに周波数の異なる高周波電圧を印加する構成でもよい。または高密度プラズマ源を有するドライエッチング装置を用いることができる。高密度プラズマ源を有するドライエッチング装置は、例えば、誘導結合型プラズマ（ＩＣＰ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置などを用いることができる。 As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate type electrodes can be used. The capacitively coupled plasma etching apparatus having the parallel plate type electrodes may be configured to apply a high frequency voltage to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency voltages may be applied to one of the parallel plate type electrodes. Alternatively, a high frequency voltage having the same frequency may be applied to each of the parallel plate type electrodes. Alternatively, a high frequency voltage having a different frequency may be applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like can be used.
　開口の形成後に、導電体２０５の第１の導電体となる導電膜を成膜する。該導電膜は、酸素の透過を抑制する機能を有する導電体を含むことが望ましい。たとえば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。または、酸素の透過を抑制する機能を有する導電体と、タンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。該導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 After forming the opening, a conductive film to be the first conductor of the conductor 205 is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film of a conductor having a function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper or molybdenum tungsten alloy. The film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　本実施の形態では、導電体２０５の第１の導電体となる導電膜として、スパッタリング法によって窒化タンタル膜、または、窒化タンタルの上に窒化チタンを積層した膜を成膜する。このような金属窒化物を導電体２０５の第１の導電体に用いることにより、後述する導電体２０５の第２の導電体として銅などの拡散しやすい金属を用いても、当該金属が導電体２０５の第１の導電体から外に拡散するのを防ぐことができる。 In the present embodiment, as the conductive film to be the first conductor of the conductor 205, a tantalum nitride film or a film in which titanium nitride is laminated on the tantalum nitride is formed by a sputtering method. By using such a metal nitride as the first conductor of the conductor 205, even if a metal such as copper, which is easily diffused, is used as the second conductor of the conductor 205, which will be described later, the metal is the conductor. It is possible to prevent the 205 from diffusing out from the first conductor.
　次に、導電体２０５の第１の導電体となる導電膜上に、導電体２０５の第２の導電体となる導電膜を成膜する。該導電膜の成膜は、メッキ法、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。本実施の形態では、該導電膜として、タングステンを成膜する。 Next, a conductive film to be the second conductor of the conductor 205 is formed on the conductive film to be the first conductor of the conductor 205. The film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, tungsten is formed as the conductive film.
　次に、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）処理を行うことで、導電体２０５の第１の導電体となる導電膜、および導電体２０５の第２の導電体となる導電膜の一部を除去し、絶縁体２１６を露出する。その結果、開口部のみに、導電体２０５の第１の導電体となる導電膜、および導電体２０５の第２の導電体となる導電膜が残存する。これにより、上面が平坦な、導電体２０５の第１の導電体および導電体２０５の第２の導電体を含む導電体２０５を形成することができる（図３参照。）。 Next, by performing a CMP (Chemical Mechanical Polishing) treatment, a part of the conductive film that becomes the first conductor of the conductor 205 and a part of the conductive film that becomes the second conductor of the conductor 205 are removed. The insulator 216 is exposed. As a result, the conductive film that becomes the first conductor of the conductor 205 and the conductive film that becomes the second conductor of the conductor 205 remain only in the opening. As a result, it is possible to form the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 having a flat upper surface (see FIG. 3).
　なお、導電体２０５を形成した後に、導電体２０５の第２の導電体の一部を除去して、導電体２０５の第２の導電体に溝を形成し、当該溝を埋め込むように導電体２０５および絶縁体２１６上に導電膜を成膜し、ＣＭＰ処理を行う工程を行ってもよい。当該ＣＭＰ処理により、当該導電膜の一部を除去し、絶縁体２１６を露出する。なお、導電体２０５の第２の導電体の一部は、ドライエッチング法などを用いて除去するとよい。 After forming the conductor 205, a part of the second conductor of the conductor 205 is removed to form a groove in the second conductor of the conductor 205, and the conductor is embedded so as to embed the groove. A step of forming a conductive film on the 205 and the insulator 216 and performing a CMP treatment may be performed. By the CMP treatment, a part of the conductive film is removed to expose the insulator 216. A part of the second conductor of the conductor 205 may be removed by a dry etching method or the like.
　上記工程により、上面が平坦な、上記導電膜を含む導電体２０５を形成することができる。絶縁体２１６と導電体２０５の上面の平坦性を向上させることにより、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃの結晶性の向上を図ることができる。なお、当該導電膜には、導電体２０５の第１の導電体または導電体２０５の第２の導電体と同様の材料を用いるとよい。 By the above steps, a conductor 205 having a flat upper surface and containing the above conductive film can be formed. By improving the flatness of the upper surfaces of the insulator 216 and the conductor 205, the crystallinity of the oxide 230a, the oxide 230b, and the oxide 230c can be improved. As the conductive film, it is preferable to use the same material as the first conductor of the conductor 205 or the second conductor of the conductor 205.
　ここからは、上記と異なる導電体２０５の形成方法について以下に説明する。 From here, a method for forming the conductor 205 different from the above will be described below.
　絶縁体２１４上に、導電体２０５となる導電膜を成膜する。導電体２０５となる導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。また、導電体２０５となる導電膜は、多層膜とすることができる。例えば、導電体２０５となる導電膜としてタングステンを成膜する。 A conductive film to be a conductor 205 is formed on the insulator 214. The film formation of the conductive film to be the conductor 205 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductive film to be the conductor 205 can be a multilayer film. For example, tungsten is formed as a conductive film to be the conductor 205.
　次に、リソグラフィー法を用いて、導電体２０５となる導電膜を加工し、導電体２０５を形成する。 Next, using the lithography method, the conductive film to be the conductor 205 is processed to form the conductor 205.
　なお、リソグラフィー法では、まず、マスクを介してレジストを露光する。次に、露光された領域を、現像液を用いて除去または残存させてレジストマスクを形成する。次に、当該レジストマスクを介してエッチング処理することで導電体、半導体、絶縁体などを所望の形状に加工することができる。例えば、ＫｒＦエキシマレーザ光、ＡｒＦエキシマレーザ光、ＥＵＶ（ＥｘｔｒｅｍｅＵｌｔｒａｖｉｏｌｅｔ）光などを用いて、レジストを露光することでレジストマスクを形成すればよい。また、基板と投影レンズとの間に液体（例えば水）を満たして露光する、液浸技術を用いてもよい。また、前述した光に代えて、電子ビームやイオンビームを用いてもよい。なお、電子ビームやイオンビームを用いる場合には、マスクは不要となる。なお、レジストマスクは、アッシングなどのドライエッチング処理を行う、ウェットエッチング処理を行う、ドライエッチング処理後にウェットエッチング処理を行う、またはウェットエッチング処理後にドライエッチング処理を行うことで、除去することができる。 In the lithography method, the resist is first exposed through a mask. Next, the exposed region is removed or left with a developing solution to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used. When using an electron beam or an ion beam, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
　また、レジストマスクの代わりに絶縁体や導電体からなるハードマスクを用いてもよい。ハードマスクを用いる場合、導電体２０５となる導電膜上にハードマスク材料となる絶縁膜や導電膜を形成し、その上にレジストマスクを形成し、ハードマスク材料をエッチングすることで所望の形状のハードマスクを形成することができる。導電体２０５となる導電膜のエッチングは、レジストマスクを除去してから行っても良いし、レジストマスクを残したまま行っても良い。後者の場合、エッチング中にレジストマスクが消失することがある。導電体２０５となる導電膜のエッチング後にハードマスクをエッチングにより除去しても良い。一方、ハードマスクの材料が後工程に影響が無い、あるいは後工程で利用できる場合、必ずしもハードマスクを除去する必要は無い。 Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film to be a hard mask material is formed on a conductive film to be a conductor 205, a resist mask is formed on the conductive film, and the hard mask material is etched to obtain a desired shape. A hard mask can be formed. The etching of the conductive film to be the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film to be the conductor 205. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.
　次に、絶縁体２１４、および導電体２０５上に絶縁体２１６となる絶縁膜を成膜する。当該絶縁膜は、導電体２０５の上面、および側面と接するように形成する。当該絶縁膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulating film to be the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film is formed so as to be in contact with the upper surface and the side surface of the conductor 205. The insulating film can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　ここで、絶縁体２１６となる絶縁膜の膜厚は、導電体２０５の膜厚以上とすることが好ましい。例えば、導電体２０５の膜厚を１とすると、絶縁体２１６となる絶縁膜の膜厚は、１以上３以下とする。 Here, the film thickness of the insulating film to be the insulator 216 is preferably equal to or greater than the film thickness of the conductor 205. For example, assuming that the film thickness of the conductor 205 is 1, the film thickness of the insulating film that becomes the insulator 216 is 1 or more and 3 or less.
　次に、絶縁体２１６となる絶縁膜にＣＭＰ処理を行うことで、絶縁体２１６となる絶縁膜の一部を除去し、導電体２０５の表面を露出させる。これにより、上面が平坦な、導電体２０５と、絶縁体２１６とを形成することができる。以上が、導電体２０５の異なる形成方法である。 Next, by performing a CMP treatment on the insulating film to be the insulator 216, a part of the insulating film to be the insulator 216 is removed to expose the surface of the conductor 205. As a result, the conductor 205 and the insulator 216 having a flat upper surface can be formed. The above is a different method for forming the conductor 205.
　次に、絶縁体２１６、および導電体２０５上に絶縁体２２２を成膜する。絶縁体２２２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２２２として、ＡＬＤ法によって、酸化ハフニウムまたは酸化アルミニウムを成膜する。 Next, the insulator 222 is formed on the insulator 216 and the conductor 205. The film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, hafnium oxide or aluminum oxide is formed as the insulator 222 by the ALD method.
　続いて、加熱処理を行うと好ましい。加熱処理は、２５０℃以上６５０℃以下、好ましくは３００℃以上５００℃以下、さらに好ましくは３２０℃以上４５０℃以下で行えばよい。なお、加熱処理は、窒素ガスもしくは不活性ガスの雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上、もしくは１０％以上含む雰囲気で行う。また、加熱処理は減圧状態で行ってもよい。または、加熱処理は、窒素ガスもしくは不活性ガスの雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上、または１０％以上含む雰囲気で加熱処理を行ってもよい。 Subsequently, it is preferable to perform heat treatment. The heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower. The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
　本実施の形態では、加熱処理として、絶縁体２２２の成膜後に窒素雰囲気にて４００℃の温度で１時間の処理を行った後に、連続して酸素雰囲気にて４００℃の温度で１時間の処理を行う。当該加熱処理によって、絶縁体２２２に含まれる水、水素などの不純物を除去することなどができる。また、加熱処理は、絶縁体２２４の成膜後などのタイミングで行うこともできる。 In the present embodiment, as the heat treatment, after the insulator 222 is formed, the insulator 222 is treated in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, and then continuously in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour. Perform processing. By the heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Further, the heat treatment can be performed at a timing such as after the film formation of the insulator 224 is performed.
　次に、絶縁体２２２上に絶縁体２２４を成膜する。絶縁体２２４の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２２４として、ＣＶＤ法によって酸化窒化シリコン膜を成膜する。 Next, the insulator 224 is formed on the insulator 222. The film formation of the insulator 224 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, a silicon oxide film is formed as the insulator 224 by the CVD method.
　ここで、絶縁体２２４に過剰酸素領域を形成するために、減圧状態で酸素を含むプラズマ処理を行ってもよい。酸素を含むプラズマ処理は、例えばマイクロ波を用いた高密度プラズマを発生させる電源を有する装置を用いることが好ましい。または、基板側にＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）を印加する電源を有してもよい。高密度プラズマを用いることより、高密度の酸素ラジカルを生成することができ、基板側にＲＦを印加することで、高密度プラズマによって生成された酸素ラジカルを効率よく絶縁体２２４内に導くことができる。または、この装置を用いて不活性ガスを含むプラズマ処理を行った後に、脱離した酸素を補うために酸素を含むプラズマ処理を行ってもよい。なお、当該プラズマ処理の条件を適宜選択することにより、絶縁体２２４に含まれる水、水素などの不純物を除去することができる。その場合、加熱処理は行わなくてもよい。 Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed in a reduced pressure state. For plasma treatment containing oxygen, for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can. Alternatively, the plasma treatment containing an inert gas may be performed using this device, and then the plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. By appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, the heat treatment does not have to be performed.
　ここで、絶縁体２２４上に、例えば、スパッタリング法によって、酸化アルミニウムを成膜した後、絶縁体２２４に達するまで、ＣＭＰ処理を行ってもよい。当該ＣＭＰ処理を行うことで絶縁体２２４表面の平坦化および平滑化を行うことができる。当該酸化アルミニウムを絶縁体２２４上に配置してＣＭＰ処理を行うことで、ＣＭＰ処理の終点検出が容易となる。また、ＣＭＰ処理によって、絶縁体２２４の一部が研磨されて、絶縁体２２４の膜厚が薄くなることがあるが、絶縁体２２４の成膜時に膜厚を調整すればよい。絶縁体２２４表面の平坦化および平滑化を行うことで、後に成膜する酸化物の被覆率の悪化を防止し、半導体装置の歩留りの低下を防ぐことができる場合がある。また、絶縁体２２４上に、スパッタリング法によって、酸化アルミニウムを成膜することにより、絶縁体２２４に酸素を添加することができるので好ましい。 Here, after forming aluminum oxide on the insulator 224 by, for example, a sputtering method, CMP treatment may be performed until the insulator 224 is reached. By performing the CMP treatment, the surface of the insulator 224 can be flattened and smoothed. By arranging the aluminum oxide on the insulator 224 and performing the CMP treatment, it becomes easy to detect the end point of the CMP treatment. Further, the CMP treatment may polish a part of the insulator 224 to reduce the film thickness of the insulator 224, but the film thickness may be adjusted when the insulator 224 is formed. By flattening and smoothing the surface of the insulator 224, it may be possible to prevent deterioration of the coverage of oxides to be formed later and prevent a decrease in the yield of the semiconductor device. Further, it is preferable that oxygen can be added to the insulator 224 by forming aluminum oxide on the insulator 224 by a sputtering method.
　次に、絶縁体２２４上に、酸化膜２３０Ａ、酸化膜２３０Ｂを順に成膜する（図３参照。）。なお、酸化膜２３０Ａおよび酸化膜２３０Ｂは、大気環境にさらさずに連続して成膜することが好ましい。大気開放せずに成膜することで、酸化膜２３０Ａ、および酸化膜２３０Ｂ上に大気環境からの不純物または水分が付着することを防ぐことができ、酸化膜２３０Ａと酸化膜２３０Ｂとの界面近傍を清浄に保つことができる。 Next, the oxide film 230A and the oxide film 230B are formed on the insulator 224 in this order (see FIG. 3). It is preferable that the oxide film 230A and the oxide film 230B are continuously formed without being exposed to the atmospheric environment. By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
　酸化膜２３０Ａ、および酸化膜２３０Ｂの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　例えば、酸化膜２３０Ａ、および酸化膜２３０Ｂをスパッタリング法によって成膜する場合は、スパッタリングガスとして酸素、または、酸素と希ガスの混合ガスを用いる。スパッタリングガスに含まれる酸素の割合を高めることで、成膜される酸化膜中の過剰酸素を増やすことができる。また、上記の酸化膜をスパッタリング法によって成膜する場合は、上記のＩｎ−Ｍ−Ｚｎ酸化物ターゲットなどを用いることができる。 For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film formed can be increased. Further, when the above oxide film is formed by a sputtering method, the above In—M—Zn oxide target or the like can be used.
　特に、酸化膜２３０Ａの成膜時に、スパッタリングガスに含まれる酸素の一部が絶縁体２２４に供給される場合がある。したがって、当該スパッタリングガスに含まれる酸素の割合は７０％以上、好ましくは８０％以上、より好ましくは１００％とすればよい。 In particular, when the oxide film 230A is formed, a part of oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.
　また、酸化膜２３０Ｂをスパッタリング法で形成する場合、スパッタリングガスに含まれる酸素の割合を、３０％を超えて１００％以下、好ましくは７０％以上１００％以下として成膜すると、酸素過剰型の酸化物半導体が形成される。酸素過剰型の酸化物半導体をチャネル形成領域に用いたトランジスタは、比較的高い信頼性が得られる。ただし、本発明の一態様はこれに限定されない。酸化膜２３０Ｂをスパッタリング法で形成する場合、スパッタリングガスに含まれる酸素の割合を１％以上３０％以下、好ましくは５％以上２０％以下として成膜すると、酸素欠乏型の酸化物半導体が形成される。酸素欠乏型の酸化物半導体をチャネル形成領域に用いたトランジスタは、比較的高い電界効果移動度が得られる。また、基板を加熱しながら成膜を行うことによって、当該酸化膜の結晶性を向上させることができる。 Further, when the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen excess type oxidation A physical semiconductor is formed. Transistors using oxygen-rich oxide semiconductors in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this. When the oxide film 230B is formed by a sputtering method and the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. To. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can obtain relatively high field-effect mobilities. Further, the crystallinity of the oxide film can be improved by forming a film while heating the substrate.
　本実施の形態では、酸化膜２３０Ａとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて成膜する。また、酸化膜２３０Ｂとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて成膜する。なお、各酸化膜は、成膜条件、および原子数比を適宜選択することで、酸化物２３０に求める特性に合わせて形成するとよい。 In the present embodiment, the oxide film 230A is formed by a sputtering method using an In—Ga—Zn oxide target having an In: Ga: Zn = 1: 3: 4 [atomic number ratio]. Further, as the oxide film 230B, a film is formed by a sputtering method using an In—Ga—Zn oxide target having an In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]. Each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film forming conditions and the atomic number ratio.
　なお、絶縁体２２２、絶縁体２２４、酸化膜２３０Ａ、および酸化膜２３０Ｂを、大気に暴露することなく成膜することが好ましい。例えば、マルチチャンバー方式の成膜装置を用いればよい。 It is preferable that the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are formed without being exposed to the atmosphere. For example, a multi-chamber type film forming apparatus may be used.
　次に、加熱処理を行ってもよい。当該加熱処理は、上述した加熱処理条件を用いることができる。当該加熱処理によって、酸化膜２３０Ａ、および酸化膜２３０Ｂ中の水、水素などの不純物を除去することなどができる。本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行った後に、連続して酸素雰囲気にて４００℃の温度で１時間の処理を行う。 Next, heat treatment may be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. By the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, after the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, the treatment is continuously carried out in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.
　次に、酸化膜２３０Ｂ上に導電膜２４０Ａを成膜する。導電膜２４０Ａの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる（図３参照。）。なお、導電膜２４０Ａの成膜前に、加熱処理を行ってもよい。当該加熱処理は、減圧下で行い、大気に暴露することなく、連続して導電膜２４０Ａを成膜してもよい。このような処理を行うことによって、酸化膜２３０Ｂの表面などに吸着している水分および水素を除去し、さらに酸化膜２３０Ａおよび酸化膜２３０Ｂ中の水分濃度および水素濃度を低減させることができる。加熱処理の温度は、１００℃以上４００℃以下が好ましい。本実施の形態では、加熱処理の温度を２００℃とする。 Next, a conductive film 240A is formed on the oxide film 230B. The film formation of the conductive film 240A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 3). The heat treatment may be performed before the film formation of the conductive film 240A. The heat treatment may be performed under reduced pressure to continuously form the conductive film 240A without exposing it to the atmosphere. By performing such a treatment, the water and hydrogen adsorbed on the surface of the oxide film 230B and the like can be removed, and the water concentration and the hydrogen concentration in the oxide film 230A and the oxide film 230B can be further reduced. The temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200 ° C.
　続いて、バリア層として機能する絶縁膜２４５Ａを形成する（図３参照。）。 Subsequently, an insulating film 245A that functions as a barrier layer is formed (see FIG. 3).
　例えば、絶縁膜２４５Ａとして、ＡＬＤ法により酸化アルミニウムを形成するとよい。ＡＬＤ法を用いて形成することで、緻密な、クラックやピンホールなどの欠陥が低減された、または均一な厚さを備える膜を形成することができる。 For example, aluminum oxide may be formed as the insulating film 245A by the ALD method. By forming using the ALD method, it is possible to form a film having a dense, reduced defects such as cracks and pinholes, or a uniform thickness.
　次に、絶縁膜２４５Ａ上に、およびハードマスクとなる膜２９０Ａを形成する（図３参照。）。例えば、ハードマスクとなる膜２９０Ａとして、タングステン、または窒化タンタルをスパッタリング法で形成するとよい。 Next, a film 290A to be a hard mask is formed on the insulating film 245A (see FIG. 3). For example, tungsten or tantalum nitride may be formed by a sputtering method as the film 290A to be a hard mask.
　次に、ハードマスクとなる膜２９０Ａ上にフォトリソグラフィ法によりレジストマスク２９２を形成する。レジストマスク２９２を用いて、ハードマスクとなる膜２９０Ａ、および絶縁膜２４５Ａの一部を選択的に除去することで、ハードマスク２９０Ｂ、および絶縁層２４５Ｂを形成する（図４）。 Next, a resist mask 292 is formed on the film 290A, which is a hard mask, by a photolithography method. The hard mask 290B and the insulating layer 245B are formed by selectively removing a part of the hard mask film 290A and the insulating film 245A using the resist mask 292 (FIG. 4).
　次に、ハードマスク２９０Ｂ、および絶縁層２４５Ｂを用いて、導電膜２４０Ａの一部を選択的に除去し、島状の導電層２４０Ｂを形成する（図５）。なお、このとき、ハードマスク２９０Ｂの一部、または全部が除去されてもよい。 Next, using the hard mask 290B and the insulating layer 245B, a part of the conductive film 240A is selectively removed to form an island-shaped conductive layer 240B (FIG. 5). At this time, a part or all of the hard mask 290B may be removed.
　続いて、島状の導電層２４０Ｂ、絶縁層２４５Ｂ、ハードマスク２９０Ｂをマスクとして酸化膜２３０Ａ、および酸化膜２３０Ｂの一部を選択的に除去する（図６）。なお、本工程において、同時に絶縁体２２４の一部も除去される場合がある。その後、ハードマスク２９０Ｂを除去することにより、島状の酸化物２３０ａ、島状の酸化物２３０ｂ、島状の導電層２４０Ｂ、島状の絶縁層２４５Ｂの積層構造を形成することができる（図６）。 Subsequently, a part of the oxide film 230A and the oxide film 230B is selectively removed using the island-shaped conductive layer 240B, the insulating layer 245B, and the hard mask 290B as masks (FIG. 6). In this step, a part of the insulator 224 may be removed at the same time. After that, by removing the hard mask 290B, a laminated structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B can be formed (FIG. 6). ).
　また、本工程において、ハードマスク２９０を用いて導電膜２４０Ａの加工を行うことで、導電体２４０の形状に不要なエッチング（ＣＤロスともいう）の形成を抑制することができる。 Further, in this step, by processing the conductive film 240A using the hard mask 290, it is possible to suppress the formation of etching (also referred to as CD loss) unnecessary for the shape of the conductor 240.
　例えば、レジストマスクを用いた場合、エッチング時にマスクがサイドエッチングされて、被加工物の端部表面が露出し、角部が丸くなる場合がある。導電体２４０において、当該不良が大きい場合、導電体２４０の体積が、設計値よりも減少し、オン電流が小さくなる場合がある。 For example, when a resist mask is used, the mask may be side-etched at the time of etching, the end surface of the workpiece may be exposed, and the corners may be rounded. In the conductor 240, when the defect is large, the volume of the conductor 240 may be smaller than the design value, and the on-current may be smaller.
　そこで、ハードマスクを用いることで、ハードマスクに対するエッチレートの選択比が大きい材質を被加工物として用いることで、エッチング時にハードマスクの形状が維持され、被加工物が形状不良となることを抑制できる。具体的には、ハードマスクに用いる材質のエッチレートを１とした場合、被加工物のエッチレートは５以上、好ましくは１０以上の材質をマスクとして用いるとよい。 Therefore, by using a hard mask, by using a material having a large selection ratio of the etch rate with respect to the hard mask as the workpiece, the shape of the hard mask is maintained at the time of etching, and it is possible to prevent the workpiece from becoming defective in shape. it can. Specifically, when the etch rate of the material used for the hard mask is 1, it is preferable to use a material having an etch rate of 5 or more, preferably 10 or more as the mask.
　次に、島状の酸化物２３０ａ、島状の酸化物２３０ｂ、島状の導電層２４０Ｂ、島状の絶縁層２４５Ｂの積層構造上に、絶縁膜２８０Ａを成膜する。絶縁膜２８０Ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁膜２８０Ａとして、ＣＶＤ法、またはスパッタリング法によって酸化シリコン膜を成膜する。なお、絶縁膜２８０Ａの成膜前に、加熱処理を行ってもよい。加熱処理は、減圧下で行い、大気に暴露することなく、連続して当該絶縁膜を成膜してもよい。このような処理を行うことによって、絶縁体２２４の表面などに吸着している水分および水素を除去し、さらに酸化物２３０ａ、酸化物２３０ｂ、および絶縁体２２４中の水分濃度および水素濃度を低減させることができる。上述した加熱処理条件を用いることができる。 Next, an insulating film 280A is formed on the laminated structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B. The insulating film 280A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, a silicon oxide film is formed as the insulating film 280A by a CVD method or a sputtering method. The heat treatment may be performed before the insulating film 280A is formed. The heat treatment may be performed under reduced pressure to continuously form the insulating film without exposing it to the atmosphere. By performing such a treatment, the water and hydrogen adsorbed on the surface of the insulator 224 and the like are removed, and the water concentration and the hydrogen concentration in the oxide 230a, the oxide 230b, and the insulator 224 are further reduced. be able to. The above-mentioned heat treatment conditions can be used.
　また、絶縁膜２８０Ａは、多層構造としてもよい。例えば、スパッタリング法によって酸化シリコン膜を成膜し、当該酸化シリコン膜上に、ＣＶＤ法によって酸化シリコン膜を成膜する構造としてもよい。 Further, the insulating film 280A may have a multilayer structure. For example, the structure may be such that a silicon oxide film is formed by a sputtering method and a silicon oxide film is formed on the silicon oxide film by a CVD method.
　次に、絶縁膜２８０ＡにＣＭＰ処理を行い、上面が平坦な絶縁体２８０を形成する（図６参照。）。 Next, the insulating film 280A is subjected to CMP treatment to form an insulator 280 having a flat upper surface (see FIG. 6).
　次に、絶縁体２８０の一部、および導電層２４０Ｂの一部を加工して、酸化物２３０ｂに達する開口を形成する。当該開口は、導電体２０５と重なるように形成することが好ましい。当該開口の形成によって、導電体２４０ａ、導電層２４０Ｂ、絶縁体２４５ａ、および絶縁層２４５Ｂを形成する。このとき、酸化物２３０ｂの当該開口と重なる領域の膜厚が薄くなる場合がある（図７参照。）。 Next, a part of the insulator 280 and a part of the conductive layer 240B are processed to form an opening reaching the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 240a, the conductive layer 240B, the insulator 245a, and the insulating layer 245B are formed. At this time, the film thickness of the region overlapping the opening of the oxide 230b may be reduced (see FIG. 7).
　また、絶縁体２８０の一部、絶縁層２４５Ｂの一部、および導電層２４０Ｂの一部の加工は、それぞれ異なる条件で加工してもよい。例えば、絶縁体２８０の一部をドライエッチング法で加工し、絶縁層２４５Ｂの一部をウェットエッチング法で加工し、導電層２４０Ｂの一部をドライエッチング法で加工してもよい。 Further, the processing of a part of the insulator 280, a part of the insulating layer 245B, and a part of the conductive layer 240B may be processed under different conditions. For example, a part of the insulator 280 may be processed by a dry etching method, a part of the insulating layer 245B may be processed by a wet etching method, and a part of the conductive layer 240B may be processed by a dry etching method.
　ここで、酸化物２３０ａ、酸化物２３０ｂなどの表面に付着または内部に拡散した不純物を除去することが好ましい。当該不純物としては、絶縁体２８０、絶縁層２４５Ｂ、および導電層２４０Ｂに含まれる成分、上記開口を形成する際に用いられる装置に使われている部材に含まれる成分、エッチングに使用するガスまたは液体に含まれる成分などに起因したものが挙げられる。当該不純物としては、例えば、アルミニウム、シリコン、タンタル、フッ素、塩素などがある。 Here, it is preferable to remove impurities adhering to or diffused inside the surface such as oxide 230a and oxide 230b. Examples of the impurities include components contained in the insulator 280, the insulating layer 245B, and the conductive layer 240B, components contained in the member used in the apparatus used for forming the opening, and gas or liquid used for etching. Examples include those caused by the components contained in. Examples of the impurities include aluminum, silicon, tantalum, fluorine, chlorine and the like.
　上記の不純物などを除去するために、洗浄処理を行ってもよい。洗浄方法としては、洗浄液など用いたウェット洗浄、プラズマを用いたプラズマ処理、熱処理による洗浄などがあり、上記洗浄を適宜組み合わせて行ってもよい。 A cleaning treatment may be performed to remove the above impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.
　ウェット洗浄としては、アンモニア水、シュウ酸、リン酸、フッ化水素酸などを炭酸水または純水で希釈した水溶液、純水、炭酸水などを用いて洗浄処理を行ってもよい。また、これらの水溶液、純水、または炭酸水を用いた超音波洗浄を行ってもよい。また、これらの洗浄を適宜組み合わせて行ってもよい。 As the wet cleaning, the cleaning treatment may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water, pure water, carbonated water or the like. Further, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Moreover, you may perform these washings in combination as appropriate.
　次に加熱処理を行ってもよい。当該加熱処理は、酸素を含む雰囲気下で行うと好適である。また、当該加熱処理は、減圧下で行い、大気に暴露することなく、連続して酸化膜２３０Ｃを成膜してもよい（図８参照。）。このような処理を行うことによって、酸化物２３０ｂの表面などに吸着している水分および水素を除去し、さらに酸化物２３０ａおよび酸化物２３０ｂ中の水分濃度および水素濃度を低減させることができる。加熱処理の温度は、１００℃以上４００℃以下が好ましい。本実施の形態では、加熱処理の温度を２００℃とする。 Next, heat treatment may be performed. It is preferable that the heat treatment is performed in an atmosphere containing oxygen. Further, the heat treatment may be carried out under reduced pressure to continuously form the oxide film 230C without exposing it to the atmosphere (see FIG. 8). By performing such a treatment, the water and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and the water concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200 ° C.
　酸化膜２３０Ｃの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。酸化膜２３０Ｃに求める特性に合わせて、酸化膜２３０Ａ、または酸化膜２３０Ｂと同様の成膜方法を用いて、酸化膜２３０Ｃを成膜すればよい。本実施の形態では、酸化膜２３０Ｃとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］、または４：２：４．１［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて成膜する。または、酸化膜２３０Ｃとして、スパッタリング法によって、４：２：４．１［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて成膜し、その上にＩｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のＩｎ−Ｇａ−Ｚｎ酸化物ターゲットを用いて成膜する。 The oxide film 230C can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C. In the present embodiment, the oxide film 230C is In-Ga- with In: Ga: Zn = 1: 3: 4 [atomic number ratio] or 4: 2: 4.1 [atomic number ratio] by the sputtering method. A film is formed using a Zn oxide target. Alternatively, as the oxide film 230C, a film is formed by a sputtering method using an In-Ga-Zn oxide target having a ratio of 4: 2: 4.1 [atomic number ratio], and In: Ga: Zn = 1: A film is formed using an In-Ga-Zn oxide target having a ratio of 3: 4 [atomic number ratio].
　特に、酸化膜２３０Ｃの成膜時に、スパッタリングガスに含まれる酸素の一部が酸化物２３０ａおよび酸化物２３０ｂに供給される場合がある。したがって、酸化膜２３０Ｃのスパッタリングガスに含まれる酸素の割合は７０％以上、好ましくは８０％以上、より好ましくは１００％とすればよい。 In particular, when the oxide film 230C is formed, a part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.
　次に加熱処理を行ってもよい。加熱処理は、減圧下で行い、大気に暴露することなく、連続して絶縁膜２５０Ａを成膜してもよい。このような処理を行うことによって、酸化膜２３０Ｃの表面などに吸着している水分および水素を除去し、さらに酸化物２３０ａ、酸化物２３０ｂ、および酸化膜２３０Ｃ中の水分濃度および水素濃度を低減させることができる。加熱処理の温度は、１００℃以上４００℃以下が好ましい。 Next, heat treatment may be performed. The heat treatment may be performed under reduced pressure to continuously form the insulating film 250A without exposing it to the atmosphere. By performing such a treatment, the water and hydrogen adsorbed on the surface of the oxide film 230C and the like are removed, and the water concentration and the hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C are further reduced. be able to. The temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower.
　絶縁膜２５０Ａは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて成膜することができる（図８参照。）。本実施の形態では、絶縁膜２５０Ａとして、ＣＶＤ法により、酸化窒化シリコンを成膜する。なお、絶縁膜２５０Ａを成膜する際の成膜温度は、３５０℃以上４５０℃未満、特に４００℃前後とすることが好ましい。絶縁膜２５０Ａを、４００℃で成膜することで、不純物が少ない絶縁膜を成膜することができる。 The insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 8). In the present embodiment, silicon oxide nitride is formed as the insulating film 250A by the CVD method. The film forming temperature at the time of forming the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly around 400 ° C. By forming the insulating film 250A at 400 ° C., an insulating film having few impurities can be formed.
　次に、導電膜２６０Ａ、導電膜２６０Ｂを順に成膜する。導電膜２６０Ａおよび導電膜２６０Ｂの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。本実施の形態では、ＡＬＤ法を用いて、導電膜２６０Ａを成膜し、ＣＶＤ法を用いて導電膜２６０Ｂを成膜する（図８参照。）。 Next, the conductive film 260A and the conductive film 260B are formed in this order. The film formation of the conductive film 260A and the conductive film 260B can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, the conductive film 260A is formed by using the ALD method, and the conductive film 260B is formed by using the CVD method (see FIG. 8).
　次に、ＣＭＰ処理によって、酸化膜２３０Ｃ、絶縁膜２５０Ａ、導電膜２６０Ａ、および導電膜２６０Ｂを絶縁体２８０が露出するまで研磨することによって、酸化物２３０ｃ、絶縁体２５０、および導電体２６０（導電体２６０ａ、および導電体２６０ｂ）を形成する（図９参照。）。これにより、酸化物２３０ｃは、酸化物２３０ｂに達する開口の内壁（側壁、および底面）を覆うように配置される。また、絶縁体２５０は、酸化物２３０ｃを介して、上記開口の内壁を覆うように配置される。また、導電体２６０は、酸化物２３０ｃおよび絶縁体２５０を介して、上記開口を埋め込むように配置される。 Next, by CMP treatment, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed, whereby the oxide 230c, the insulator 250, and the conductor 260 (conductive). The body 260a and the conductor 260b) are formed (see FIG. 9). Thereby, the oxide 230c is arranged so as to cover the inner wall (side wall and bottom surface) of the opening reaching the oxide 230b. Further, the insulator 250 is arranged so as to cover the inner wall of the opening via the oxide 230c. Further, the conductor 260 is arranged so as to embed the opening via the oxide 230c and the insulator 250.
　次に、加熱処理を行ってもよい。本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行う。該加熱処理によって、絶縁体２５０および絶縁体２８０中の水分濃度および水素濃度を低減させることができる。 Next, heat treatment may be performed. In the present embodiment, the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour. By the heat treatment, the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
　次に、酸化物２３０ｃ、絶縁体２５０、導電体２６０、および絶縁体２８０上に、絶縁体２８２を成膜する。絶縁体２８２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる。絶縁体２８２としては、例えば、スパッタリング法によって、酸化アルミニウム膜、または窒化シリコン膜を成膜することが好ましい。スパッタリング法によって、酸化アルミニウム膜、または窒化シリコン膜を成膜することによって、絶縁体２８４が有する水素を酸化物２３０へ拡散することを抑制することができる。また、導電体２６０と接するように絶縁体２８２を形成することで、導電体２６０の酸化を抑制することができ、好ましい。 Next, the insulator 282 is formed on the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The film formation of the insulator 282 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, it is preferable to form an aluminum oxide film or a silicon nitride film by a sputtering method. By forming an aluminum oxide film or a silicon nitride film by a sputtering method, it is possible to suppress the diffusion of hydrogen contained in the insulator 284 to the oxide 230. Further, by forming the insulator 282 so as to be in contact with the conductor 260, oxidation of the conductor 260 can be suppressed, which is preferable.
　また、絶縁体２８２として、スパッタリング法によって、酸化アルミニウム膜を形成することで、絶縁体２８０に酸素を供給することができる。絶縁体２８０に供給された酸素は、酸化物２３０ｃを介して、酸化物２３０ｂが有するチャネル形成領域に供給される場合がある。また、絶縁体２８０に酸素が供給されることで、絶縁体２８２形成前に絶縁体２８０に含まれていた酸素が、酸化物２３０ｃを介して、酸化物２３０ｂが有するチャネル形成領域に供給される場合がある。 Further, as the insulator 282, oxygen can be supplied to the insulator 280 by forming an aluminum oxide film by a sputtering method. The oxygen supplied to the insulator 280 may be supplied to the channel forming region of the oxide 230b via the oxide 230c. Further, by supplying oxygen to the insulator 280, oxygen contained in the insulator 280 before the formation of the insulator 282 is supplied to the channel forming region of the oxide 230b via the oxide 230c. In some cases.
　また、絶縁体２８２は、多層構造としてもよい。例えば、スパッタリング法によって酸化アルミニウム膜を成膜し、当該酸化アルミニウム膜上に、スパッタリング法によって窒化シリコンを成膜する構造としてもよい。 Further, the insulator 282 may have a multi-layer structure. For example, the structure may be such that an aluminum oxide film is formed by a sputtering method and silicon nitride is formed on the aluminum oxide film by a sputtering method.
　次に、加熱処理を行ってもよい。加熱処理は、前述の加熱処理条件を用いることができる。当該加熱処理によって、絶縁体２８０の水分濃度および水素濃度を低減させることができる。また、絶縁体２８２が有する酸素を絶縁体２８０に注入することができる。 Next, heat treatment may be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. By the heat treatment, the water concentration and the hydrogen concentration of the insulator 280 can be reduced. Further, the oxygen contained in the insulator 282 can be injected into the insulator 280.
　なお、絶縁体２８２を成膜する前に、はじめに、絶縁体２８０などの上に、スパッタリング法によって酸化アルミニウム膜を成膜し、次に、上述した加熱処理条件を用いて加熱処理を行い、次に、ＣＭＰ処理によって、当該酸化アルミニウム膜を除去する工程を行ってもよい。当該工程により、絶縁体２８０に過剰酸素領域をより多く形成することができる。なお、当該工程において、絶縁体２８０の一部、導電体２６０の一部、絶縁体２５０の一部、および酸化物２３０ｃの一部が除去される場合がある。 Before forming the insulator 282, first, an aluminum oxide film is formed on the insulator 280 or the like by a sputtering method, and then heat treatment is performed using the above-mentioned heat treatment conditions. In addition, a step of removing the aluminum oxide film by CMP treatment may be performed. By this step, more excess oxygen regions can be formed in the insulator 280. In this step, a part of the insulator 280, a part of the conductor 260, a part of the insulator 250, and a part of the oxide 230c may be removed.
　また、絶縁体２８０と絶縁体２８２との間に、絶縁体を設けてもよい。当該絶縁体として、例えば、スパッタリング法を用いて成膜した酸化シリコンを用いればよい。当該絶縁体を設けることで、絶縁体２８０に過剰酸素領域を形成することができる。 Further, an insulator may be provided between the insulator 280 and the insulator 282. As the insulator, for example, silicon oxide formed by a sputtering method may be used. By providing the insulator, an excess oxygen region can be formed in the insulator 280.
　次に絶縁体２８２上に、絶縁体２８４を成膜してもよい。絶縁体２８４の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて行うことができる（図１参照。）。 Next, the insulator 284 may be formed on the insulator 282. The film formation of the insulator 284 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 1).
　以上により、図１に示すトランジスタ２００を有する半導体装置を作製することができる。 From the above, the semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured.
　また、トランジスタ２００の形成後、トランジスタ２００を囲むように開口を形成し、当該開口を覆うように、水素、または水に対するバリア性が高い絶縁体を形成してもよい。上述のバリア性の高い絶縁体でトランジスタ２００を包み込むことで、外部から水分、および水素が侵入するのを防止することができる。または、複数のトランジスタ２００をまとめて、水素、または水に対するバリア性が高い絶縁体で包み込んでもよい。なお、トランジスタ２００を囲むように開口を形成する場合、例えば、絶縁体２１４または絶縁体２２２に達する開口を形成し、絶縁体２１４または絶縁体２２２に接するように上述のバリア性の高い絶縁体を形成すると、トランジスタ２００の作製工程の一部を兼ねられるため、好適である。なお、水素、または水に対するバリア性が高い絶縁体としては、例えば、絶縁体２２２と同様の材料を用いればよい。 Further, after the transistor 200 is formed, an opening may be formed so as to surround the transistor 200, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening. By wrapping the transistor 200 with the above-mentioned insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, the plurality of transistors 200 may be put together and wrapped with an insulator having a high barrier property against hydrogen or water. When an opening is formed so as to surround the transistor 200, for example, an opening reaching the insulator 214 or the insulator 222 is formed, and the above-mentioned insulator having a high barrier property is provided so as to be in contact with the insulator 214 or the insulator 222. When formed, it is suitable because it can also serve as a part of the manufacturing process of the transistor 200. As the insulator having a high barrier property to hydrogen or water, for example, the same material as the insulator 222 may be used.
　本発明の一態様により、信頼性が良好な半導体装置を提供することができる。また、本発明の一態様により、良好な電気特性を有する半導体装置を提供することができる。また、本発明の一態様により、オン電流の大きい半導体装置を提供することができる。また、本発明の一態様により、微細化または高集積化が可能な半導体装置を提供することができる。また、本発明の一態様により、低消費電力の半導体装置を提供することができる。 According to one aspect of the present invention, it is possible to provide a semiconductor device having good reliability. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having good electrical characteristics. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Further, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Further, according to one aspect of the present invention, a semiconductor device having low power consumption can be provided.
＜半導体装置の変形例＞
　以下では、図１０を用いて、本発明の一態様に係るトランジスタ２００を有する半導体装置の一例について説明する。 <Modification example of semiconductor device>
Hereinafter, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described with reference to FIG.
　ここで、図１０Ａは上面図を示す。また、図１０Ｂは図１０Ａに示すＡ１−Ａ２の一点鎖線で示す部位に対応する断面図である。また、図１０Ｃは、図１０ＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図である。図１０Ａの上面図では、図の明瞭化のために一部の要素を省いて図示している。 Here, FIG. 10A shows a top view. Further, FIG. 10B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 10A. Further, FIG. 10C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line of A3-A4 in FIG. 10A. In the top view of FIG. 10A, some elements are omitted for the sake of clarity.
　図１０に示す半導体装置は、図２に示した半導体装置とは、酸化物２３０ｂが積層構造であることが異なる。また、酸化物２３０ｃが積層構造であることが異なる。また、絶縁体２７３、および絶縁体２７４を有することが異なる。 The semiconductor device shown in FIG. 10 is different from the semiconductor device shown in FIG. 2 in that the oxide 230b has a laminated structure. Another difference is that the oxide 230c has a laminated structure. It is also different from having an insulator 273 and an insulator 274.
　酸化物２３０ｃは、２層以上の積層構造を有していてもよい。例えば、図１０では、酸化物２３０ｃの第１の酸化物と、酸化物２３０ｃの第１の酸化物の上に配置された酸化物２３０ｃの第２の酸化物と、を有する。 The oxide 230c may have a laminated structure of two or more layers. For example, FIG. 10 has a first oxide of oxide 230c and a second oxide of oxide 230c disposed on top of the first oxide of oxide 230c.
　具体的には、酸化物２３０ｃの第１の酸化物は、酸化物２３０ｂに用いられる金属酸化物を構成する金属元素の少なくとも一つを含むことが好ましく、当該金属元素を全て含むことがより好ましい。例えば、酸化物２３０ｃの第１の酸化物として、Ｉｎ−Ｇａ−Ｚｎ酸化物を用い、酸化物２３０ｃの第２の酸化物として、Ｉｎ−Ｇａ−Ｚｎ酸化物、Ｇａ−Ｚｎ酸化物、または酸化ガリウムを用いるとよい。当該構造により、酸化物２３０ｂと酸化物２３０ｃの第１の酸化物との界面における欠陥準位密度を低くすることができる。 Specifically, the first oxide of the oxide 230c preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230b, and more preferably contains all the metal elements. .. For example, In-Ga-Zn oxide is used as the first oxide of the oxide 230c, and In-Ga-Zn oxide, Ga-Zn oxide, or oxidation is used as the second oxide of the oxide 230c. Gallium should be used. With this structure, the defect level density at the interface between the oxide 230b and the first oxide of the oxide 230c can be lowered.
　また、酸化物２３０ｃの第２の酸化物は、酸化物２３０ｃの第１の酸化物より、酸素の拡散または透過を抑制する金属酸化物であることが好ましい。絶縁体２５０と酸化物２３０ｃの第１の酸化物との間に酸化物２３０ｃの第２の酸化物を設けることで、絶縁体２８０に含まれる酸素が、絶縁体２５０に拡散するのを抑制することができる。したがって、当該酸素は、酸化物２３０ｃの第１の酸化物を介して、酸化物２３０ｂに供給されやすくなる。 Further, the second oxide of the oxide 230c is preferably a metal oxide that suppresses the diffusion or permeation of oxygen, rather than the first oxide of the oxide 230c. By providing the second oxide of the oxide 230c between the insulator 250 and the first oxide of the oxide 230c, oxygen contained in the insulator 280 is suppressed from diffusing into the insulator 250. be able to. Therefore, the oxygen is likely to be supplied to the oxide 230b via the first oxide of the oxide 230c.
　また、酸化物２３０ｃの第２の酸化物に用いる金属酸化物において、主成分である金属元素に対するＩｎの原子数比が、酸化物２３０ｃの第１の酸化物に用いる金属酸化物における、主成分である金属元素に対するＩｎの原子数比より小さくすることで、Ｉｎが絶縁体２５０側に拡散するのを抑制することができる。絶縁体２５０は、ゲート絶縁体として機能するため、Ｉｎが絶縁体２５０などに混入した場合、トランジスタの特性不良となる。したがって、酸化物２３０ｃを積層構造とすることで、信頼性の高い半導体装置を提供することが可能となる。 Further, in the metal oxide used for the second oxide of the oxide 230c, the atomic number ratio of In to the metal element as the main component is the main component in the metal oxide used for the first oxide of the oxide 230c. By making it smaller than the atomic number ratio of In to the metal element, In can be suppressed from diffusing to the insulator 250 side. Since the insulator 250 functions as a gate insulator, if In is mixed in the insulator 250 or the like, the characteristics of the transistor become poor. Therefore, by forming the oxide 230c in a laminated structure, it is possible to provide a highly reliable semiconductor device.
　また、酸化物２３０ｂは、２層以上の積層構造を有していてもよい。例えば、図１０では、酸化物２３０ｂの第１の酸化物と、酸化物２３０ｂの第１の酸化物の上に配置された酸化物２３０ｂの第２の酸化物と、を有する。 Further, the oxide 230b may have a laminated structure of two or more layers. For example, FIG. 10 has a first oxide of oxide 230b and a second oxide of oxide 230b disposed on top of the first oxide of oxide 230b.
　具体的には、酸化物２３０ｂの第２の酸化物は、酸化物２３０ｂの第１の酸化物と、ソース電極またはドレイン電極として機能する導電体２４０（導電体２４０ａよび導電体２４０ｂ）と、の間に設けるとよい。当該構造において、酸化物２３０ｂの第２の酸化物は、酸素の透過を抑制する機能を有することが好ましい。 Specifically, the second oxide of the oxide 230b is composed of the first oxide of the oxide 230b and the conductor 240 (conductor 240a and conductor 240b) that functions as a source electrode or a drain electrode. It is good to provide it in between. In the structure, the second oxide of the oxide 230b preferably has a function of suppressing the permeation of oxygen.
　従って、ソース電極やドレイン電極として機能する導電体２４０と酸化物２３０ｂの第１の酸化物との間に酸素の透過を抑制する機能を有する酸化物２３０ｂの第２の酸化物を配置することで、導電体２４０と、酸化物２３０ｂの第１の酸化物との間の電気抵抗が低減されるので好ましい。このような構成とすることで、トランジスタ２００の電気特性および信頼性を向上させることができる。 Therefore, by arranging the second oxide of the oxide 230b having the function of suppressing the permeation of oxygen between the conductor 240 functioning as the source electrode or the drain electrode and the first oxide of the oxide 230b. , It is preferable because the electric resistance between the conductor 240 and the first oxide of the oxide 230b is reduced. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved.
　つまり、導電体２４０と、酸化物２３０ｂの第１の酸化物とが接しない構成となるので、導電体２４０が、酸化物２３０ｂの第１の酸化物の酸素を吸収することを抑制できる。導電体２４０の酸化を防止することで、導電体２４０の導電率の低下を抑制することができる。 That is, since the conductor 240 and the first oxide of the oxide 230b do not come into contact with each other, it is possible to suppress the conductor 240 from absorbing the oxygen of the first oxide of the oxide 230b. By preventing the conductor 240 from being oxidized, it is possible to suppress a decrease in the conductivity of the conductor 240.
　酸化物２３０ｂの第２の酸化物として、元素Ｍを有する金属酸化物を用いてもよい。特に、元素Ｍは、アルミニウム、ガリウム、イットリウム、または錫を用いるとよい。酸化物２３０ｂの第２の酸化物は、酸化物２３０ｂの第１の酸化物よりも元素Ｍの濃度が高いことが好ましい。また、酸化物２３０ｂの第２の酸化物として、酸化ガリウムを用いてもよい。また、酸化物２３０ｂの第２の酸化物として、Ｉｎ−Ｍ−Ｚｎ酸化物等の金属酸化物を用いてもよい。 As the second oxide of the oxide 230b, a metal oxide having an element M may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. The second oxide of the oxide 230b preferably has a higher concentration of element M than the first oxide of the oxide 230b. Further, gallium oxide may be used as the second oxide of the oxide 230b. Further, as the second oxide of the oxide 230b, a metal oxide such as In—M—Zn oxide may be used.
　具体的には、酸化物２３０ｂの第２の酸化物に用いる金属酸化物において、Ｉｎに対する元素Ｍの原子数比が、酸化物２３０ｂの第１の酸化物に用いる金属酸化物における、Ｉｎに対する元素Ｍの原子数比より大きいことが好ましい。また、酸化物２３０ｂの第２の酸化物の膜厚は、０．５ｎｍ以上５ｎｍ以下が好ましく、より好ましくは、１ｎｍ以上３ｎｍ以下である。また、酸化物２３０ｂの第２の酸化物は、結晶性を有すると好ましい。酸化物２３０ｂの第２の酸化物が、結晶性を有する場合、酸化物２３０ｂの第１の酸化物中の酸素の放出を低減することが出来る。例えば、酸化物２３０ｂの第２の酸化物としては、六方晶などの結晶構造であれば、酸化物２３０ｂの第１の酸化物中の酸素の放出を抑制できる場合がある。 Specifically, in the metal oxide used for the second oxide of the oxide 230b, the atomic number ratio of the element M to In is the element to In in the metal oxide used for the first oxide of the oxide 230b. It is preferably larger than the number of atoms ratio of M. The film thickness of the second oxide of the oxide 230b is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. Moreover, it is preferable that the second oxide of the oxide 230b has crystalline property. When the second oxide of the oxide 230b has crystalline property, the release of oxygen in the first oxide of the oxide 230b can be reduced. For example, if the second oxide of the oxide 230b has a crystal structure such as a hexagonal crystal, the release of oxygen in the first oxide of the oxide 230b may be suppressed.
　また、導電体２４０（導電体２４０ａ、および導電体２４０ｂ）と酸化物２３０とが接することで、酸化物２３０中の酸素が導電体２４０へ拡散し、導電体２４０が酸化する場合がある。導電体２４０が酸化することで、導電体２４０の導電率が低下する蓋然性が高い。なお、酸化物２３０中の酸素が導電体２４０へ拡散することを、導電体２４０が酸化物２３０中の酸素を吸収する、と言い換えることができる。 Further, when the conductor 240 (conductor 240a and the conductor 240b) and the oxide 230 come into contact with each other, oxygen in the oxide 230 may diffuse to the conductor 240 and the conductor 240 may be oxidized. It is highly probable that the conductivity of the conductor 240 will decrease due to the oxidation of the conductor 240. The diffusion of oxygen in the oxide 230 to the conductor 240 can be rephrased as the conductor 240 absorbing the oxygen in the oxide 230.
　また、酸化物２３０（代表的には酸化物２３０ｂ）中の酸素が導電体２４０へ拡散することで、導電体２４０と酸化物２３０との間に異層が形成される場合がある。当該異層は、導電体２４０よりも酸素を多く含むため、当該異層は絶縁性を有すると推定される。このとき、導電体２４０と、当該異層と、酸化物２３０との３層構造は、金属−絶縁体−半導体からなる３層構造とみなすことができ、ＭＩＳ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構造と呼ぶ、またはＭＩＳ構造を主としたダイオード接合構造と呼ぶ場合がある。 Further, oxygen in the oxide 230 (typically the oxide 230b) may diffuse to the conductor 240 to form a different layer between the conductor 240 and the oxide 230. Since the different layer contains more oxygen than the conductor 240, it is presumed that the different layer has insulating properties. At this time, the three-layer structure of the conductor 240, the different layer, and the oxide 230 can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and has a MIS (Metal-Insulator-Semiconductor) structure. It may be called, or it may be called a diode junction structure mainly composed of a MIS structure.
　また、導電体２４０の上面と、酸化物２３０ａ、酸化物２３０ｂ、および導電体２４０の側面とを覆うように、バリア性を有する絶縁体２７３を設けてもよい。なお、絶縁体２７３を設ける場合、絶縁体２４５は必ずしも設けなくともよい。 Further, an insulator 273 having a barrier property may be provided so as to cover the upper surface of the conductor 240 and the side surfaces of the oxide 230a, the oxide 230b, and the conductor 240. When the insulator 273 is provided, the insulator 245 does not necessarily have to be provided.
　例えば、酸化物２３０の導電体２４０と重畳する領域は、導電体２４０の金属元素が添加、または導電体２４０に酸素が吸収され酸素欠損が生じる。つまり、酸化物２３０の導電体２４０と接する面近傍は、局地的に低抵抗化する場合がある。酸化物２３０の導電体２４０とが重畳する領域が低抵抗化することで、トランジスタ２００のオン電流を向上させることができる。 For example, in the region where the oxide 230 overlaps with the conductor 240, a metal element of the conductor 240 is added, or oxygen is absorbed by the conductor 240, causing oxygen deficiency. That is, the resistance of the oxide 230 in the vicinity of the surface in contact with the conductor 240 may be locally reduced. By lowering the resistance of the region where the oxide 230 overlaps with the conductor 240, the on-current of the transistor 200 can be improved.
　一方、絶縁体２８０が有する過剰酸素は、導電体２４０と重畳する領域の酸化物２３０における側面から、酸化物２３０へと拡散するため、導電体２４０と重畳する領域の酸化物２３０に生じた局地的な低抵抗化領域が減少し、トランジスタ２００のオン電流が低下する場合がある。 On the other hand, the excess oxygen contained in the insulator 280 diffuses from the side surface of the oxide 230 in the region overlapping the conductor 240 to the oxide 230, so that the station generated in the oxide 230 in the region overlapping the conductor 240 is generated. The geologically low resistance region may decrease, and the on-current of the transistor 200 may decrease.
　そこで、絶縁体２７３を設けることで、導電体２４０と重畳する領域の酸化物２３０における側面から、絶縁体２８０が有する過剰酸素が供給されることを抑制することができる。一方で、絶縁体２８０が有する過剰酸素は、酸化物２３０ｃを介して、酸化物２３０ｂのチャネル形成領域へと供給することができる。従って、酸化物２３０の導電体２４０と接する面近傍に生じた低抵抗化領域が減少することなく、酸化物２３０のチャネル形成領域に生じた酸素欠損を、効率よく補償することができる。 Therefore, by providing the insulator 273, it is possible to suppress the supply of excess oxygen contained in the insulator 280 from the side surface of the oxide 230 in the region overlapping with the conductor 240. On the other hand, the excess oxygen contained in the insulator 280 can be supplied to the channel forming region of the oxide 230b via the oxide 230c. Therefore, the oxygen deficiency generated in the channel forming region of the oxide 230 can be efficiently compensated without reducing the resistance-reducing region generated in the vicinity of the surface of the oxide 230 in contact with the conductor 240.
　また、絶縁体２２４が過剰酸素領域を有している場合、酸化物２３０において、酸化物２３０ａを介して、絶縁体２２４が有する過剰酸素が酸化物２３０ｂへと拡散する。つまり、酸化物２３０ａ側から、過剰酸素を供給することができる。従って、酸化物２３０の導電体２４０と接する面近傍に生じた低抵抗化領域の減少を抑制しながら、酸化物２３０のチャネル形成領域に生じた酸素欠損を、補償することができる。 Further, when the insulator 224 has an excess oxygen region, in the oxide 230, the excess oxygen of the insulator 224 diffuses into the oxide 230b via the oxide 230a. That is, excess oxygen can be supplied from the oxide 230a side. Therefore, it is possible to compensate for the oxygen deficiency generated in the channel formation region of the oxide 230 while suppressing the decrease of the low resistance region generated in the vicinity of the surface of the oxide 230 in contact with the conductor 240.
　なお、絶縁体２７３は、スパッタリング装置を用いて成膜した酸化アルミニウム膜を用いるとよい。絶縁体２７３として、酸化アルミニウム膜を、酸素ガス雰囲気下で成膜を行うことで、絶縁体２７３を成膜しながら、絶縁体２２４に過剰酸素を導入することができる。 As the insulator 273, it is preferable to use an aluminum oxide film formed by using a sputtering apparatus. By forming an aluminum oxide film as the insulator 273 in an oxygen gas atmosphere, excess oxygen can be introduced into the insulator 224 while forming the insulator 273.
　また、絶縁体２７３上に絶縁体２７４を設けてもよい。なお、絶縁体２７４は、絶縁体２７３と同様に、酸素の拡散を抑制する機能を有することが好ましい。 Further, the insulator 274 may be provided on the insulator 273. The insulator 274, like the insulator 273, preferably has a function of suppressing the diffusion of oxygen.
　具体的には、スパッタリング法で成膜した絶縁体２７３は、被膜性が低い。従って、絶縁体２７４は、ＡＬＤ法を用いて、成膜することが好ましい。ＡＬＤ法は、段差被覆性と、厚さの均一性に優れた膜を成膜できるため、被処理物の形状の影響を受けにくく、良好な段差被覆性を有するためである。 Specifically, the insulator 273 formed by the sputtering method has a low film property. Therefore, it is preferable that the insulator 274 is formed into a film by using the ALD method. This is because the ALD method can form a film having excellent step covering property and thickness uniformity, so that it is not easily affected by the shape of the object to be treated and has good step covering property.
＜半導体装置の応用例＞
　以下では、図１１を用いて、本実施の形態に係るトランジスタ２００を有する半導体装置に、本発明の一態様の層間膜の積層構造、およびプラグを応用した一例を説明する。 <Application example of semiconductor device>
Hereinafter, an example in which the multilayer structure of the interlayer film of one aspect of the present invention and the plug are applied to the semiconductor device having the transistor 200 according to the present embodiment will be described with reference to FIG.
　ここで、図１１Ａは上面図を示す。また、図１１Ｂは図１１Ａに示すＡ１−Ａ２の一点鎖線で示す部位に対応する断面図である。また、図１１Ｃは、図１１ＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図である。また、図１１Ｄは、図１１ＡにＡ５−Ａ６の一点鎖線で示す部位に対応する断面図である。図１１Ａの上面図では、図の明瞭化のために一部の要素を省いて図示している。 Here, FIG. 11A shows a top view. Further, FIG. 11B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 11A. 11C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in A3-A4 in FIG. 11A. Further, FIG. 11D is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 11A. In the top view of FIG. 11A, some elements are omitted for the sake of clarity.
　図１１に示す半導体装置おいて、絶縁体２８０、絶縁体２８２、絶縁体２８３、および絶縁体２８４は、トランジスタ２００を露出する開口部を有する。また、当該開口部内には、トランジスタ２００と接続するプラグとして機能する導電体２４６（導電体２４６ａ、導電体２４６ｂ）を有する。また、開口部の側面に、絶縁体２４７を有する。 In the semiconductor device shown in FIG. 11, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 have an opening for exposing the transistor 200. Further, in the opening, there is a conductor 246 (conductor 246a, conductor 246b) that functions as a plug for connecting to the transistor 200. In addition, an insulator 247 is provided on the side surface of the opening.
　なお、導電体２４６は、トランジスタ２００と電気的に接続するプラグ、または配線としての機能を有する。 The conductor 246 has a function as a plug or wiring that electrically connects to the transistor 200.
　また、図１１に示す半導体装置は、トランジスタ２００の上下にバリア層として機能する絶縁体２１２、および絶縁体２８３を有する。また、絶縁体２１２と絶縁体２８３とは、トランジスタ２００の側面、または基板の端部となる領域において、接する。つまり、図１１に示す半導体装置は、トランジスタ２００と過剰酸素領域を有する絶縁体２８０とを、バリア層により封止する構造を有する。 Further, the semiconductor device shown in FIG. 11 has an insulator 212 and an insulator 283 that function as a barrier layer above and below the transistor 200. Further, the insulator 212 and the insulator 283 are in contact with each other in a side surface of the transistor 200 or a region serving as an end portion of the substrate. That is, the semiconductor device shown in FIG. 11 has a structure in which the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.
　また、絶縁体２１２と絶縁体２８３とが接する領域は、スクライブラインに沿って設けてもよい。また、例えば、複数のトランジスタ２００をマトリクス状に配置する場合、複数のトランジスタが排列する行列に沿うように、絶縁体２１２と絶縁体２８３とが接する領域を設けてもよい。 Further, the region where the insulator 212 and the insulator 283 are in contact with each other may be provided along the scribe line. Further, for example, when a plurality of transistors 200 are arranged in a matrix, a region in which the insulator 212 and the insulator 283 are in contact with each other may be provided so as to follow a matrix in which the plurality of transistors are arranged.
　なお、絶縁体２１２と絶縁体２８３とが接する領域を基板の端部に設ける場合、当該領域をスクライブラインと重畳して設けてもよい。 When a region in contact between the insulator 212 and the insulator 283 is provided at the end of the substrate, the region may be provided so as to overlap with the scribe line.
　なお、絶縁体２８３は、絶縁体２８２上に設ける。絶縁体２８４は、導電体２４８を加工する場合に、導電体２４８に対し、エッチレートの選択比が大きい材質を用いている。従って、絶縁体２８４は、必要に応じて絶縁体２８３上に設けるとよい。 The insulator 283 is provided on the insulator 282. When processing the conductor 248, the insulator 284 uses a material having a large etch rate selection ratio with respect to the conductor 248. Therefore, the insulator 284 may be provided on the insulator 283 as needed.
　また、絶縁体２４７は、絶縁体２８３と接することが好ましい。絶縁体２４７と絶縁体２８３が接することで、トランジスタ２００と過剰酸素領域を有する絶縁体２８０とを、バリア層により、封止する構造を有する。 Further, it is preferable that the insulator 247 is in contact with the insulator 283. When the insulator 247 and the insulator 283 are in contact with each other, the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.
　具体的には、絶縁体２８３、絶縁体２８２、および絶縁体２８０の開口の側壁に接して、絶縁体２４７が設けられ、その側面に接して導電体２４６が形成されている。当該開口の底部の少なくとも一部にはトランジスタ２００が位置しており、導電体２４６は、トランジスタ２００と接する。 Specifically, the insulator 247 is provided in contact with the side wall of the opening of the insulator 283, the insulator 282, and the insulator 280, and the conductor 246 is formed in contact with the side surface thereof. The transistor 200 is located at least a part of the bottom of the opening, and the conductor 246 is in contact with the transistor 200.
　なお、＜半導体装置の変形例＞および＜半導体装置の応用例＞において、＜半導体装置の構成例＞に示した半導体装置を構成する構造と同機能を有する構造には、同符号を付記する。なお、当該項目においても、半導体装置の構成材料については＜半導体装置の構成例＞で詳細に説明した材料を用いることができる。 In <Modification example of semiconductor device> and <Application example of semiconductor device>, the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices shown in <Semiconductor device configuration example>. In this item as well, the materials described in detail in <Semiconductor device configuration example> can be used as the constituent materials of the semiconductor device.
　以上より、信頼性が良好な半導体装置を提供することができる。また、良好な電気特性を有する半導体装置を提供することができる。また、微細化または高集積化が可能な半導体装置を提供することができる。また、低消費電力の半導体装置を提供することができる。 From the above, it is possible to provide a semiconductor device with good reliability. Further, it is possible to provide a semiconductor device having good electrical characteristics. Further, it is possible to provide a semiconductor device capable of miniaturization or high integration. Further, it is possible to provide a semiconductor device having low power consumption.
　以上、本実施の形態に示す構成、方法などは、他の実施の形態や実施例に示す構成、方法などと適宜組み合わせて用いることができる。 As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments and examples.
（実施の形態３）
　本実施の形態では、半導体装置の一形態を、図１２および図１３を用いて説明する。 (Embodiment 3)
In this embodiment, one embodiment of the semiconductor device will be described with reference to FIGS. 12 and 13.
［記憶装置１］
　本発明の一態様である容量素子を使用した、半導体装置（記憶装置）の一例を図１２に示す。本発明の一態様の半導体装置は、トランジスタ２００はトランジスタ３００の上方に設けられ、容量素子１００はトランジスタ２００の上方に設けられている。容量素子１００、またはトランジスタ３００は、少なくとも一部がトランジスタ２００と重畳することが好ましい。これにより、容量素子１００、トランジスタ２００、およびトランジスタ３００の上面視における占有面積を低減することができるので、本実施の形態に係る半導体装置を微細化または高集積化させることができる。なお、本実施の形態に係る半導体装置は、例えば、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）またはＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）に代表されるロジック回路、あるいはＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）またはＮＶＭ（Ｎｏｎ−Ｖｏｌａｔｉｌｅ　Ｍｅｍｏｒｙ）に代表されるメモリ回路に適用することができる。 [Storage device 1]
FIG. 12 shows an example of a semiconductor device (storage device) using a capacitive element which is one aspect of the present invention. In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 200. It is preferable that at least a part of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. As a result, the occupied area of the capacitive element 100, the transistor 200, and the transistor 300 in the top view can be reduced, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated. The semiconductor device according to the present embodiment is, for example, a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a DRAM (Dynamic Random Access Memory) or NVM (Non-Volatile Memory). It can be applied to a memory circuit represented by.
　なお、トランジスタ２００として、先の実施の形態で説明したトランジスタ２００を用いることができる。よって、トランジスタ２００、およびトランジスタ２００を含む層については、先の実施の形態の記載を参酌することができる。 As the transistor 200, the transistor 200 described in the previous embodiment can be used. Therefore, for the transistor 200 and the layer including the transistor 200, the description of the previous embodiment can be taken into consideration.
　トランジスタ２００は、酸化物半導体を有する半導体層にチャネルが形成されるトランジスタである。トランジスタ２００は、オフ電流が小さいため、これを記憶装置に用いることにより長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、あるいは、リフレッシュ動作の頻度が極めて少ないため、記憶装置の消費電力を十分に低減することができる。また、半導体層にシリコンを用いるトランジスタと比較して、トランジスタ２００は、高温における電気特性が良好である。例えば、トランジスタ２００は、１２５℃乃至１５０℃の温度範囲においても良好な電気特性を示す。また、１２５℃乃至１５０℃の温度範囲において、トランジスタ２００は、トランジスタのオン／オフ比が１０桁以上を有する。別言すると、半導体層にシリコンを用いるトランジスタと比較して、トランジスタ２００は、トランジスタ特性の一例であるオン電流、周波数特性などが高温になるほど優れた特性を有する。 The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced. Further, the transistor 200 has better electrical characteristics at high temperatures than a transistor using silicon for the semiconductor layer. For example, the transistor 200 exhibits good electrical characteristics even in the temperature range of 125 ° C to 150 ° C. Further, in the temperature range of 125 ° C. to 150 ° C., the transistor 200 has a transistor on / off ratio of 10 digits or more. In other words, the transistor 200 has better characteristics as the on-current, frequency characteristics, and the like, which are examples of transistor characteristics, become higher than those of a transistor using silicon for the semiconductor layer.
　図１２に示す半導体装置において、配線１００１はトランジスタ３００のソースと電気的に接続され、配線１００２はトランジスタ３００のドレインと電気的に接続され、配線１００７はトランジスタ３００のゲートと電気的に接続されている。また、配線１００３はトランジスタ２００のソースおよびドレインの一方と電気的に接続され、配線１００４はトランジスタ２００の第１のゲートと電気的に接続され、配線１００６はトランジスタ２００の第２のゲートと電気的に接続されている。そして、トランジスタ２００のソースおよびドレインの他方は、容量素子１００の電極の一方と電気的に接続され、配線１００５は容量素子１００の電極の他方と電気的に接続されている。 In the semiconductor device shown in FIG. 12, the wiring 1001 is electrically connected to the source of the transistor 300, the wiring 1002 is electrically connected to the drain of the transistor 300, and the wiring 1007 is electrically connected to the gate of the transistor 300. There is. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. The other of the source and drain of the transistor 200 is electrically connected to one of the electrodes of the capacitance element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitance element 100.
　図１２に示す半導体装置は、トランジスタ２００のスイッチングによって、容量素子１００の電極の一方に充電された電荷が保持可能という特性を有することで、情報の書き込み、保持、読み出しが可能である。また、トランジスタ２００は、ソース、ゲート（トップゲート）、ドレインに加え、バックゲートが設けられた素子である。すなわち、４端子素子であるため、ＭＴＪ（Ｍａｇｎｅｔｉｃ　Ｔｕｎｎｅｌ　Ｊｕｎｃｔｉｏｎ）特性を利用したＭＲＡＭ（Ｍａｇｎｅｔｏｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＲｅＲＡＭ（Ｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、相変化メモリ（Ｐｈａｓｅ−ｃｈａｎｇｅ　ｍｅｍｏｒｙ）などに代表される２端子素子と比較して、入出力の独立制御が簡便に行うことができるといった特徴を有する。また、ＭＲＡＭ、ＲｅＲＡＭ、相変化メモリは、情報の書き換えの際に、原子レベルで構造変化が生じる場合がある。一方で図１２に示す半導体装置は、情報の書き換えの際にトランジスタ及び容量素子を利用した電子のチャージ、またはディスチャージにより動作するため、繰り返し書き換え耐性に優れ、構造変化も少ないといった特徴を有する。 The semiconductor device shown in FIG. 12 has a characteristic that the charged charge can be held in one of the electrodes of the capacitive element 100 by switching the transistor 200, so that information can be written, held, and read out. Further, the transistor 200 is an element provided with a back gate in addition to a source, a gate (top gate), and a drain. That is, since it is a 4-terminal element, MRAM (Magnetoresistive Random Access Memory) utilizing MTJ (Magnetic Tunnel Junction) characteristics, ReRAM (Resistive Random Access Memory), ReRAM (Resistive Random Access Memory), etc. Compared to terminal elements, it has the feature that independent control of input and output can be performed easily. Further, the MRAM, the ReRAM, and the phase change memory may undergo a structural change at the atomic level when the information is rewritten. On the other hand, the semiconductor device shown in FIG. 12 operates by charging or discharging electrons using a transistor and a capacitive element when rewriting information, so that it has excellent resistance to repeated rewriting and has few structural changes.
　また、図１２に示す半導体装置は、マトリクス状に配置することで、メモリセルアレイを構成することができる。この場合、トランジスタ３００は、当該メモリセルアレイに接続される読み出し回路、または駆動回路などとして用いることができる。また、図１２に示す半導体装置は、上述のようにメモリセルアレイを構成している。図１２に示す半導体装置をメモリ素子として用いた場合、例えば、駆動電圧が２．５Ｖ、評価環境温度が−４０℃乃至８５℃の範囲において、２００ＭＨｚ以上の動作周波数を実現することができる。 Further, the semiconductor devices shown in FIG. 12 can form a memory cell array by arranging them in a matrix. In this case, the transistor 300 can be used as a read circuit, a drive circuit, or the like connected to the memory cell array. Further, the semiconductor device shown in FIG. 12 constitutes a memory cell array as described above. When the semiconductor device shown in FIG. 12 is used as a memory element, for example, an operating frequency of 200 MHz or more can be realized in a range of a drive voltage of 2.5 V and an evaluation environment temperature of −40 ° C. to 85 ° C.
＜トランジスタ３００＞
　トランジスタ３００は、基板３１１上に設けられ、ゲート電極として機能する導電体３１６、ゲート絶縁体として機能する絶縁体３１５、基板３１１の一部からなる半導体領域３１３、ならびにソース領域またはドレイン領域として機能する低抵抗領域３１４ａ、および低抵抗領域３１４ｂを有する。 <Transistor 300>
The transistor 300 is provided on the substrate 311 and functions as a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b.
　ここで、半導体領域３１３の上に絶縁体３１５が配置され、絶縁体３１５の上に導電体３１６が配置される。また、同じ層に形成されるトランジスタ３００は、素子分離絶縁層として機能する絶縁体３１２によって、電気的に分離されている。絶縁体３１２は、後述する絶縁体３２６などと同様の絶縁体を用いることができる。トランジスタ３００は、ｐチャネル型、あるいはｎチャネル型のいずれでもよい。 Here, the insulator 315 is arranged on the semiconductor region 313, and the conductor 316 is arranged on the insulator 315. Further, the transistors 300 formed in the same layer are electrically separated by an insulator 312 that functions as an element separation insulating layer. As the insulator 312, the same insulator as the insulator 326 described later can be used. The transistor 300 may be either a p-channel type or an n-channel type.
　基板３１１は、半導体領域３１３のチャネルが形成される領域、その近傍の領域、ソース領域、またはドレイン領域となる低抵抗領域３１４ａ、および低抵抗領域３１４ｂなどにおいて、シリコン系半導体などの半導体を含むことが好ましく、単結晶シリコンを含むことが好ましい。または、Ｇｅ（ゲルマニウム）、ＳｉＧｅ（シリコンゲルマニウム）、ＧａＡｓ（ガリウムヒ素）、ＧａＡｌＡｓ（ガリウムアルミニウムヒ素）などを有する材料で形成してもよい。結晶格子に応力を与え、格子間隔を変化させることで有効質量を制御したシリコンを用いた構成としてもよい。またはＧａＡｓとＧａＡｌＡｓ等を用いることで、トランジスタ３００をＨＥＭＴ（Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）としてもよい。 The substrate 311 includes a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like. Is preferable, and it is preferable to contain single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
　低抵抗領域３１４ａ、および低抵抗領域３１４ｂは、半導体領域３１３に適用される半導体材料に加え、ヒ素、リンなどのｎ型の導電性を付与する元素、またはホウ素などのｐ型の導電性を付与する元素を含む。 In the low resistance region 314a and the low resistance region 314b, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic and phosphorus, or a p-type conductivity such as boron is imparted. Contains elements that
　ゲート電極として機能する導電体３１６は、ヒ素、リンなどのｎ型の導電性を付与する元素、もしくはホウ素などのｐ型の導電性を付与する元素を含むシリコンなどの半導体材料、金属材料、合金材料、または金属酸化物材料などの導電性材料を用いることができる。 The conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A material or a conductive material such as a metal oxide material can be used.
　なお、導電体の材料により、仕事関数が定まるため、導電体の材料を変更することで、しきい値電圧を調整することができる。具体的には、導電体に窒化チタンや窒化タンタルなどの材料を用いることが好ましい。さらに導電性と埋め込み性を両立するために導電体にタングステンやアルミニウムなどの金属材料を積層として用いることが好ましく、特にタングステンを用いることが耐熱性の点で好ましい。 Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
　ここで、図１２に示すトランジスタ３００はチャネルが形成される半導体領域３１３（基板３１１の一部）が凸形状を有する。また、半導体領域３１３の側面および上面を、絶縁体３１５を介して、導電体３１６が覆うように設けられている。このようなトランジスタ３００は半導体基板の凸部を利用していることからＦＩＮ型トランジスタとも呼ばれる。なお、凸部の上部に接して、凸部を形成するためのマスクとして機能する絶縁体を有していてもよい。また、ここでは半導体基板の一部を加工して凸部を形成する場合を示したが、ＳＯＩ基板を加工して凸形状を有する半導体膜を形成してもよい。 Here, in the transistor 300 shown in FIG. 12, the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
　なお、図１２に示すトランジスタ３００は一例であり、その構造に限定されず、回路構成や駆動方法に応じて適切なトランジスタを用いればよい。 Note that the transistor 300 shown in FIG. 12 is an example, and the transistor 300 is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.
　また、図１２に示すように半導体装置は、トランジスタ３００と、トランジスタ２００とを、積層して設けている。例えば、トランジスタ３００をシリコン系半導体材料で形成し、トランジスタ２００を酸化物半導体で形成することができる。このように、図１２に示す半導体装置は、シリコン系半導体材料と、酸化物半導体とを、異なるレイヤーに混載して形成することが可能である。また、図１２に示す半導体装置は、シリコン系半導体材料で用いる製造装置と同様のプロセスで作製することが可能であり、高集積化することも可能である。 Further, as shown in FIG. 12, the semiconductor device is provided by stacking the transistor 300 and the transistor 200. For example, the transistor 300 can be made of a silicon-based semiconductor material, and the transistor 200 can be made of an oxide semiconductor. As described above, in the semiconductor device shown in FIG. 12, the silicon-based semiconductor material and the oxide semiconductor can be mixedly mounted on different layers to form the semiconductor device. Further, the semiconductor device shown in FIG. 12 can be manufactured by the same process as the manufacturing device used for the silicon-based semiconductor material, and can be highly integrated.
＜容量素子＞
　容量素子１００は、絶縁体１６０上の絶縁体１１４と、絶縁体１１４上の絶縁体１４０と、絶縁体１１４および絶縁体１４０に形成された開口の中に配置された導電体１１０と、導電体１１０および絶縁体１４０上の絶縁体１３０と、絶縁体１３０上の導電体１２０と、導電体１２０および絶縁体１３０上の絶縁体１５０と、を有する。ここで、絶縁体１１４および絶縁体１４０に形成された開口の中に導電体１１０、絶縁体１３０、および導電体１２０の少なくとも一部が配置される。 <Capacitive element>
The capacitive element 100 includes an insulator 114 on the insulator 160, an insulator 140 on the insulator 114, a conductor 110 arranged in the insulator 114 and an opening formed in the insulator 140, and a conductor. It has an insulator 130 on the 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130. Here, at least a part of the conductor 110, the insulator 130, and the conductor 120 is arranged in the openings formed in the insulator 114 and the insulator 140.
　導電体１１０は容量素子１００の下部電極として機能し、導電体１２０は容量素子１００の上部電極として機能し、絶縁体１３０は、容量素子１００の誘電体として機能する。容量素子１００は、絶縁体１１４および絶縁体１４０の開口において、底面だけでなく、側面においても上部電極と下部電極とが誘電体を挟んで対向する構成となっており、単位面積当たりの静電容量を大きくすることができる。よって、当該開口の深さを深くするほど、容量素子１００の静電容量を大きくすることができる。このように容量素子１００の単位面積当たりの静電容量を大きくすることにより、半導体装置の微細化または高集積化を推し進めることができる。 The conductor 110 functions as a lower electrode of the capacitance element 100, the conductor 120 functions as an upper electrode of the capacitance element 100, and the insulator 130 functions as a dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched not only on the bottom surface but also on the side surface at the openings of the insulator 114 and the insulator 140, and the capacitance per unit area is electrostatic. The capacity can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitance element 100 can be. By increasing the capacitance per unit area of the capacitive element 100 in this way, it is possible to promote miniaturization or high integration of the semiconductor device.
　絶縁体１１４、および絶縁体１５０は、絶縁体２８０に用いることができる絶縁体を用いればよい。また、絶縁体１４０は、絶縁体１１４の開口を形成するときのエッチングストッパとして機能することが好ましく、絶縁体２１４に用いることができる絶縁体を用いればよい。 As the insulator 114 and the insulator 150, an insulator that can be used for the insulator 280 may be used. Further, the insulator 140 preferably functions as an etching stopper when forming an opening of the insulator 114, and an insulator that can be used for the insulator 214 may be used.
　絶縁体１１４および絶縁体１４０に形成された開口を上面から見た形状は、四角形としてもよいし、四角形以外の多角形状としてもよいし、多角形状において角部を湾曲させた形状としてもよいし、楕円を含む円形状としてもよい。ここで、上面視において、当該開口とトランジスタ２００の重なる面積が多い方が好ましい。このような構成にすることにより、容量素子１００とトランジスタ２００を有する半導体装置の占有面積を低減することができる。 The shape of the openings formed in the insulator 114 and the insulator 140 when viewed from above may be a quadrangle, a polygonal shape other than the quadrangle, or a polygonal shape with curved corners. , It may be a circular shape including an ellipse. Here, in top view, it is preferable that the area where the opening and the transistor 200 overlap is large. With such a configuration, the occupied area of the semiconductor device having the capacitance element 100 and the transistor 200 can be reduced.
　導電体１１０は、絶縁体１４０、および絶縁体１１４に形成された開口に接して配置される。導電体１１０の上面は、絶縁体１４０の上面と略一致することが好ましい。また、導電体１１０の下面には、絶縁体１６０上に設けられた導電体１５２が接する。導電体１１０は、ＡＬＤ法またはＣＶＤ法などを用いて成膜することが好ましく、例えば、導電体２０５に用いることができる導電体を用いればよい。 The conductor 110 is arranged in contact with the insulator 140 and the opening formed in the insulator 114. It is preferable that the upper surface of the conductor 110 substantially coincides with the upper surface of the insulator 140. Further, the conductor 152 provided on the insulator 160 is in contact with the lower surface of the conductor 110. The conductor 110 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
　絶縁体１３０は、導電体１１０および絶縁体１４０を覆うように配置される。例えば、ＡＬＤ法またはＣＶＤ法などを用いて絶縁体１３０を成膜することが好ましい。絶縁体１３０は、例えば、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化ジルコニウム、酸化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、窒化アルミニウム、酸化ハフニウム、酸化窒化ハフニウム、窒化酸化ハフニウム、窒化ハフニウムなどを用いればよく、積層または単層で設けることができる。例えば、絶縁体１３０として、酸化ジルコニウム、酸化アルミニウム、酸化ジルコニウムの順番で積層された絶縁膜を用いることができる。 The insulator 130 is arranged so as to cover the conductor 110 and the insulator 140. For example, it is preferable to form the insulator 130 by using an ALD method, a CVD method, or the like. The insulator 130 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium oxide, and nitride. Hafnium or the like may be used, and it can be provided in a laminated or single layer. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
　また、絶縁体１３０には、酸化窒化シリコンなどの絶縁耐力が大きい材料、または高誘電率（ｈｉｇｈ−ｋ）材料を用いることが好ましい。または、絶縁耐力が大きい材料と高誘電率（ｈｉｇｈ−ｋ）材料の積層構造を用いてもよい。 Further, it is preferable to use a material having a large dielectric strength such as silicon oxide or a material having a high dielectric constant (high-k) for the insulator 130. Alternatively, a laminated structure of a material having a large dielectric strength and a high dielectric constant (high-k) material may be used.
　なお、高誘電率（ｈｉｇｈ−ｋ）材料（高い比誘電率の材料）の絶縁体としては、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウムおよびハフニウムを有する酸化物、アルミニウムおよびハフニウムを有する酸化窒化物、シリコンおよびハフニウムを有する酸化物、シリコンおよびハフニウムを有する酸化窒化物、シリコンおよびハフニウムを有する窒化物などがある。このようなｈｉｇｈ−ｋ材料を用いることで、絶縁体１３０を厚くしても容量素子１００の静電容量を十分確保することができる。絶縁体１３０を厚くすることにより、導電体１１０と導電体１２０の間に生じるリーク電流を抑制することができる。 As the insulator of the high dielectric constant (high-k) material (material having a high specific dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, and nitrides having aluminum and hafnium. , Oxides with silicon and hafnium, nitrides with silicon and hafnium, nitrides with silicon and hafnium, and the like. By using such a high-k material, it is possible to sufficiently secure the capacitance of the capacitance element 100 even if the insulator 130 is thickened. By making the insulator 130 thicker, the leakage current generated between the conductor 110 and the conductor 120 can be suppressed.
　一方、絶縁耐力が大きい材料としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコン、樹脂などがある。例えば、ＡＬＤ法を用いて成膜した窒化シリコン（ＳｉＮｘ）、ＰＥＡＬＤ法を用いて成膜した酸化シリコン（ＳｉＯｘ）、ＡＬＤ法を用いて成膜した窒化シリコン（ＳｉＮｘ）の順番で積層された絶縁膜を用いることができる。このような、絶縁耐力が大きい絶縁体を用いることで、絶縁耐力が向上し、容量素子１００の静電破壊を抑制することができる。 On the other hand, as materials having high insulation strength, silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and vacancies are used. There are silicon oxide, resin, etc. For example, laminated in the order of silicon nitride was deposited using ALD (SiN x), silicon oxide was deposited using PEALD method (SiO x), silicon nitride was deposited using ALD (SiN x) An insulating film that has been formed can be used. By using such an insulator having a large dielectric strength, the dielectric strength can be improved and electrostatic breakdown of the capacitive element 100 can be suppressed.
　導電体１２０は、絶縁体１４０および絶縁体１１４に形成された開口を埋めるように配置される。また、導電体１２０は、導電体１１２、および導電体１５３を介して配線１００５と電気的に接続している。導電体１２０は、ＡＬＤ法またはＣＶＤ法などを用いて成膜することが好ましく、例えば、導電体２０５に用いることができる導電体を用いればよい。 The conductor 120 is arranged so as to fill the openings formed in the insulator 140 and the insulator 114. Further, the conductor 120 is electrically connected to the wiring 1005 via the conductor 112 and the conductor 153. The conductor 120 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
　また、トランジスタ２００は、酸化物半導体を用いる構成であるため、容量素子１００との相性が優れている。具体的には、酸化物半導体を用いるトランジスタ２００は、オフ電流が小さいため、容量素子１００と組み合わせて用いることで長期にわたり記憶内容を保持することが可能である。 Further, since the transistor 200 is configured to use an oxide semiconductor, the compatibility with the capacitive element 100 is excellent. Specifically, since the transistor 200 using an oxide semiconductor has a small off-current, it is possible to retain the stored contents for a long period of time by using it in combination with the capacitive element 100.
＜配線層＞
　各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線として機能する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。 <Wiring layer>
A wiring layer provided with an interlayer film, wiring, a plug, or the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design. Here, the conductor that functions as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
　例えば、トランジスタ３００上には、層間膜として、絶縁体３２０、絶縁体３２２、絶縁体３２４、および絶縁体３２６が順に積層して設けられている。 For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order on the transistor 300 as an interlayer film.
　なお、絶縁体３２２、絶縁体３２４、および絶縁体３２６は先の実施の形態で説明した調整層としての機能を有していてもよい。 The insulator 322, the insulator 324, and the insulator 326 may have a function as an adjusting layer described in the previous embodiment.
　また、絶縁体３２０、絶縁体３２２、絶縁体３２４、および絶縁体３２６には、端子として機能する導電体１５３と電気的に接続する導電体３２８、および導電体３３０等が埋め込まれている。なお、導電体３２８、および導電体３３０はプラグ、または配線として機能する。 Further, in the insulator 320, the insulator 322, the insulator 324, and the insulator 326, a conductor 328 and a conductor 330 that are electrically connected to the conductor 153 that functions as a terminal are embedded. The conductor 328 and the conductor 330 function as plugs or wirings.
　また、層間膜として機能する絶縁体は、その下方の凹凸形状を被覆する平坦化膜として機能してもよい。例えば、絶縁体３２２の上面は、平坦性を高めるために化学機械研磨（ＣＭＰ）法等を用いた平坦化処理により平坦化されていてもよい。 Further, the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
　絶縁体３２６、および導電体３３０上に、配線層を設けてもよい。例えば、図１２において、絶縁体３５０、絶縁体３５２、および絶縁体３５４が順に積層して設けられている。 A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 12, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
　絶縁体３５０、絶縁体３５２、および絶縁体３５４は先の実施の形態で説明した調整層としての機能を有していてもよい。 The insulator 350, the insulator 352, and the insulator 354 may have a function as an adjusting layer described in the previous embodiment.
　また、絶縁体３５０、絶縁体３５２、および絶縁体３５４には、導電体３５６が形成されている。導電体３５６は、プラグ、または配線として機能する。 Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.
　絶縁体３５４、および導電体３５６上には、絶縁体２１０、絶縁体２１２、絶縁体２１４、および絶縁体２１６が順に積層して設けられている。 On the insulator 354 and the conductor 356, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are laminated in this order.
　絶縁体２１０、絶縁体２１２および絶縁体２１４は先の実施の形態で説明した調整層として機能しうる。 The insulator 210, the insulator 212, and the insulator 214 can function as the adjusting layer described in the previous embodiment.
　また、絶縁体２１０、絶縁体２１２、絶縁体２１４、および絶縁体２１６には、導電体２１８、及びトランジスタ２００を構成する導電体（導電体２０５）等が埋め込まれている。なお、導電体２１８は、トランジスタ３００と電気的に接続するプラグ、または配線として機能する。 Further, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like. The conductor 218 functions as a plug or wiring that electrically connects to the transistor 300.
　また、絶縁体１１４、絶縁体１４０、絶縁体１３０、絶縁体１５０、および絶縁体１５４には、導電体１１２、および容量素子１００を構成する導電体（導電体１２０、導電体１１０）等が埋め込まれている。なお、導電体１１２は、容量素子１００、トランジスタ２００、またはトランジスタ３００と、端子として機能する導電体１５３と、を電気的に接続するプラグ、または配線として機能する。 Further, the conductor 112, the conductors constituting the capacitive element 100 (conductor 120, conductor 110) and the like are embedded in the insulator 114, the insulator 140, the insulator 130, the insulator 150, and the insulator 154. It has been. The conductor 112 functions as a plug or wiring that electrically connects the capacitive element 100, the transistor 200, or the transistor 300 and the conductor 153 that functions as a terminal.
　また、絶縁体１５４上に導電体１５３が設けられ、導電体１５３は、絶縁体１５６に覆われている。ここで、導電体１５３は導電体１１２の上面に接しており、容量素子１００、トランジスタ２００、またはトランジスタ３００の端子として機能する。 Further, the conductor 153 is provided on the insulator 154, and the conductor 153 is covered with the insulator 156. Here, the conductor 153 is in contact with the upper surface of the conductor 112, and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.
　なお、層間膜として用いることができる絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。例えば、層間膜として機能する絶縁体は、比誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。したがって、絶縁体の機能に応じて、材料を選択するとよい。 Examples of the insulator that can be used as the interlayer film include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties. For example, for an insulator that functions as an interlayer film, by using a material having a low relative permittivity, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, the material may be selected according to the function of the insulator.
　例えば、絶縁体３２０、絶縁体３２２、絶縁体３２６、絶縁体３５２、絶縁体３５４、絶縁体２１２、絶縁体１１４、絶縁体１５０、絶縁体１５６等は、比誘電率の低い絶縁体を有することが好ましい。例えば、当該絶縁体は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコン、樹脂などを有することが好ましい。または、当該絶縁体は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコンまたは空孔を有する酸化シリコンと、樹脂と、の積層構造を有することが好ましい。酸化シリコンおよび酸化窒化シリコンは、熱的に安定であるため、樹脂と組み合わせることで、熱的に安定かつ比誘電率の低い積層構造とすることができる。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネート、アクリルなどがある。 For example, the insulator 320, the insulator 322, the insulator 326, the insulator 352, the insulator 354, the insulator 212, the insulator 114, the insulator 150, the insulator 156, and the like have an insulator having a low relative dielectric constant. Is preferable. For example, the insulator includes silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores. , Resin and the like are preferable. Alternatively, the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores. And resin, it is preferable to have a laminated structure. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
　また、導電体１５２または導電体１５３の上または下に設けられる絶縁体の抵抗率が１．０×１０１２Ωｃｍ以上１．０×１０１５Ωｃｍ以下、好ましくは５．０×１０１２Ωｃｍ以上１．０×１０１４Ωｃｍ以下、より好ましくは１．０×１０１３Ωｃｍ以上５．０×１０１３Ωｃｍ以下であることが好ましい。導電体１５２または導電体１５３の上または下に設けられる絶縁体の抵抗率を上記の範囲にすることで、当該絶縁体は、絶縁性を維持しつつ、トランジスタ２００、トランジスタ３００、容量素子１００、および導電体１５２等の配線間に蓄積される電荷を分散し、該電荷によるトランジスタ、該トランジスタを有する半導体装置の特性不良や静電破壊を抑制することができ、好ましい。このような絶縁体として、窒化シリコン、または窒化酸化シリコンを用いることができる。例えば、絶縁体１６０または絶縁体１５４の抵抗率を上記の範囲にすればよい。 Further, the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 is 1.0 × 10 12 Ωcm or more and 1.0 × 10 15 Ωcm or less, preferably 5.0 × 10 12 Ωcm or more 1 It is preferably 0.0 × 10 14 Ωcm or less, more preferably 1.0 × 10 13 Ωcm or more and 5.0 × 10 13 Ωcm or less. By setting the resistance of the insulator provided above or below the conductor 152 or the conductor 153 to the above range, the insulator maintains the insulating property, and the transistor 200, the transistor 300, the capacitive element 100, and the like. And, the charge accumulated between the wirings of the conductor 152 and the like can be dispersed, and the characteristics of the transistor and the semiconductor device having the transistor can be suppressed due to the charge, and electrostatic destruction can be suppressed, which is preferable. Silicon nitride or silicon nitride oxide can be used as such an insulator. For example, the resistivity of the insulator 160 or the insulator 154 may be set within the above range.
　また、酸化物半導体を用いたトランジスタは、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体で囲うことによって、トランジスタの電気特性を安定にすることができる。従って、絶縁体３２４、絶縁体３５０、絶縁体２１０等には、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体を用いればよい。 Further, a transistor using an oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 324, the insulator 350, the insulator 210, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
　水素などの不純物および酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。具体的には、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体として、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムまたは酸化タンタルなどの金属酸化物、窒化酸化シリコンまたは窒化シリコンなどを用いることができる。 Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulations containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.
　配線、プラグに用いることができる導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を１種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium. , A material containing one or more metal elements selected from ruthenium and the like can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and SiO such as nickel silicide may be used.
　例えば、導電体３２８、導電体３３０、導電体３５６、導電体２１８、導電体１１２、導電体１５２、導電体１５３等としては、上記の材料で形成される金属材料、合金材料、金属窒化物材料、または金属酸化物材料などの導電性材料を、単層または積層して用いることができる。耐熱性と導電性を両立するタングステンやモリブデンなどの高融点材料を用いることが好ましく、タングステンを用いることが好ましい。または、アルミニウムや銅などの低抵抗導電性材料で形成することが好ましい。低抵抗導電性材料を用いることで配線抵抗を低くすることができる。 For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, the conductor 152, the conductor 153, and the like include a metal material, an alloy material, and a metal nitride material formed of the above materials. , Or a conductive material such as a metal oxide material can be used as a single layer or laminated. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
＜酸化物半導体が設けられた層の配線、またはプラグ＞
　なお、トランジスタ２００に、酸化物半導体を用いる場合、酸化物半導体の近傍に過剰酸素領域を有する絶縁体が設けることがある。その場合、該過剰酸素領域を有する絶縁体と、該過剰酸素領域を有する絶縁体に設ける導電体との間に、バリア性を有する絶縁体を設けることが好ましい。 <Wiring or plug of layer provided with oxide semiconductor>
When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
　例えば、図１２では、過剰酸素を有する絶縁体２８０と、導電体２４８との間に、絶縁体２４７を設けるとよい。絶縁体２４７と、絶縁体２８２とが接して設けられることで、導電体２４８、およびトランジスタ２００が、バリア性を有する絶縁体によって、封止される構造とすることができる。 For example, in FIG. 12, it is preferable to provide an insulator 247 between the insulator 280 having excess oxygen and the conductor 248. By providing the insulator 247 and the insulator 282 in contact with each other, the conductor 248 and the transistor 200 can be sealed by the insulator having a barrier property.
　つまり、絶縁体２４７を設けることで、絶縁体２８０が有する過剰酸素が、導電体２４８に吸収されることを抑制することができる。また、絶縁体２４７を有することで、不純物である水素が、導電体２４８を介して、トランジスタ２００へ拡散することを抑制することができる。 That is, by providing the insulator 247, it is possible to suppress the excess oxygen contained in the insulator 280 from being absorbed by the conductor 248. Further, by having the insulator 247, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 248.
　ここで、導電体２４８は、トランジスタ２００、またはトランジスタ３００と電気的に接続するプラグ、または配線としての機能を有する。 Here, the conductor 248 has a function as a transistor 200 or a plug or wiring that electrically connects to the transistor 300.
　具体的には、絶縁体２８４、絶縁体２８２、および絶縁体２８０の開口の側壁に接して、絶縁体２４７が設けられ、その側面に接して導電体２４８が形成されている。当該開口の底部の少なくとも一部には導電体２４０が位置しており、導電体２４８が導電体２４０と接する。 Specifically, the insulator 247 is provided in contact with the side wall of the opening of the insulator 284, the insulator 282, and the insulator 280, and the conductor 248 is formed in contact with the side surface thereof. The conductor 240 is located at least a part of the bottom of the opening, and the conductor 248 is in contact with the conductor 240.
　導電体２４８は、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。また、導電体２４８は積層構造としてもよい。なお、トランジスタ２００では、導電体２４８を、２層の積層構造として設ける構成について示しているが、本発明はこれに限られるものではない。例えば、導電体２４８を単層、または３層以上の積層構造として設ける構成にしてもよい。 As the conductor 248, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 248 may have a laminated structure. The transistor 200 shows a configuration in which the conductor 248 is provided as a two-layer laminated structure, but the present invention is not limited to this. For example, the conductor 248 may be provided as a single layer or a laminated structure having three or more layers.
　また、導電体２４８を積層構造とする場合、導電体２４０と接し、かつ、絶縁体２８０、絶縁体２８２、および絶縁体２８４と、絶縁体２４７を介して接する導電体には、水、水素などの不純物の透過を抑制する機能を有する導電性材料を用いることが好ましい。例えば、タンタル、窒化タンタル、チタン、窒化チタン、ルテニウム、酸化ルテニウムなどを用いることが好ましい。また、水、水素などの不純物の透過を抑制する機能を有する導電性材料は、単層または積層で用いてもよい。当該導電性材料を用いることで、絶縁体２８０に添加された酸素が導電体２４８に吸収されるのを防ぐことができる。また、絶縁体２８４より上層に含まれる、水、水素などの不純物が、導電体２４８を通じて酸化物２３０に拡散するのを抑制することができる。 When the conductor 248 has a laminated structure, the conductors in contact with the conductor 240 and in contact with the insulator 280, the insulator 282, and the insulator 284 via the insulator 247 include water, hydrogen, and the like. It is preferable to use a conductive material having a function of suppressing the permeation of impurities. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used. Further, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated state. By using the conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 248. Further, it is possible to prevent impurities such as water and hydrogen contained in the layer above the insulator 284 from diffusing into the oxide 230 through the conductor 248.
　絶縁体２４７としては、例えば、絶縁体２１４等に用いることができる絶縁体を用いればよい。絶縁体２４７は、絶縁体２８０などに含まれる水、水素などの不純物が、導電体２４８を通じて酸化物２３０に拡散するのを抑制することができる。また、絶縁体２８０に含まれる酸素が導電体２４８に吸収されるのを防ぐことができる。 As the insulator 247, for example, an insulator that can be used for the insulator 214 or the like may be used. The insulator 247 can suppress impurities such as water and hydrogen contained in the insulator 280 and the like from diffusing into the oxide 230 through the conductor 248. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 248.
　また、図示しないが、導電体２４８の上面に接して配線として機能する導電体１５２を配置してもよい。配線として機能する導電体は、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。また、当該導電体は、積層構造としてもよく、例えば、チタン、または窒化チタンと上記導電性材料との積層としてもよい。なお、当該導電体は、絶縁体に設けられた開口に埋め込むように形成してもよい。 Further, although not shown, a conductor 152 that is in contact with the upper surface of the conductor 248 and functions as wiring may be arranged. As the conductor that functions as wiring, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.
　以上が構成例についての説明である。本構成を用いることで、酸化物半導体を有するトランジスタを用いた半導体装置を微細化または高集積化させることができる。また、酸化物半導体を有するトランジスタを用いた半導体装置において、電気特性の変動を抑制すると共に、信頼性を向上させることができる。また、オン電流が大きい酸化物半導体を有するトランジスタを提供することができる。また、オフ電流が小さい酸化物半導体を有するトランジスタを提供することができる。また、消費電力が低減された半導体装置を提供することができる。 The above is the explanation of the configuration example. By using this configuration, a semiconductor device using a transistor having an oxide semiconductor can be miniaturized or highly integrated. Further, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Further, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Further, it is possible to provide a transistor having an oxide semiconductor having a small off-current. Further, it is possible to provide a semiconductor device having reduced power consumption.
［記憶装置２］
　本発明の一態様である半導体装置を使用した、半導体装置（記憶装置）の一例を図１３に示す。図１３に示す半導体装置は、図１２で示した半導体装置と同様に、トランジスタ２００、トランジスタ３００、および容量素子１００を有する。ただし、図１３に示す半導体装置は、容量素子１００がプレーナ型である点、およびトランジスタ２００とトランジスタ３００が電気的に接続されている点において、図１２に示す半導体装置と異なる。 [Storage device 2]
FIG. 13 shows an example of a semiconductor device (storage device) using the semiconductor device according to one aspect of the present invention. The semiconductor device shown in FIG. 13 has a transistor 200, a transistor 300, and a capacitive element 100, similarly to the semiconductor device shown in FIG. However, the semiconductor device shown in FIG. 13 is different from the semiconductor device shown in FIG. 12 in that the capacitive element 100 is a planar type and the transistor 200 and the transistor 300 are electrically connected.
　本発明の一態様の半導体装置は、トランジスタ２００はトランジスタ３００の上方に設けられ、容量素子１００はトランジスタ３００、およびトランジスタ２００の上方に設けられている。容量素子１００、またはトランジスタ３００は、少なくとも一部がトランジスタ２００と重畳することが好ましい。これにより、容量素子１００、トランジスタ２００、およびトランジスタ３００の上面視における占有面積を低減することができるので、本実施の形態に係る半導体装置を微細化または高集積化させることができる。 In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. It is preferable that at least a part of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. As a result, the occupied area of the capacitive element 100, the transistor 200, and the transistor 300 in the top view can be reduced, so that the semiconductor device according to the present embodiment can be miniaturized or highly integrated.
　なお、トランジスタ２００およびトランジスタ３００として、上記のトランジスタ２００およびトランジスタ３００を用いることができる。よって、トランジスタ２００、トランジスタ３００、およびこれらを含む層については、上記の記載を参酌することができる。 The above-mentioned transistor 200 and transistor 300 can be used as the transistor 200 and the transistor 300. Therefore, the above description can be taken into consideration for the transistor 200, the transistor 300, and the layer including these.
　図１３に示す半導体装置において、配線２００１はトランジスタ３００のソースと電気的に接続され、配線２００２はトランジスタ３００のドレインと電気的に接続されている。また、配線２００３はトランジスタ２００のソースおよびドレインの一方と電気的に接続され、配線２００４はトランジスタ２００の第１のゲートと電気的に接続され、配線２００６はトランジスタ２００の第２のゲートと電気的に接続されている。そして、トランジスタ３００のゲート、およびトランジスタ２００のソースおよびドレインの他方は、容量素子１００の電極の一方と電気的に接続され、配線２００５は容量素子１００の電極の他方と電気的に接続されている。なお、以下において、トランジスタ３００のゲートと、トランジスタ２００のソースおよびドレインの他方と、容量素子１００の電極の一方と、が接続されたノードをノードＦＧと呼ぶ場合がある。 In the semiconductor device shown in FIG. 13, the wiring 2001 is electrically connected to the source of the transistor 300, and the wiring 2002 is electrically connected to the drain of the transistor 300. Further, the wiring 2003 is electrically connected to one of the source and drain of the transistor 200, the wiring 2004 is electrically connected to the first gate of the transistor 200, and the wiring 2006 is electrically connected to the second gate of the transistor 200. It is connected to the. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitance element 100, and the wiring 2005 is electrically connected to the other of the electrodes of the capacitance element 100. .. In the following, a node in which the gate of the transistor 300, the other of the source and drain of the transistor 200, and one of the electrodes of the capacitive element 100 are connected may be referred to as a node FG.
　図１３に示す半導体装置は、トランジスタ２００のスイッチングによって、トランジスタ３００のゲート（ノードＦＧ）の電位が保持可能という特性を有することで、情報の書き込み、保持、読み出しが可能である。 The semiconductor device shown in FIG. 13 has a characteristic that the potential of the gate (node FG) of the transistor 300 can be held by switching the transistor 200, so that information can be written, held, and read out.
　また、図１３に示す半導体装置は、マトリクス状に配置することで、メモリセルアレイを構成することができる。 Further, the semiconductor devices shown in FIG. 13 can form a memory cell array by arranging them in a matrix.
　トランジスタ３００を含む層は、図１２に示す半導体装置と同様の構造を有するので、絶縁体３５４より下の構造は、上記の記載を参酌することができる。 Since the layer containing the transistor 300 has the same structure as the semiconductor device shown in FIG. 12, the structure below the insulator 354 can take the above description into consideration.
　絶縁体３５４の上に、絶縁体２１０、絶縁体２１２、絶縁体２１４、および絶縁体２１６が配置される。ここで、絶縁体２１０は、絶縁体３５０などと同様に、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体を用いればよい。 The insulator 210, the insulator 212, the insulator 214, and the insulator 216 are arranged on the insulator 354. Here, as the insulator 210, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used, similarly to the insulator 350 and the like.
　絶縁体２１０、絶縁体２１２、絶縁体２１４、および絶縁体２１６には、導電体２１８が埋め込まれている。導電体２１８は、容量素子１００、トランジスタ２００、またはトランジスタ３００と電気的に接続するプラグ、または配線として機能する。例えば、導電体２１８は、トランジスタ３００のゲート電極として機能する導電体３１６と電気的に接続されている。 A conductor 218 is embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. The conductor 218 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300. For example, the conductor 218 is electrically connected to the conductor 316 which functions as a gate electrode of the transistor 300.
　また、導電体２４８は、トランジスタ２００、またはトランジスタ３００と電気的に接続するプラグ、または配線として機能する。例えば、導電体２４８は、トランジスタ２００のソースおよびドレインの他方として機能する導電体２４０ｂと、容量素子１００の電極の一方として機能する導電体１１０を、導電体２４８を介して電気的に接続している。 Further, the conductor 248 functions as a plug or wiring that electrically connects to the transistor 200 or the transistor 300. For example, in the conductor 248, the conductor 240b that functions as the other of the source and drain of the transistor 200 and the conductor 110 that functions as one of the electrodes of the capacitive element 100 are electrically connected via the conductor 248. There is.
　また、プレーナ型の容量素子１００は、トランジスタ２００の上方に設けられる。容量素子１００は、第１の電極として機能する導電体１１０、第２の電極として機能する導電体１２０、および誘電体として機能する絶縁体１３０を有する。なお、導電体１１０、導電体１２０、および絶縁体１３０は、上述の記憶装置１で記載したものを用いることができる。 Further, the planar type capacitive element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. As the conductor 110, the conductor 120, and the insulator 130, those described in the storage device 1 described above can be used.
　導電体２４８の上面に接して導電体１５３および導電体１１０が設けられる。導電体１５３は、導電体２４８の上面に接しており、トランジスタ２００またはトランジスタ３００の端子として機能する。 The conductor 153 and the conductor 110 are provided in contact with the upper surface of the conductor 248. The conductor 153 is in contact with the upper surface of the conductor 248 and functions as a terminal of the transistor 200 or the transistor 300.
　導電体１５３および導電体１１０は絶縁体１３０に覆われており、絶縁体１３０を介して導電体１１０と重なるように導電体１２０が配置される。さらに、導電体１２０、および絶縁体１３０上には、絶縁体１１４が配置されている。 The conductor 153 and the conductor 110 are covered with an insulator 130, and the conductor 120 is arranged so as to overlap the conductor 110 via the insulator 130. Further, an insulator 114 is arranged on the conductor 120 and the insulator 130.
　また、図１３において、容量素子１００として、プレーナ型の容量素子を用いる例について示したが、本実施の形態に示す半導体装置はこれに限られるものではない。例えば、容量素子１００として、図１２に示すようなシリンダ型の容量素子１００を用いてもよい。 Further, in FIG. 13, an example in which a planar type capacitive element is used as the capacitive element 100 is shown, but the semiconductor device shown in the present embodiment is not limited to this. For example, as the capacitance element 100, a cylinder-type capacitance element 100 as shown in FIG. 12 may be used.
［記憶装置３］
　本発明の一態様である半導体装置を使用した、記憶装置の一例を図１４に示す。図１４に示す記憶装置は、図１３で示したトランジスタ２００、トランジスタ３００、および容量素子１００を有する半導体装置に加え、トランジスタ４００を有している。 [Storage device 3]
FIG. 14 shows an example of a storage device using the semiconductor device which is one aspect of the present invention. The storage device shown in FIG. 14 includes a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitive element 100 shown in FIG.
　トランジスタ４００は、トランジスタ２００の第２のゲート電圧を制御することができる。例えば、トランジスタ４００の第１のゲート及び第２のゲートをソースとダイオード接続し、トランジスタ４００のソースと、トランジスタ２００の第２のゲートを接続する構成とする。当該構成でトランジスタ２００の第２のゲートの負電位を保持するとき、トランジスタ４００の第１のゲートーソース間の電圧および、第２のゲートーソース間の電圧は、０Ｖになる。トランジスタ４００において、第２のゲート電圧及び第１のゲート電圧が０Ｖのときのドレイン電流が非常に小さいため、トランジスタ２００およびトランジスタ４００に電源供給をしなくても、トランジスタ２００の第２のゲートの負電位を長時間維持することができる。これにより、トランジスタ２００、およびトランジスタ４００を有する記憶装置は、長期にわたり記憶内容を保持することが可能である。 The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the second gate of the transistor 200 are connected. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source become 0V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the second gate of the transistor 200 does not need to be supplied with power to the transistor 200 and the transistor 400. The negative potential can be maintained for a long time. As a result, the storage device having the transistor 200 and the transistor 400 can retain the stored contents for a long period of time.
　従って、図１４において、配線１００１はトランジスタ３００のソースと電気的に接続され、配線１００２はトランジスタ３００のドレインと電気的に接続されている。また、配線１００３はトランジスタ２００のソースおよびドレインの一方と電気的に接続され、配線１００４はトランジスタ２００のゲートと電気的に接続され、配線１００６はトランジスタ２００の第２のゲート（バックゲート）と電気的に接続されている。そして、トランジスタ３００のゲート、およびトランジスタ２００のソースおよびドレインの他方は、容量素子１００の電極の一方と電気的に接続され、配線１００５は容量素子１００の電極の他方と電気的に接続されている。配線１００７はトランジスタ４００のソースと電気的に接続され、配線１００８はトランジスタ４００のゲートと電気的に接続され、配線１００９はトランジスタ４００の第２のゲート（バックゲート）と電気的に接続され、配線１０１０はトランジスタ４００のドレインと電気的に接続されている。ここで、配線１００６、配線１００７、配線１００８、及び配線１００９が電気的に接続されている。 Therefore, in FIG. 14, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate (back gate) of the transistor 200. Is connected. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitance element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitance element 100. .. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, and the wiring 1009 is electrically connected to the second gate (back gate) of the transistor 400. The 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
　また、図１４に示す記憶装置は、図１２及び図１３に示す記憶装置と同様に、マトリクス状に配置することで、メモリセルアレイを構成することができる。なお、１個のトランジスタ４００は、複数のトランジスタ２００の第２のゲート電圧を制御することができる。そのため、トランジスタ４００は、トランジスタ２００よりも、少ない個数を設けるとよい。 Further, the storage devices shown in FIG. 14 can form a memory cell array by arranging them in a matrix like the storage devices shown in FIGS. 12 and 13. One transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, it is preferable to provide a smaller number of transistors 400 than the transistors 200.
＜トランジスタ４００＞
　トランジスタ４００は、トランジスタ２００と、同じ層に形成されており、並行して作製することができるトランジスタである。トランジスタ４００は、第１のゲート電極として機能する導電体４６０（導電体４６０ａ、および導電体４６０ｂ）と、第２のゲート電極として機能する導電体４０５と、ゲート絶縁層として機能する絶縁体２２２、絶縁体２２４、および絶縁体４５０と、チャネルが形成される領域を有する酸化物４３０ｃと、ソースまたはドレインの一方として機能する導電体４４０ａ、酸化物４３１ａ、および酸化物４３１ｂと、ソースまたはドレインの他方として機能する導電体４４０ｂ、酸化物４３２ａ、および酸化物４３２ｂと、バリア層として機能する絶縁体４４５ａ、および４４５ｂと、を有する。 <Transistor 400>
The transistor 400 is a transistor formed in the same layer as the transistor 200 and can be manufactured in parallel with the transistor 200. The transistor 400 includes a conductor 460 (conductor 460a and a conductor 460b) that functions as a first gate electrode, a conductor 405 that functions as a second gate electrode, and an insulator 222 that functions as a gate insulating layer. Insulator 224, and insulator 450, an oxide 430c having a region where a channel is formed, a conductor 440a, an oxide 431a, and an oxide 431b that function as one of a source or a drain, and the other of the source or drain. It has conductors 440b, oxides 432a, and oxides 432b that function as barrier layers, and insulators 445a and 445b that function as barrier layers.
　トランジスタ４００において、導電体４０５は、導電体２０５と、同じ層である。酸化物４３１ａ、および酸化物４３２ａと、酸化物２３０ａと、同じ層であり、酸化物４３１ｂ、および酸化物４３２ｂと、酸化物２３０ｂと、同じ層である。導電体４４０（導電体４４０ａ、および導電体４４０ｂ）は、導電体２４０と、同じ層である。絶縁体４４５（絶縁体４４５ａ、および絶縁体４４５ｂ）は、絶縁体２４５と、同じ層である。酸化物４３０ｃは、酸化物２３０ｃと、同じ層である。絶縁体４５０は、絶縁体２５０と、同じ層である。導電体４６０は、導電体２６０と、同じ層である。 In the transistor 400, the conductor 405 is the same layer as the conductor 205. Oxide 431a, oxide 432a, and oxide 230a are in the same layer, and oxide 431b, oxide 432b, and oxide 230b are in the same layer. The conductor 440 (conductor 440a and conductor 440b) is the same layer as the conductor 240. The insulator 445 (insulator 445a and insulator 445b) is the same layer as the insulator 245. Oxide 430c is the same layer as oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260.
　なお、同じ層に形成された構造体は、同時に形成することができる。例えば、酸化物４３０ｃは、酸化物２３０ｃとなる酸化膜を加工することで、形成することができる。 The structures formed in the same layer can be formed at the same time. For example, the oxide 430c can be formed by processing an oxide film that becomes the oxide 230c.
　トランジスタ４００の活性層として機能する酸化物４３０ｃは、酸化物２３０などと同様に、酸素欠損が低減され、水素または水などの不純物が低減されている。これにより、トランジスタ４００のしきい値電圧を０Ｖより大きくし、オフ電流を低減し、第２のゲート電圧及び第１のゲート電圧が０Ｖのときのドレイン電流を非常に小さくすることができる。 Oxide 430c, which functions as an active layer of the transistor 400, has reduced oxygen deficiency and impurities such as hydrogen and water, similarly to oxide 230 and the like. As a result, the threshold voltage of the transistor 400 can be made larger than 0V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small.
　本実施の形態は、他の実施の形態および実施例などに記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and examples.
（実施の形態４）
　本実施の形態では、図１５および図１６を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ（以下、ＯＳトランジスタと呼ぶ場合がある。）、および容量素子が適用されている記憶装置（以下、ＯＳメモリ装置と呼ぶ場合がある。）について説明する。ＯＳメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するＯＳトランジスタを有する記憶装置である。ＯＳトランジスタのオフ電流は極めて小さいので、ＯＳメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。 (Embodiment 4)
In the present embodiment, using FIGS. 15 and 16, a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitive element according to one aspect of the present invention are applied. A storage device (hereinafter, may be referred to as an OS memory device) will be described. The OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.
＜記憶装置の構成例＞
　図１５ＡにＯＳメモリ装置の構成の一例を示す。記憶装置１４００は、周辺回路１４１１、およびメモリセルアレイ１４７０を有する。周辺回路１４１１は、行回路１４２０、列回路１４３０、出力回路１４４０、およびコントロールロジック回路１４６０を有する。 <Configuration example of storage device>
FIG. 15A shows an example of the configuration of the OS memory device. The storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
　列回路１４３０は、例えば、列デコーダ、プリチャージ回路、センスアンプ、書き込み回路等を有する。プリチャージ回路は、配線をプリチャージする機能を有する。センスアンプは、メモリセルから読み出されたデータ信号を増幅する機能を有する。なお、上記配線は、メモリセルアレイ１４７０が有するメモリセルに接続されている配線であり、詳しくは後述する。増幅されたデータ信号は、出力回路１４４０を介して、データ信号ＲＤＡＴＡとして記憶装置１４００の外部に出力される。また、行回路１４２０は、例えば、行デコーダ、ワード線ドライバ回路等を有し、アクセスする行を選択することができる。 The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a writing circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. The wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. Further, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and the row to be accessed can be selected.
　記憶装置１４００には、外部から電源電圧として低電源電圧（ＶＳＳ）、周辺回路１４１１用の高電源電圧（ＶＤＤ）、メモリセルアレイ１４７０用の高電源電圧（ＶＩＬ）が供給される。また、記憶装置１４００には、制御信号（ＣＥ、ＷＥ、ＲＥ）、アドレス信号ＡＤＤＲ、データ信号ＷＤＡＴＡが外部から入力される。アドレス信号ＡＤＤＲは、行デコーダおよび列デコーダに入力され、データ信号ＷＤＡＴＡは書き込み回路に入力される。 A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400 from the outside as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
　コントロールロジック回路１４６０は、外部からの制御信号（ＣＥ、ＷＥ、ＲＥ）を処理して、行デコーダ、列デコーダの制御信号を生成する。ＣＥは、チップイネーブル信号であり、ＷＥは、書き込みイネーブル信号であり、ＲＥは、読み出しイネーブル信号である。コントロールロジック回路１４６０が処理する信号は、これに限定されるものではなく、必要に応じて、他の制御信号を入力すればよい。 The control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for row decoders and column decoders. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
　メモリセルアレイ１４７０は、行列状に配置された、複数個のメモリセルＭＣと、複数の配線を有する。なお、メモリセルアレイ１４７０と行回路１４２０とを接続している配線の数は、メモリセルＭＣの構成、一列に有するメモリセルＭＣの数などによって決まる。また、メモリセルアレイ１４７０と列回路１４３０とを接続している配線の数は、メモリセルＭＣの構成、一行に有するメモリセルＭＣの数などによって決まる。 The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in a row, and the like. The number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
　なお、図１５Ａにおいて、周辺回路１４１１とメモリセルアレイ１４７０を同一平面上に形成する例について示したが、本実施の形態はこれに限られるものではない。例えば、図１５Ｂに示すように、周辺回路１４１１の一部の上に、メモリセルアレイ１４７０が重なるように設けられてもよい。例えば、メモリセルアレイ１４７０の下に重なるように、センスアンプを設ける構成にしてもよい。 Although FIG. 15A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited to this. For example, as shown in FIG. 15B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.
　図１６に上述のメモリセルＭＣに適用できるメモリセルの構成例について説明する。 FIG. 16 describes an example of a memory cell configuration applicable to the above-mentioned memory cell MC.
［ＤＯＳＲＡＭ］
　図１６Ａ乃至図１６Ｃに、ＤＲＡＭのメモリセルの回路構成例を示す。本明細書等において、１ＯＳトランジスタ１容量素子型のメモリセルを用いたＤＲＡＭを、ＤＯＳＲＡＭ（Ｄｙｎａｍｉｃ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）と呼ぶ場合がある。図１６Ａに示す、メモリセル１４７１は、トランジスタＭ１と、容量素子ＣＡと、を有する。なお、トランジスタＭ１は、ゲート（トップゲートと呼ぶ場合がある。）、及びバックゲートを有する。 [DOSRAM]
16A to 16C show an example of a circuit configuration of a DRAM memory cell. In the present specification and the like, a DRAM using a memory cell of a 1OS transistor and 1 capacitance element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 16A includes a transistor M1 and a capacitive element CA. The transistor M1 has a gate (sometimes called a top gate) and a back gate.
　トランジスタＭ１の第１端子は、容量素子ＣＡの第１端子と接続され、トランジスタＭ１の第２端子は、配線ＢＩＬと接続され、トランジスタＭ１のゲートは、配線ＷＯＬと接続され、トランジスタＭ１のバックゲートは、配線ＢＧＬと接続されている。容量素子ＣＡの第２端子は、配線ＬＬと接続されている。 The first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1. Is connected to the wiring BGL. The second terminal of the capacitive element CA is connected to the wiring LL.
　配線ＢＩＬは、ビット線として機能し、配線ＷＯＬは、ワード線として機能する。配線ＬＬは、容量素子ＣＡの第２端子に所定の電位を印加するための配線として機能する。データの書き込み時、及び読み出し時において、配線ＬＬは、接地電位でも、低レベル電位としてもよい。配線ＢＧＬは、トランジスタＭ１のバックゲートに電位を印加するための配線として機能する。配線ＢＧＬに任意の電位を印加することによって、トランジスタＭ１のしきい値電圧を増減することができる。 The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, the wiring LL may have a ground potential or a low level potential. The wiring BGL functions as wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
　ここで、図１６Ａに示すメモリセル１４７１は、図１２に示す記憶装置に対応している。つまり、トランジスタＭ１はトランジスタ２００に、容量素子ＣＡは容量素子１００に、配線ＢＩＬは配線１００３に、配線ＷＯＬは配線１００４に、配線ＢＧＬは配線１００６に、配線ＬＬは配線１００５に対応している。なお、図１２に記載のトランジスタ３００は、図１５Ａ、および図１５Ｂに示す記憶装置１４００の周辺回路１４１１に設けられるトランジスタに対応する。 Here, the memory cell 1471 shown in FIG. 16A corresponds to the storage device shown in FIG. That is, the transistor M1 corresponds to the transistor 200, the capacitive element CA corresponds to the capacitive element 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring LL corresponds to the wiring 1005. The transistor 300 shown in FIG. 12 corresponds to a transistor provided in the peripheral circuit 1411 of the storage device 1400 shown in FIGS. 15A and 15B.
　また、メモリセルＭＣは、メモリセル１４７１に限定されず、回路構成の変更を行うことができる。例えば、メモリセルＭＣは、図１６Ｂに示すメモリセル１４７２のように、トランジスタＭ１のバックゲートが、配線ＢＧＬでなく、配線ＷＯＬと接続される構成にしてもよい。また、例えば、メモリセルＭＣは、図１６Ｃに示すメモリセル１４７３のように、シングルゲート構造のトランジスタ、つまりバックゲートを有さないトランジスタＭ１で構成されたメモリセルとしてもよい。 Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 16B. Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 having no back gate, as in the memory cell 1473 shown in FIG. 16C.
　上記実施の形態に示す半導体装置をメモリセル１４７１等に用いる場合、トランジスタＭ１としてトランジスタ２００を用い、容量素子ＣＡとして容量素子１００を用いることができる。トランジスタＭ１としてＯＳトランジスタを用いることによって、トランジスタＭ１のリーク電流を非常に低くすることができる。つまり、書き込んだデータをトランジスタＭ１によって長時間保持することができるため、メモリセルのリフレッシュの頻度を少なくすることができる。または、メモリセルのリフレッシュ動作を不要にすることができる。また、リーク電流が非常に低いため、メモリセル１４７１、メモリセル１４７２、メモリセル１４７３に対して多値データ、又はアナログデータを保持することができる。 When the semiconductor device shown in the above embodiment is used for a memory cell 1471 or the like, a transistor 200 can be used as the transistor M1 and a capacitance element 100 can be used as the capacitance element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very low. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cells can be reduced. Alternatively, the memory cell refresh operation can be eliminated. Further, since the leak current is very low, it is possible to hold multi-valued data or analog data for the memory cell 1471, the memory cell 1472, and the memory cell 1473.
　また、ＤＯＳＲＡＭにおいて、上記のように、メモリセルアレイ１４７０の下に重なるように、センスアンプを設ける構成にすると、ビット線を短くすることができる。これにより、ビット線容量が小さくなり、メモリセルの保持容量を低減することができる。 Further, in the DOSRAM, if the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.
［ＮＯＳＲＡＭ］
　図１６Ｄ乃至図１６Ｇに、２トランジスタ１容量素子のゲインセル型のメモリセルの回路構成例を示す。図１６Ｄに示す、メモリセル１４７４は、トランジスタＭ２と、トランジスタＭ３と、容量素子ＣＢと、を有する。なお、トランジスタＭ２は、トップゲート（単にゲートと呼ぶ場合がある。）、及びバックゲートを有する。本明細書等において、トランジスタＭ２にＯＳトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、ＮＯＳＲＡＭ（Ｎｏｎｖｏｌａｔｉｌｅ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ）と呼ぶ場合がある。 [NOSRAM]
16D to 16G show an example of a circuit configuration of a gain cell type memory cell having a 2-transistor and 1-capacity element. The memory cell 1474 shown in FIG. 16D includes a transistor M2, a transistor M3, and a capacitance element CB. The transistor M2 has a top gate (sometimes referred to simply as a gate) and a back gate. In the present specification and the like, a storage device having a gain cell type memory cell using an OS transistor in the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).
　トランジスタＭ２の第１端子は、容量素子ＣＢの第１端子と接続され、トランジスタＭ２の第２端子は、配線ＷＢＬと接続され、トランジスタＭ２のゲートは、配線ＷＯＬと接続され、トランジスタＭ２のバックゲートは、配線ＢＧＬと接続されている。容量素子ＣＢの第２端子は、配線ＣＡＬと接続されている。トランジスタＭ３の第１端子は、配線ＲＢＬと接続され、トランジスタＭ３の第２端子は、配線ＳＬと接続され、トランジスタＭ３のゲートは、容量素子ＣＢの第１端子と接続されている。 The first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2. Is connected to the wiring BGL. The second terminal of the capacitive element CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
　配線ＷＢＬは、書き込みビット線として機能し、配線ＲＢＬは、読み出しビット線として機能し、配線ＷＯＬは、ワード線として機能する。配線ＣＡＬは、容量素子ＣＢの第２端子に所定の電位を印加するための配線として機能する。データの書き込み時、およびデータの読み出し時においては、配線ＣＡＬには、高レベル電位を印加するのが好ましい。また、データ保持中においては、配線ＣＡＬには、低レベル電位を印加するのが好ましい。配線ＢＧＬは、トランジスタＭ２のバックゲートに電位を印加するための配線として機能する。配線ＢＧＬに任意の電位を印加することによって、トランジスタＭ２のしきい値電圧を増減することができる。 The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data and reading data, it is preferable to apply a high level potential to the wiring CAL. Further, during data retention, it is preferable to apply a low level potential to the wiring CAL. The wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
　ここで、図１６Ｄに示すメモリセル１４７４は、図１３に示す記憶装置に対応している。つまり、トランジスタＭ２はトランジスタ２００に、容量素子ＣＢは容量素子１００に、トランジスタＭ３はトランジスタ３００に、配線ＷＢＬは配線２００３に、配線ＷＯＬは配線２００４に、配線ＢＧＬは配線２００６に、配線ＣＡＬは配線２００５に、配線ＲＢＬは配線２００２に、配線ＳＬは配線２００１に対応している。 Here, the memory cell 1474 shown in FIG. 16D corresponds to the storage device shown in FIG. That is, the transistor M2 is connected to the transistor 200, the capacitive element CB is connected to the capacitive element 100, the transistor M3 is connected to the transistor 300, the wiring WBL is connected to the wiring 2003, the wiring WOL is connected to the wiring 2004, the wiring BGL is connected to the wiring 2006, and the wiring CAL is connected to the wiring 2006. In 2005, the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.
　また、メモリセルＭＣは、メモリセル１４７４に限定されず、回路の構成を適宜変更することができる。例えば、メモリセルＭＣは、図１６Ｅに示すメモリセル１４７５のように、トランジスタＭ２のバックゲートが、配線ＢＧＬでなく、配線ＷＯＬと接続される構成にしてもよい。また、例えば、メモリセルＭＣは、図１６Ｆに示すメモリセル１４７６のように、シングルゲート構造のトランジスタ、つまりバックゲートを有さないトランジスタＭ２で構成されたメモリセルとしてもよい。また、例えば、メモリセルＭＣは、図１６Ｇに示すメモリセル１４７７のように、配線ＷＢＬと配線ＲＢＬを一本の配線ＢＩＬとしてまとめた構成であってもよい。 Further, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 16E. Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 16F. Further, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL, as in the memory cell 1477 shown in FIG. 16G.
　上記実施の形態に示す半導体装置をメモリセル１４７４等に用いる場合、トランジスタＭ２としてトランジスタ２００を用い、トランジスタＭ３としてトランジスタ３００を用い、容量素子ＣＢとして容量素子１００を用いることができる。トランジスタＭ２としてＯＳトランジスタを用いることによって、トランジスタＭ２のリーク電流を非常に低くすることができる。これにより、書き込んだデータをトランジスタＭ２によって長時間保持することができるため、メモリセルのリフレッシュの頻度を少なくすることができる。または、メモリセルのリフレッシュ動作を不要にすることができる。また、リーク電流が非常に低いため、メモリセル１４７４に多値データ、又はアナログデータを保持することができる。メモリセル１４７５乃至メモリセル１４７７も同様である。 When the semiconductor device shown in the above embodiment is used for a memory cell 1474 or the like, a transistor 200 can be used as the transistor M2, a transistor 300 can be used as the transistor M3, and a capacitance element 100 can be used as the capacitance element CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very low. As a result, the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cells can be reduced. Alternatively, the memory cell refresh operation can be eliminated. Further, since the leak current is very low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
　なお、トランジスタＭ３は、チャネル形成領域にシリコンを有するトランジスタ（以下、Ｓｉトランジスタと呼ぶ場合がある）であってもよい。Ｓｉトランジスタの導電型は、ｎチャネル型としてもよいし、ｐチャネル型としてもよい。Ｓｉトランジスタは、ＯＳトランジスタよりも電界効果移動度が高くなる場合がある。よって、読み出しトランジスタとして機能するトランジスタＭ３として、Ｓｉトランジスタを用いてもよい。また、トランジスタＭ３にＳｉトランジスタを用いることで、トランジスタＭ３の上に積層してトランジスタＭ２を設けることができるので、メモリセルの占有面積を低減し、記憶装置の高集積化を図ることができる。 The transistor M3 may be a transistor having silicon in the channel forming region (hereinafter, may be referred to as a Si transistor). The conductive type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a readout transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by stacking the transistor M3 on the transistor M3, so that the occupied area of the memory cell can be reduced and the storage device can be highly integrated.
　また、トランジスタＭ３はＯＳトランジスタであってもよい。トランジスタＭ２およびトランジスタＭ３にＯＳトランジスタを用いた場合、メモリセルアレイ１４７０をｎ型トランジスタのみを用いて回路を構成することができる。 Further, the transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M2 and the transistor M3, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.
　また、図１６Ｈに３トランジスタ１容量素子のゲインセル型のメモリセルの一例を示す。図１６Ｈに示すメモリセル１４７８は、トランジスタＭ４乃至トランジスタＭ６、および容量素子ＣＣを有する。容量素子ＣＣは適宜設けられる。メモリセル１４７８は、配線ＢＩＬ、配線ＲＷＬ、配線ＷＷＬ、配線ＢＧＬ、および配線ＧＮＤＬに電気的に接続されている。配線ＧＮＤＬは低レベル電位を与える配線である。なお、メモリセル１４７８を、配線ＢＩＬに代えて、配線ＲＢＬ、配線ＷＢＬに電気的に接続してもよい。 Further, FIG. 16H shows an example of a gain cell type memory cell having a 3-transistor and 1-capacity element. The memory cell 1478 shown in FIG. 16H includes transistors M4 to M6 and a capacitive element CC. The capacitive element CC is appropriately provided. The memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL. Wiring GNDL is a wiring that gives a low level potential. The memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
　トランジスタＭ４は、バックゲートを有するＯＳトランジスタであり、バックゲートは配線ＢＧＬに電気的に接続されている。なお、トランジスタＭ４のバックゲートとゲートとを互いに電気的に接続してもよい。あるいは、トランジスタＭ４はバックゲートを有さなくてもよい。 The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. The back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not have to have a back gate.
　なお、トランジスタＭ５、トランジスタＭ６はそれぞれ、ｎチャネル型Ｓｉトランジスタまたはｐチャネル型Ｓｉトランジスタでもよい。或いは、トランジスタＭ４乃至トランジスタＭ６がＯＳトランジスタでもよい。この場合、メモリセルアレイ１４７０をｎ型トランジスタのみを用いて回路を構成することができる。 The transistor M5 and the transistor M6 may be an n-channel Si transistor or a p-channel Si transistor, respectively. Alternatively, the transistor M4 to the transistor M6 may be an OS transistor. In this case, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.
　上記実施の形態に示す半導体装置をメモリセル１４７８に用いる場合、トランジスタＭ４としてトランジスタ２００を用い、トランジスタＭ５、トランジスタＭ６としてトランジスタ３００を用い、容量素子ＣＣとして容量素子１００を用いることができる。トランジスタＭ４としてＯＳトランジスタを用いることによって、トランジスタＭ４のリーク電流を非常に低くすることができる。 When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitance element 100 can be used as the capacitance element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very low.
　なお、本実施の形態に示す、周辺回路１４１１、メモリセルアレイ１４７０等の構成は、上記に限定されるものではない。これらの回路、および当該回路に接続される配線、回路素子等の、配置または機能は、必要に応じて、変更、削除、または追加してもよい。 The configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above. The arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
　本実施の形態に示す構成は、他の実施の形態、実施例などに示す構成と適宜組み合わせて用いることができる。 The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments, examples, and the like.
（実施の形態５）
　本実施の形態では、図１７を用いて、本発明の半導体装置が実装されたチップ１２００の一例を示す。チップ１２００には、複数の回路（システム）が実装されている。このように、複数の回路（システム）を一つのチップに集積する技術を、システムオンチップ（Ｓｙｓｔｅｍ　ｏｎ　Ｃｈｉｐ：ＳｏＣ）と呼ぶ場合がある。 (Embodiment 5)
In the present embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIG. A plurality of circuits (systems) are mounted on the chip 1200. Such a technique of integrating a plurality of circuits (systems) on one chip may be called a system on chip (SoC).
　図１７Ａに示すように、チップ１２００は、ＣＰＵ１２１１、ＧＰＵ１２１２、一または複数のアナログ演算部１２１３、一または複数のメモリコントローラ１２１４、一または複数のインターフェース１２１５、一または複数のネットワーク回路１２１６等を有する。 As shown in FIG. 17A, the chip 1200 includes a CPU 1211, GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
　チップ１２００には、バンプ（図示しない）が設けられ、図１７Ｂに示すように、プリント基板（Ｐｒｉｎｔｅｄ　Ｃｉｒｃｕｉｔ　Ｂｏａｒｄ：ＰＣＢ）１２０１の第１の面と接続する。また、ＰＣＢ１２０１の第１の面の裏面には、複数のバンプ１２０２が設けられており、マザーボード１２０３と接続する。 The chip 1200 is provided with a bump (not shown) and is connected to the first surface of a printed circuit board (Printed Circuit Board: PCB) 1201 as shown in FIG. 17B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
　マザーボード１２０３には、ＤＲＡＭ１２２１、フラッシュメモリ１２２２等の記憶装置が設けられていてもよい。例えば、ＤＲＡＭ１２２１に先の実施の形態に示すＤＯＳＲＡＭを用いることができる。また、例えば、フラッシュメモリ１２２２に先の実施の形態に示すＮＯＳＲＡＭを用いることができる。 The motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Further, for example, the NO SRAM shown in the previous embodiment can be used for the flash memory 1222.
　ＣＰＵ１２１１は、複数のＣＰＵコアを有することが好ましい。また、ＧＰＵ１２１２は、複数のＧＰＵコアを有することが好ましい。また、ＣＰＵ１２１１、およびＧＰＵ１２１２は、それぞれ一時的にデータを格納するメモリを有していてもよい。または、ＣＰＵ１２１１、およびＧＰＵ１２１２に共通のメモリが、チップ１２００に設けられていてもよい。該メモリには、前述したＮＯＳＲＡＭや、ＤＯＳＲＡＭを用いることができる。また、ＧＰＵ１２１２は、多数のデータの並列計算に適しており、画像処理や積和演算に用いることができる。ＧＰＵ１２１２に、本発明の酸化物半導体を用いた画像処理回路や、積和演算回路を設けることで、画像処理、および積和演算を低消費電力で実行することが可能になる。 The CPU 1211 preferably has a plurality of CPU cores. Further, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. As the memory, the above-mentioned NOSRAM or DOSRAM can be used. Further, GPU1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, it becomes possible to execute image processing and product-sum calculation with low power consumption.
　また、ＣＰＵ１２１１、およびＧＰＵ１２１２が同一チップに設けられていることで、ＣＰＵ１２１１およびＧＰＵ１２１２間の配線を短くすることができ、ＣＰＵ１２１１からＧＰＵ１２１２へのデータ転送、ＣＰＵ１２１１、およびＧＰＵ１２１２が有するメモリ間のデータ転送、およびＧＰＵ１２１２での演算後に、ＧＰＵ１２１２からＣＰＵ１２１１への演算結果の転送を高速に行うことができる。 Further, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memory of the CPU 1211 and the GPU 1212, And after the calculation on the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
　アナログ演算部１２１３はＡ／Ｄ（アナログ／デジタル）変換回路、およびＤ／Ａ（デジタル／アナログ）変換回路の一、または両方を有する。また、アナログ演算部１２１３に上記積和演算回路を設けてもよい。 The analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.
　メモリコントローラ１２１４は、ＤＲＡＭ１２２１のコントローラとして機能する回路、およびフラッシュメモリ１２２２のインターフェースとして機能する回路を有する。 The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
　インターフェース１２１５は、表示装置、スピーカー、マイクロフォン、カメラ、コントローラなどの外部接続機器とのインターフェース回路を有する。コントローラとは、マウス、キーボード、ゲーム用コントローラなどを含む。このようなインターフェースとして、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＨＤＭＩ（登録商標）（Ｈｉｇｈ−Ｄｅｆｉｎｉｔｉｏｎ　Ｍｕｌｔｉｍｅｄｉａ　Ｉｎｔｅｒｆａｃｅ）などを用いることができる。 The interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface) and the like can be used.
　ネットワーク回路１２１６は、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）などのネットワーク用の回路を有する。また、ネットワークセキュリティー用の回路を有してもよい。 The network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.
　チップ１２００には、上記回路（システム）を同一の製造プロセスで形成することが可能である。そのため、チップ１２００に必要な回路の数が増えても、製造プロセスを増やす必要が無く、チップ１２００を低コストで作製することができる。 The above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
　ＧＰＵ１２１２を有するチップ１２００が設けられたＰＣＢ１２０１、ＤＲＡＭ１２２１、およびフラッシュメモリ１２２２が設けられたマザーボード１２０３は、ＧＰＵモジュール１２０４と呼ぶことができる。 The PCB 1201, the DRAM 1221 provided with the chip 1200 having the GPU 1212, and the motherboard 1203 provided with the flash memory 1222 can be referred to as the GPU module 1204.
　ＧＰＵモジュール１２０４は、ＳｏＣ技術を用いたチップ１２００を有しているため、そのサイズを小さくすることができる。また、画像処理に優れていることから、スマートフォン、タブレット端末、ラップトップＰＣ、携帯型（持ち出し可能な）ゲーム機などの携帯型電子機器に用いることが好適である。また、ＧＰＵ１２１２を用いた積和演算回路により、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの手法を実行することができるため、チップ１２００をＡＩチップ、またはＧＰＵモジュール１２０４をＡＩシステムモジュールとして用いることができる。 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines. In addition, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DEM) by a product-sum calculation circuit using GPU1212 Since a method such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
　本実施の形態に示す構成は、他の実施の形態、実施例などに示す構成と適宜組み合わせて用いることができる。 The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments, examples, and the like.
（実施の形態６）
　本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器（例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ（ビデオカメラも含む）、録画再生装置、ナビゲーションシステムなど）の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータ、ノート型のコンピュータ、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード（例えば、ＳＤカード）、ＵＳＢメモリ、ＳＳＤ（ソリッド・ステート・ドライブ）等の各種のリムーバブル記憶装置に適用される。図１８にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。 (Embodiment 6)
In this embodiment, an application example of the storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Can be applied to. Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 18 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
　図１８ＡはＵＳＢメモリの模式図である。ＵＳＢメモリ１１００は、筐体１１０１、キャップ１１０２、ＵＳＢコネクタ１１０３および基板１１０４を有する。基板１１０４は、筐体１１０１に収納されている。例えば、基板１１０４には、メモリチップ１１０５、コントローラチップ１１０６が取り付けられている。基板１１０４のメモリチップ１１０５などに先の実施の形態に示す半導体装置を組み込むことができる。 FIG. 18A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like of the substrate 1104.
　図１８ＢはＳＤカードの外観の模式図であり、図１８Ｃは、ＳＤカードの内部構造の模式図である。ＳＤカード１１１０は、筐体１１１１、コネクタ１１１２および基板１１１３を有する。基板１１１３は筐体１１１１に収納されている。例えば、基板１１１３には、メモリチップ１１１４、コントローラチップ１１１５が取り付けられている。基板１１１３の裏面側にもメモリチップ１１１４を設けることで、ＳＤカード１１１０の容量を増やすことができる。また、無線通信機能を備えた無線チップを基板１１１３に設けてもよい。これによって、ホスト装置とＳＤカード１１１０間の無線通信によって、メモリチップ１１１４のデータの読み出し、書き込みが可能となる。基板１１１３のメモリチップ１１１４などに先の実施の形態に示す半導体装置を組み込むことができる。 FIG. 18B is a schematic view of the appearance of the SD card, and FIG. 18C is a schematic view of the internal structure of the SD card. The SD card 1110 has a housing 1111 and a connector 1112 and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 on the back surface side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. As a result, data on the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like of the substrate 1113.
　図１８ＤはＳＳＤの外観の模式図であり、図１８Ｅは、ＳＳＤの内部構造の模式図である。ＳＳＤ１１５０は、筐体１１５１、コネクタ１１５２および基板１１５３を有する。基板１１５３は筐体１１５１に収納されている。例えば、基板１１５３には、メモリチップ１１５４、メモリチップ１１５５、コントローラチップ１１５６が取り付けられている。メモリチップ１１５５はコントローラチップ１１５６のワークメモリであり、例えばＤＯＳＲＡＭチップを用いればよい。基板１１５３の裏面側にもメモリチップ１１５４を設けることで、ＳＳＤ１１５０の容量を増やすことができる。基板１１５３のメモリチップ１１５４などに先の実施の形態に示す半導体装置を組み込むことができる。 FIG. 18D is a schematic view of the appearance of the SSD, and FIG. 18E is a schematic view of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like of the substrate 1153.
　本実施の形態は、他の実施の形態、実施例などに記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, and the like.
（実施の形態７）
　本発明の一態様に係る半導体装置は、ＣＰＵやＧＰＵなどのプロセッサ、またはチップに用いることができる。図１９に、本発明の一態様に係るＣＰＵやＧＰＵなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。 (Embodiment 7)
The semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip. FIG. 19 shows a specific example of an electronic device provided with a processor such as a CPU or GPU or a chip according to one aspect of the present invention.
＜電子機器・システム＞
　本発明の一態様に係るＧＰＵまたはチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型またはノート型の情報端末用などのモニタ、デジタルサイネージ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｇｅ：電子看板）、パチンコ機などの大型ゲーム機、などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、電子ブックリーダー、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係るＧＰＵまたはチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。 <Electronic equipment / system>
The GPU or chip according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signage), and large game machines such as pachinko machines. In addition to electronic devices equipped with the above, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be mentioned. Further, by providing the GPU or chip according to one aspect of the present invention in the electronic device, artificial intelligence can be mounted on the electronic device.
　本発明の一態様の電子機器は、アンテナを有していてもよい。アンテナで信号を受信することで、表示部で映像や情報等の表示を行うことができる。また、電子機器がアンテナ及び二次電池を有する場合、アンテナを、非接触電力伝送に用いてもよい。 The electronic device of one aspect of the present invention may have an antenna. By receiving the signal with the antenna, the display unit can display images, information, and the like. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.
　本発明の一態様の電子機器は、センサ（力、変位、位置、速度、加速度、角速度、回転数、距離、光、液、磁気、温度、化学物質、音声、時間、硬度、電場、電流、電圧、電力、放射線、流量、湿度、傾度、振動、においまたは赤外線を測定する機能を含むもの）を有していてもよい。 The electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
　本発明の一態様の電子機器は、様々な機能を有することができる。例えば、様々な情報（静止画、動画、テキスト画像など）を表示部に表示する機能、タッチパネル機能、カレンダー、日付または時刻などを表示する機能、様々なソフトウェア（プログラム）を実行する機能、無線通信機能、記録媒体に記録されているプログラムまたはデータを読み出す機能等を有することができる。図１９に、電子機器の例を示す。 The electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like. FIG. 19 shows an example of an electronic device.
［情報端末］
　図１９Ａには、情報端末の一種である携帯電話（スマートフォン）が図示されている。情報端末５１００は、筐体５１０１と、表示部５１０２と、を有しており、入力用インターフェースとして、タッチパネルが表示部５１０２に備えられ、ボタンが筐体５１０１に備えられている。 [Information terminal]
FIG. 19A illustrates a mobile phone (smartphone) which is a kind of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102, and as an input interface, a touch panel is provided in the display unit 5102 and buttons are provided in the housing 5101.
　情報端末５１００は、本発明の一態様のチップを適用することで、人工知能を利用したアプリケーションを実行することができる。人工知能を利用したアプリケーションとしては、例えば、会話を認識してその会話内容を表示部５１０２に表示するアプリケーション、表示部５１０２に備えるタッチパネルに対してユーザが入力した文字、図形などを認識して、表示部５１０２に表示するアプリケーション、指紋や声紋などの生体認証を行うアプリケーションなどが挙げられる。 The information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention. Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102. Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
　図１９Ｂには、ノート型情報端末５２００が図示されている。ノート型情報端末５２００は、情報端末の本体５２０１と、表示部５２０２と、キーボード５２０３と、を有する。 FIG. 19B illustrates a notebook type information terminal 5200. The notebook type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
　ノート型情報端末５２００は、先述した情報端末５１００と同様に、本発明の一態様のチップを適用することで、人工知能を利用したアプリケーションを実行することができる。人工知能を利用したアプリケーションとしては、例えば、設計支援ソフトウェア、文章添削ソフトウェア、献立自動生成ソフトウェアなどが挙げられる。また、ノート型情報端末５２００を用いることで、新規の人工知能の開発を行うことができる。 Similar to the information terminal 5100 described above, the notebook-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
　なお、上述では、電子機器としてスマートフォン、およびノート型情報端末を例として、それぞれ図１９Ａ、図１９Ｂに図示したが、スマートフォン、およびノート型情報端末以外の情報端末を適用することができる。スマートフォン、およびノート型情報端末以外の情報端末としては、例えば、ＰＤＡ（Ｐｅｒｓｏｎａｌ　Ｄｉｇｉｔａｌ　Ａｓｓｉｓｔａｎｔ）、デスクトップ型情報端末、ワークステーションなどが挙げられる。 In the above description, a smartphone and a notebook-type information terminal are taken as examples of electronic devices, which are shown in FIGS. 19A and 19B, respectively, but information terminals other than the smartphone and the notebook-type information terminal can be applied. Examples of information terminals other than smartphones and notebook-type information terminals include PDA (Personal Digital Assistant), desktop-type information terminals, workstations, and the like.
［ゲーム機］
　図１９Ｃは、ゲーム機の一例である携帯ゲーム機５３００を示している。携帯ゲーム機５３００は、筐体５３０１、筐体５３０２、筐体５３０３、表示部５３０４、接続部５３０５、操作キー５３０６等を有する。筐体５３０２、および筐体５３０３は、筐体５３０１から取り外すことが可能である。筐体５３０１に設けられている接続部５３０５を別の筐体（図示せず）に取り付けることで、表示部５３０４に出力される映像を、別の映像機器（図示せず）に出力することができる。このとき、筐体５３０２、および筐体５３０３は、それぞれ操作部として機能することができる。これにより、複数のプレイヤーが同時にゲームを行うことができる。筐体５３０１、筐体５３０２、および筐体５３０３の基板に設けられているチップなどに先の実施の形態に示すチップを組み込むことができる。 [game machine]
FIG. 19C shows a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided in the housing 5301 to another housing (not shown), the image output to the display unit 5304 can be output to another video device (not shown). it can. At this time, the housing 5302 and the housing 5303 can each function as operation units. As a result, a plurality of players can play the game at the same time. The chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
　また、図１９Ｄは、ゲーム機の一例である据え置き型ゲーム機５４００を示している。据え置き型ゲーム機５４００には、無線または有線でコントローラ５４０２が接続されている。 Further, FIG. 19D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
　携帯ゲーム機５３００、据え置き型ゲーム機５４００などのゲーム機に本発明の一態様のＧＰＵまたはチップを適用することによって、低消費電力のゲーム機を実現することができる。また、低消費電力により、回路からの発熱を低減することができるため、発熱によるその回路自体、周辺回路、およびモジュールへの影響を少なくすることができる。 By applying the GPU or chip of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400, a low power consumption game machine can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
　更に、携帯ゲーム機５３００に本発明の一態様のＧＰＵまたはチップを適用することによって、人工知能を有する携帯ゲーム機５３００を実現することができる。 Further, by applying the GPU or chip of one aspect of the present invention to the portable game machine 5300, the portable game machine 5300 having artificial intelligence can be realized.
　本来、ゲームの進行、ゲーム上に登場する生物の言動、ゲーム上で発生する現象などの表現は、そのゲームが有するプログラムによって定められているが、携帯ゲーム機５３００に人工知能を適用することにより、ゲームのプログラムに限定されない表現が可能になる。例えば、プレイヤーが問いかける内容、ゲームの進行状況、時刻、ゲーム上に登場する人物の言動が変化するといった表現が可能となる。 Originally, expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are defined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5300. , Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
　また、携帯ゲーム機５３００で複数のプレイヤーが必要なゲームを行う場合、人工知能によって擬人的にゲームプレイヤーを構成することができるため、対戦相手を人工知能によるゲームプレイヤーとすることによって、１人でもゲームを行うことができる。 Further, when a plurality of players are required to play a game on the portable game machine 5300, the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one person can play the game. You can play the game.
　図１９Ｃ、図１９Ｄでは、ゲーム機の一例として携帯ゲーム機、および据え置き型ゲーム機を図示しているが、本発明の一態様のＧＰＵまたはチップを適用するゲーム機はこれに限定されない。本発明の一態様のＧＰＵまたはチップを適用するゲーム機としては、例えば、娯楽施設（ゲームセンター、遊園地など）に設置されるアーケードゲーム機、スポーツ施設に設置されるバッティング練習用の投球マシンなどが挙げられる。 19C and 19D show a portable game machine and a stationary game machine as examples of the game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this. Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like. Can be mentioned.
［大型コンピュータ］
　本発明の一態様のＧＰＵまたはチップは、大型コンピュータに適用することができる。 [Large computer]
The GPU or chip of one aspect of the present invention can be applied to a large computer.
　図１９Ｅは、大型コンピュータの一例である、スーパーコンピュータ５５００を示す図である。図１９Ｆは、スーパーコンピュータ５５００が有するラックマウント型の計算機５５０２を示す図である。 FIG. 19E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 19F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
　スーパーコンピュータ５５００は、ラック５５０１と、複数のラックマウント型の計算機５５０２と、を有する。なお、複数の計算機５５０２は、ラック５５０１に格納されている。また、計算機５５０２には、複数の基板５５０４が設けられ、当該基板上に上記実施の形態で説明したＧＰＵまたはチップを搭載することができる。 The supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502. The plurality of calculators 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or chip described in the above embodiment can be mounted on the substrate.
　スーパーコンピュータ５５００は、主に科学技術計算に利用される大型コンピュータである。科学技術計算では、膨大な演算を高速に処理する必要があるため、消費電力が高く、チップの発熱が大きい。スーパーコンピュータ５５００に本発明の一態様のＧＰＵまたはチップを適用することによって、低消費電力のスーパーコンピュータを実現することができる。また、低消費電力により、回路からの発熱を低減することができるため、発熱によるその回路自体、周辺回路、およびモジュールへの影響を少なくすることができる。 The supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the chip generates a lot of heat. By applying the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
　図１９Ｅ、図１９Ｆでは、大型コンピュータの一例としてスーパーコンピュータを図示しているが、本発明の一態様のＧＰＵまたはチップを適用する大型コンピュータはこれに限定されない。本発明の一態様のＧＰＵまたはチップを適用する大型コンピュータとしては、例えば、サービスを提供するコンピュータ（サーバー）、大型汎用コンピュータ（メインフレーム）などが挙げられる。 In FIGS. 19E and 19F, a supercomputer is illustrated as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this. Examples of the large computer to which the GPU or chip of one aspect of the present invention is applied include a computer (server) that provides a service, a large general-purpose computer (mainframe), and the like.
［移動体］
　本発明の一態様のＧＰＵまたはチップは、移動体である自動車、および自動車の運転席周辺に適用することができる。 [Mobile]
The GPU or chip of one aspect of the present invention can be applied to a moving vehicle and around the driver's seat of the vehicle.
　図１９Ｇは、移動体の一例である自動車の室内におけるフロントガラス周辺を示す図である。図１９Ｇでは、ダッシュボードに取り付けられた表示パネル５７０１、表示パネル５７０２、表示パネル５７０３の他、ピラーに取り付けられた表示パネル５７０４を図示している。 FIG. 19G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body. In FIG. 19G, the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are shown.
　表示パネル５７０１乃至表示パネル５７０３は、スピードメーターやタコメーター、走行距離、燃料計、ギア状態、エアコンの設定などを表示することで、その他様々な情報を提供することができる。また、表示パネルに表示される表示項目やレイアウトなどは、ユーザの好みに合わせて適宜変更することができ、デザイン性を高めることが可能である。表示パネル５７０１乃至表示パネル５７０３は、照明装置として用いることも可能である。 The display panel 5701 to the display panel 5703 can provide various other information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like. In addition, the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panel 5701 to 5703 can also be used as a lighting device.
　表示パネル５７０４には、自動車に設けられた撮像装置（図示しない。）からの映像を映し出すことによって、ピラーで遮られた視界（死角）を補完することができる。すなわち、自動車の外側に設けられた撮像装置からの画像を表示することによって、死角を補い、安全性を高めることができる。また、見えない部分を補完する映像を映すことによって、より自然に違和感なく安全確認を行うことができる。表示パネル５７０４は、照明装置として用いることもできる。 The display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an image pickup device (not shown) provided in the automobile. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.
　本発明の一態様のＧＰＵまたはチップは人工知能の構成要素として適用できるため、例えば、当該チップを自動車の自動運転システムに用いることができる。また、当該チップを道路案内、危険予測などを行うシステムに用いることができる。表示パネル５７０１乃至表示パネル５７０４には、道路案内、危険予測などの情報を表示する構成としてもよい。 Since the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system of an automobile. In addition, the chip can be used in a system for road guidance, danger prediction, and the like. The display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
　なお、上述では、移動体の一例として自動車について説明しているが、移動体は自動車に限定されない。例えば、移動体としては、電車、モノレール、船、飛行体（ヘリコプター、無人航空機（ドローン）、飛行機、ロケット）なども挙げることができ、これらの移動体に本発明の一態様のチップを適用して、人工知能を利用したシステムを付与することができる。 In the above, the automobile is described as an example of the moving body, but the moving body is not limited to the automobile. For example, moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, a system using artificial intelligence can be provided.
［電化製品］
　図１９Ｈは、電化製品の一例である電気冷凍冷蔵庫５８００を示している。電気冷凍冷蔵庫５８００は、筐体５８０１、冷蔵室用扉５８０２、冷凍室用扉５８０３等を有する。 [Electrical appliances]
FIG. 19H shows an electric refrigerator / freezer 5800, which is an example of an electric appliance. The electric refrigerator / freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
　電気冷凍冷蔵庫５８００に本発明の一態様のチップを適用することによって、人工知能を有する電気冷凍冷蔵庫５８００を実現することができる。人工知能を利用することによって電気冷凍冷蔵庫５８００は、電気冷凍冷蔵庫５８００に保存されている食材、その食材の消費期限などを基に献立を自動生成する機能や、電気冷凍冷蔵庫５８００に保存されている食材に合わせた温度に自動的に調節する機能などを有することができる。 By applying the chip of one aspect of the present invention to the electric refrigerator / freezer 5800, the electric refrigerator / freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric freezer / refrigerator 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800, the expiration date of the foodstuffs, etc., and is stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the food.
　電化製品の一例として電気冷凍冷蔵庫について説明したが、その他の電化製品としては、例えば、掃除機、電子レンジ、電子オーブン、炊飯器、湯沸かし器、ＩＨ調理器、ウォーターサーバ、エアーコンディショナーを含む冷暖房器具、洗濯機、乾燥機、オーディオビジュアル機器などが挙げられる。 Although electric refrigerators and freezers have been described as an example of electric appliances, other electric appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
　本実施の形態で説明した電子機器、その電子機器の機能、人工知能の応用例、その効果などは、他の電子機器の記載と適宜組み合わせることができる。 The electronic device described in this embodiment, the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
　本実施の形態は、他の実施の形態、実施例などに記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, and the like.
　本実施例では、試料１Ａとして、第１のトランジスタと第２のトランジスタを積層して有する半導体装置を作製した。その後、当該半導体装置の断面観察を行った。なお、第１のトランジスタおよび第２のトランジスタとして、図２に示すトランジスタ２００を、作製した。 In this embodiment, as sample 1A, a semiconductor device having a first transistor and a second transistor stacked on top of each other was manufactured. After that, the cross section of the semiconductor device was observed. The transistor 200 shown in FIG. 2 was manufactured as the first transistor and the second transistor.
＜試料の作製方法＞
　以下に、試料１Ａの作製方法を説明する。 <Sample preparation method>
The method for producing sample 1A will be described below.
　まず、下地上に第１のトランジスタ２００を有する第１層（１ｓｔ　ｌａｙｅｒ）作成した。 First, a first layer (1st layer) having a first transistor 200 on the base was created.
　具体的に、試料１Ａにおいて、酸化物２３０ａとなる第１の酸化物（酸化膜２３０Ａ）として、Ｉｎ−Ｇａ−Ｚｎ酸化物をスパッタリング法により、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜した。続いて、第１の酸化物上に、酸化物２３０ｂとなる第２の酸化物（酸化膜２３０Ｂ）として、Ｉｎ−Ｇａ−Ｚｎ酸化物をスパッタリング法により、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のターゲットを用いて成膜した後、Ｉｎ−Ｇａ−Ｚｎ酸化物をスパッタリング法により、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜することで、２層の積層構造として形成した。なお、第１の酸化物と第２の酸化物とは、連続成膜した。 Specifically, in sample 1A, In-Ga-Zn oxide is sputtered as the first oxide (oxide film 230A) to be oxide 230a, and In: Ga: Zn = 1: 3: 4 [atomic]. A film was formed using a target of [number ratio]. Subsequently, In—Ga—Zn oxide is spun on the first oxide as the second oxide (oxide film 230B) to be the oxide 230b by a sputtering method, In: Ga: Zn = 4: 2: 2: After forming a film using a target of 4.1 [atomic number ratio], In-Ga-Zn oxide is precipitated by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic number ratio]. It was formed as a two-layer laminated structure by forming a film. The first oxide and the second oxide were continuously formed into a film.
　続いて、試料１Ａにおいて、第２の酸化物上に、導電体２４０となるタングステン膜を成膜した。その後、当該導電体、第２の酸化物、および第１の酸化物を、ハードマスクを用いて加工し、酸化物２３０ａ、酸化物２３０ｂ、導電層２４０Ｂ、および絶縁層２４５となる絶縁層を形成した。 Subsequently, in sample 1A, a tungsten film to be a conductor 240 was formed on the second oxide. After that, the conductor, the second oxide, and the first oxide are processed using a hard mask to form an insulating layer to be the oxide 230a, the oxide 230b, the conductive layer 240B, and the insulating layer 245. did.
　次に、試料１Ａ、および試料１Ｂにおいて、絶縁体２８０となる酸化窒化シリコン膜を成膜した。続いて、ＣＭＰ処理を行ない、当該酸化窒化シリコン膜を研磨し、酸化窒化シリコン膜の表面を平坦化することで、絶縁体２８０を形成した。 Next, in Sample 1A and Sample 1B, a silicon oxide film serving as an insulator 280 was formed. Subsequently, CMP treatment was performed, the silicon oxide film was polished, and the surface of the silicon oxide film was flattened to form an insulator 280.
　続いて、試料１Ａにおいて、絶縁体２８０となる酸化窒化シリコン膜に開口部を形成した。続いて、当該開口部の底面に露出した導電層２４０Ｂを除去し、導電体２４０ａ、および導電体２４０ｂを形成した。 Subsequently, in sample 1A, an opening was formed in the silicon oxide nitride film to be the insulator 280. Subsequently, the conductive layer 240B exposed on the bottom surface of the opening was removed to form the conductor 240a and the conductor 240b.
　次に、試料１Ａにおいて、酸化物２３０ｃとなる第３の酸化物（酸化膜２３０Ｃ）として、Ｉｎ−Ｇａ−Ｚｎ酸化物をスパッタリング法により、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のターゲットを用いて成膜した後、Ｉｎ−Ｇａ−Ｚｎ酸化物をスパッタリング法により、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜することで、２層の積層構造として形成した。 Next, in sample 1A, In-Ga-Zn oxide was used as a third oxide (oxide film 230C) to be oxide 230c by a sputtering method, and In: Ga: Zn = 4: 2: 4.1 [. After forming a film using the target of [atomic number ratio], the In-Ga-Zn oxide is formed by the sputtering method using the target of In: Ga: Zn = 1: 3: 4 [atomic number ratio]. As a result, it was formed as a two-layer laminated structure.
　次に、試料１Ａにおいて、絶縁体２５０となる酸化窒化シリコン膜（絶縁膜２５０Ａ）を成膜した。 Next, in sample 1A, a silicon oxide film (insulating film 250A) to be an insulator 250 was formed.
　次に、試料１Ａにおいて、絶縁体２５０となる酸化窒化シリコン膜上に、導電体２６０ａとなる導電膜（導電膜２６０Ａ）として、窒化チタン膜を成膜した。続いて、導電体２６０ｂとなる導電膜（導電膜２６０Ｂ）として、タングステン膜を成膜した。なお、窒化チタン膜、およびタングステン膜は連続成膜により形成した。 Next, in sample 1A, a titanium nitride film was formed as a conductive film (conductive film 260A) to be a conductor 260a on a silicon oxide film to be an insulator 250. Subsequently, a tungsten film was formed as a conductive film (conductive film 260B) to be the conductor 260b. The titanium nitride film and the tungsten film were formed by continuous film formation.
　続いて、試料１Ａにおいて、導電膜２６０Ａ、導電膜２６０Ｂ、絶縁膜２５０Ａ、および酸化膜２３０Ｃの一部を除去し、導電体２６０、絶縁体２５０、および酸化物２３０ｃを形成した。 Subsequently, in sample 1A, a part of the conductive film 260A, the conductive film 260B, the insulating film 250A, and the oxide film 230C was removed to form the conductor 260, the insulator 250, and the oxide 230c.
　続いて、トランジスタ２００と電気的に接続するプラグ、絶縁体２８２となる膜として酸化アルミニウム膜と酸化ハフニウム膜の積層構造を有する膜、および絶縁体２８４となる膜として酸化窒化シリコンを有する膜を成膜した。 Subsequently, a plug electrically connected to the transistor 200, a film having a laminated structure of an aluminum oxide film and a hafnium oxide film as a film to be an insulator 282, and a film having silicon oxide as a film to be an insulator 284 are formed. Membrane.
　上記工程により、第１のトランジスタ２００を有する第１層を作成した。続いて、第１のトランジスタと第２のトランジスタとの間に、層間膜を作成した。 By the above process, the first layer having the first transistor 200 was prepared. Subsequently, an interlayer film was formed between the first transistor and the second transistor.
　層間膜として、上記第１層の反り方向と逆の応力を有する膜を成膜した。つまり、第１層を構成する全膜を合わせた応力（第１層の総応力ともいう）が、圧縮応力の場合、層間膜は引張応力を有する層を用いる。また、第１層の総応力が、引張応力である場合、層間膜は圧縮応力を有する層を用いる。 As an interlayer film, a film having a stress opposite to the warping direction of the first layer was formed. That is, when the total stress of all the films constituting the first layer (also referred to as the total stress of the first layer) is compressive stress, the interlayer film uses a layer having tensile stress. When the total stress of the first layer is tensile stress, a layer having compressive stress is used as the interlayer film.
　本実施例では、第１層の総応力が、圧縮応力であった。従って、層間膜は総応力として引張応力を有する層を用いた。具体的には、圧縮応力を有する酸化シリコン膜と、引張応力を有する酸化シリコン膜とを積層し、引張応力を有する酸化シリコン膜の膜厚を、圧縮応力を有する酸化シリコン膜の膜厚よりも厚く成膜した。 In this example, the total stress of the first layer was the compressive stress. Therefore, as the interlayer film, a layer having a tensile stress was used as the total stress. Specifically, a silicon oxide film having a compressive stress and a silicon oxide film having a tensile stress are laminated, and the film thickness of the silicon oxide film having a tensile stress is set to be larger than the film thickness of the silicon oxide film having a compressive stress. A thick film was formed.
　次に、層間膜上に第２のトランジスタ２００を有する第２層（２ｎｄ　ｌａｙｅｒ）作成した。当該第２層は、第１層と同様の工程で作成した。 Next, a second layer (2nd layer) having a second transistor 200 on the interlayer film was prepared. The second layer was prepared in the same process as the first layer.
　以上の工程より、試料１Ａを作製した。 Sample 1A was prepared from the above steps.
＜試料１Ａの断面観察、およびトランジスタ特性の評価結果＞
　まず、試料１Ａに対し、断面観察を行った。なお、断面観察は、走査型透過電子顕微鏡（ＳＴＥＭ：Ｓｃａｎｎｉｎｇ　Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）により行った。観察用の装置は日立ハイテクノロジーズ社製ＨＤ−２７００を用いた。図２０、および図２１に断面ＳＴＥＭ観察結果を示した。 <Cross-section observation of sample 1A and evaluation results of transistor characteristics>
First, the cross section of sample 1A was observed. The cross section was observed with a scanning transmission electron microscope (STEM). As the observation device, HD-2700 manufactured by Hitachi High-Technologies Corporation was used. The cross-sectional STEM observation results are shown in FIGS. 20 and 21.
　図２０Ａに示すように、試料１Ａのチャネル部におけるＬ長方向の長さは、７２ｎｍであった。図２０Ｂに示すように、試料１Ａのチャネル部におけるＷ長方向の長さは、５１ｎｍであった。図２１に示すように、第１のトランジスタ、および第２のトランジスタを積層して作製することができた。 As shown in FIG. 20A, the length in the L length direction in the channel portion of sample 1A was 72 nm. As shown in FIG. 20B, the length in the W length direction in the channel portion of sample 1A was 51 nm. As shown in FIG. 21, the first transistor and the second transistor could be laminated and manufactured.
　次に、試料１Ａに対し、トランジスタ特性の評価を行った。 Next, the transistor characteristics of sample 1A were evaluated.
　まず、第１層のトランジスタ２００、および第２層のトランジスタ２００において、導電体２０５に印加する電圧（Ｖｂｇ）を変化させることで、閾値が変化すること確認した。具体的には、各トランジスタ２００の導電体２０５に印加する電圧（Ｖｂｇ）の条件ぶりを行い、トランジスタ２００のＩｄ−Ｖｇ測定を行うことにより確認した。 First, it was confirmed that the threshold value was changed by changing the voltage (Vbg) applied to the conductor 205 in the transistor 200 of the first layer and the transistor 200 of the second layer. Specifically, do condition the first time the voltage (Vbg) is applied to the conductor 205 of each transistor 200, it was confirmed by performing I d -V g Measurement of transistor 200.
　図２２Ａには、第１層のトランジスタ２００におけるＩｄ−Ｖｇ測定結果を示す。また、図２２Ｂには、第２層のトランジスタ２００におけるＩｄ−Ｖｇ測定結果を示す。 FIG 22A, shows the I d -V g measurement results in transistor 200 of the first layer. Further, in the FIG. 22B, the shows the I d -V g measurement results in transistor 200 of the second layer.
　また、図２２に示す結果を用い、各層に設けたトランジスタ２００の導電体２０５に印加する電圧（Ｖｂｇ）に対する閾値の変化量を求めた。当該結果を図２３Ａに示す。図２３Ａに示すように、トランジスタ２００は、導電体２０５に印加する電圧（Ｖｂｇ）を適宜調節することで、回路用途に応じて、閾値制御が可能であることが分かった。 Further, using the results shown in FIG. 22, the amount of change in the threshold value with respect to the voltage (Vbg) applied to the conductor 205 of the transistor 200 provided in each layer was determined. The result is shown in FIG. 23A. As shown in FIG. 23A, it was found that the transistor 200 can control the threshold value according to the circuit application by appropriately adjusting the voltage (V bg) applied to the conductor 205.
　次に、第１層、および第２層のトランジスタ２００において、各トランジスタ２００の閾値の変動が、各トランジスタ２００の電界効果移動度（μＦＥｓ）に与える影響を調べた。当該結果を、図２３Ｂに示す。図２３Ｂに示すように、閾値変動量−∂Ｖｔｈ／∂Ｖｂｇは、０．１３Ｖ／Ｖである。導電体２０５に印加する電圧（Ｖｂｇ）を調節することにより、各トランジスタ２００の閾値が変動する一方、導電体２０５に印加する電圧（Ｖｂｇ）の値による電界効果移動度（μＦＥｓ）への影響は小さいことが分かった。 Next, in the transistors 200 of the first layer and the second layer, the influence of the fluctuation of the threshold value of each transistor 200 on the field effect mobility (μ FEs ) of each transistor 200 was investigated. The result is shown in FIG. 23B. As shown in FIG. 23B, the threshold fluctuation amount −∂V th / ∂V bg is 0.13 V / V. By adjusting the voltage (V bg) to be applied to the conductor 205, while the threshold of each transistor 200 is varied, the field effect mobility according to the value of the voltage applied to the conductor 205 (Vbg) (μ FEs) to The impact was found to be small.
　続いて、第１層、および第２層に設けたトランジスタ２００について、トランジスタ特性の温度依存性を評価した。測定条件は、−４０℃、２７℃、および８５℃とし、半導体装置を、条件温度下で動作させトランジスタ特性を測定した。なお、図２４Ａには、第１層のトランジスタ２００におけるＩｄ−Ｖｇ測定結果を示す。また、図２４Ｂには、第２層のトランジスタ２００におけるＩｄ−Ｖｇ測定結果を示す。 Subsequently, the temperature dependence of the transistor characteristics of the transistors 200 provided in the first layer and the second layer was evaluated. The measurement conditions were −40 ° C., 27 ° C., and 85 ° C., and the semiconductor device was operated under the condition temperature to measure the transistor characteristics. Although FIG 24A, shows the I d -V g measurement results in transistor 200 of the first layer. Further, FIG. 24B, shows the I d -V g measurement results in transistor 200 of the second layer.
　図２４に示すように、第１層、および第２層に設けられたトランジスタ２００のオフリーク電流は−４０~８５℃の温度範囲で常に測定下限（ｄｅｔｅｃｔｉｏｎ　ｌｉｍｉｔ）（１×１０−１３Ａ）以下であることが分かった。また、各トランジスタ２００の電界効果移動度の温度依存性を同図中に示す。電界効果移動度は、温度変化に対して、ほぼ変化がないことが確認できた。これは高温において電界効果移動度が低下するＳｉトランジスタにはない特長である。 As shown in FIG. 24, the off-leakage current of the transistors 200 provided in the first layer and the second layer is always below the detection limit (1 × 10-13 A) in the temperature range of −40 to 85 ° C. It turned out to be. Further, the temperature dependence of the field effect mobility of each transistor 200 is shown in the figure. It was confirmed that the field effect mobility was almost unchanged with respect to the temperature change. This is a feature not found in Si transistors whose field-effect mobility decreases at high temperatures.
　次に、第１層のトランジスタ２００において、８５℃の高温状態において、導電体２４０ａと導電体２４０ｂの間、導電体２４０ａと導電体２６０との間、および導電体２４０ａと導電体２０５との間におけるオフリーク電流を測定した。その結果を図２５に示す。図２５において、縦軸はＬｅａｋａｇｅ　ｃｕｒｒｅｎｔ、横軸は１０００／Ｔを表す。また、白丸はＤｒａｉｎ、四角はＤ−ＴＧ、三角はＤ−ＢＧ、菱形はＳｉ　ＦＥＴ［５］の結果を示す。図２５に示すように、各導電体間におけるオフリークの値は５．０×１０−２０Ａ／μｍ以下であった。従って、トランジスタ２００は、オフリーク電流が極めて低い値であることから、リフレッシュ電力を大幅に削減可能であることが分かった。 Next, in the first layer transistor 200, at a high temperature of 85 ° C., between the conductor 240a and the conductor 240b, between the conductor 240a and the conductor 260, and between the conductor 240a and the conductor 205. The off-leakage current was measured in. The result is shown in FIG. In FIG. 25, the vertical axis represents Leakage current and the horizontal axis represents 1000 / T. The white circles indicate the results of Drain, the squares indicate the results of D-TG, the triangles indicate the results of D-BG, and the diamonds indicate the results of Si FET [5]. As shown in FIG. 25, the off-leakage value between the conductors was 5.0 × 10 -20 A / μm or less. Therefore, it was found that the refresh power of the transistor 200 can be significantly reduced because the off-leakage current is extremely low.
　次に、トランジスタ２００を用いたＤＯＳＲＡＭ、あるいはＮＯＳＲＡＭを想定した場合の、書き込み速度を擬似的に算出した。当該結果を図２６に示す。図２６において、縦軸はＷｒｉｔｅ　ＴｉｍｅおよびＥｒａｓｅ　Ｔｉｍｅ、横軸はＲｅｔｅｎｔｉｏｎ　Ｔｉｍｅを表す。図２６Ａには、ＤＯＳＲＡＭを想定した場合の結果、図２６Ｂには、ＮＯＳＲＡＭを想定した場合の結果を示す。なお、保持時間はリーク原因としてサブスレッショルドリークのみを想定し、サブスレッショルドスウィングによってＩｄ−Ｖｇカーブを外挿することによって算出した。 Next, the writing speed when DOSRAM using the transistor 200 or NOSRAM was assumed was calculated in a pseudo manner. The result is shown in FIG. In FIG. 26, the vertical axis represents the Write Time and the Erase Time, and the horizontal axis represents the Retension Time. FIG. 26A shows the result when DOSRAM is assumed, and FIG. 26B shows the result when NOSRAM is assumed. The holding time is assumed to only the sub-threshold leakage as leakage caused was calculated by extrapolating the I d -V g curve by subthreshold swing.
　なお、半導体装置は、−４０℃以上８５℃以下での使用を想定し、導電体２０５に電圧（Ｖｂｇ電圧）を印加することでオフリーク電流が最大となる８５℃におけるデータ保持時間を調整した。また、保持と書き込みに使用する電源電圧を−０．８Ｖ／２．５Ｖ、許容する電圧変動量０．２Ｖ、書き込み判定電圧を０．５２Ｖ駆動回路の動作速度を２．５ＧＨｚとした。 Assuming that the semiconductor device is used at -40 ° C or higher and 85 ° C or lower, the data retention time at 85 ° C, which maximizes the off-leakage current, is adjusted by applying a voltage (V pg voltage) to the conductor 205. .. The power supply voltage used for holding and writing was −0.8V / 2.5V, the allowable voltage fluctuation amount was 0.2V, the writing determination voltage was 0.52V, and the operating speed of the drive circuit was 2.5GHz.
　図２６Ａに示すように、書き込み電流が最も小さくなる−４０℃において、ＤＯＳＲＡＭ駆動想定（保持容量３．５ｆＦ、８５℃でデータ保持時間１ｈｒ想定）での書き込み速度は約１．０~３．０ｎｓｅｃと見積もることができた。これはＤＯＳＲＡＭの動作速度として１００ＭＨｚ以上に相当する。 As shown in FIG. 26A, at −40 ° C., where the write current is the smallest, the write speed under the assumption of DOSRAM drive (holding capacity 3.5 fF, data holding time 1 hr at 85 ° C.) is about 1.0 to 3.0 nsec. I was able to estimate. This corresponds to an operating speed of 100 MHz or more for the DOS RAM.
　図２６Ｂに示すように、ＮＯＳＲＡＭ駆動想定（保持容量１．２ｆＦ、８５℃でデータ保持時間５年想定）での書き込み時間は１０．０ｎｓｅｃ以下と見積もることができた。なお、ＮＯＳＲＡＭに用いる場合、積層構造を利用することで、ビットラインなどの配線の負荷を小さくできるため、読み出し速度の影響は小さく、書き込み速度が全体の動作速度を決定することができる。従って、書き込み時間が１０．０ｎｓｅｃ以下である場合、動作速度として４０ＭＨｚ以上に相当する。 As shown in FIG. 26B, the write time under the NO SRAM drive assumption (holding capacity 1.2 fF, data holding time assumed to be 5 years at 85 ° C.) could be estimated to be 10.0 nsec or less. When used for NO SRAM, the load on wiring such as bit lines can be reduced by using the laminated structure, so that the influence of the read speed is small and the write speed can determine the overall operating speed. Therefore, when the writing time is 10.0 nsec or less, the operating speed corresponds to 40 MHz or more.
　また、図２６Ｂに、書き込まれたデータを消去するのに要する時間の見積もり結果も示した。データ消去時間は書き込み時間の算出と同様の手順で、Ｖｓ＝０Ｖ，Ｖｇ＝２．２５ＶのＩｄ−Ｖｄ特性から、Ｖｄ＝１．０８Ｖから０．１１Ｖ（１．０８Ｖの１０％）まで保持容量の電圧を低下させるのに要する時間を見積もった。データ消去時間は第１層で２．０　ｎｓｅｃ以下と見積もられた。 In addition, FIG. 26B also shows the estimation result of the time required to erase the written data. The data erasure time is the same procedure as the calculation of the write time, and the holding capacity is from Vd = 1.08V to 0.11V (10% of 1.08V) from the Id-Vd characteristics of Vs = 0V and Vg = 2.25V. Estimated the time required to reduce the voltage of. The data erasure time was estimated to be 2.0 nsec or less in the first layer.
　図２６Ｂより、トランジスタ２００を積層した半導体装置をメモリセルに採用することで、ＤＯＳＲＡＭ動作、およびＮＯＳＲＡＭ動作のいずれの動作を想定した場合でも、長時間保持と高速動作の両立が可能であることが分かった。 From FIG. 26B, by adopting a semiconductor device in which transistors 200 are stacked in a memory cell, it is possible to achieve both long-term holding and high-speed operation regardless of whether the DOSRAM operation or the NOSRAM operation is assumed. Do you get it.
　次に、図２７に、第１層のトランジスタ２００において、静特性から見積もられる多値動作でのｄａｔａ：０００（ＶＳＮ＝０．００Ｖ）→ｄａｔａ：１１１（ＶＳＮ＝１．０８Ｖの９０％）に要する書き込み時間、およびｄａｔａ：１１１（ＶＳＮ＝１．０８Ｖ）→ｄａｔａ：０００（ＶＳＮ＝１．０８Ｖの１０％）に要する消去時間の見積もり結果を示す。図２７において、縦軸はＷｒｉｔｅ　ＴｉｍｅおよびＥｒａｓｅ　Ｔｉｍｅ、横軸はＲｅｔｅｎｔｉｏｎ　Ｔｉｍｅを表す。 Next, in FIG. 27, in the transistor 200 of the first layer, 90% of data: 000 (V SN = 0.00V) → data: 111 (V SN = 1.08V) in the multi-valued operation estimated from the static characteristics. ), And the estimation result of the erasing time required for data: 111 (V SN = 1.08 V) → data: 000 ( 10% of V SN = 1.08 V) are shown. In FIG. 27, the vertical axis represents the Write Time and the Erase Time, and the horizontal axis represents the Retension Time.
　保持容量は３．５ｆＦ、多値（３ｂｉｔ／ｃｅｌｌ）の保持で許容される電圧変動は０．０２Ｖとした。ＮＯＳＲＡＭに用いることを想定した場合、保持ノードに直接アナログ電圧を書き込むことができるため、フラッシュメモリと異なりｖｅｒｉｆｙ動作を必要としない。従って、保持時間１年以下の範囲において、書き込み時間とデータ消去時間は共に駆動回路の書き込み時間１００ｎｓｅｃより十分短いことが確認された。 The holding capacity was 3.5 fF, and the voltage fluctuation allowed for holding multiple values (3 bits / cell) was 0.02 V. Assuming that it is used for NO SRAM, analog voltage can be written directly to the holding node, so unlike flash memory, verify operation is not required. Therefore, it was confirmed that both the writing time and the data erasing time were sufficiently shorter than the writing time of the drive circuit of 100 nsec in the range of the holding time of 1 year or less.
　次に、試料１Ａを、多値メモリとして機能した場合（Ｍｕｌｔｉｌｅｖｅｌ　ｏｐｅｒａｔｉｏｎ）の書き込み動作と保持試験を行った。図２８において、縦軸はＲｅａｄ　Ｖｏｌｔａｇｅ、横軸はＲｅｔｅｎｔｉｏｎ　Ｔｉｍｅを表す。図２８に評価結果により得られた保持特性を示す。図２８より、多値メモリとして駆動させた場合でも、１００ｎｓｅｃで８値相当の書き込みが可能であり、２７℃で１ｈｒ以上データ保持が可能であることが示された。 Next, a writing operation and a holding test were performed when the sample 1A functioned as a multi-valued memory (Multilevel operation). In FIG. 28, the vertical axis represents Read Voltage and the horizontal axis represents Retention Time. FIG. 28 shows the holding characteristics obtained from the evaluation results. From FIG. 28, it was shown that even when driven as a multi-valued memory, writing equivalent to 8 values is possible in 100 nsec, and data can be retained for 1 hr or more at 27 ° C.
　続いて、試料１Ａを、環境温度２７℃において、ＮＯＳＲＡＭメモリセルとして機能した場合の２値動作における書き換え耐性試験を行った。図２９に、当該評価結果による書き換え耐性を示す。図２９において、横軸はＷｒｉｔｅ　ｃｙｃｌｅｓを表す。図２９より、１０１２回以上の書き換え動作を行っても、問題なくデータが保持できていることが確認することができた。 Subsequently, a rewrite resistance test was performed on the sample 1A in a binary operation when the sample 1A functioned as a NO SRAM memory cell at an ambient temperature of 27 ° C. FIG. 29 shows the rewrite resistance based on the evaluation result. In FIG. 29, the horizontal axis represents Write cycles. From FIG. 29, it was confirmed that the data could be retained without any problem even if the rewriting operation was performed 10 or 12 times or more.
　ここで、トランジスタ２００の遮断周波数ｆＴの評価を行った。当該結果を図３０に示す。図３０において、横軸はＩｎｐｕｔ　Ｆｒｅｑｕｅｎｃｙを表す。なお、本評価において、第１層のみ作製したサンプルを用いた。当該評価は、導電体２０５に印加する電圧（Ｖｇ）、および導電体２４０ａに印加する電圧（Ｖｄ）を２．５Ｖとし、評価を行った。図３０に示すように、遮断周波数ｆＴは約４３ＧＨｚと見積もることができた。当該結果はトランジスタ２００がメモリへの応用だけでなく、高周波回路などのアナログ回路へも応用可能であることが示すものである。 Here, it was evaluated for the cut-off frequency f T of the transistor 200. The result is shown in FIG. In FIG. 30, the horizontal axis represents Input Frequency. In this evaluation, a sample prepared only for the first layer was used. The evaluation was performed by setting the voltage (V g ) applied to the conductor 205 and the voltage (V d ) applied to the conductor 240 a to 2.5 V. As shown in FIG. 30, the cut-off frequency f T could be estimated to be about 43 GHz. The result shows that the transistor 200 can be applied not only to a memory but also to an analog circuit such as a high frequency circuit.
　本実施例は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
１０：半導体装置、１１：基板、１２：調整層、１４：層、１６：調整層、１８：層、２０：半導体装置、２１：基板、２３：絶縁体、２４：層、２６：調整層、２７：絶縁体、２８：層 10: Semiconductor device, 11: Substrate, 12: Adjusting layer, 14: Layer, 16: Adjusting layer, 18: Layer, 20: Semiconductor device, 21: Substrate, 23: Insulator, 24: Layer, 26: Adjusting layer, 27: Insulator, 28: Layer

Claims (7)

  1. 　基板上に、酸化物半導体を有する第１のトランジスタを設けた第１の層と、
    　前記第１の層上に、第２の層と、
    　前記第２の層上に、酸化物半導体を有する第２のトランジスタを設けた第３の層と、を有し、
    　前記第１の層の総内部応力と、前記第３の層の総内部応力とは、第１の方向に作用し、
    　前記第２の層の総内部応力は、前記第１の方向と逆方向に作用する半導体装置。     A first layer provided with a first transistor having an oxide semiconductor on the substrate, and
    On top of the first layer, a second layer,
    On the second layer, there is a third layer provided with a second transistor having an oxide semiconductor.
    The total internal stress of the first layer and the total internal stress of the third layer act in the first direction.
    A semiconductor device in which the total internal stress of the second layer acts in a direction opposite to that of the first direction.
  2. 　基板上に、酸化物半導体を有する第１のトランジスタを設けた第１の層と、
    　前記第１の層上に、第２の層と、
    　前記第２の層上に、酸化物半導体を有する第２のトランジスタを設けた第３の層と、
    　前記第１の層と前記第２の層との間に、第４の層と、
    　前記第２の層と前記第３の層との間に、第５の層と、を有し、
    　前記第１の層の総内部応力と、前記第３の層の総内部応力とは、第１の方向に作用し、
    　前記第２の層の総内部応力は、前記第１の方向と逆方向に作用し、
    　前記第４の層と、前記第５の層は、バリア性を有する膜を含む半導体装置。     A first layer provided with a first transistor having an oxide semiconductor on the substrate, and
    On top of the first layer, a second layer,
    A third layer in which a second transistor having an oxide semiconductor is provided on the second layer, and
    Between the first layer and the second layer, a fourth layer,
    A fifth layer is provided between the second layer and the third layer.
    The total internal stress of the first layer and the total internal stress of the third layer act in the first direction.
    The total internal stress of the second layer acts in the direction opposite to that of the first direction.
    The fourth layer and the fifth layer are semiconductor devices including a film having a barrier property.
  3. 　請求項２において、
    　前記第４の層の総内部応力と、前記第５の層の総内部応力とは、前記第１の方向に作用する半導体装置。     In claim 2,
    The total internal stress of the fourth layer and the total internal stress of the fifth layer are semiconductor devices that act in the first direction.
  4. 　請求項３において、
    　前記バリア性を有する膜は、水素、および不純物の拡散を抑制する半導体装置。     In claim 3,
    The film having a barrier property is a semiconductor device that suppresses the diffusion of hydrogen and impurities.
  5. 　請求項２乃至４のいずれか一において、
    　前記第４の層は、前記第１の層を封止し、
    　前記第５の層は、前記第３の層を封止する半導体装置。     In any one of claims 2 to 4,
    The fourth layer seals the first layer.
    The fifth layer is a semiconductor device that seals the third layer.
  6. 　請求項１乃至請求項５のいずれか一において、
    　前記第２の層は配線として機能する導電体を有する半導体装置。     In any one of claims 1 to 5,
    The second layer is a semiconductor device having a conductor that functions as wiring.
  7. 　請求項１乃至請求項６のいずれか一において、
    　前記酸化物半導体は、Ｉｎ−Ｇａ−Ｚｎ酸化物である半導体装置。     In any one of claims 1 to 6,
    The oxide semiconductor is a semiconductor device which is an In-Ga-Zn oxide.
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