JP7069865B2 - Infrared detector, infrared image pickup device using this, and method of manufacturing infrared detector - Google Patents

Description

The present invention relates to an infrared detector, an infrared image pickup device using the infrared detector, and a method for manufacturing the infrared detector.

In the infrared detector array, the number of pixels is increasing due to the demand for high-definition images. On the other hand, there is also a strong demand for multiple wavelengths in which one pixel has sensitivity in different wavelength bands. Regarding the increase in the number of pixels, since there are restrictions on the wafer size and the exposure size of lithography, the size per pixel is reduced and the number of pixels is increased. On the other hand, in the case of multi-wavelength, the number of contact holes and bumps per pixel increases.

FIG. 1 shows a pixel structure of a general two-wavelength element. Each pixel is partitioned by a pixel separation groove DTI (Deep Trench Isolation). A lower contact layer (BC), a lower active layer (BA), an intermediate contact layer (MC), an upper active layer (TA), and an upper contact layer (TC) are laminated on the insulating layer, and each of them is contained in one pixel. Three contact holes CH1, CH2, CH3 and three bump electrodes (BMP) connected to the contact layer of the above are arranged.

There is a limit to the miniaturization of contact holes and bump electrodes, and an increase in the number of contact holes and bump electrodes hinders the reduction of pixel size. That is, the increase in the number of pixels and the number of wavelengths are contradictory requirements.

Japanese Unexamined Patent Publication No. 2015-50331 Japanese Unexamined Patent Publication No. 2008-228850

In addition to the problem of the trade-off between the number of pixels and the number of wavelengths, there is a problem of confinement of incident light. In a solid-state image sensor, an infrared detector having a two-dimensional pixel array is electrically connected to a signal processing circuit chip, and a light current proportional to the amount of infrared light absorbed by the active layer of each pixel is generated in the signal processing circuit. It is processed. In the configuration where the back surface of the infrared detector is the incident side, a part of the incident light passes through the gaps between the electrodes and the wiring formed in each pixel, and the detection efficiency is lowered. In addition, light diffusely reflected by the metal on the surface of the element may enter adjacent pixels, which causes crosstalk.

An object of the present invention is to provide an infrared detector capable of reducing the pixel size and suppressing a decrease in detection efficiency and crosstalk, and a method for manufacturing the same.

In one aspect of the invention, in an infrared detector containing an array of multiple pixels,
A lower contact layer, a lower active layer sensitive to a first wavelength in the infrared band, an intermediate contact layer, an upper active layer sensitive to a second wavelength different from the first wavelength in the infrared band, and an upper part. A laminate in which the contact layers are laminated in this order, and
A pixel separation groove formed in the laminate to partition the pixels,
The entire upper surface and side surface in the stacking direction of the pixels are connected to the first wiring connected to the upper contact layer, the second wiring connected to the lower contact layer, and the intermediate contact layer. It is covered by one of the third wires.

In the infrared detector, the pixel size can be reduced, and the detection efficiency can be reduced and crosstalk can be suppressed.

It is a figure which shows the pixel composition of the general two-wavelength type infrared detector. It is a schematic diagram of the image pickup apparatus to which the infrared detector of this invention is applied. It is sectional drawing of the infrared detector of an embodiment. It is a figure which shows an example of the plane structure of the infrared detector of an embodiment. It is a schematic diagram of the XX'cross section of FIG. 4A. It is a figure of the cross section A of FIG. 4A. It is a bird's-eye view which shows the surface state of the pixel of the infrared detector before the bump formation. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a manufacturing process diagram of the infrared detector of an embodiment. It is a figure which shows the specific example of the process of FIG. 10A. It is a figure which shows the specific example of the process of FIG. 10A. It is a figure which shows the specific example of the process of FIG. 11B. It is a figure which shows the specific example of the process of FIG. 11B. It is a figure which shows the surface state of the element immediately after the process of FIG. 8A. It is a figure which shows the surface state of the element immediately after the process of FIG. 8B. It is a figure which shows the surface state of the element immediately after the process of FIG. 10A. It is a figure which shows the surface state of the element immediately after the process of FIG. 11B. It is a schematic block diagram of the infrared imaging system using the infrared imaging apparatus of embodiment.

In the embodiment, the present invention provides a configuration and a manufacturing method of an infrared detector capable of reducing the pixel size and suppressing leakage of incident light, diffused reflection to adjacent pixels, and the like.

In order to reduce the pixel size, the number of bump electrodes in one pixel is reduced to two. The electrical connection between one of the three contact layers, such as the intermediate contact layer and the signal processing circuit chip, is achieved by pulling the surface wiring formed on the inner wall of the element separation groove to the outer periphery of the infrared detector array. do. The surface wiring formed on the inner wall of the element separation groove also functions to prevent diffusely reflected light inside the pixel from entering the adjacent pixel.

Further, the wiring arranged on the surface of each pixel is overlapped with each other with the insulating film interposed therebetween so that there is no gap through which light penetrates when viewed from the incident direction.

FIG. 2 is a schematic diagram of an infrared image pickup device 150 to which the infrared detector 100 of the embodiment is applied. The infrared image pickup device 150 includes an infrared detector 100 and a signal processing circuit chip 50. The infrared detector 100 is electrically and mechanically connected to the signal processing circuit chip 50 by the bump electrode 104.

The signal processing circuit chip 50 includes a readout circuit component, reads out the optical current generated in each pixel 1 for each channel via the bump electrode 104, and processes the signal in the signal processing circuit. The readout circuit component may include a transimpedance amplifier, a peak detection circuit, a time detection circuit, and the like provided for each pixel.

The light enters from the back surface of the infrared detector 100 and is absorbed by the active layer formed inside the infrared detector 100. As will be described later, the pixel surface of the infrared detector 100 of the embodiment opposite to the light incident surface, that is, the surface of the bump electrode 104 side is covered without gaps by wiring layers that overlap each other with an insulating film in between. Therefore, it is possible to prevent the light incident from the back surface from passing through. In addition, the inner wall of the pixel separation groove that separates each pixel is also covered with surface wiring. Diffusely reflected light inside the pixel is prevented from entering the adjacent pixel, and crosstalk between the pixels is suppressed.

FIG. 3 is a schematic cross-sectional view showing the pixel configuration of the infrared detector 100 of the embodiment. Each pixel 1 of the infrared detector 100 is separated from each other by a pixel separation groove 21. Pixels 1 are arranged, for example, in a two-dimensional array. In each pixel 1, a lower contact layer 12, a lower active layer 13, an intermediate contact layer 14, an upper active layer 15, and an upper contact layer 16 are laminated on the insulating layer 11 in this order. These layers are formed by epitaxial growth and may be referred to as "epitaxial lamination".

A contact hole 32 reaching the upper contact layer 16 and a contact hole 33 reaching the lower contact layer 12 are formed in the pixel 1. The contact hole that reaches the intermediate contact layer 14 is provided at the end of the pixel 1 and is open to the pixel separation groove 21.

A metal pad 51 that makes ohmic contact with the upper contact layer 16 is provided on the bottom surface of the contact hole 32. Wiring 24 is formed in the region including the metal pad 51 on the outermost surface of the epitaxial laminate and is connected to the bump electrode 41.

A metal pad 53 that makes ohmic contact with the lower contact layer 12 is provided on the bottom surface of the contact hole 33. A wiring 61 connected to the metal pad 53 is formed on the inner wall of the contact hole 33. The wiring 61 extends to the surface region of the pixel 1, and a part thereof overlaps with the wiring 24 via the insulating film. In the surface area of pixel 1, the wiring 61 is connected to the bump electrode 42.

A metal pad 52 that makes ohmic contact with the intermediate contact layer 14 is provided on the bottom surface of the contact hole 31. The contact hole 31 communicates with the pixel separation groove 21, and a surface wiring 66 that covers the pixel separation groove 21 and the inner wall of the contact hole 31 is formed.

The surface wiring 66 extends to the upper surface of the pixel 1. The portion of the surface wiring 66 extending from the contact hole 31 to the upper surface of the pixel 1 is an overlap region 66a that overlaps with the wiring 24 electrically connected to the upper contact layer 16 and the bump electrode 41. The portion of the surface wiring 66 extending from the pixel separation groove 21 to the upper surface of the pixel 1 is an overlap region 66b that overlaps with the wiring 61 electrically connected to the lower contact layer 12 and the bump electrode 42.

The light is incident from the back surface of the pixel 1, that is, the side of the insulating layer 11. The pixel surface region on the opposite side of the incident surface is covered without gaps by the wiring 24 and the wiring 61 that overlap each other, and the surface wiring 66 including the overlapping regions 66a and 66b. As a result, it is possible to prevent the incident light that was not absorbed by the lower active layer 13 and the upper active layer 15 from passing through the pixel 1 as it is.

The pixel 1 is provided with two bump electrodes 41 and 42 connected to the upper contact layer 16 and the lower contact layer 12, respectively, to reduce the pixel size.

The intermediate contact layer 14 is drawn out around the pixel region by the surface wiring 66 formed inside the pixel separation groove 21. The surface wiring 66 covers the inner wall of the pixel separation groove 21, and functions to prevent light incident on the pixel 1 and diffusely reflected on the surface from incident on the adjacent pixel.

4A is a schematic view showing a planar configuration of the infrared detector 100, FIG. 4B is a sectional view taken along the line XX'of FIG. 4A, and FIG. 4C is a sectional view taken along the line A of FIG. 4A. A plurality of pixels 1 are arranged two-dimensionally in the pixel area 101. An intermediate contact extraction bump region 111 is arranged on the outer periphery of the pixel region 101. At the same time as the formation of the bump electrodes 41 and 42 in the pixel region 101, the bump electrode 82 is formed in the bump region 111 for taking out the intermediate contact.

The bump electrode 82 of the bump region 111 for taking out the intermediate contact is connected to the surface wiring 66 connected to each pixel of the pixel region 101.

With this configuration, the number of bump electrodes arranged in each pixel 1 is set to two, and the intermediate contact layer 14 is drawn out to the intermediate contact extraction bump region 111 on the outer periphery of the pixel region 101. The intermediate contact layer 14 is configured to prevent penetration of incident light by pulling it out to the outer periphery with a surface wiring 66 that partially covers the upper surface of each pixel 1 and covers the inner wall of the pixel separation groove 21.

Returning to FIG. 3, the operation of the infrared detector 100 is as follows. A bias voltage is applied from the intermediate contact layer 14 connected to the surface wiring 66 to the upper active layer 15 and the lower active layer 13. A bias voltage is applied from the lower contact layer 12 connected to the bump electrode 42 to the lower active layer 13.

The current proportional to the amount of infrared light absorbed by the upper active layer 15 and the current proportional to the amount of infrared light absorbed by the lower active layer 13 are the bump electrode 41 electrically connected to the upper contact layer 16, respectively. , It is taken out as a signal from the bump electrode 42 electrically connected to the lower contact layer 12.

FIG. 5 is a bird's-eye view showing the surface state of the pixel 1 of the infrared detector 100 before the bump formation. More precisely, it shows a state in which the wiring 24 connected to the upper contact layer 16 and the wiring 61 connected to the lower contact layer 12 are formed on the upper surface of the epitaxial laminated structure.

Of the regions covered by the wiring 24, the region where the metal pad 51 is provided is the bump forming region 141 where the bump electrode 41 is provided. The bump electrode 41 is connected to the upper contact layer 16 by the wiring 24 and the metal pad 51.

A contact hole 31 that reaches the intermediate contact layer 14 is provided at a corner of the pixel 1, and a metal pad 52 that makes ohmic contact with the intermediate contact layer 14 is formed on the bottom surface of the contact hole 31.

A contact hole 33 that reaches the lower contact layer 12 is provided at a position diagonal to the contact hole 31 in the area covered by the wiring 61. The inner wall of the contact hole 33 is covered with the wiring 61, and the wiring 61 is connected to the metal pad 53 on the bottom surface of the contact hole 33.

Of the regions covered by the wiring 61, the region diagonal to the metal pad 51 on the uppermost layer is the bump forming region 142 in which the bump electrode 42 is provided. The bump electrode 42 is connected to the lower contact layer 12 by the wiring 61 and the metal pad 53 on the bottom surface of the contact hole 33.

At this stage, most of the upper surface of the pixel 1 is covered with metal wiring, but incident light may penetrate through the gap between the wiring. Therefore, the surface wiring 66 covering the contact hole 31 and the inner wall of the pixel separation groove is extended to the upper surface of the pixel 1 via the insulating film and overlapped so as to cover the gap between the wiring 24 and the wiring 61. At the stage where the bump electrode 41 and the bump electrode 42 are mounted on the pixel 1, the upper surface of the pixel 1 and the side wall of the pixel separation groove 21 are completely covered with a film opaque to infrared light when viewed from the light incident direction. Will be

6 to 13 are manufacturing process diagrams of the infrared detector 100. For convenience of illustration, the manufacturing process is shown focusing on one pixel 1, but the same process is performed over the entire pixel region 101.

In FIG. 6A, a lower contact layer 12, a lower active layer 13, an intermediate contact layer 14, an upper active layer 15, and an upper contact layer 16 are placed in this order on an insulating layer 11 provided on a substrate (not shown). Form. The lower contact layer 12, the lower active layer 13, the intermediate contact layer 14, the upper active layer 15, and the upper contact layer 16 are sequentially formed by epitaxial growth to form an epitaxial laminate.

The insulating layer 11 is, for example, a non-doped GaAs layer formed on a non-doped GaAs substrate, and exhibits electrical insulation. The lower contact layer 12 is, for example, an n-type GaAs layer. An n-type GaAs layer is formed by introducing a raw material gas containing silicon (Si), germanium (Ge), sulfur (S), selenium (Se), etc. as an n-type dopant gas during vapor phase growth of GaAs. ..

The lower active layer 13 is a light absorption layer having sensitivity to the first wavelength, and a layer of a quantum well or a quantum dot and a barrier layer are repeatedly laminated. The intermediate contact layer 14 is, for example, an n-type GaAs layer. The upper active layer 15 is a light absorption layer having sensitivity to a second wavelength different from the first wavelength. The upper contact layer 16 is, for example, an n-type GaAs layer.

In FIG. 6B, holes 17a and 17b reaching the intermediate contact layer 14 are formed by dry etching and wet etching. The hole 17a is a hole that becomes a contact hole 31 to the intermediate contact layer 14 at the end of the pixel. The hole 17b is a hole for forming a contact hole 33 to the lower contact layer 12 in a later step.

In FIG. 7A, a region other than the hole 17b is covered with a resist, and the hole 17b is etched to the lower contact layer 12 by dry etching and wet etching to form the contact hole 33. Then, the resist is peeled off.

In FIG. 7B, the pixel separation groove 21 that reaches the insulating layer 11 is formed. As a result, the hole 17a communicates with the pixel separation groove 21 and becomes a contact hole 31 opened with respect to the pixel separation groove 21.

In FIG. 8A, a metal pad is formed at a required position of each pixel 1. Specifically, a metal pad 52 that makes ohmic contact with the intermediate contact layer 14 is formed on the bottom surface of the contact hole 31, and a metal pad 53 that makes ohmic contact with the lower contact layer 12 is formed on the bottom surface of the contact hole 33. A metal pad 51 that makes ohmic contact with the upper contact layer 16 is formed at a predetermined position on the surface of the upper contact layer 16. The metal pads 51, 52, and 53 are manufactured, for example, by forming a predetermined resist pattern and then depositing gold (Au) and germanium (Ge) in this order to form a Ge / Au film having a predetermined shape by lift-off. Will be done.

In FIG. 8B, the wiring 24 connected to the metal pad 51 is formed in a predetermined region on the surface of the upper contact layer 16. For example, after patterning using a two-layer resist, the sunken (Ti) and platinum (Pt) are vapor-deposited in this order and lifted off to form the wiring 24. As shown in FIG. 5, the wiring 24 may cover about half of the upper surface of the pixel 1. The wiring 24 functions as an electrode connected to the bump electrode in a later process.

In FIG. 9A, the insulating film 25 is deposited on the entire surface. The type of the insulating film 25 is not limited, but for example, a silicon nitride film (SiN) is formed to a thickness of 300 nm by plasma CVD. The upper surface of the epitaxial laminated structure, the metal pad 51, the wiring 24, the inner wall of the pixel separation groove 21, and the inner walls of the contact holes 31 and 33 are covered with the insulating film 25.

In FIG. 9B, the insulating film 25 on the bottom surface of the contact hole 33 is removed by etching to expose the metal pad 53.

In FIG. 10A, the wiring 61 connected to the metal pad 53 is formed by ion milling or the like at a required location inside the contact hole 33 and on the upper surface of the epitaxial laminated structure. The wiring 61 functions as a pull-out electrode for pulling out the lower contact. As a feature of the embodiment, a part of the wiring 61 overlaps with the wiring 24 via the insulating film 25.

In FIG. 10B, an insulating film 62 such as SiN is deposited on the entire surface.

In FIG. 11A, the insulating film on the bottom surface of the contact hole 31 is removed by etching to expose the metal pad 52 that makes ohmic contact with the intermediate contact layer 14.

In FIG. 11B, the inner wall of the pixel separation groove 21 and the surface wiring 66 covering a predetermined region on the uppermost surface of the pixel 1 are formed by ion milling or the like, which is connected to the metal pad 52. Of the surface wiring 66, the portion of the upper surface of the pixel 1 that overlaps with the wiring 24 via the insulating film 62 is the overlap region 66a, and the portion that overlaps with the wiring 61 via the insulating film 62 is the overlap region 66b. Is.

In FIG. 12A, an insulating film 47 such as SiN is deposited on the entire surface.

In FIG. 12B, a part of the insulating film is removed by etching at a predetermined position to form an opening 48 that exposes the wiring 24 and an opening 49 that exposes the wiring 61.

In FIG. 13, the bump electrode 41 is formed in the opening 48, and the bump electrode 42 is formed in the opening 49. For example, the bump electrodes 41 and 42 cover the area other than the opening 48 and the opening 49 with a resist mask to deposit a metal such as indium (In), and lift off to form the bump electrodes 41 and 42 that fill the opening 48 and the opening 49. do. The bump electrode 41 is connected to the upper contact layer 16 by a wiring 24 and a metal pad 51. The bump electrode 42 is connected to the lower contact layer 12 by a wiring 61 and a metal pad 53.

In this configuration, the upper surface of the pixel 1 on the side opposite to the incident surface is covered without gaps by the wiring 24 and the wiring 61 which are overlapped with each other via the insulating film, and the overlapping regions 66a and 66b of the surface wiring 66. Further, the side surface of the pixel 1, that is, the side wall of the pixel separation groove 21, is covered with the surface wiring 66 for taking out the intermediate contact. With this wiring structure, the two-wavelength infrared detector 100 can reduce the number of bump electrodes in one pixel to two, and prevent the penetration of incident light and the intrusion of diffusely reflected light into adjacent pixels. .. With the infrared detector 100 having a compact structure, improvement of detection sensitivity and suppression of crosstalk are realized.

14 and 15 show specific examples of the process of forming the wiring 61 of FIG. 10 (A). In FIG. 14A, the pixel separation groove 21 and the contact hole 31 opened to the pixel separation groove 21 are filled with the resist 26. The surface of the resist 26 is rounded by baking in the photolithography process.

In FIG. 14B, a metal film 28 for wiring is formed on the entire surface by sputtering. The metal film 28 is, for example, a film obtained by sputtering Ti and Pt in this order.

In FIG. 15A, a resist pattern 29 is formed in a portion left by milling. The cross-sectional shape of the resist pattern 29 is rounded by baking.

In FIG. 15B, the unnecessary portion of the metal film 28 is removed by milling, and then the resist pattern 29 and the resist 26 are peeled off. As a result, the wiring 61 that partially overlaps with the wiring 24 is formed.

16 and 17 show specific examples of the process of forming the surface wiring 66 of FIG. 11 (B).

In FIG. 16A, the resist 44 protects the contact hole 33 and its surroundings. The resist is rounded by baking in the photolithography process.

In FIG. 16B, a metal film 46 for wiring is formed on the entire surface by sputtering. The metal film 46 is, for example, a film obtained by sputtering Ti and Pt in this order.

In FIG. 17A, a resist pattern 67 is formed in a portion left by milling. The resist pattern is rounded by baking.

In FIG. 17B, the unnecessary portion of the metal film 46 is removed by milling, and then the resist 44 and the resist pattern 67 are removed. As a result, a surface wiring 66 having an overlap region 66a that partially overlaps with the wiring 24 on the surface of the pixel 1 and an overlap region 66b that partially overlaps with the wiring 61 is formed.

FIG. 18 is a top view of the pixel 1 immediately after the formation of the ohmic contact of FIG. 8A. A contact hole 31 opened with respect to the pixel separation groove 21 is formed at a corner portion of the pixel 1. The contact hole 31 reaches the intermediate contact layer 14, and a metal pad 52 that makes ohmic contact with the intermediate contact layer 14 is provided on the bottom surface of the contact hole 31.

A contact hole 33 that reaches the lower contact layer 12 is formed at a position diagonal to the contact hole 31. A metal pad 53 that makes ohmic contact with the lower contact layer 12 is arranged on the bottom surface of the contact hole 33.

The bump forming region 141 and the bump forming region 142 are set on the diagonal line intersecting the diagonal line connecting the contact hole 31 and the contact hole 33. The bump forming region 141 includes the arrangement position of the metal pad 51.

FIG. 19 is a top view of the pixel 1 immediately after the formation of the wiring 24 of FIG. 8B. The wiring 24 is connected to a metal pad 51 that makes ohmic contact with the upper contact layer 16 and occupies almost half an area of the upper surface of the pixel 1. The wiring 24 is electrically insulated from the metal pad 52 in the contact hole 31 and the metal pad 53 in the contact hole 33.

FIG. 20 is a top view of the pixel 1 immediately after the formation of the wiring 61 of FIG. 10 (A). The wiring 61 is formed by partially overlapping with the wiring 24 connected to the upper contact layer 16 via the metal pad 51. The wiring 61 is connected to the lower contact layer 12 by a metal pad 53. As can be seen from the cross-sectional view of FIG. 10A, the wiring 24 and the wiring 61 are separated by the insulating film 25 in the stacking direction and are electrically insulated.

The overlapping region extends in the vertical direction of the paper surface, but the wiring 24 and the wiring 61 may be overlapped in any way as long as the arrangement can reduce the gap in the light incident direction. For example, the wiring 24 may be formed in a region of about 1/4 of the pixel 1 including the metal pad 51, the wiring 61 may be an L-shaped region, and the wiring 24 may be overlapped with the wiring 24 at the end of the L-shaped region. good.

At this stage, most of the upper surface of the pixel 1 is covered with a film that is opaque to the incident light. Therefore, it is possible to prevent the incident light from the back surface of the pixel 1 from penetrating in the stacking direction.

FIG. 21 is a top view of the pixel 1 immediately after the formation of the surface wiring 66 of FIG. 11B. A surface wiring 66 that is connected to the metal pad 52 and covers the inner wall of the pixel separation groove 21 is formed. A part of the surface wiring 66 extends to the upper surface of the pixel 1. The region that overlaps with the wiring 24 is the overlap region 66a of the surface wiring 66, and the region that overlaps with the wiring 61 is the overlap region 66b.

At this stage, the upper surface of the pixel 1 is completely covered with a film that is opaque to the incident light. Further, the side surface of the pixel 1, that is, the inner wall (side wall) of the pixel separation groove 21, is also covered with the surface wiring 66. Therefore, it is possible not only to prevent the incident light from penetrating from the back surface, but also to prevent the component diffusely reflected by the wiring layer on the front surface from incident on the adjacent pixel.

FIG. 22 is a schematic block diagram of an image pickup system 1000 using the infrared image pickup apparatus 150 of the embodiment. The image pickup system 1000 includes an infrared image pickup device 150, an optical system 1001, a display device 1002, a storage device 1003, a power supply 1004, and an input / output device 1006. The optical system includes optical elements such as a lens and a mirror, and collects light from the outside on the infrared detector 100 of the infrared image pickup device 150. In the infrared detector 100 of the embodiment, since light is incident from the back surface, the microlens array may be arranged so as to face the back surface of the infrared detector 100.

The display device 1002 displays an image captured by the infrared image pickup device 150. The storage device is a memory device such as an SSD (Solid State Drive), and records image data captured by the infrared image pickup device 150. The power supply 1004 supplies the entire power of the imaging system 1000. The input / output device 1006 includes an input / output interface with an external device.

The image pickup system 1000 uses the infrared detector 100 of the embodiment, and the size per pixel is small, so that the penetration of incident light and the incident of diffusely reflected light on adjacent pixels are suppressed. The image pickup system 1000 realizes high resolution, high sensitivity, and low crosstalk, and can be applied to a security system, an unmanned exploration system, and the like. Since it detects infrared light, it can be effectively applied to nighttime surveillance systems.

Although the present invention has been described above with reference to specific examples, the present invention is not limited to the configurations exemplified in the embodiments. The infrared detector 100 may be combined with a cooling device to further increase the sensitivity. A III-V compound semiconductor other than GaAs may be used for each layer forming the epitaxial laminate. The metal that makes ohmic contact with each contact layer is appropriately selected according to the conductive type of the contact layer. As the ohmic contact with the n-type contact layer, a metal material in which GeAu and Ni are combined may be used.

In either case, in the infrared detector 100 of the embodiment, the pixel size is reduced, the penetration of the incident light and the incident of the diffusely reflected light to the adjacent pixels are suppressed, and high resolution and high sensitivity sensing are possible. ..

The following additional notes are presented for the above explanation.
(Appendix 1)
In an infrared detector containing an array of multiple pixels
A lower contact layer, a lower active layer sensitive to a first wavelength in the infrared band, an intermediate contact layer, an upper active layer sensitive to a second wavelength different from the first wavelength in the infrared band, and an upper part. A laminate in which the contact layers are laminated in this order, and
A pixel separation groove formed in the laminate to partition the pixels,
The entire upper surface and side surface in the stacking direction of the pixels are connected to the first wiring connected to the upper contact layer, the second wiring connected to the lower contact layer, and the intermediate contact layer. An infrared detector characterized by being covered by any of the third wires.
(Appendix 2)
The back surface of the laminate is the light incident surface,
On the upper surface of the pixel, at least a part of the first wiring, the second wiring, and the third wiring overlap in the stacking direction, and the upper surface is covered without a gap when viewed from the light incident direction. The infrared detector according to Appendix 1, wherein the infrared detector is provided.
(Appendix 3)
A first bump electrode connected to the first wiring and a second bump electrode connected to the second wiring are provided on the upper surface of the pixel.
The infrared detector according to Appendix 1 or 2, wherein the third wiring is drawn from the pixel separation groove to the outer periphery of the pixel region of the infrared detector.
(Appendix 4)
A first contact hole that reaches the upper contact layer,
A second contact hole that reaches the lower contact layer,
A third contact hole that reaches the intermediate contact layer,
Have,
The infrared detector according to any one of Supplementary note 1 to 3, wherein the third contact hole is open to the pixel separation groove.
(Appendix 5)
The first wiring extends from the first contact hole to the upper surface of the pixel.
The second wiring extends from the second contact hole to the upper surface of the pixel.
The infrared detector according to Appendix 4, wherein the second wiring overlaps the first wiring via the first insulating film (25) on the upper surface.
(Appendix 6)
The third wiring extends from the third contact hole and the pixel separation groove to the upper surface of the pixel, and on the upper surface, overlaps the first wiring and the second wiring with the second insulating film. The infrared detector according to Appendix 4, wherein the infrared detector is provided.
(Appendix 7)
The infrared detector according to Appendix 4, wherein the inner wall of the pixel separation groove is entirely covered with the third wiring.
(Appendix 8)
The infrared detector according to any one of Supplementary note 1 to 7 and the infrared detector.
A signal processing circuit device electrically connected to the infrared detector,
Infrared imaging device with.
(Appendix 9)
The infrared image pickup device described in Appendix 8 and
An optical system that collects light from the outside on the infrared image pickup device,
Imaging system with.
(Appendix 10)
On the insulating layer, a lower contact layer, a lower active layer having sensitivity to the first wavelength in the infrared band, an intermediate contact layer, and a second wavelength in the infrared band different from the first wavelength. The upper active layer and the upper contact layer are deposited in this order to form a laminate.
A pixel separation groove for partitioning pixels is formed in the laminate, and a pixel separation groove is formed.
A first wiring connected to the upper contact layer, a second wiring connected to the lower contact layer, and a third wiring connected to the intermediate contact layer are formed on the pixel.
The entire upper surface and side surface in the stacking direction of the pixels are covered with any of the first wiring, the second wiring, and the third wiring.
A method for manufacturing an infrared detector.
(Appendix 11)
On the upper surface of the pixel, at least a part of the first wiring, the second wiring, and the third wiring are overlapped with each other in the stacking direction with an insulating film in between, and viewed in the stacking direction. The method for manufacturing an infrared detector according to Appendix 10, wherein the upper surface is sometimes covered without gaps.
(Appendix 12)
A first bump electrode connected to the first wiring and a second bump electrode connected to the second wiring are formed on the upper surface of the pixel.
The method for manufacturing an infrared detector according to Appendix 10 or 11, wherein the third wiring is pulled out from the pixel separation groove to the outer periphery of the pixel region of the infrared detector.
(Appendix 13)
Forming a first contact hole that reaches the upper contact layer,
A second contact hole that reaches the lower contact layer is formed and
A third contact hole that reaches the intermediate contact layer is formed so as to open with respect to the pixel separation groove.
The method for manufacturing an infrared detector according to any one of Supplementary Provisions 10 to 12, characterized in that.
(Appendix 14)
The first wiring is extended from the first contact hole to the upper surface of the pixel.
The second wiring is extended from the second contact hole to the upper surface of the pixel.
The method for manufacturing an infrared detector according to Appendix 13, wherein the second wiring is overlapped with the first wiring on the upper surface via a first insulating film.
(Appendix 15)
The third wiring is extended from the third contact hole and the pixel separation groove to the upper surface of the pixel, and the third wiring is connected to the first wiring on the upper surface via the second insulating film. The method for manufacturing an infrared detector according to Appendix 13, wherein the infrared detector is overlapped with the second wiring.
(Appendix 16)
The method for manufacturing an infrared detector according to Appendix 13, wherein the third wiring covers the entire inner wall of the pixel separation groove.

1 Pixel 11 Insulation layer 12 Lower contact layer 13 Lower active layer 14 Intermediate contact layer 15 Upper active layer 16 Upper contact layer 21 Pixel separation groove 24 Wiring (first wiring)
25, 47, 62 Insulation film 31, 32, 33 Contact hole 41, 42 Bump electrode 50 Signal processing circuit chip (signal processing circuit device)
61 wiring (second wiring)
66 Surface wiring (3rd wiring)
66a, 66b Overlap area 100 Infrared detector 101 Pixel area 111 Intermediate contact extraction bump area 133 Lower contact extraction groove 141, 142 Bump formation area 150 Infrared imager 1000 Imaging system

Claims (8)

In an infrared detector containing an array of multiple pixels
A lower contact layer, a lower active layer sensitive to a first wavelength in the infrared band, an intermediate contact layer, an upper active layer sensitive to a second wavelength different from the first wavelength in the infrared band, and an upper part. A laminate in which the contact layers are laminated in this order, and
A pixel separation groove formed in the laminate and partitioning the entire circumference of the pixel by a groove extending from the upper contact layer to the lower contact layer.
Have,
The entire upper surface and side surfaces of the pixels in the stacking direction are connected to the upper contact layer, the second wiring connected to the lower contact layer, and the third wiring connected to the intermediate contact layer. The third wiring, which is covered by any of the above and is connected to the intermediate contact layer, covers the entire inner wall of the pixel separation groove extending from the upper contact layer to the lower contact layer. Infrared detector. The back surface of the laminate is the light incident surface,
At least a part of the first wiring, the second wiring, and the third wiring overlap in the stacking direction on the upper surface of the pixel, and the upper surface is covered without a gap when viewed from the light incident direction. The infrared detector according to claim 1, wherein the infrared detector is provided. A first bump electrode connected to the first wiring and a second bump electrode connected to the second wiring are provided on the upper surface of the pixel.
The infrared detector according to claim 1 or 2, wherein the third wiring is drawn from the pixel separation groove to the outer periphery of the pixel region of the infrared detector. A first contact hole that reaches the upper contact layer,
A second contact hole that reaches the lower contact layer,
A third contact hole that reaches the intermediate contact layer,
Have,
The infrared detector according to any one of claims 1 to 3, wherein the third contact hole is open to the pixel separation groove. The infrared detector according to any one of claims 1 to 4,
A signal processing circuit device electrically connected to the infrared detector,
Infrared imaging device with. The infrared image pickup apparatus according to claim 5 and
An optical system that collects light from the outside on the infrared image pickup device,
Imaging system with. On the insulating layer, a lower contact layer, a lower active layer having sensitivity to the first wavelength in the infrared band, an intermediate contact layer, and a second wavelength in the infrared band different from the first wavelength. The upper active layer and the upper contact layer are deposited in this order to form a laminate.
In the laminated body, a pixel separation groove extending from the upper contact layer to the lower contact layer and partitioning the entire circumference of the pixel is formed.
A first wiring connected to the upper contact layer, a second wiring connected to the lower contact layer, and a third wiring connected to the intermediate contact layer are formed on the pixel.
The third wiring, which covers the entire upper surface and side surface of the pixels in the stacking direction with the first wiring, the second wiring, or the third wiring, and is connected to the intermediate contact layer. A method for manufacturing an infrared detector, which covers the entire inner wall of the pixel separation groove extending from the upper contact layer to the lower contact layer . On the upper surface of the pixel, at least a part of the first wiring, the second wiring, and the third wiring are overlapped with each other in the stacking direction with an insulating film in between, and viewed in the stacking direction. The method for manufacturing an infrared detector according to claim 7, wherein the upper surface thereof is sometimes covered without gaps.

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