JP7065794B2 - グラフベースの類似度検索を用いたfpga実装のインクリメンタル方式による生成 - Google Patents
グラフベースの類似度検索を用いたfpga実装のインクリメンタル方式による生成 Download PDFInfo
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- JP7065794B2 JP7065794B2 JP2019001636A JP2019001636A JP7065794B2 JP 7065794 B2 JP7065794 B2 JP 7065794B2 JP 2019001636 A JP2019001636 A JP 2019001636A JP 2019001636 A JP2019001636 A JP 2019001636A JP 7065794 B2 JP7065794 B2 JP 7065794B2
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/901—Indexing; Data structures therefor; Storage structures
- G06F16/9024—Graphs; Linked lists
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/903—Querying
- G06F16/90335—Query processing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2117/00—Details relating to the type or aim of the circuit design
- G06F2117/06—Spare resources, e.g. for permanent fault suppression
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Databases & Information Systems (AREA)
- Data Mining & Analysis (AREA)
- Computational Linguistics (AREA)
- Software Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102018100423.0A DE102018100423A1 (de) | 2018-01-10 | 2018-01-10 | Inkrementelles Generieren einer FPGA Implementierung mit Graphen-basierter Ähnlichkeitssuche |
| DE102018100423.0 | 2018-01-10 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019121404A JP2019121404A (ja) | 2019-07-22 |
| JP2019121404A5 JP2019121404A5 (enExample) | 2021-12-23 |
| JP7065794B2 true JP7065794B2 (ja) | 2022-05-12 |
Family
ID=66995361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019001636A Active JP7065794B2 (ja) | 2018-01-10 | 2019-01-09 | グラフベースの類似度検索を用いたfpga実装のインクリメンタル方式による生成 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10706196B2 (enExample) |
| JP (1) | JP7065794B2 (enExample) |
| CN (1) | CN110020456B (enExample) |
| DE (1) | DE102018100423A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111353182B (zh) * | 2020-03-11 | 2023-05-05 | 电子科技大学 | 一种面向fpga芯片的网表环路识别方法 |
| US20220321403A1 (en) * | 2021-04-02 | 2022-10-06 | Nokia Solutions And Networks Oy | Programmable network segmentation for multi-tenant fpgas in cloud infrastructures |
| CN113836863B (zh) * | 2021-09-30 | 2024-05-28 | 安徽大学 | 一种Logisim电路图的查重方法及系统 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001515247A (ja) | 1997-08-28 | 2001-09-18 | ザイリンクス, インコーポレイテッド | 動的再形態特定可能演算用のfpga設計方法 |
| JP2017191556A (ja) | 2016-04-15 | 2017-10-19 | 富士通株式会社 | 類似度検索装置、類似度検索方法および類似度検索プログラム |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3196950B2 (ja) * | 1993-11-30 | 2001-08-06 | 日本電信電話株式会社 | 回路情報の検証システム |
| JPH11219379A (ja) * | 1998-01-30 | 1999-08-10 | Nec Eng Ltd | Vhdlモデルの変更方法 |
| US6453454B1 (en) | 1999-03-03 | 2002-09-17 | Oridus Inc. | Automatic engineering change order methodology |
| US7017043B1 (en) * | 1999-03-19 | 2006-03-21 | The Regents Of The University Of California | Methods and systems for the identification of circuits and circuit designs |
| US7055120B2 (en) * | 2000-12-06 | 2006-05-30 | Cadence Design Systems, Inc. | Method and apparatus for placing circuit modules |
| US7237214B1 (en) * | 2003-03-04 | 2007-06-26 | Synplicity, Inc. | Method and apparatus for circuit partitioning and trace assignment in circuit design |
| US7394288B1 (en) * | 2004-12-13 | 2008-07-01 | Massachusetts Institute Of Technology | Transferring data in a parallel processing environment |
| US7284228B1 (en) * | 2005-07-19 | 2007-10-16 | Xilinx, Inc. | Methods of using ant colony optimization to pack designs into programmable logic devices |
| US8136076B2 (en) * | 2006-08-31 | 2012-03-13 | Fuji Xerox Co., Ltd. | Method and system for mounting circuit design on reconfigurable device |
| KR100935124B1 (ko) * | 2006-12-04 | 2010-01-06 | 후지쯔 가부시끼가이샤 | 회로 설계 지원 장치, 회로 설계 지원 방법, 회로 설계지원 프로그램을 기록한 컴퓨터 판독가능한 기록매체 및프린트 기판의 제조 방법 |
| US20080162777A1 (en) * | 2006-12-29 | 2008-07-03 | Sap Ag | Graph abstraction pattern for generic graph evaluation |
| US8060355B2 (en) * | 2007-07-27 | 2011-11-15 | Synopsys, Inc. | Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation |
| CN101620643B (zh) * | 2009-07-03 | 2011-03-09 | 中国人民解放军国防科学技术大学 | 一种基于fpga的体系结构仿真系统设计方法 |
| US8196081B1 (en) | 2010-03-31 | 2012-06-05 | Xilinx, Inc. | Incremental placement and routing |
| US8533643B2 (en) * | 2010-12-17 | 2013-09-10 | Advanced Micro Devices, Inc. | Method and apparatus for performing template-based classification of a circuit design |
| WO2012103151A2 (en) * | 2011-01-25 | 2012-08-02 | Micron Technology, Inc. | State grouping for element utilization |
| CN102054110A (zh) * | 2011-01-27 | 2011-05-11 | 复旦大学 | Fpga可编程逻辑块通用装箱方法 |
| US8904325B2 (en) * | 2012-01-31 | 2014-12-02 | Mentor Graphics Corporation | Verification test set and test bench map maintenance |
| CN103366028B (zh) * | 2012-03-31 | 2016-03-16 | 中国科学院微电子研究所 | 一种现场可编程门阵列芯片布局方法 |
| US8578311B1 (en) * | 2012-05-09 | 2013-11-05 | International Business Machines Corporation | Method and system for optimal diameter bounding of designs with complex feed-forward components |
| US10152557B2 (en) * | 2014-01-31 | 2018-12-11 | Google Llc | Efficient similarity ranking for bipartite graphs |
| US9449133B2 (en) | 2014-05-07 | 2016-09-20 | Lattice Semiconductor Corporation | Partition based design implementation for programmable logic devices |
| US9444702B1 (en) * | 2015-02-06 | 2016-09-13 | Netspeed Systems | System and method for visualization of NoC performance based on simulation output |
| US9875333B1 (en) * | 2016-01-19 | 2018-01-23 | Cadence Design Systems, Inc. | Comprehensive path based analysis process |
| CN105843982B (zh) * | 2016-03-07 | 2019-04-12 | 深圳市紫光同创电子有限公司 | 用于可编程逻辑器件的位流生成方法、装置及设计系统 |
-
2018
- 2018-01-10 DE DE102018100423.0A patent/DE102018100423A1/de active Pending
- 2018-12-03 US US16/207,457 patent/US10706196B2/en active Active
- 2018-12-28 CN CN201811616236.2A patent/CN110020456B/zh active Active
-
2019
- 2019-01-09 JP JP2019001636A patent/JP7065794B2/ja active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001515247A (ja) | 1997-08-28 | 2001-09-18 | ザイリンクス, インコーポレイテッド | 動的再形態特定可能演算用のfpga設計方法 |
| JP2017191556A (ja) | 2016-04-15 | 2017-10-19 | 富士通株式会社 | 類似度検索装置、類似度検索方法および類似度検索プログラム |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110020456B (zh) | 2024-08-27 |
| US20190213294A1 (en) | 2019-07-11 |
| JP2019121404A (ja) | 2019-07-22 |
| DE102018100423A1 (de) | 2019-07-11 |
| US10706196B2 (en) | 2020-07-07 |
| CN110020456A (zh) | 2019-07-16 |
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