CN110020456B - 利用基于图的相似性搜索逐步生成fpga实现的方法 - Google Patents

利用基于图的相似性搜索逐步生成fpga实现的方法 Download PDF

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CN110020456B
CN110020456B CN201811616236.2A CN201811616236A CN110020456B CN 110020456 B CN110020456 B CN 110020456B CN 201811616236 A CN201811616236 A CN 201811616236A CN 110020456 B CN110020456 B CN 110020456B
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fpga
implementation
graph
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CN110020456A (zh
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D·卢贝雷
H·卡尔特
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Desbeth Co ltd
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Desbeth Co ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/901—Indexing; Data structures therefor; Storage structures
    • G06F16/9024—Graphs; Linked lists
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/06—Spare resources, e.g. for permanent fault suppression

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Databases & Information Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Software Systems (AREA)
  • Computational Linguistics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
CN201811616236.2A 2018-01-10 2018-12-28 利用基于图的相似性搜索逐步生成fpga实现的方法 Active CN110020456B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018100423.0A DE102018100423A1 (de) 2018-01-10 2018-01-10 Inkrementelles Generieren einer FPGA Implementierung mit Graphen-basierter Ähnlichkeitssuche
DE102018100423.0 2018-01-10

Publications (2)

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CN110020456A CN110020456A (zh) 2019-07-16
CN110020456B true CN110020456B (zh) 2024-08-27

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US (1) US10706196B2 (enExample)
JP (1) JP7065794B2 (enExample)
CN (1) CN110020456B (enExample)
DE (1) DE102018100423A1 (enExample)

Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
CN111353182B (zh) * 2020-03-11 2023-05-05 电子科技大学 一种面向fpga芯片的网表环路识别方法
US20220321403A1 (en) * 2021-04-02 2022-10-06 Nokia Solutions And Networks Oy Programmable network segmentation for multi-tenant fpgas in cloud infrastructures
CN113836863B (zh) * 2021-09-30 2024-05-28 安徽大学 一种Logisim电路图的查重方法及系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101196945A (zh) * 2006-12-04 2008-06-11 富士通株式会社 电路设计支持装置及方法、计算机产品和印刷电路板制造方法
CN101620643A (zh) * 2009-07-03 2010-01-06 中国人民解放军国防科学技术大学 一种基于fpga的体系结构仿真系统设计方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3196950B2 (ja) * 1993-11-30 2001-08-06 日本電信電話株式会社 回路情報の検証システム
US6078736A (en) * 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing
JPH11219379A (ja) * 1998-01-30 1999-08-10 Nec Eng Ltd Ｖｈｄｌモデルの変更方法
US6453454B1 (en) 1999-03-03 2002-09-17 Oridus Inc. Automatic engineering change order methodology
US7017043B1 (en) * 1999-03-19 2006-03-21 The Regents Of The University Of California Methods and systems for the identification of circuits and circuit designs
US7055120B2 (en) * 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7237214B1 (en) * 2003-03-04 2007-06-26 Synplicity, Inc. Method and apparatus for circuit partitioning and trace assignment in circuit design
US7635987B1 (en) * 2004-12-13 2009-12-22 Massachusetts Institute Of Technology Configuring circuitry in a parallel processing environment
US7284228B1 (en) * 2005-07-19 2007-10-16 Xilinx, Inc. Methods of using ant colony optimization to pack designs into programmable logic devices
JP4998806B2 (ja) * 2006-08-31 2012-08-15 富士ゼロックス株式会社 再構成可能なデバイスに回路デザインを実装するための方法およびシステム
US20080162777A1 (en) * 2006-12-29 2008-07-03 Sap Ag Graph abstraction pattern for generic graph evaluation
US8060355B2 (en) * 2007-07-27 2011-11-15 Synopsys, Inc. Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation
US8196081B1 (en) 2010-03-31 2012-06-05 Xilinx, Inc. Incremental placement and routing
US8533643B2 (en) * 2010-12-17 2013-09-10 Advanced Micro Devices, Inc. Method and apparatus for performing template-based classification of a circuit design
KR101551045B1 (ko) * 2011-01-25 2015-09-07 마이크론 테크놀로지, 인크. 요소 이용을 위한 상태 그룹화
CN102054110A (zh) * 2011-01-27 2011-05-11 复旦大学 Fpga可编程逻辑块通用装箱方法
US8904325B2 (en) * 2012-01-31 2014-12-02 Mentor Graphics Corporation Verification test set and test bench map maintenance
CN103366028B (zh) * 2012-03-31 2016-03-16 中国科学院微电子研究所 一种现场可编程门阵列芯片布局方法
US8578311B1 (en) * 2012-05-09 2013-11-05 International Business Machines Corporation Method and system for optimal diameter bounding of designs with complex feed-forward components
US10152557B2 (en) * 2014-01-31 2018-12-11 Google Llc Efficient similarity ranking for bipartite graphs
US9449133B2 (en) 2014-05-07 2016-09-20 Lattice Semiconductor Corporation Partition based design implementation for programmable logic devices
US9444702B1 (en) * 2015-02-06 2016-09-13 Netspeed Systems System and method for visualization of NoC performance based on simulation output
US9875333B1 (en) * 2016-01-19 2018-01-23 Cadence Design Systems, Inc. Comprehensive path based analysis process
CN105843982B (zh) * 2016-03-07 2019-04-12 深圳市紫光同创电子有限公司 用于可编程逻辑器件的位流生成方法、装置及设计系统
JP2017191556A (ja) * 2016-04-15 2017-10-19 富士通株式会社 類似度検索装置、類似度検索方法および類似度検索プログラム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101196945A (zh) * 2006-12-04 2008-06-11 富士通株式会社 电路设计支持装置及方法、计算机产品和印刷电路板制造方法
CN101620643A (zh) * 2009-07-03 2010-01-06 中国人民解放军国防科学技术大学 一种基于fpga的体系结构仿真系统设计方法

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Publication number Publication date
US20190213294A1 (en) 2019-07-11
JP7065794B2 (ja) 2022-05-12
DE102018100423A1 (de) 2019-07-11
CN110020456A (zh) 2019-07-16
US10706196B2 (en) 2020-07-07
JP2019121404A (ja) 2019-07-22

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