JP7046692B2 - Semiconductor device - Google Patents

Description

One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one aspect of the invention relates to semiconductor wafers, modules, and electronic devices.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of a semiconductor device. Display devices (liquid crystal display devices, light emission display devices, etc.), projection devices, lighting devices, electro-optic devices, power storage devices, storage devices, semiconductor circuits, image pickup devices, electronic devices, etc. may be said to have semiconductor devices. ..

It should be noted that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).

Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials. As the oxide semiconductor, for example, not only oxides of single-unit metals such as indium oxide and zinc oxide, but also oxides of multi-element metals are known. Among the oxides of multidimensional metals, research on In-Ga-Zn oxide (hereinafter, also referred to as IGZO) is being actively conducted.

Studies on IGZO have found CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystals nor amorphous in oxide semiconductors (see Non-Patent Documents 1 to 3). .). Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, it is shown in Non-Patent Documents 4 and 5 that even oxide semiconductors having a lower crystallinity than the CAAC structure and the nc structure have minute crystals.

Further, a transistor using IGZO as an active layer has an extremely low off-current (see Non-Patent Document 6), and LSIs and displays utilizing the characteristics have been reported (see Non-Patent Documents 7 and 8). .).

S. Yamazaki et al. , "SID Symposium Digital Papers", 2012, volume 43, issu 1, p. 183-186 S. Yamazaki et al. , "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. , "The Proceedings of AM-FPD'13 Digital of Technical Papers", 2013, p. 151-154 S. Yamazaki et al. , “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issu 9, p. Q3012-Q3022 S. Yamazaki, “ECS Transitions”, 2014, volume 64, issu 10, p. 155-164 K. Kato et al. , “Japane Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , “2015 Symposium on VLSI Technology Digital Papers”, 2015, p. T216-T217 S. Amano et al. , "SID Symposium Digital Papers", 2010, volume 41, issu 1, p. 626-629

One aspect of the present invention is to provide a semiconductor device having a large on-current. Alternatively, one aspect of the present invention is to provide a semiconductor device having high frequency characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device having good reliability. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention is to provide a highly productive semiconductor device.

One of the problems of one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One aspect of the present invention is to provide a semiconductor device having a high information writing speed. One aspect of the present invention is to provide a semiconductor device having a high degree of freedom in design. One aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. One aspect of the present invention is to provide a novel semiconductor device.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. Is.

One aspect of the present invention is a first insulator, a first oxide on a first insulator, a second oxide on a first oxide, and a second oxide on a second oxide. Located on the second oxide, the third oxide and the fourth oxide, the fifth oxide on the second oxide, the second insulator on the fifth oxide, and so on. It has a conductor that overlaps the second oxide, and the second oxide comprises a first region, a second region, and a third region located between the first region and the second. The first region and the second region each have a region having a lower resistance than the third region, and the third oxide overlaps with the first region and has a third region. The fourth oxide is a semiconductor device having a region that overlaps with the second region and has a region that overlaps with the third region.

In the above, the third oxide has a lower resistance in the region overlapping with the first region than the region overlapping with the third region, and the fourth oxide is in the region overlapping with the second region. , It is preferable that the resistance is lower than that of the region overlapping with the third region.

A first insulator, a first oxide on a first insulator, a second oxide on a first oxide, a third oxide on a second oxide, and a fourth Oxide, a fifth oxide on a second oxide, a second insulator on a fifth oxide, located on a second insulator and overlaps with a second oxide. With a conductor, the second oxide has a first region, a second region, and a third region located between the first region and the second, the first region. , And the second region each have a region with lower crystallinity than the third region, and the third oxide has a region that overlaps with the first region and overlaps with the third region. The fourth oxide is a semiconductor device having a region that overlaps with the second region and also overlaps with the third region.

In the above, the third oxide has lower crystallinity in the region superimposing on the first region than the region superimposing on the third region, and the fourth oxide is the region superimposing on the second region. It is preferable that the crystallinity is lower than that of the region superimposing on the third region.

In the above, it is preferable that the third oxide and the fourth oxide each contain zinc.

In the above, it is preferable that the conductor has a region overlapping with the third oxide and the fourth oxide.

In the above, the second oxide preferably contains In, the element M (M is Al, Ga, Y, or Sn), and Zn.

In the above, the first region and the second region preferably contain one of phosphorus and boron.

According to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Alternatively, one aspect of the present invention can provide a semiconductor device having high frequency characteristics. Alternatively, one aspect of the present invention can provide a semiconductor device with good reliability. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention can provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

Alternatively, it is possible to provide a semiconductor device capable of retaining data for a long period of time. Alternatively, it is possible to provide a semiconductor device having a high data writing speed. Alternatively, it is possible to provide a semiconductor device having a high degree of freedom in design. Alternatively, it is possible to provide a semiconductor device capable of suppressing power consumption. Alternatively, a new semiconductor device can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure explaining the energy band structure of an oxide semiconductor. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. The block diagram which shows the structural example of the storage device which concerns on one aspect of this invention. The circuit diagram which shows the structural example of the storage device which concerns on one aspect of this invention. The schematic diagram of the semiconductor device which concerns on one aspect of this invention. The schematic diagram of the storage device which concerns on one aspect of this invention. The figure explaining the product image which can be used for the semiconductor device of one aspect of this invention. The figure which shows the electronic device which concerns on one aspect of this invention.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that embodiments can be implemented in many different embodiments and that the embodiments and details can be varied in various ways without departing from the spirit and scope thereof. To. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may be omitted for ease of understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular reference numeral may be added.

Further, in order to facilitate understanding of the invention, in particular, in a top view (also referred to as a “plan view”) or a perspective view, the description of some components may be omitted. In addition, some hidden lines may be omitted.

Further, in the present specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Further, in the present specification and the like, words and phrases indicating arrangements such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

For example, in the present specification and the like, when it is explicitly stated that X and Y are directly connected and that X and Y are connected, X and Y are electric. It is assumed that the case where X and Y are functionally connected and the case where X and Y are functionally connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is also described in the figure or text.

Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Further, the functions of the source and the drain may be switched when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.

In the present specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor. (Hereinafter, also referred to as "apparent channel width") and may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the ratio of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

As used herein, the term channel width may refer to an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

The semiconductor impurities are, for example, other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may result in, for example, an increase in DOS (Density of States) of the semiconductor, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors. There are transition metals other than the main components of the above, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, water may also function as an impurity. Further, in the case of an oxide semiconductor, oxygen deficiency may be formed, for example, by mixing impurities. When the semiconductor is silicon, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements excluding oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

In the present specification and the like, silicon oxide is composed of silicon oxide having a higher oxygen content than nitrogen. Further, silicon nitride oxide has a higher nitrogen content than oxygen in its composition.

Further, in the present specification and the like, the term "insulator" can be paraphrased as an insulating film or an insulating layer. Further, the term "conductor" can be paraphrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be paraphrased as a semiconductor film or a semiconductor layer.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

In the present specification, the barrier membrane is a membrane having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, and when the barrier membrane has conductivity, it is referred to as a conductive barrier membrane. I may call it.

In the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS FET or an OS transistor, it can be rephrased as a transistor having an oxide or an oxide semiconductor.

Further, in the present specification and the like, normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the current per 1 μm of the channel width flowing through the transistor is 1 × 10 ^-20 at room temperature. A or less, 1 × 10 ^-18 A or less at 85 ° C, or 1 × 10 ^-16 A or less at 125 ° C.

(Embodiment 1)
Hereinafter, an example of a semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

<Semiconductor device configuration example>
1 (A), 1 (B), and 1 (C) are a top view and a cross-sectional view of the transistor 200 according to one aspect of the present invention and the periphery of the transistor 200.

FIG. 1A is a top view of a semiconductor device having a transistor 200. Further, FIGS. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 1C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 1 (A), some elements are omitted for the sake of clarity of the figure.

The semiconductor device of one aspect of the present invention includes an insulator 214 on a substrate (not shown), a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, and an insulator 282 on the insulator 280. And an insulator 274 on the insulator 282 and an insulator 281 on the insulator 274. Here, the conductor 260 that functions as the gate of the transistor 200, the insulator 250 that functions as the gate insulating film, the oxide 230c, and the insulator 266 are provided so as to be embedded in the openings formed in the insulator 280. The insulator 214, the insulator 216, the insulator 280, the insulator 282, the insulator 274, and the insulator 281 function as an interlayer film. Further, it has a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. An insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. Further, on the insulator 281 and on the conductor 240, a conductor 246 (conductor 246a and conductor 246b) that electrically connects to the conductor 240 and functions as wiring is provided.

Further, the insulator 241a is provided in contact with the inner wall of the opening of the insulator 272, the insulator 270, the insulator 280, the insulator 282, the insulator 274, and the insulator 281, and is in contact with the side surface of the insulator 240a. The conductor 1 is provided, and the second conductor of the conductor 240a is further provided inside. Further, the insulator 241b is provided in contact with the inner wall of the opening of the insulator 272, the insulator 270, the insulator 280, the insulator 282, the insulator 274, and the insulator 281, and is in contact with the side surface of the insulator 240b. The conductor 1 is provided, and the second conductor of the conductor 240b is further provided inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made equal to each other. In the transistor 200, the configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.

[Transistor 200]
As shown in FIG. 1, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and a conductor 205b) arranged so as to be embedded in the insulator 216, and an insulator 216. Above, the insulator 222 on the conductor 205, the insulator 224 on the insulator 222, the oxide 230a on the insulator 224, the oxide 230b on the oxide 230a, and the oxide on the oxide 230b. 243a and oxide 243b, oxide 230c on oxide 230b, insulator 250 on oxide 230c, and conductor 260 located on insulator 250 and overlapping with oxide 230c (conductor 260a and conductivity). Body 260b) and a part of the upper surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243a, the upper surface of the oxide 243a, the side surface of the oxide 243b, and the upper surface of the oxide 243b. It has an insulator 272 in contact with the insulator 272 and an insulator 270 on the insulator 272. Here, the oxide 230c is in contact with the side surface of the oxide 243a and the side surface of the oxide 243b, respectively, and via the insulator 266, the oxide 230c is on the oxide 243a, on the oxide 243b, on the side surface of the insulator 272, and is insulated. It is provided on the side surface of the body 270. Further, the oxide 230c is provided on the side surface of the insulator 280 via the insulator 266 and the insulator 270. The insulator 250 is provided inside the oxide 230c, and the conductor 260 is provided inside the insulator 250. The conductor 260 has a conductor 260a and a conductor 260b, and the conductor 260a is arranged so as to wrap the bottom surface and the side surface of the conductor 260b. Here, as shown in FIG. 1 (B), the upper surface of the conductor 260 is arranged substantially in agreement with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Further, the insulator 282 is in contact with the upper surfaces of the conductor 260, the oxide 230c, the insulator 250, and the insulator 280, respectively.

Here, a part of the oxide 230b, the oxide 243a, and the oxide 243b is provided with a region 253a and a region 253b which are low resistance regions, one of which functions as a source region and the other of which functions as a drain region. do. Further, the oxide 243a and the oxide 243b have a region that does not overlap with the insulator 272. That is, the oxide 243a and the oxide 243b are provided so as to have a portion protruding into the opening provided in the insulator 280.

Further, the insulator 214, the insulator 222, the insulator 272, the insulator 270, the insulator 282, and the insulator 281 have a function of suppressing the diffusion of at least one hydrogen (for example, a hydrogen atom, a hydrogen molecule, etc.). Is preferable. Further, it is preferable that the insulator has a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.). For example, it is preferable that the insulator has lower permeability of one or both of oxygen and hydrogen than the insulator 224, respectively. It is preferable that the insulator has lower permeability of one or both of oxygen and hydrogen than the insulator 250, respectively. It is preferable that the insulator has lower permeability of one or both of oxygen and hydrogen than the insulator 280, respectively.

As shown in FIG. 1 (B), the insulator 272 is attached to the upper surface and the side surface of the oxide 243a, the upper surface and the side surface of the oxide 243b, the side surface of the oxide 230a, the side surface of the oxide 230b, and the upper surface of the insulator 224. It is preferable to touch them. Further, it is preferable that the insulator 270 is provided in contact with the insulator 272. Thereby, the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulator 272 and the insulator 270.

Further, the oxide 230 is arranged on the oxide 230a on the insulator 224, the oxide 230b on the oxide 230a, and the oxide 230c which is arranged on the oxide 230b and at least a part of which is in contact with the upper surface of the oxide 230b. , It is preferable to have.

In the transistor 200, a configuration in which three layers of oxide 230a, oxide 230b, and oxide 230c are laminated is shown in a region where a channel is formed (hereinafter, also referred to as a channel formation region) and in the vicinity thereof. However, the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a laminated structure of four or more layers may be provided. Further, in the transistor 200, the conductor 260 is shown as a two-layer laminated structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers.

It is preferable that the oxide 230b and the oxide 243 (oxide 243a and oxide 243b) each have a region 253 (region 253a and region 253b) whose resistance is reduced by the addition of impurities. Region 253 functions as a source region or a drain region. Further, the oxide 243 (oxide 243a and oxide 243b) is preferably conductive. The oxide 243 functions as a source electrode, a drain electrode, or an auxiliary electrode. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved. The oxide 243 may have a crystal structure.

As the oxide 243, an oxide containing zinc can be used. For example, zinc oxide, gallium zinc oxide, indium zinc oxide, indium gallium zinc oxide and the like can be used. Alternatively, indium oxide, indium tin oxide and the like may be used. Further, the oxide 243 is preferably a metal oxide having a high binding energy between a metal atom and an oxygen atom. Further, the conductivity of the oxide 243 is preferably higher than the conductivity in the channel forming region of the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) or the region to which impurities are not added. The film thickness of the oxide 243 is preferably 1 nm or more and 10 nm or less, more preferably 1 nm or more and 5 nm or less. Further, the oxide 243 is preferably crystalline. When the oxide 243 has crystallinity, the release of oxygen in the oxide 230 can be suitably suppressed. For example, as the oxide 243, if it has a crystal structure such as a hexagonal crystal, it may be possible to suppress the release of oxygen in the oxide 230.

Here, the conductor 260 functions as a gate electrode of the transistor. The transistor 200 is self-aligned so that the conductor 260 that functions as a gate electrode fills the opening formed by the insulator 280 or the like. By forming the conductor 260 in this way, it is possible to reliably arrange the conductor 260 in the region between the regions 253a and the region 253b without aligning the conductor 260.

FIG. 3 is an enlarged view of the vicinity of the channel formation region of the transistor 200 in FIG. 1 (B). As shown in FIG. 3, the region 253a and the region 253b that function as a source region or a drain region are formed so as to overlap with the insulator 272. That is, the facing ends of the regions 253a and 253b and the facing sides of the insulator 272 substantially coincide with each other. Further, the side surfaces of the oxide 243a and the oxide 243b facing each other are provided inside the side surfaces of the insulator 272 facing each other. With such a structure, a region on which the conductor 260 functioning as a gate electrode and the oxide 243 overlap is provided on the oxide 230b.

Here, the low resistance region will be described. Impurities are added to the regions 253a and 253b, and they function as low resistance regions. In the oxide 230b, impurities are added to the regions 231 (regions 231a and 231b), and the oxides have higher conductivity than the regions 234 and 232 (regions 232a and 232b). Similarly, in the oxide 243, impurities are added to the region 231 and the region 232 has higher conductivity than the region 232. That is, in the oxide 230b, the region 231 has a lower resistance than the regions 234 and 232, and in the oxide 243, the region 231 has a lower resistance than the region 232. Further, in the oxide 230b, the region 234 and the region 232 can be referred to as a high resistance region because the resistance is higher than that of the region 231. Further, in the oxide 243, the region 232 has a higher resistance than the region 231 and can be referred to as a high resistance region. In the oxide 230b, the region 253 is shown to be formed only on the oxide 243 side of the region 231, but the present invention is not limited to this. The region 253 may be formed in the entire oxide 230b in the region 231, or may be formed in a part or the whole of the region 232. Further, the region 253 may be formed in a part or the whole of the oxide 230a in the region 231.

Further, when impurities are added to the oxide 230b and the oxide 243 to form the region 253 by adding the ionized raw material gas, the arrangement of atoms in the region 253 is disturbed or the crystal orientation (or crystal orientation (). For example, the orientation of the c-axis) may be disturbed. For example, when an oxide having a crystal structure is used as the oxide 230b and the oxide 243, the crystallinity may decrease in the region 253. That is, in the oxide 230b, the region 253 may have lower crystallinity than the region 234 or the region 232. Further, in the oxide 243, the region 253 may have a lower crystallinity than the region 232. Further, in the region 253, the oxide 230b and the oxide 243 may have an amorphous structure, a polycrystalline structure, or a microcrystal structure. Further, in the oxide 230b, the region 253 may have more disorder in the crystal orientation (for example, the orientation of the c-axis) than the region 234 or the region 232. Further, in the oxide 243, the region 253 may have more disorder in the crystal orientation (for example, the orientation of the c-axis) than the region 232.

Here, when the conductivity of the oxide 243 is sufficiently high and the oxide 243 functions as a source electrode or a drain electrode, the distance (L) between the oxide 243a and the oxide 243b is the channel length of the transistor 200. .. At this time, in the oxide 230b, the region 234 functions as a channel forming region, the region 231a and the region 232a function as one of the source region and the drain region, and the region 231b and the region 232b are the other of the source region and the drain region. Functions as. The distance between the oxide 243a and the oxide 243b can be shorter than the width of the opening provided in the insulator 280 and the width of the opening of the insulator 272. That is, since the opening provided in the insulator 280 can be made large, the oxide 230c, the insulator 250, and the conductor 260 can be easily embedded even when the channel length of the transistor 200 is shortened.

For example, when the channel length (L) of the transistor 200 is 20 nm, if the width of the region of the oxide 243 that does not overlap with the insulator 272 can be 20 nm, the width of the opening formed in the insulator 272 is 60 nm. can do. Similarly, if the width of the region of the oxide 243 that does not overlap with the insulator 272 can be 5 nm, the width of the opening formed in the insulator 272 can be 30 nm. Further, a part of the oxide 243 and a part of the conductor 260 can be superimposed. Further, for example, when the width (L') of the opening formed in the insulator 272 shown in FIG. 3 is 60 nm, the length of the channel length (L) is less than 60 nm, preferably 30 nm or less, more preferably 5 nm or more. It can be 10 nm or less. The width (L') of the opening formed in the insulator 272 substantially coincides with the width of the dummy gate described later. That is, the width (L') of the opening formed in the insulator 272 can be controlled by the width of the dummy gate.

Further, since the oxide 243, that is, the region 232 (region 232a and region 232b) and the conductor 260 can be superimposed, the transistor 200 can be a transistor without an offset region. In addition, such a transistor may be called a transistor having a Lov structure. The transistor having an offset region is a transistor having a region in which the gate electrode does not overlap with the low resistance region functioning as the source region and the drain region, or the gate electrode does not overlap with either the source electrode or the drain electrode. A transistor with a structure.

On the other hand, when the conductivity of the oxide 243 is not sufficiently high, that is, the conductivity of the oxide 243 is higher than that of the oxide 230 in the region where impurities are not added, but the oxide 243 in the region where impurities are added. If the conductivity of the oxide 230 is lower than the conductivity of the oxide 230 in the region to which impurities are added, the oxide 243 that does not overlap with the insulator 272 functions as an auxiliary electrode. At this time, in the oxide 230b, the region 234 functions as a channel forming region, the region 231a and the region 231b function as a source region or a drain region, and the region 232a and the region 232b form an LDD region or a channel formation. It serves as a junction region between the region and the source or drain region.

At this time, since the oxide 243, that is, the region 232 (region 232a and region 232b) and the conductor 260 can be superimposed, the transistor 200 has an LDD region or a region where the junction region and the conductor 260 are superimposed. It can be a transistor. Such a transistor may also be referred to as a transistor having a Lov structure.

Since the transistor 200 has a Lov structure, it is possible to obtain a transistor having an improved operating frequency.

Further, the transistor 200 has a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor in the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) containing a channel forming region. It is preferable to use it.

Since the transistor 200 using the oxide semiconductor in the channel forming region has an extremely small leakage current (off current) in the non-conducting state, it is possible to provide a semiconductor device having low power consumption. Further, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for the transistor 200 constituting the highly integrated semiconductor device.

For example, as the oxide 230, an In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium). , Neodim, hafnium, tantalum, tungsten, or gallium, etc. (one or more) and the like may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

Further, in a transistor using an oxide semiconductor, if impurities and oxygen deficiency are present in the region where a channel is formed in the oxide semiconductor, the electrical characteristics are liable to fluctuate and the reliability may be deteriorated. Further, if oxygen deficiency is contained in the region where the channel is formed in the oxide semiconductor, the transistor tends to have a normally-on characteristic. Therefore, it is preferable that oxygen deficiency in the region where the channel is formed is reduced as much as possible. For example, oxygen may be supplied to the oxide 230 via an insulator 250 or the like to compensate for the oxygen deficiency. As a result, it is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

As shown in FIGS. 1B and 1C, the transistor 200 according to one aspect of the present invention has a structure in which the insulator 282 and the insulator 250 are in direct contact with each other. With such a structure, oxygen contained in the insulator 280 is less likely to be absorbed by the conductor 260. Therefore, oxygen contained in the insulator 280 can be efficiently injected into the oxide 230a and the oxide 230b via the oxide 230c, thereby reducing oxygen deficiency in the oxide 230a and the oxide 230b. , The electrical characteristics and reliability of the transistor 200 can be improved. Further, since impurities such as hydrogen contained in the insulator 280 can be suppressed from being mixed into the insulator 250, it is possible to suppress adverse effects on the electrical characteristics and reliability of the transistor 200. As the insulator 282, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used.

The insulator 270 preferably has a function of suppressing the permeation of impurities such as hydrogen and water and oxygen.

FIG. 4A is a cross-sectional view of the portion shown by the alternate long and short dash line of A5-A6 in FIG. 1A, and is also a cross-sectional view of the source region or drain region of the transistor 200 in the channel width direction. As shown in FIG. 4A, the upper surface of the oxide 243b, the side surface of the oxide 243b, the side surface of the oxide 230a, and the side surface of the oxide 230b are covered with the insulator 272 and the insulator 270. Therefore, it is possible to suppress the diffusion of impurities such as hydrogen and water and oxygen contained in the insulator 280 into the oxides 230a, 230b, and 243b. The oxide 243a also has the same effect. As the insulator 272 and the insulator 270, silicon oxide, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used. For example, a silicon oxide film, a silicon nitride film, or a silicon nitride film can be used as the insulator 272, and aluminum oxide, hafnium oxide, or silicon nitride can be used as the insulator 270.

FIG. 4B is a cross-sectional view of the portion shown by the alternate long and short dash line of A7-A8 in FIG. 1A, which is a cross section in the channel width direction of the conductor 240b which is electrically connected to the transistor 200 and functions as a plug. It is also a figure. As shown in FIG. 4B, since the insulator 241b is arranged on the side surface of the conductor 240b, impurities such as hydrogen and water and oxygen from the insulator 280 diffuse to the conductor 240b. It can be suppressed. The conductor 240a has the same effect.

Further, as shown in FIG. 1C, the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap with respect to the bottom surface or the top surface of the insulator 222. It is preferable that the conductor is arranged at a position lower than the height of the bottom surface of the oxide 230b. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230b and the conductor 260 do not overlap is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm. Hereinafter, it is more preferably 5 nm or more and 20 nm or less.

In this way, the conductor 260 that functions as a gate electrode covers the side surface and the upper surface of the oxide 230b in the channel forming region via the oxide 230c and the insulator 250, and channels the electric field of the conductor 260. It becomes easy to act on the entire oxide 230b in the forming region. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

From the above, it is possible to provide a semiconductor device having a transistor having a large on-current. Alternatively, it is possible to provide a semiconductor device having a transistor having a high frequency characteristic. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability. Alternatively, it is possible to provide a semiconductor device having a transistor having a small off-current.

Hereinafter, a detailed configuration of the semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

The conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Further, it is preferable that the conductor 205 is embedded in the insulator 214 and the insulator 216.

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to make the Vth of the transistor 200 larger than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when it is not applied.

As shown in FIG. 1A, the conductor 205 may be provided larger than the size of the region that does not overlap with the oxides 243a and 243b of the oxide 230. In particular, as shown in FIG. 1C, it is preferable that the conductor 205 is also stretched in a region outside the end portion intersecting the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on each other via the insulator on the side surface of the oxide 230 in the channel width direction. Alternatively, by providing the conductor 205 in a large size, local charging (also referred to as charge-up) may be alleviated in the treatment using plasma in the manufacturing process after the formation of the conductor 205. However, one aspect of the present invention is not limited to this. The conductor 205 may be superimposed on the oxide 230 located between at least the oxide 243a and the oxide 243b.

By having the above configuration, the channel forming region is electrically surrounded by the electric field of the conductor 260 having the function as the first gate electrode and the electric field of the conductor 205 having the function as the second gate electrode. Can be done. In the present specification, the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is referred to as a curved channel (S-channel) structure.

Further, the conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Further, as the conductor 205b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205 is shown in two layers, it may have a multi-layer structure of three or more layers.

Here, the oxide semiconductor, the insulator or the conductor located in the lower layer of the oxide semiconductor, and the insulator or the conductor located in the upper layer of the oxide semiconductor are made of different films without opening to the atmosphere. By continuously forming the seeds, it is possible to form an oxide semiconductor film having a substantially high purity and intrinsicity in which the concentration of impurities (particularly hydrogen and water) is reduced, which is preferable.

For example, using a film forming apparatus having five processing chambers, an insulator 222, an insulating film to be an insulator 224, an oxide film to be an oxide 230a, and an oxide arranged on the insulator 216 and the conductor 205 are used. The oxide film to be the object 230b and the oxide film to be the oxide 243 may be continuously formed in this order.

The insulator 214, the insulator 272, the insulator 270, and the insulator 281 function as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Is preferable. Therefore, the insulator 214, the insulator 272, the insulator 270, and the insulator 281 are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules _{(N2O, NO, NO 2 ,} etc.). It is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule) (the above oxygen is difficult to permeate).

For example, it is preferable to use at least one of the insulator 214, the insulator 272 and the insulator 270, and silicon nitride as the insulator 281. This makes it possible to prevent impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side of the insulator 214. Alternatively, it is possible to prevent oxygen contained in the insulator 224 or the like from diffusing toward the substrate side of the insulator 214. Further, it is possible to prevent impurities such as water and hydrogen from diffusing toward the transistor 200 from the insulator 280 and / or the conductor 246 arranged above the insulator 272.

Further, it may be preferable to reduce the resistivity of the insulator 214, the insulator 272, the insulator 270, and the insulator 281. For example, by setting the resistance of the insulator 214, the insulator 272, the insulator 270, and the insulator 281 to approximately 1 × 10 ¹³ Ωcm, the insulator 214 can be insulated in a process using plasma or the like in the process of manufacturing a semiconductor device. In some cases, the body 272, the insulator 270, and the insulator 281 can alleviate the charge-up of the conductor 205, or the conductor 260. The resistivity of the insulator 214, the insulator 272, the insulator 270, and the insulator 281 is preferably 1 × 10 ¹⁰ Ωcm or more and 1 × 10 ¹⁵ Ωcm or less.

Further, the insulator 214 may have a laminated structure. For example, it is suitable to use a laminated structure of an aluminum oxide film and a silicon nitride film for the insulator 214. The aluminum oxide film can supply oxygen below the insulator 214. Further, the silicon nitride film can suppress the diffusion of impurities such as hydrogen and water that diffuse from the substrate side to the transistor 200 side.

Further, it is preferable that the insulator 216, the insulator 280, and the insulator 274 have a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 216, the insulator 280, and the insulator 274, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon and nitrogen were added. Silicon oxide, silicon oxide having pores, or the like may be appropriately used.

The insulator 222 and the insulator 224 have a function as a gate insulator.

Here, it is preferable that the insulator 224 in contact with the oxide 230 desorbs oxygen by heating. In the present specification, oxygen released by heating may be referred to as excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be appropriately used for the insulator 224. By providing an insulator containing oxygen in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

Specifically, as the insulator 224, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. An oxide that desorbs oxygen by heating is an oxide having a desorption amount of oxygen in terms of oxygen molecules of 1.0 × 10 ¹⁸ molecules / cm ³ or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis. An oxide film having a size of 0.0 × 10 ¹⁹ molecules / cm ³ or more, more preferably 2.0 × 10 ¹⁹ molecules / cm ³ , or 3.0 × 10 ²⁰ molecules / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.

It is preferable that the insulator 222 functions as a barrier insulating film that prevents impurities such as water and hydrogen from being mixed into the transistor 200 from the substrate side. For example, the insulator 222 preferably has a lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, and the like with the insulator 222, the insulator 272, and the insulator 270, impurities such as water or hydrogen can be suppressed from entering the transistor 200 from the outside.

Further, it is preferable that the insulator 222 has a function of suppressing the diffusion of at least one oxygen (for example, an oxygen atom, an oxygen molecule, etc.) (the oxygen is difficult to permeate). For example, the insulator 222 preferably has a lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, it is possible to reduce the diffusion of oxygen contained in the oxide 230 below the insulator 222, which is preferable. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.

As the insulator 222, it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium, which are insulating materials. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. When the insulator 222 is formed by using such a material, the insulator 222 suppresses the release of oxygen from the oxide 230 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Functions as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.

Further, the insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST). Insulators containing so-called high-k material may be used in a single layer or laminated. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

The oxide 230 has an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By having the oxide 230a under the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b. Further, by having the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b.

The oxide 230 preferably has a laminated structure due to oxides having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 230b. Is preferable. Further, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a. Further, as the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

Further, the oxide 230b preferably has crystallinity. For example, it is preferable to use CAAC-OS (c-axis aligned crystalline semiconductor documentor) described later. Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, oxygen can be reduced from being extracted from the oxide 230b even if heat treatment is performed, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

Further, it is preferable that the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b.

Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c.

Specifically, as the oxide 230a, a metal oxide having In: Ga: Zn = 1: 3: 4 [atomic number ratio] or 1: 1: 0.5 [atomic number ratio] may be used. Further, as the oxide 230b, a metal oxide having In: Ga: Zn = 4: 2: 3 [atomic number ratio] or 1: 1: 1 [atomic number ratio] may be used. Further, as the oxide 230c, In: Ga: Zn = 1: 3: 4 [atom number ratio], In: Ga: Zn = 4: 2: 3 [atom number ratio], Ga: Zn = 2: 1 [atom]. A metal oxide having a [number ratio] or Ga: Zn = 2: 5 [atomic number ratio] may be used. Specific examples of the case where the oxide 230c has a laminated structure include In: Ga: Zn = 4: 2: 3 [atomic number ratio] and In: Ga: Zn = 1: 3: 4 [atomic number ratio]. ], A laminated structure of In: Ga: Zn = 4: 2: 3 [atomic number ratio] and Ga: Zn = 2: 1 [atomic number ratio], In: Ga: Zn = 4: 2. Laminated structure of: 3 [atomic number ratio] and Ga: Zn = 2: 5 [atomic number ratio], laminated structure of In: Ga: Zn = 4: 2: 3 [atomic number ratio] and gallium oxide And so on.

At this time, the main path of the carrier is the oxide 230b. By configuring the oxide 230a and the oxide 230c as described above, the defect level density at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-current and high frequency characteristics. When the oxide 230c has a laminated structure, in addition to the effect of lowering the defect level density at the interface between the oxide 230b and the oxide 230c, the constituent elements of the oxide 230c are on the insulator 250 side. It is expected to suppress the spread to. More specifically, since the oxide 230c has a laminated structure and the oxide containing no In is positioned above the laminated structure, In that can be diffused to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, if In is diffused, the characteristics of the transistor become poor. Therefore, by forming the oxide 230c in a laminated structure, it is possible to provide a highly reliable semiconductor device.

As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. For example, it is preferable to use an energy gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using the metal oxide having a large energy gap, the off-current of the transistor can be reduced. By using such a transistor, a semiconductor device having low power consumption can be provided.

As shown in FIG. 18, the electron affinity or the energy level Ec at the lower end of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the upper end of the valence band, and the energy gap Eg. The ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) apparatus. The energy gap Eg can be measured, for example, using a spectroscopic ellipsometer.

Oxide 243 is provided on the oxide 230b.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably arranged in contact with the upper surface of the oxide 230c. As the insulator 250, silicon oxide, silicon nitriding, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having holes are used. be able to. In particular, silicon oxide and silicon nitride nitride are preferable because they are heat-stable.

Like the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen by heating. By providing an insulator that releases oxygen by heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the channel forming region of the oxide 230b. Further, as with the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing the metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. In addition, the oxidation of the conductor 260 by oxygen of the insulator 250 can be suppressed.

In addition, the metal oxide may have a function as a part of a gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

Specifically, it is possible to use one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. can. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both oxides of aluminum or hafnium.

Alternatively, the metal oxide may have a function as a part of the gate electrode. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.

In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

Although the conductor 260 is shown as a two-layer structure in FIG. 1, it may have a single-layer structure or a laminated structure of three or more layers.

The conductor 260a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ₍ N2O, NO, _NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule).

Further, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.

Further, as the conductor 260b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.

The insulator 280 may be, for example, silicon oxide, silicon oxide, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or a hole as the insulator 280. It is preferable to have silicon oxide or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen desorbed by heating.

It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Further, the upper surface of the insulator 280 may be flattened.

The insulator 282 preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from being mixed into the insulator 280 from above. As the insulator 282, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride may be used.

Further, it is preferable to provide an insulator 274 that functions as an interlayer film on the insulator 282. It is preferable that the insulator 2274 has a reduced concentration of impurities such as water or hydrogen in the membrane, similarly to the insulator 224 and the like.

As the conductor 240a and the conductor 240b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 240a and the conductor 240b may have a laminated structure.

When the conductor 240 has a laminated structure, the conductor in contact with the insulator 281, the insulator 274, the insulator 282, the insulator 280, the insulator 273, and the insulator 272 contains impurities such as water or hydrogen. It is preferable to use a conductive material having a function of suppressing permeation. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used. Further, the conductive material having a function of suppressing the permeation of impurities such as water or hydrogen may be used in a single layer or in a laminated manner. By using the conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 240a and the conductor 240b. Further, it is possible to prevent impurities such as water or hydrogen from being mixed into the oxide 230 from the layer above the insulator 281 through the conductor 240a and the conductor 240b.

As the insulator 241a and the insulator 241b, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 272 and the insulator 273, impurities such as water or hydrogen from the insulator 280 and the like are mixed into the oxide 230 through the conductor 240a and the conductor 240b. Can be suppressed. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

Further, the conductor 246 (conductor 246a and conductor 246b) which is in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b and functions as wiring may be arranged. As the conductor 246, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.

<Constituent materials for semiconductor devices>
Hereinafter, the constituent materials that can be used in the semiconductor device will be described.

<Board>
As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, and the like. Examples of the semiconductor substrate include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

<Insulator>
Examples of the insulator include oxides having insulating properties, nitrides, nitride oxides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like.

For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material having a low relative permittivity for the insulator that functions as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. Therefore, the material may be selected according to the function of the insulator.

Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.

Insulators having a low relative permittivity include silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. There are silicon oxide, resin, etc.

Further, the transistor using the oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding the transistor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulations containing, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in layers. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, etc. Alternatively, a metal oxide such as tantalum oxide, a metal nitride such as aluminum nitride, titanium nitride, titanium nitride, silicon nitride or silicon nitride can be used.

Further, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, the oxygen deficiency of the oxide 230 can be compensated by having the structure in which silicon oxide or silicon oxide having a region containing oxygen desorbed by heating is in contact with the oxide 230.

<Conductor>
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

When an oxide is used in the channel forming region of the transistor, a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined is used for the conductor functioning as a gate electrode. Is preferable. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.

In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

<Metal oxide>
As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.

The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. Further, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.

Here, consider the case where the metal oxide is an In—M—Zn oxide having indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

In addition, in this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as a metal oxynitride.

[Structure of metal oxide]
Oxide semiconductors (metal oxides) are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS, polycrystal oxide semiconductor, nc-OS, pseudoamorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), and amorphous oxidation. There are physical semiconductors.

CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have non-regular hexagonal shapes. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the substitution of metal elements. Because.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as a (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can also be expressed as a (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, it is difficult to confirm a clear grain boundary, so it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the metal oxide may be deteriorated due to the mixing of impurities or the generation of defects, CAAC-OS is a metal having few impurities and defects (oxygen deficiency (VO: _oxygen vacancy), etc.). It can also be called an oxide. Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

Indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may have a stable structure by forming the above-mentioned nanocrystals. be. In particular, since IGZO tends to have difficulty in crystal growth in the atmosphere, it is better to use smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, a few mm crystal or a few cm crystal). However, it may be structurally stable.

The a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors (metal oxides) have various structures, and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

In the semiconductor device of one aspect of the present invention, the structure of the oxide semiconductor (metal oxide) is not particularly limited, but it is preferably crystalline. For example, the oxide 230 can have a CAAC-OS structure and the oxide 243 can have a hexagonal crystal structure. By forming the oxide 230 and the oxide 243 in the above-mentioned crystal structure, a semiconductor device having high reliability can be obtained.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, it may form a defect level and generate a carrier. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in the channel forming region tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS (concentration obtained by secondary ion mass spectrometry (SIMS)) is 1 × 10 ¹⁸ atoms. / Cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing hydrogen tends to have a normally-on characteristic.

Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . By using a metal oxide having sufficiently reduced impurities in the channel forming region of the transistor, stable electrical characteristics can be imparted.

It is preferable to use a thin film having high crystallinity as the metal oxide used for the semiconductor of the transistor. By using the thin film, the stability or reliability of the transistor can be improved. Examples of the thin film include a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, in order to form a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide on a substrate, a high temperature or laser heating step is required. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

It is reported in Non-Patent Document 1 and Non-Patent Document 2 that an In-Ga-Zn oxide (referred to as CAAC-IGZO) having a CAAC structure was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, grain boundaries are not clearly confirmed, and can be formed on a substrate at a low temperature. Furthermore, it has been reported that transistors using CAAC-IGZO have excellent electrical characteristics and reliability.

Further, in 2013, an In-Ga-Zn oxide (referred to as nc-IGZO) having an nc structure was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity in crystal orientation is observed between the different regions. There is.

Non-Patent Document 4 and Non-Patent Document 5 show changes in the average crystal size of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO thin films having low crystallinity by irradiation with an electron beam. In a thin film of IGZO having low crystallinity, crystalline IGZO of about 1 nm is observed even before irradiation with an electron beam. Therefore, it is reported here that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, it has been shown that the CAAC-IGZO thin film and the nc-IGZO thin film are more stable to electron beam irradiation than the IGZO thin film having low crystallinity. Therefore, it is preferable to use a CAAC-IGZO thin film or an nc-IGZO thin film as the semiconductor of the transistor.

A transistor using a metal oxide has an extremely small leakage current in a non-conducting state, specifically, the off-current per 1 μm of the channel width of the transistor is on the order of yA / μm ( ^10-24 A / μm). Is shown in Non-Patent Document 6. For example, a low power consumption CPU that applies the characteristic that the leakage current of a transistor using a metal oxide is low is disclosed (see Non-Patent Document 7).

Further, it has been reported that the transistor using a metal oxide has a low leakage current, and that the transistor is applied to a display device (see Non-Patent Document 8). On the display device, the displayed image is switched several tens of times per second. The number of image switchings per second is called the refresh rate. Also, the refresh rate may be called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is considered to be the cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device to reduce the number of times the image is rewritten. In addition, it is possible to reduce the power consumption of the display device by driving with a reduced refresh rate. Such a drive method is called an idling stop (IDS) drive.

The discovery of the CAAC structure and the nc structure has contributed to the improvement of the electrical characteristics and reliability of the transistor using the CAAC structure or the metal oxide having the nc structure, as well as the reduction of the cost of the manufacturing process and the improvement of the throughput. Further, research on application of the transistor to a display device and an LSI utilizing the characteristic that the leakage current of the transistor is low is underway.

<Method of manufacturing semiconductor devices>
Next, the manufacturing method of the semiconductor device having the transistor 200 according to the present invention shown in FIG. 1 will be described with reference to FIGS. 5 to 17. Further, in FIGS. 5 to 17, (A) in each figure shows a top view. Further, (B) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of (A) in each figure, some elements are omitted for the purpose of clarifying the figure.

First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The film formation of the insulator 214 is performed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or a pulsed laser deposition (PLD) method. It can be performed by using the (Atomic Layer Deposition) method or the like.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (Metal CVD) method and an organic metal CVD (MOCVD: Metalorganic CVD) method depending on the raw material gas used.

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage during film formation does not occur, so that a film having few defects can be obtained.

In addition, the ALD method utilizes the characteristics of atoms, which are self-regulating properties, and can deposit atoms layer by layer, so ultra-thin film formation is possible, and film formation into structures with a high aspect ratio is possible. It has the effects of being able to form a film with few defects such as holes, being able to form a film with excellent coverage, and being able to form a film at a low temperature. The ALD method also includes a PEALD (Plasma Enhanced ALD) method, which is a film forming method using plasma. By using plasma, it is possible to form a film at a lower temperature, which may be preferable. Some precursors used in the ALD method contain impurities such as carbon. Therefore, the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods. The quantification of impurities can be performed by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

The CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage. In particular, the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film forming speed, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming speed.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas. Further, for example, in the CVD method and the ALD method, a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for film formation is shortened because it does not require time for transportation and pressure adjustment as compared with the case of forming a film using multiple film forming chambers. can do. Therefore, it may be possible to increase the productivity of the semiconductor device.

In the present embodiment, silicon nitride is formed as the insulator 214 by the CVD method. Alternatively, silicon nitride may be formed into a film by using a sputtering method as the insulator 214. In the CVD method, hydrogen may be contained in the film-forming gas, and this hydrogen can become an impurity by being contained in the film. It is preferable to use a sputtering method that does not contain hydrogen in the film-forming gas because the concentration of impurities such as hydrogen in the insulator 214 can be reduced. As described above, by using an insulator such as silicon nitride that is difficult for copper to permeate as the insulator 214, even if a metal such as copper that is easily diffused is used for the conductor in the layer below the insulator 214 (not shown). It is possible to prevent the metal from diffusing into the layer above the insulator 214.

Next, the insulator 216 is formed on the insulator 214. The film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As described above, it is preferable to use the sputtering method for forming the film of the insulator 216 because the concentration of impurities such as hydrogen in the insulator 216 can be reduced.

Next, an opening is formed in the insulator 216 to reach the insulator 214. The opening also includes, for example, a groove or a slit. Further, the area where the opening is formed may be referred to as an opening. Although wet etching may be used to form the openings, it is preferable to use dry etching for microfabrication. Further, as the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when a silicon oxide film is used for the insulator 216 forming the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film may be used for the insulator 214.

After forming the opening, a conductive film to be the conductor 205 is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The film formation of the conductive film to be the conductor 205 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the present embodiment, the conductive film to be the conductor 205 has a multilayer structure. First, as a conductive film to be the conductor 205a, tantalum nitride is formed into a film by a sputtering method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride for the conductive film to be the conductor 205a, even if a easily diffusible metal such as copper is used as the conductive film to be the conductor 205b described later, the metal can be removed from the conductor 205a. It can be prevented from spreading.

Next, a conductive film to be the conductor 205b is formed. The film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, as the conductive film to be the conductor 205b, a low resistance conductive material containing tungsten, aluminum, copper or the like as a main component is formed.

Next, by performing the CMP treatment, the conductive film to be the conductor 205b and a part of the conductive film to be the conductor 205a are removed, and the insulator 216 is exposed. As a result, the conductive film that becomes the conductor 205 (conductor 205a and conductor 205b) remains only in the opening. This makes it possible to form the conductor 205 having a flat upper surface. In addition, a part of the insulator 216 may be removed by the CMP treatment (see FIG. 5).

From here, a method for forming the conductor 205 different from the above will be described below.

A conductive film to be a conductor 205 is formed on the insulator 214. The film formation of the conductive film to be the conductor 205 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductive film to be the conductor 205 can be a multilayer film. In the present embodiment, tungsten is formed as a conductive film to be the conductor 205.

Next, the conductive film to be the conductor 205 is processed by a lithographic method to form the conductor 205.

In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left with a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used. When using an electron beam or an ion beam, a mask is not required. To remove the resist mask, a dry etching process such as ashing, a wet etching process, a wet etching process after the dry etching process, or a dry etching process after the wet etching process can be performed.

Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film to be a hard mask material is formed on a conductive film to be a conductor 205, a resist mask is formed on the insulating film or a conductive film, and the hard mask material is etched to obtain a desired shape. A hard mask can be formed. The etching of the conductive film to be the conductor 205 may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film to be the conductor 205. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate type electrodes can be used. The capacitive coupling type plasma etching apparatus having a parallel plate type electrode may be configured to apply a high frequency power supply to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate type electrodes. Alternatively, a high frequency power supply having the same frequency may be applied to each of the parallel plate type electrodes. Alternatively, a high frequency power supply having a different frequency may be applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

Next, an insulating film to be the insulator 216 is formed on the insulator 214 and the conductor 205. The film formation of the insulator to be the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed by a CVD method as an insulating film to be an insulator 216.

Here, the film thickness of the insulating film to be the insulator 216 is preferably equal to or larger than the film thickness of the conductor 205. For example, assuming that the film thickness of the conductor 205 is 1, the film thickness of the insulating film to be the insulator 216 is 1 or more and 3 or less. In the present embodiment, the film thickness of the conductor 205 is 150 nm, and the film thickness of the insulating film to be the insulator 216 is 350 nm.

Next, by performing a CMP (chemical mechanical polishing) treatment on the insulating film to be the insulator 216, a part of the insulating film to be the insulator 216 is removed to expose the surface of the conductor 205. This makes it possible to form the conductor 205 and the insulator 216 having a flat upper surface. The above is a different forming method of the conductor 205. FIG. 2 shows an example of a semiconductor device having a transistor 200 having a conductor 205 and an insulator 216 formed as described above.

Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. , The formation of oxygen deficiency in the oxide 230 can be suppressed.

The film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an insulating film 224A is formed on the insulator 222. The film formation of the insulating film 224A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, it is preferable to perform heat treatment. The heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower. The heat treatment is carried out in an atmosphere of nitrogen or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more. Further, the heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas to supplement the desorbed oxygen after the heat treatment in a nitrogen or inert gas atmosphere. good.

In the present embodiment, after the treatment is performed in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, the treatment is continuously performed in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour. By the heat treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed.

Further, the heat treatment may be performed after the film formation of the insulator 222 is performed. For the heat treatment, the above-mentioned heat treatment conditions can be used.

Here, in order to form an excess oxygen region in the insulating film 224A, plasma treatment containing oxygen may be performed in a reduced pressure state. For plasma treatment containing oxygen, for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulating film 224A. can. Alternatively, plasma treatment containing an inert gas may be performed using this apparatus, and then plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. By appropriately selecting the plasma treatment conditions, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed.

Here, aluminum oxide may be formed on the insulating film 224A by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulating film 224A. By performing the CMP, the surface of the insulating film 224A can be flattened and the surface of the insulating film 224A can be smoothed. By arranging the aluminum oxide on the insulating film 224A and performing CMP, it becomes easy to detect the end point of CMP. Further, the insulating film 224A may be partially polished by the CMP to reduce the film thickness of the insulating film 224A. However, the film thickness may be adjusted when the insulating film 224A is formed. By flattening and smoothing the surface of the insulating film 224A, it may be possible to prevent deterioration of the coverage of the oxide to be formed later and prevent a decrease in the yield of the semiconductor device. Further, it is preferable that oxygen can be added to the insulating film 224A by forming aluminum oxide on the insulating film 224A by a sputtering method.

Next, the oxide film 230A and the oxide film 230B are sequentially formed on the insulating film 224A (see FIG. 5). It is preferable that the oxide film is continuously formed without being exposed to the atmospheric environment. By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.

The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film formed can be increased. Further, when the above oxide film is formed by a sputtering method, the above In—M—Zn oxide target can be used.

In particular, when the oxide film 230A is formed, a part of oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

Further, when the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. It is formed. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can obtain relatively high field-effect mobilities.

In the present embodiment, the oxide film 230A is In: Ga: Zn = 1: 1: 0.5 [atomic number ratio] (2: 2: 1 [atomic number ratio]) or 1: 3 by the sputtering method. : 4 [Atomic number ratio] is used to form a film. Further, as the oxide film 230B, a film is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio] or 1: 1: 1 [atomic number ratio]. Each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film forming conditions and the atomic number ratio.

Next, heat treatment may be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. By heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, after the treatment is performed in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, the treatment is continuously performed in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.

Next, the oxide film 243A is formed on the oxide film 230B. The oxide film 243A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 5).

Next, the oxide film 230A, the oxide film 230B, and the oxide film 243A are processed into an island shape to form the oxide 230a, the oxide 230b, and the oxide layer 243B (see FIG. 6). Although not shown, the film thickness of the region that does not overlap with the oxide 230a of the insulating film 224A may be reduced in the process.

Here, the oxide 230a, the oxide 230b, and the oxide layer 243B are formed so that at least a part thereof overlaps with the conductor 205. Further, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, and the oxide layer 243B are substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, and the oxide layer 243B are substantially perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when a plurality of transistors 200 are provided. It becomes. Alternatively, the angle formed by the oxide 230a, the oxide 230b, and the oxide layer 243B and the upper surface of the insulator 222 may be low. In that case, the angle formed by the side surface of the oxide 230a, the oxide 230b, and the oxide layer 243B and the upper surface of the insulator 222 is preferably 60 ° or more and less than 70 °. With such a shape, in the subsequent steps, the covering property of the insulator 272 and the like can be improved, and defects such as voids can be reduced.

Further, it is preferable to have a curved surface between the side surface of the oxide layer 243B and the upper surface of the oxide layer 243B. That is, it is preferable that the end portion of the side surface and the end portion of the upper surface are curved (hereinafter, also referred to as a round shape). The curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at the end of the oxide layer 243B. By having no corners at the ends, the coverage of the film in the subsequent film forming process is improved.

The oxide film and the conductive film may be processed by using a lithography method. Further, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication.

Next, the insulating film 272A is formed on the insulating film 224A, the oxide 230a, the oxide 230b, and the oxide layer 243B (see FIG. 7).

The insulating film 272A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 272A, it is preferable to use an insulating film having a function of suppressing the permeation of oxygen. For example, silicon nitride or silicon oxide is formed by a sputtering method.

Next, a dummy gate film to be a dummy gate layer 262A is formed on the insulating film 272A.

The dummy gate film to be the dummy gate layer 262A is processed and used as a dummy gate. The dummy gate is a temporary gate electrode. That is, a temporary gate electrode is formed by processing the dummy gate film to be the dummy gate layer 262A, the dummy gate is removed in a later step, and a gate electrode made of a conductive film or the like is formed instead. Therefore, it is preferable to use a dummy gate film to be the dummy gate layer 262A, which is easy to microfabricate and easy to remove.

The film formation of the dummy gate film to be the dummy gate layer 262A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, insulators, semiconductors, or conductors can be used. Specifically, silicon such as polysilicon, microcrystalline silicon and amorphous silicon, and a metal film such as aluminum, titanium and tungsten may be used. Alternatively, a carbon-containing film, SOG (Spin On Glass), a resin film, or the like may be formed by using a coating method. For example, photoresists, polyesters, polyolefins, polyamides (nylon, aramid, etc.), polyimides, polycarbonates or acrylics. By forming the SOG and the resin film by the coating method, the surface of the dummy gate film can be flattened. By flattening the surface of the dummy gate film in this way, microfabrication is facilitated, and further, removal is easy.

Further, the dummy gate film to be the dummy gate layer 262A can be a multilayer film by using different film types. For example, the dummy gate film to be the dummy gate layer 262A can be a conductive film and a film having a two-layer structure in which a resin film is formed on the conductive film. By having such a structure of the dummy gate film, for example, the conductive film may function as a stopper film for CMP treatment in a later CMP step. Alternatively, it may be possible to detect the end point of the CMP process, and it may be possible to reduce machining variations.

Next, the dummy gate film to be the dummy gate layer 262A is etched by the lithography method to form the dummy gate layer 262A (see FIG. 7). The dummy gate layer 262A is formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.

Next, the dopant 257 is added to the oxide layer 243B and the oxide 230b using the dummy gate layer 262A as a mask (see FIG. 8). As a result, a region 253 (regions 253a and region 253b) containing the dopant 257 is formed in a region that does not overlap with the oxide layer 243B and the dummy gate layer 262A of the oxide 230b. The region 253 functions as a low resistance region. In this way, the distance between the region 253a and the region 253b, that is, the length of L'in FIG. 3, can be controlled by the length of the dummy gate layer 262A in the channel length direction.

As a method for adding the dopant 257, an ion implantation method in which the ionized raw material gas is added by mass separation, an ion implantation method in which the ionized raw material gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. be able to. When mass separation is performed, the ion species to be added and the concentration thereof can be strictly controlled. On the other hand, when mass separation is not performed, high-concentration ions can be added in a short time. Further, an ion doping method in which a cluster of atoms or molecules is generated and ionized may be used. The dopant may be paraphrased as an ion, a donor, an acceptor, an impurity, an element, or the like.

As the dopant 257, the above-mentioned element that forms an oxygen deficiency, an element that binds to an oxygen deficiency, or the like may be used. Typical examples of such an element include boron and phosphorus. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gas and the like may be used. Typical examples of rare gas elements include helium, neon, argon, krypton, xenon and the like. Also, metals such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. One or more metal elements selected from the elements may be added. Among the above, boron and phosphorus are preferable as the dopant 257. When boron or phosphorus is used as the dopant 257, equipment on a production line for amorphous silicon or low-temperature polysilicon can be used, so that capital investment can be suppressed.

Further, in FIG. 8, the dopant 257 is added substantially perpendicularly to the upper surface of the insulator 214, but the addition is not limited to this, and the dopant 257 may be added at an angle with respect to the upper surface of the insulator 214. By inclining the upper surface of the insulator 214 with respect to the addition of the dopant, the region 253a and the region 253b can be formed in a part of the region overlapping with the dummy gate layer 262A.

Due to the addition of the dopant 257, in the oxide layer 243B and the oxide 230b, the crystallinity of the region 253 may be lower than the crystallinity of the region superimposing on the dummy gate layer 262A. Further, in the oxide layer 243B and the oxide 230b, the crystal orientation (for example, the orientation of the c-axis) of the region 253 may be disturbed as compared with the region superposed on the dummy gate layer 262A. For example, region 253 may have an amorphous structure, a polycrystalline structure, or a microcrystal structure.

Further, in the method for producing the present embodiment, the dopant 257 is added to the oxide layer 243B and the oxide 230b via the insulating film 272A. By this preparation method, the dopant 257 is also added to the insulating film 272A. That is, all of the oxide layer 243B, the oxide 230b, and the insulating film 272A have an element contained in the dopant 257. Further, when the insulating film 272A has excess oxygen, the dopant 257 may be able to suppress the diffusion of excess oxygen to the outside.

As described above, by forming the region 253, the conductor 260 formed in the later step can be arranged in a self-aligned manner between the region 253a and the region 253b.

Next, the insulating film 270A is formed on the insulating film 272A and the dummy gate layer 262A. The insulating film 270A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to form an aluminum oxide film by the ALD method. The dummy gate layer 262A may be deformed by the reaction with the gas used for forming the insulating film 280A or the collision of ions in the formation of the insulating film 280A in the subsequent process. By providing the insulating film 270A, the dummy gate layer 262A can be protected and deformation can be suppressed. In the present embodiment, an aluminum oxide film is formed by the ALD method, and then the aluminum oxide film is formed by the sputtering method to form an insulating film 270A having a laminated structure (see FIG. 9).

Next, an insulating film 280A is formed on the insulating film 270A (see FIG. 9). The insulating film 280A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 280A, for example, silicon oxide formed by a sputtering method, silicon oxide nitride formed by a CVD method, or the like is preferably used, and a laminated film thereof may be used.

Next, the insulating film 280A, the insulating film 270A, and a part of the dummy gate layer 262A are removed until a part of the dummy gate layer 262A is exposed to form the insulator 280, the insulator 270, and the dummy gate 262. (See FIG. 10). It is preferable to use CMP treatment for forming the insulator 280, the insulator 270, and the dummy gate 262.

Further, as described above, by forming the dummy gate layer 262A into, for example, a film having a two-layer structure in which a conductive film and a resin film are formed on the conductive film, the conductive film is a stopper film for CMP treatment in the CMP step. May function as. Alternatively, the conductive film may be able to detect the end point of the CMP treatment, and may be able to reduce variations in the height of the dummy gate 262. As shown in FIGS. 10B and 10C, the upper surface of the dummy gate 262 and the upper surfaces of the insulator 270 and the insulator 280 substantially coincide with each other.

Next, the dummy gate 262 is removed (see FIG. 11). The removal of the dummy gate 262 can be performed by wet etching, dry etching, ashing or the like. Alternatively, a plurality of the above processes may be combined as appropriate. For example, a wet etching process can be performed after the ashing process. By removing the dummy gate 262, a part of the insulating film 272A is exposed.

Next, the insulator 272 is formed by removing a part of the insulating film 272A exposed by removing the dummy gate 262 (see FIG. 12). The insulating film 272A can be removed by using wet etching, dry etching, ashing, or the like. Alternatively, a plurality of the above processes may be combined as appropriate. By removing the insulating film 272A, the insulator 272 has an opening, and a part of the surface of the oxide layer 243B is exposed at the opening. The width of the aperture in the channel length direction roughly coincides with the length of L'in FIG. Further, as shown in FIG. 12C, at this time, the film thickness may be reduced in a part of the insulating film 224A.

Next, an insulating film 266A is formed on the insulator 280, the insulator 270, the insulator 272, the insulating film 224A, and the oxide layer 243B, and a dummy film 265A is formed on the insulating film 266A (see FIG. 13). .). Here, the insulating film 266A needs to be formed in contact with the insulator 270 and the side wall of the insulator 272, and is formed by the thickness of the dummy film 265A or the reaction between the dummy film 265A described later and the etching gas. The distance between the oxide 243a and the oxide 243b, that is, the length of L in FIG. 3, is determined depending on the width of the by-product 267 to be formed. Therefore, it is preferable that the insulating film 266A and the dummy film 265A are formed by using the ALD method, which has high coverage and relatively easy fine adjustment of the film thickness. The film thicknesses of the insulating film 266A and the dummy film 265A may be appropriately set according to the electrical characteristics required for the transistor 200. For example, the film thickness of the insulating film 266A may be 0.5 nm or more, preferably 1 nm or more. Further, for example, the film thickness of the dummy film 265A may be 5 nm or more and 25 nm or less, preferably 10 nm or more and 20 nm or less.

Here, since the dummy film 265A is finally removed, it is preferable to use a film that is easy to microfabricate and is easy to remove. For example, in the present embodiment, aluminum oxide formed by the ALD method may be used as the dummy film 265A. Further, the insulating film 266A functions as an etching stopper when the dummy film 265A is removed. Therefore, in the etching for removing the dummy film 265A, an insulator having an etching rate lower than that of the dummy film 265A is used. For example, in the present embodiment, hafnium oxide formed by the ALD method may be used as the insulating film 266A.

Next, the insulating film 266A and the dummy film 265A are anisotropically etched to remove a part of the insulating film 266A and the dummy film 265A, and the upper surface of the oxide layer 243B and the side surface of the insulator 270 and the insulator 272 are removed. The insulator 266 is formed in contact with the insulator 266, the dummy layer 265 is formed on the insulator 266, and the by-product 267 is deposited on the dummy layer 265 (see FIG. 14). The insulator 266, the dummy layer 265, and the by-product 267 remain only in the vicinity of the side wall of the insulator 270 and the insulator 272. In the later step, the insulator 266, the dummy layer 265, and the by-product 267 are not formed in the portion where the channel forming region of the transistor 200 is formed, and the oxide layer 243B is exposed. Therefore, the cross-sectional shapes of the insulator 266 and the dummy layer 265 are L-shaped as shown in FIGS. 14 (B) and 14 (C). Further, the insulator 266, the dummy layer 265, and the by-product 267 formed in the vicinity of the side wall of the insulator 272 can be collectively referred to as a sidewall.

It is preferable to use dry etching for anisotropic etching. The dry etching includes, for example, C ₄ F ₆ gas, C ₅ F ₆ gas, C ₄ F ₈ gas, CF ₄ gas, SF ₆ gas, CHF ₃ gas, Cl ₂ gas, BCl ₃ gas or SiCl ₄ gas, etc. Can be used alone or in admixture of two or more gases. Alternatively, oxygen gas, helium gas, argon gas, hydrogen gas and the like can be appropriately added to the above gas. These etching gases can be appropriately switched and used according to the objects to be etched (insulating film 266A and dummy film 265A).

The above-mentioned apparatus can be used as the dry etching apparatus, but a parallel plate type dry etching apparatus having a configuration in which a high frequency power supply having a different frequency is connected to each of the opposing electrodes can perform anisotropic etching relatively easily. Therefore, it is preferable to use the dry etching apparatus.

Further, it is preferable that the etching step is performed under conditions that facilitate the formation of by-product 267. As a condition of such an etching step, for example, it is preferable to use a gas containing a large amount of carbon as at least one of the etching gases. Specifically, the carbon-rich gas preferably contains carbon and fluorine, and the atomic number ratio of carbon is 50% or more of the atomic number ratio of fluorine. As such an etching gas, for example, C ₄ F ₆ gas, C ₅ F ₆ gas, C ₄ F ₈ gas, or the like can be used alone or in combination of two or more gases. Alternatively, oxygen gas, helium gas, argon gas, nitrogen gas, hydrogen gas and the like can be appropriately added to the above gas.

By performing etching using such an etching gas, the gas is decomposed by plasma, and carbon contained in the gas reacts with a component (for example, aluminum) contained in the dummy film 265A to form a carbon compound. Is formed. Further, the fluorine contained in the gas reacts with the component (for example, aluminum) contained in the dummy film 265A to form a fluorine compound. These carbon compounds, fluorine compounds, and the like are deposited on the dummy layer 265 to form a by-product 267. Therefore, the by-product 267 is formed to include the dummy layer 265, the insulator 266, the insulator 280, and the components contained in the etching gas. Thus, the by-product 267 may contain aluminum, fluorine, and carbon.

By forming the by-product 267, the width of the sidewall composed of the insulator 266, the dummy layer 265, and the by-product 267 is increased with the insulator 270 and the insulating film 266A formed on the side wall of the insulator 272. It can be larger than the total film thickness of the dummy film 265A. Since the oxide 243a and the oxide 243b can be formed on the portion overlapping the insulator 266 and the dummy layer 265, the region 232a and the region 232b shown in FIG. 3 can be sufficiently lengthened in the channel length direction. L can be sufficiently shortened with respect to L'. For example, if L'corresponding to the width of the dummy gate 262 in the channel length direction is 60 nm, and if the width of the sidewall composed of the insulator 266, the dummy layer 265, and the by-product 267 can be 15 nm, then L is It can be 30 nm. Similarly, if the width of the sidewall can be 20 nm, L can be 20 nm. Further, if the width of the sidewall can be 25 nm, L can be 10 nm. Further, if the width of the sidewall can be 27.5 nm, L can be 5 nm. That is, even if L'has a length of 60 nm or more, L can be made sufficiently small. Since L'can be increased regardless of the length of L, the oxide film 230C, the insulating film 250A, the conductive film 260Aa and the conductive film 260Ab are applied to the oxide 230b, the oxide 243, the insulator 266 and the like in the subsequent step. Therefore, it can be formed with good coverage.

Next, using the insulator 266, the dummy layer 265, and the by-product 267 as masks, a part of the oxide layer 243B is removed to form the oxide 243a and the oxide 243b. It is preferable to use a wet etching method for etching the oxide layer 243B. In etching the oxide layer 243B, the by-product 267 and the dummy layer 265 may also be etched (see FIG. 15). The by-product 267 and the dummy layer 265 may be etched after the oxides 243a and 243b are formed.

When etching the dummy layer 265 and the by-product 267, the insulator 266 functions as an etching stopper. This makes it possible to prevent the insulator 254 and the insulator 244 from being etched when the dummy layer 265 and the by-product 267 are etched. Hereinafter, the process will be described with the insulator 266 remaining, but the insulator 266 may be removed.

In the above, an example in which a sidewall composed of an insulator 266, a dummy layer 265, and a by-product 267 is used as a mask in the processing of the oxide layer 243B has been shown, but the present embodiment is not limited to this. A sidewall may be formed by a known method, the oxide layer 243B may be processed, and the sidewall may be removed after the oxide layer 243B is processed. Further, the oxide layer 243B may be processed by using a lithography method without using a sidewall for processing the oxide layer 243B.

By performing the conventional dry etching or the like, impurities caused by the etching gas or the like may adhere to or diffuse on the surface or the inside of the oxide 230a and the oxide 230b. Impurities include, for example, fluorine or chlorine.

Cleaning is performed to remove the above impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.

As the wet cleaning, the cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, aqueous ammonia, or hydrofluoric acid with carbonated water or pure water. Alternatively, ultrasonic cleaning may be performed using pure water or carbonated water.

Next, heat treatment may be performed. The heat treatment may be performed under reduced pressure to continuously form the oxide film 230C without exposing it to the atmosphere. By performing such a treatment, it is possible to remove the water and hydrogen adsorbed on the surface of the oxide 230b and the like, and further reduce the water concentration and the hydrogen concentration in the oxide 230a and the oxide 230b. .. The temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200 ° C. (see FIG. 16).

Here, the oxide film 230C is in contact with at least a part of the side surface of the oxide 230a, a part of the side surface and the upper surface of the oxide 230b, a part of the side surface of the oxide 243, and the upper surface and the side surface of the insulator 266. It is preferable that it is provided as follows. When the insulator 266 is removed before the oxide film 230C is formed, the oxide film 230C is a part of the side surface of the oxide 230a, a part of the side surface and a part of the upper surface of the oxide 230b, and the oxide 243. In addition to a part of the side surface, the upper surface of the region that does not overlap with the insulator 272 of the oxide 243, the side surface of the insulator 272, and the side surface of the insulator 270 are provided so as to be in contact with each other, and the structure shown in FIG. 2 is obtained. At this time, the conductor 205 is not limited to the structure shown in FIG. 2, and the conductor 205 having the structure shown in FIG. 16 can be used.

The film formation of the oxide film 230C can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C. In the present embodiment, as the oxide film 230C, a target of In: Ga: Zn = 1: 3: 4 [atomic number ratio] or 4: 2: 4.1 [atomic number ratio] is used by the sputtering method. Form a film.

The oxide film 230C may be laminated. For example, by a sputtering method, a film is formed using a target of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio], and In: Ga: Zn = 1: 3: 4 [atomic number ratio] is continuously formed. A film may be formed using a target of [number ratio].

In particular, when the oxide film 230C is formed, a part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

Next, heat treatment may be performed. The heat treatment may be performed under reduced pressure to continuously form the insulating film 250A without exposing it to the atmosphere. By performing such a treatment, the water and hydrogen adsorbed on the surface of the oxide film 230C and the like are removed, and the water concentration and the hydrogen concentration in the oxide 230a, the oxide 230b and the oxide film 230C are further reduced. Can be made to. The temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower (see FIG. 16).

The insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, it is preferable to form silicon oxide nitride by a CVD method. The film forming temperature at the time of forming the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly around 400 ° C. By forming the insulating film 250A at 400 ° C., an insulator having few impurities can be formed.

Next, the conductive film 260Aa and the conductive film 260Ab are formed. The film formation of the conductive film 260Aa and the conductive film 260Ab can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use the CVD method. In the present embodiment, the conductive film 260Aa is formed by using the ALD method, and the conductive film 260Ab is formed by using the CVD method (see FIG. 16).

Next, by CMP treatment, the oxide film 230C, the insulating film 250A, the conductive film 260Aa and the conductive film 260Ab are polished until the insulator 280 is exposed, so that the oxide 230c, the insulator 250 and the conductor 260 (conductor 260a) are polished. And the conductor 260b) (see FIG. 17).

Next, heat treatment may be performed. In the present embodiment, the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour. By the heat treatment, the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.

Next, an insulating film to be an insulator 282 may be formed on the conductor 260, the insulator 250, the oxide 230c, and the insulator 280. The film formation of the insulating film to be the insulator 282 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 282, for example, aluminum oxide formed by a sputtering method, silicon nitride formed by a sputtering method, silicon nitride formed by a CVD method, or the like can be used. By forming the insulator 282 in contact with the upper surface of the conductor 260 in this way, it is possible to suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 in the subsequent heat treatment. Therefore, it is preferable (see FIG. 17).

Next, heat treatment may be performed. In the present embodiment, the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour. By the heat treatment, oxygen added by the film formation of the insulator 282 can be injected into the insulator 280. Further, the oxygen can be injected into the oxide 230a and the oxide 230b via the oxide 230c.

Next, an insulator to be the insulator 274 may be formed on the insulator 282. The film formation of the insulating film to be the insulator 274 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 17).

Next, an insulator to be the insulator 281 may be formed on the insulator 274. The film formation of the insulating film to be the insulator 281 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 281, for example, it is preferable to form silicon nitride by a sputtering method. (See FIG. 17).

Next, the insulator 272, the insulator 270, the insulator 280, the insulator 282, the insulator 274 and the insulator 281 are formed with openings reaching the oxides 243a and 243b. The opening may be formed by using a lithography method.

Next, an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 241, it is preferable to use an insulating film having a function of suppressing the permeation of oxygen. For example, it is preferable to form aluminum oxide or silicon nitride by the ALD method. Further, the anisotropic etching may be performed by, for example, a dry etching method. By having such a structure on the side wall portion of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. Further, it is possible to prevent impurities such as water and hydrogen from diffusing from the conductor 240a and the conductor 240b to the outside.

Next, a conductive film to be the conductor 240a and the conductor 240b is formed. It is desirable that the conductive film to be the conductor 240a and the conductor 240b has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum nitride, titanium nitride and the like can be laminated with tungsten, molybdenum, copper and the like. The film formation of the conductive film to be the conductor 240 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, by performing the CMP treatment, a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed. As a result, the conductor 240a and the conductor 240b having a flat upper surface can be formed by the conductive film remaining only in the opening (see FIG. 1). In addition, a part of the insulator 281 may be removed by the CMP treatment.

Next, a conductive film to be a conductor 246 is formed. The film formation of the conductive film to be the conductor 246 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductor 246 is processed by a lithography method to form a conductor 246a in contact with the upper surface of the conductor 240a and a conductor 246b in contact with the upper surface of the conductor 240b (see FIG. 1).

As described above, the semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 5 to 17, the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device shown in the present embodiment.

According to one aspect of the present invention, it is possible to provide a semiconductor device having a large on-current. Alternatively, one aspect of the present invention can provide a semiconductor device having high frequency characteristics. Alternatively, one aspect of the present invention can provide a semiconductor device with good reliability. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention can provide a semiconductor device having good electrical characteristics. Alternatively, according to one aspect of the present invention, a semiconductor device having a small off-current can be provided. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments and examples.

(Embodiment 2)
In this embodiment, one embodiment of the semiconductor device will be described with reference to FIGS. 19 and 20.

[Storage device 1]
FIG. 19 shows an example of a semiconductor device (storage device) using a capacitive element which is one aspect of the present invention. In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. As the transistor 200, the transistor 200 described in the previous embodiment can be used.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

In the semiconductor device shown in FIG. 19, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100. ..

Further, the storage devices shown in FIG. 19 can form a memory cell array by arranging them in a matrix.

<Transistor 300>
The transistor 300 is provided on the substrate 311 and functions as a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a source region or a drain region. It has a low resistance region 314a and a low resistance region 314b. The transistor 300 may be either a p-channel type or an n-channel type.

Here, in the transistor 300 shown in FIG. 19, the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered by the conductor 316 via the insulator 315. The conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. In addition, it may have an insulator that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

The transistor 300 shown in FIG. 19 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

<Capacitive element 100>
The capacitive element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.

Further, for example, the conductor 112 provided on the conductor 246 and the conductor 110 can be formed at the same time. The conductor 112 has a function as a plug or wiring for electrically connecting to the capacitive element 100, the transistor 200, or the transistor 300.

In FIG. 19, the conductor 112 and the conductor 110 show a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having the barrier property and the conductor having a high conductivity.

Further, the insulator 130 is, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, hafnium nitride. Etc. may be used, and it can be provided in a laminated manner or in a single layer.

For example, it is preferable to use a laminated structure of a material having a large dielectric strength such as silicon oxide and a high dielectric constant (high—k) material for the insulator 130. With this configuration, the capacitive element 100 can secure a sufficient capacitance by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacitance is improved. It is possible to suppress electrostatic breakdown of the element 100.

As the insulator of the high dielectric constant (high-k) material (material having a high specific dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, and nitrides having aluminum and hafnium. , Oxides with silicon and hafnium, nitrides with silicon and hafnium or nitrides with silicon and hafnium, and the like.

On the other hand, as materials with high dielectric strength (materials with low relative permittivity), silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon added, carbon and nitrogen are used. There are added silicon oxide, silicon oxide with pores or resin and the like.

<Wiring layer>
A wiring layer provided with an interlayer film, wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design. Here, the conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numeral. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated on the transistor 300 in this order as an interlayer film. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitive element 100, a conductor 328 electrically connected to the transistor 200, a conductor 330, and the like. The conductor 328 and the conductor 330 function as a plug or wiring.

Further, the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 19, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.

A plurality of wiring layers including the insulator 350, the insulator 352, the insulator 354, and the conductor 356 may be provided depending on the circuit configuration required for the storage device 1. For example, four or more wiring layers may be provided.

Similarly, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like. The conductor 218 has a function as a plug or wiring for electrically connecting to the capacitive element 100 or the transistor 300. Further, an insulator 150 is provided on the conductor 120 and the insulator 130.

Examples of the insulator that can be used as the interlayer film include oxides having insulating properties, nitrides, nitride oxides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides.

For example, by using a material having a low relative permittivity for an insulator that functions as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, the material may be selected according to the function of the insulator.

For example, it is preferable that the insulator 150, the insulator 212, the insulator 352, the insulator 354, and the like have an insulator having a low relative permittivity. For example, the insulator includes silicon oxide, silicon nitriding, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores. Alternatively, it is preferable to have a resin or the like. Alternatively, the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with carbon and nitrogen, or silicon oxide with pores. And resin, it is preferable to have a laminated structure. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

Further, the transistor using the oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding the transistor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, the insulator 350, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulations containing, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in layers. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.

Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium, and indium. , A material containing one or more metal elements selected from ruthenium and the like can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like include a metal material, an alloy material, a metal nitride material, a metal oxide material, and the like formed of the above materials. Can be used as a single layer or laminated. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

<Wiring or plug of layer provided with oxide semiconductor>
When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.

For example, in FIG. 19, it is preferable to provide an insulator 276 between the insulator 224 having excess oxygen and the conductor 245. By providing the insulator 276, the insulator 222, and the insulator 272 in contact with each other, the insulator 224 and the transistor 200 can be configured to be sealed by the insulator having a barrier property. Further, the insulator 276 is preferably in contact with a part of the insulator 280. Since the insulator 276 extends to the insulator 280, the diffusion of oxygen and impurities can be further suppressed.

That is, by providing the insulator 276, it is possible to suppress the excess oxygen contained in the insulator 224 from being absorbed by the conductor 245. Further, by having the insulator 276, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 245.

As the insulator 276, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride or silicon nitride can be used.

The above is the description of the configuration example. By using this configuration, it is possible to suppress fluctuations in electrical characteristics and improve reliability in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a small off-current. Alternatively, it is possible to provide a semiconductor device with reduced power consumption.

[Storage device 2]
FIG. 20 shows an example of a storage device using a semiconductor device which is one aspect of the present invention. The storage device shown in FIG. 20 includes a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitive element 100 shown in FIG.

The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are connected to the source by a diode, and the source of the transistor 400 and the second gate of the transistor 200 are connected to each other. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source become 0V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the second gate of the transistor 200 does not need to be supplied with power to the transistor 200 and the transistor 400. The negative potential can be maintained for a long time. As a result, the storage device having the transistor 200 and the transistor 400 can retain the stored contents for a long period of time.

Therefore, in FIG. 20, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200. .. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100. .. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is the drain of the transistor 400. Is electrically connected to. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

Further, the storage device shown in FIG. 20 can form a memory cell array by arranging the storage devices in a matrix like the storage device shown in FIG. It should be noted that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, it is preferable to provide a smaller number of transistors 400 than the transistors 200.

<Transistor 400>
The transistor 400 is a transistor formed in the same layer as the transistor 200 and can be manufactured in parallel with the transistor 200. The transistor 400 includes a conductor 460 (conductor 460a and a conductor 460b) that functions as a first gate electrode, a conductor 405 that functions as a second gate electrode, and an insulator 222 that functions as a gate insulating layer. And an insulator 450, an oxide 430c having a region where a channel is formed, an oxide 443a, an oxide 431a, and an oxide 431b acting as one of the source or drain, and an oxidation acting as the other of the source or drain. On the objects 443b, the oxide 432a, and the oxide 432b, the conductor 440 (conductor 440a, and the conductor 440b), the oxide 443a, and the oxide 443b, and on the side surface of the insulator 272 and the insulator 270. It has an insulator 466 provided. Further, the oxide 443a and the oxide 431b are formed with a region 453a which is a low resistance region, and the oxide 443b and the oxide 432b are formed with a region 453b which is a low resistance region.

In the transistor 400, the conductor 405 is the same layer as the conductor 205. Oxide 431a and oxide 432a are in the same layer as oxide 230a, and oxide 431b and oxide 432b are in the same layer as oxide 230b. Oxide 443 is the same layer as oxide 243. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260. The insulator 466 is the same layer as the insulator 266. The region 453a and the region 453b are regions formed at the same time as the region 253.

The structures formed in the same layer can be formed at the same time. For example, the oxide 430c can be formed by processing an oxide film that becomes the oxide 230c.

Oxide 430c, which functions as an active layer of the transistor 400, has reduced oxygen deficiency and reduced impurities such as hydrogen and water, similarly to oxide 230 and the like. As a result, the threshold voltage of the transistor 400 can be made larger than 0V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small.

<Dicing line>
Hereinafter, a dicing line (sometimes referred to as a scribe line, a division line, or a cutting line) provided when a plurality of semiconductor devices are taken out in the form of chips by dividing a large-area substrate into semiconductor elements will be described. .. As a dividing method, for example, there is a case where a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, then the dicing line is cut, and the semiconductor device is divided (divided) into a plurality of semiconductor devices.

Here, for example, as shown in FIG. 20, it is preferable to design the region where the insulator 272 and the insulator 222 are in contact as a dicing line. That is, an opening is provided in the insulator 224 in the vicinity of the memory cell having the plurality of transistors 200 and the region serving as the dicing line provided on the outer edge of the transistor 400. Further, the insulator 272 is provided so as to cover the side surface of the insulator 224.

That is, the insulator 222 and the insulator 272 are in contact with each other in the opening provided in the insulator 224. For example, at this time, the insulator 222 and the insulator 272 may be formed by using the same material and the same method. By providing the insulator 222 and the insulator 272 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide or silicon nitride.

With this structure, the insulator 222 and the insulator 272 can enclose the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 272 have a function of suppressing the diffusion of oxygen, hydrogen, and water, the substrate is divided for each circuit region in which the semiconductor element shown in the present embodiment is formed. This makes it possible to prevent impurities such as hydrogen or water from being mixed in from the side surface direction of the divided substrate and diffusing into the transistor 200 and the transistor 400 even if the chips are processed into a plurality of chips.

Further, the structure can prevent the excess oxygen of the insulator 224 from diffusing to the outside of the insulator 272 and the insulator 222. Therefore, the excess oxygen of the insulator 224 is efficiently supplied to the transistor 200 or the oxide in which the channel is formed in the transistor 400. The oxygen can reduce the oxygen deficiency of the oxide in which the channel is formed in the transistor 200 or the transistor 400. As a result, the oxide in which the channel is formed in the transistor 200 or the transistor 400 can be made into an oxide semiconductor having a low defect level density and having stable characteristics. That is, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 or the transistor 400 and improve reliability.

This embodiment can be appropriately combined with the configurations described in other embodiments and examples.

(Embodiment 3)
In the present embodiment, using FIGS. 21 and 22, a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitive element according to one aspect of the present invention are applied. The storage device (hereinafter, may be referred to as an OS memory device) is described. The OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.

<Configuration example of storage device>
FIG. 21A shows an example of the configuration of the OS memory device. The storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. The wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. Further, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and the row to be accessed can be selected.

The storage device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (SiO) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. The address signal ADDR is input to the row decoder and column decoder, and WDATA is input to the write circuit.

The control logic circuit 1460 processes input signals (CE, WE, RE) from the outside to generate control signals for a row decoder and a column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.

The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.

Although FIG. 21A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited to this. For example, as shown in FIG. 21B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.

FIG. 22 describes an example of a memory cell configuration applicable to the above-mentioned memory cell MC.

[DOSRAM]
22 (A) to 22 (C) show an example of a circuit configuration of a DRAM memory cell. In the present specification and the like, a DRAM using a memory cell of a 1OS transistor and a 1-capacity element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 22 (A) has a transistor M1 and a capacitive element CA. The transistor M1 has a gate (sometimes referred to as a front gate) and a back gate.

The first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected. Is connected to the wiring BGL. The second terminal of the capacitive element CA is connected to the wiring CAL.

The wiring BIL functions as a bit line and the wiring WOL functions as a word line. The wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL when writing and reading data. The wiring BGL functions as wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1472 shown in FIG. 22 (B). Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 having no back gate, as in the memory cell 1473 shown in FIG. 22 (C).

When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitive element 100 can be used as the capacitive element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cells can be reduced. Further, the refresh operation of the memory cell can be eliminated. Further, since the leak current is very low, it is possible to hold multi-valued data or analog data for the memory cell 1471, the memory cell 1472, and the memory cell 1473.

Further, in the DOSRAM, if the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.

[NOSRAM]
22 (D) to 22 (H) show an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitance element. The memory cell 1474 shown in FIG. 22D has a transistor M2, a transistor M3, and a capacitive element CB. The transistor M2 has a front gate (sometimes referred to simply as a gate) and a back gate. In the present specification and the like, a storage device having a gain cell type memory cell using an OS transistor in the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

The first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2. Is connected to the wiring BGL. The second terminal of the capacitive element CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. It is preferable to apply a low level potential to the wiring CAL during data writing, data retention, and data reading. The wiring BGL functions as wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Further, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1475 shown in FIG. 22 (E). Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 22 (F). Further, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL, as in the memory cell 1477 shown in FIG. 22 (G).

When the semiconductor device shown in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitive element 100 can be used as the capacitive element CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very low. As a result, the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cells can be reduced. Further, the refresh operation of the memory cell can be eliminated. Further, since the leak current is very low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

The transistor M3 may be a transistor having silicon in the channel forming region (hereinafter, may be referred to as a Si transistor). The conductive type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a readout transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by stacking it on the transistor M3, so that the occupied area of the memory cell can be reduced and the storage device can be highly integrated.

Further, the transistor M3 may be an OS transistor. When an OS transistor is used for the transistors M2 and M3, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.

Further, FIG. 22H shows an example of a gain cell type memory cell having a 3-transistor and 1-capacity element. The memory cell 1478 shown in FIG. 22 (H) has transistors M4 to M6 and a capacitive element CC. The capacitive element CC is appropriately provided. The memory cell 1478 is electrically connected to the wiring BIL, RWL, WWL, BGL, and GNDL. Wiring GNDL is wiring that gives a low level potential. The memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. The back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not have to have a back gate.

The transistors M5 and M6 may be n-channel type Si transistors or p-channel type Si transistors, respectively. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured by using only n-type transistors.

When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitive element 100 can be used as the capacitive element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very low.

The configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above. The arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.

The configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and examples.

(Embodiment 4)
In this embodiment, FIG. 23 shows an example of a chip 1200 on which the semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. Such a technique for integrating a plurality of circuits (systems) on one chip may be called a system on chip (SoC).

As shown in FIG. 23A, the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more. Interface 1215, one or more network circuits 1216 and the like.

The chip 1200 is provided with a bump (not shown) and is connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 23 (B). Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.

The motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Further, for example, the NO SRAM shown in the previous embodiment can be used for the flash memory 1222.

The CPU 1211 preferably has a plurality of CPU cores. Further, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. As the memory, the above-mentioned NOSRAM or DOSRAM can be used. Further, the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, it becomes possible to execute image processing and product-sum calculation with low power consumption.

Further, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, and data transfer between the memories of the CPU 1211 and the GPU 1212. And after the calculation on the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.

The analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.

The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.

The interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface) and the like can be used.

The network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.

The circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

A PCB 1201 provided with a chip 1200 having a GPU 1212, a DRAM 1221, and a motherboard 1203 provided with a flash memory 1222 can be referred to as a GPU module 1204.

Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines. In addition, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DEM) are provided by a product-sum calculation circuit using GPU1212. Since the operation such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 5)
In this embodiment, an application example of a storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording / playback device, a navigation system, etc.). Can be applied to. Here, the computer includes a tablet-type computer, a notebook-type computer, a desktop-type computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 24 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.

FIG. 24A is a schematic diagram of the USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like of the substrate 1104.

FIG. 24B is a schematic diagram of the appearance of the SD card, and FIG. 24C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 on the back surface side of the board 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. As a result, the data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like of the substrate 1113.

FIG. 24 (D) is a schematic diagram of the appearance of the SSD, and FIG. 24 (E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like of the substrate 1153.

This embodiment can be appropriately combined with the configurations described in other embodiments and examples.

(Embodiment 6)
In the present embodiment, a product image applicable to the semiconductor device of one aspect of the present invention and specific examples of electronic devices will be described with reference to FIGS. 25 and 26.

First, FIG. 25 shows a product image that can be used in the semiconductor device of one aspect of the present invention. The region 501 shown in FIG. 25 represents a high temperature characteristic, the region 502 represents a high frequency characteristic, the region 503 represents a low off characteristic (Off), and the region 504 represents the region 501. , Region 502, and region 503 represent an overlapping region.

When the region 501 is to be filled, it can be roughly filled by applying a carbide or a nitride such as silicon carbide or gallium nitride as the channel forming region of the semiconductor device. Further, when the region 502 is to be filled, it can be roughly filled by applying a silicified product such as single crystal silicon or crystalline silicon as the channel forming region of the semiconductor device. Further, when the region 503 is to be filled, it can be roughly filled by using an oxide semiconductor or a metal oxide as the channel forming region of the semiconductor device.

The semiconductor device of one aspect of the present invention can be suitably used for products in the range shown in region 504, for example.

In conventional products, it has been difficult to fill all the regions 501, 502, and 503. However, the semiconductor device of one aspect of the present invention has a crystalline OS in the channel forming region. When the crystalline OS is provided in the channel forming region, it is possible to provide a semiconductor device and an electronic device that satisfy high temperature characteristics, high frequency characteristics, and low off characteristics.

Examples of products in the range shown in the region 504 include electronic devices such as CPUs with low power consumption and high performance, and in-vehicle electronic devices that are required to have high reliability in a high temperature environment.

More specifically, the semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip. FIG. 26 shows a specific example of a processor such as a CPU or GPU, or an electronic device provided with a chip according to one aspect of the present invention.

<Electronic devices / systems>
The GPU or chip according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include television devices, desktop or notebook personal chips, monitors for chips, digital signage (electronic signage), and relatively large game machines such as pachinko machines. In addition to electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, mobile information terminals, sound reproduction devices, and the like can be mentioned. Further, by providing an integrated circuit or chip according to one aspect of the present invention in an electronic device, artificial intelligence can be mounted on the electronic device.

The electronic device of one aspect of the present invention may have an antenna. By receiving the signal with the antenna, the display unit can display images, information, and the like. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

The electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).

The electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like. FIG. 26 shows an example of an electronic device.

[cell phone]

FIG. 26A illustrates a mobile phone (smartphone) which is a kind of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and a button is provided in the housing 5510.

The information terminal 5500 can execute an application utilizing artificial intelligence by applying the chip of one aspect of the present invention. Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5511. Examples include an application displayed on the display unit 5511 and an application for performing biometric authentication such as fingerprints and voice prints.

[Information terminal 1]
FIG. 26B shows a desktop information terminal 5300. The desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

Similar to the information terminal 5500 described above, the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like. Further, by using the desktop type information terminal 5300, it is possible to develop a new artificial intelligence.

In the above description, smartphones and desktop information terminals are taken as examples as electronic devices, and although they are shown in FIGS. 26A and 26B, respectively, information terminals other than smartphones and desktop information terminals can be applied. can. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[electric appliances]
FIG. 26C shows an electric freezer / refrigerator 5800, which is an example of an electric appliance. The electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

By applying the chip of one aspect of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric refrigerator-freezer 5800, the expiration date of the foodstuffs, etc., and is stored in the electric refrigerator-freezer 5800. It can have a function to automatically adjust the temperature according to the food.

In this example, an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an microwave oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Examples include appliances, washing machines, dryers, audiovisual equipment, etc.

[game machine]
FIG. 26D shows a portable game machine 5200, which is an example of a game machine. The portable game machine has a housing 5201, a display unit 5202, a button 5203, and the like.

By applying the GPU or chip of one aspect of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.

Further, by applying the GPU or chip of one aspect of the present invention to the portable game machine 5200, the portable game machine 5200 having artificial intelligence can be realized.

Originally, expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5200, , Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.

Further, when a plurality of players are required to play a game on the portable game machine 5200, the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one person can play the game. You can play the game.

FIG. 26 (D) illustrates a portable game machine as an example of a game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this. Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a sports facility. A throwing machine for practicing batting can be mentioned.

[Mobile]
The GPU or chip of one aspect of the present invention can be applied to a moving vehicle and the vicinity of the driver's seat of the vehicle.

FIG. 26 (E1) shows an automobile 5700 which is an example of a moving body, and FIG. 26 (E2) is a diagram showing a periphery of a windshield in the interior of an automobile. FIG. 26 (E1) illustrates the display panel 5701, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar, which are attached to the dashboard.

The display panel 5701 to the display panel 5703 can provide various other information such as a speedometer, a tachometer, a mileage, a refueling amount, a gear state, and an air conditioner setting. In addition, the display items and layouts displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panel 5701 to 5703 can also be used as a lighting device.

The display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an image pickup device (not shown) provided in the automobile 5700. That is, by displaying the image from the image pickup device provided on the outside of the automobile 5700, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, it is possible to confirm safety more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

Since the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system of an automobile 5700. In addition, the chip can be used in a system for performing road guidance, danger prediction, and the like. The display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.

In the above description, the automobile is described as an example of the moving body, but the moving body is not limited to the automobile. For example, moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, it is possible to provide a system using artificial intelligence.

[Broadcasting system]
The GPU or chip of one aspect of the present invention can be applied to a broadcasting system.

FIG. 26F schematically shows data transmission in a broadcasting system. Specifically, FIG. 26F shows a route for a radio wave (broadcast signal) transmitted from a broadcasting station 5680 to reach a television receiving device (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.

In FIG. 26 (F), the antenna 5650 illustrates a UHF (Ultra High Frequency) antenna, but as the antenna 5650, a BS / 110 ° CS antenna, a CS antenna, or the like can also be applied.

The radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio waves 5675A and transmits the radio waves 5675B. In each home, by receiving the radio wave 5675B with the antenna 5650, it is possible to watch the terrestrial TV broadcast on the TV 5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 26 (F), and may be satellite broadcasting using an artificial satellite, data broadcasting by an optical line, or the like.

The above-mentioned broadcasting system may be a broadcasting system using artificial intelligence by applying the chip of one aspect of the present invention. When broadcasting data is transmitted from the broadcasting station 5680 to the TV 5600 of each household, the broadcasting data is compressed by the encoder, and when the antenna 5650 receives the broadcasting data, the decoder of the receiving device included in the TV 5600 compresses the broadcasting data. Restoration is done. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of an encoder, it is possible to recognize a display pattern included in a display image. In-frame prediction using artificial intelligence can also be performed. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, it is possible to perform image interpolation processing such as up-conversion in the restoration of the broadcast data by the decoder.

The above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.

Further, as an application of artificial intelligence on the TV5600 side, for example, a recording device having artificial intelligence may be provided on the TV5600. With such a configuration, it is possible to automatically record a program that suits the user's preference by having the recording device learn the user's preference by artificial intelligence.

The electronic device described in this embodiment, the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be appropriately combined with the description of other electronic devices.

This embodiment can be appropriately combined with the configurations described in other embodiments and examples.

200 Transistors 205, 218, 240, 245, 246, 260 Conductors 210, 212, 214, 216, 222, 224, 241 and 244, 250, 254, 266, 270, 272, 273, 274, 276, 280, 281 , 282 Insulator 230, 243 Oxide 231, 232, 234, 253 Region 257 Dopant 262 Dummy Gate 265 Dummy Layer 267 By-Product

Claims (8)

With the first insulator,
With the first oxide on the first insulator,
With the second oxide on the first oxide,
With the third oxide and the fourth oxide on the second oxide,
With the fifth oxide on the second oxide,
With the second insulator on the fifth oxide,
It has a conductor that is located on the second insulator and overlaps with the second oxide.
The second oxide has a first region, a second region, and a third region located between the first region and the second region .
The first region and the second region each have a region having a lower resistance than the third region.
The third oxide has a region that overlaps with the first region and also overlaps with the third region.
A semiconductor device in which the fourth oxide has a region that overlaps with the second region and also overlaps with the third region. In claim 1,
The third oxide superimposed on the first region has a lower resistance than the third oxide superimposed on the third region.
A semiconductor device in which the fourth oxide superimposed on the second region has a lower resistance than the fourth oxide superimposed on the third region. With the first insulator,
With the first oxide on the first insulator,
With the second oxide on the first oxide,
With the third oxide and the fourth oxide on the second oxide,
With the fifth oxide on the second oxide,
With the second insulator on the fifth oxide,
It has a conductor that is located on the second insulator and overlaps with the second oxide.
The second oxide has a first region, a second region, and a third region located between the first region and the second region .
The first region and the second region each have a region having a lower crystallinity than the third region.
The third oxide has a region that overlaps with the first region and also overlaps with the third region.
A semiconductor device in which the fourth oxide has a region that overlaps with the second region and also overlaps with the third region. In claim 3,
The third oxide superimposed on the first region has lower crystallinity than the third oxide superimposed on the third region.
A semiconductor device in which the fourth oxide superimposed on the second region has lower crystallinity than the fourth oxide superimposed on the third region. A semiconductor device according to any one of claims 1 to 4, wherein the third oxide and the fourth oxide each contain zinc. In any one of claims 1 to 5,
The conductor is a semiconductor device having a region that overlaps with the third oxide and the fourth oxide. In any one of claims 1 to 6,
The second oxide is a semiconductor device having In, an element M (M is Al, Ga, Y, or Sn), and Zn. In any one of claims 1 to 7,
The first region and the second region are semiconductor devices containing one of phosphorus and boron.

Images