JP2009016469A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus capable of improving reliability, and to provide a method of manufacturing the same. <P>SOLUTION: A TFT comprises an underlying SiN film 2, an underlying SiO<SB>2</SB>film 3 and a Si film 14 which are sequentially placed on a substrate 1 made of glass. The Si film 14 comprises a source region 6 and a drain region 7 which are placed via an LDD region 5 on both adjacent sides of an active region 4. A predetermined drain voltage is applied between the source region 6 and the drain region 7 via a source electrode 11 and a drain electrode 12. In addition, a predetermined gate voltage is applied to the active region 4 via a gate electrode 9. An edge region located at an edge of the Si film 14 is formed by etching and has a tapered cross section. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique for improving reliability in a thin film transistor (TFT).

For example, as disclosed in Patent Document 1, a conventional TFT includes a substrate, a base SiN, a base SiO ₂ , an active region, an LDD region, a source region, a drain region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, A drain electrode and a passivation film are included.

  Such a TFT operates as follows. When a positive voltage (in the case of an n-type transistor) is applied to the gate electrode, a channel having a high electron concentration is formed in the active region, and the resistance of the transistor is reduced. At this time, when a voltage is applied between the source and the drain, a drain current flows in proportion to the drain voltage, so it is called a linear region. When the drain voltage is increased, the drain current also increases. However, when the drain voltage becomes approximately the same as the gate voltage, the drain current is saturated. Since the drain potential at this time is high, electrons in the active region near the drain are depleted, and a high-resistance region is formed. As a result, a phenomenon in which the drain current is saturated with respect to the drain voltage is observed. Such a region is called a saturation region. On the other hand, when the gate voltage falls below the threshold voltage, the electron concentration in the active region decreases, and the resistance of the transistor becomes extremely high. Such an area is called an OFF area. As described above, by changing the gate voltage, the resistance of the transistor can be controlled, and a switching operation can be realized.

JP 2006-126293 A

  As described above, since electrons in the active region near the drain are depleted in the saturation region, a large electric field is generated at the junction on the drain side. When this electric field is increased, electrons accelerated by the strong electric field cause an impact ionization phenomenon and generate electron-hole pairs. The electrons are accelerated toward the drain region and become hot carriers, causing fluctuations in transistor characteristics. When the transistor characteristics deteriorate, the current drive capability of the transistor becomes low, so that the operation of the digital circuit becomes unstable and further causes a malfunction. In addition, the analog circuit causes a problem that a desired voltage or current cannot be obtained. That is, the conventional semiconductor device has a problem that reliability is lowered.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of improving reliability and a manufacturing method thereof.

  A semiconductor device according to the present invention includes an active region and a semiconductor layer having at least first and second impurity regions on both sides of the active region and disposed on an insulating substrate or an insulating film, and a gate to the active region. A gate electrode disposed in contact with the active region via a gate insulating film to apply a voltage, and a current corresponding to the gate voltage between the first and second impurity regions to flow a current through the channel. A semiconductor device comprising: first and second electrodes arranged to be in contact with the first and second impurity regions, respectively, wherein the active region includes a predetermined region provided by etching; The ratio of the surface area of the predetermined region to the surface area of the region is 2% or more.

  In the semiconductor device according to the present invention, the active region includes a predetermined region provided by etching, and the ratio of the surface area of the predetermined region to the surface area of the active region is 2% or more. Accordingly, recombination of holes can be increased and impact ionization can be suppressed. Therefore, reliability can be improved.

<Embodiment 1>
Hereinafter, the first embodiment will be described in detail with reference to FIGS.

  FIG. 1 is a cross-sectional view showing the structure of a TFT as a semiconductor device according to the present embodiment. FIG. 2 is a top view corresponding to the main part (Si film 14 or semiconductor layer) of FIG. In FIG. 2, some of the members in FIG. 1 are omitted.

As shown in FIG. 1, in the TFT according to the present embodiment, on a substrate 1 made of glass, the underlying SiN film 2, the underlying SiO ₂ film 3 and the Si film 14, are disposed in this order.

  In the Si film 14, the source region 6 and the drain region 7 are arranged on both sides of the active region 4 with the LDD region 5 interposed therebetween.

  A gate electrode 9 is connected to the active region 4 through a gate insulating film 8. Further, the source electrode 11 and the drain electrode 12 (first and second electrodes) are connected to the source region 6 and the drain region 7 (first and second impurity regions) via the connection part 16, respectively. Yes.

  A predetermined drain voltage is applied between the source region 6 and the drain region 7 using the source electrode 11 and the drain electrode 12 (the source electrode 11 is grounded). A predetermined gate voltage is applied to the active region 4 using the gate electrode 9. A channel is formed in the active region 4 in accordance with the applied gate voltage, and a drain current flows between the source electrode 11 and the drain electrode 12 through this channel. The size of the channel is determined by the channel length corresponding to the horizontal direction and the channel width corresponding to the depth direction in FIG.

  As shown in FIG. 1, the end region located at the end of the Si film 14 has a tapered cross-sectional shape.

  Therefore, as shown in FIG. 2, the active region 4 is composed of an active region body 4a having a flat cross-sectional shape and an active region end portion 4b having a tapered cross-sectional shape. The LDD region 5 includes an LDD region body 5a having a flat cross-sectional shape and an LDD region end portion 5b having a tapered cross-sectional shape. The source region 6 includes a source region body 6a having a flat cross-sectional shape and a source region end portion 6b having a tapered cross-sectional shape. The drain region 7 includes a drain region body 7a having a flat cross-sectional shape and a drain region end portion 7b having a tapered cross-sectional shape. Hereinafter, the active region end 4b, the LDD region end 5b, the source region end 6b, and the drain region end 7b are collectively referred to simply as an end b (end region).

In the present embodiment, the case where the cross-sectional shape of the end b is tapered will be described. However, the shape is not limited to the tapered shape, and the surface forms an acute angle with the substrate 1 or the underlying SiN film 2 and the underlying SiO ₂ film 3. As long as it is a region formed by etching so as to have

  Next, a manufacturing method of the TFT of FIGS. 1-2 will be described with reference to FIG.

First, referring to FIG. 3A, a 100 nm base SiN film ₂ , a 100 nm base SiO ₂ film 3, and a 50 nm amorphous Si film 14 are formed on a substrate 1 made of glass by plasma CVD. Were sequentially formed. As glass for the substrate 1, Corning 1737 was used.

  In addition, the board | substrate 1 should just have insulation, not restricted to glass. For example, quartz or resin can be used. Alternatively, an insulating film formed on a conductive substrate such as a Si substrate or a metal substrate can be substituted.

The underlying SiN film 2 is formed in order to prevent impurities in the substrate 1 from diffusing into the Si film 14, and is not limited to SiN. Materials such as SiON, SiC, AlN, Al ₂ O ₃ are used. It may be used.

In addition, this time, a two-layer structure of SiO ₂ (base SiO ₂ film 3) and SiN (base SiN film 2) is used as the base film of the Si film 14, but the present invention is not limited to this. May be omitted, or a laminated structure of three or more layers may be used.

  Next, the Si film 14 was heat-treated in vacuum to remove unnecessary hydrogen. Next, the Si film 14 was irradiated with a XeCl laser to be polycrystallized. The grain size of the polycrystalline film is about 0.5 μm. This time, a XeCl laser was used for crystallization, but the present invention is not limited to this. A YAG laser may be used, a CW laser may be used, and thermal annealing may be used. In thermal annealing, polycrystalline Si having a large grain size can be obtained by a method using a catalyst such as Ni.

  Next, a resist (not shown) was formed by photolithography, and the Si film 14 was processed into an island shape by dry etching using this resist as a mask. At this time, the etching process was performed so that the end of the Si film 14 was tapered by adjusting the cross-sectional shape of the resist. Then, the resist was removed by ashing and chemical treatment.

Next, a gate insulating film 8 made of a 100 nm SiO ₂ film was formed on the Si film 14 by plasma CVD. TEOS and O ₂ were used as raw materials for the plasma CVD method.

Next, B was implanted into the island-like Si film 14 in order to control the threshold value. As the injection conditions, the injection amount was 1E12 atom / cm ² and the acceleration energy was 60 eV. Note that this step may be omitted as necessary.

  Next, referring to FIG. 3B, 200 nm of Cr was formed on the entire surface of the gate insulating film 8 by sputtering. Then, a resist (not shown) was formed by photolithography and the gate electrode 9 was formed by wet etching of Cr using this resist as a mask. The channel length of the TFT is determined by the width of the gate electrode 9, but this time, the width of the gate electrode 9 is set to 5 μm.

  Next, a resist 15 was formed so as to cover the gate electrode 9 by photolithography, and P was implanted into the Si film 14 using the resist 15 as a mask. As the injection conditions, the injection amount was 1E14 atom / cm 2 and the acceleration energy was 80 eV. As a result, the source region 6 and the drain region 7 having a relatively high impurity concentration could be formed in the Si film 14.

Next, referring to FIG. 3C, after removing the resist 15 by ashing and chemical treatment, P was implanted into the Si film 14 using the gate electrode 9 as a mask. As the injection conditions, the injection amount was 1E13 atom / cm ² and the acceleration energy was 80 eV. As a result, the LDD region 5 having a lower impurity concentration than the source region 6 and the drain region 7 could be formed in the Si film 14. This time, the LDD length was set to 1 μm.

Next, referring to FIG. 3 (d), the by plasma CVD to cover the gate insulating film 8 and gate electrode 9, forming an interlayer insulating film 10 made of SiO ₂ film of 400 nm. Then, a resist (not shown) was formed by photolithography, and the interlayer insulating film 10 and the gate insulating film 8 were dry-etched using this resist as a mask to form connection holes. Further, a laminated film of Cr and Al was formed, and photolithography and wet etching were performed on the laminated film, thereby forming the connection portion 16, the source electrode 11, and the drain electrode 12. Finally, a passivation film 13 made of 200 nm SiN was formed by plasma CVD.

  FIG. 4 is a graph showing the evaluation of the reliability of the TFT formed by the above process. In FIG. 4, the horizontal axis indicates the channel width, and the vertical axis indicates the lifetime of the TFT when stress is applied under a predetermined stress condition.

As stress conditions, the gate voltage was 1 V, the drain voltage was 15 V, and the source was grounded. Then, the drain current-gate voltage characteristics of the TFT before and after the stress application were measured, and when the gate voltage was 10 V and the drain voltage was 1 V, the stress time when the drain current changed by 10% was estimated as the lifetime. In the evaluated TFT sample, the taper angle of the end b of the active region 4 was 20 °, the channel length was 5 μm, and the channel width was 3 to 500 μm. The taper angle is an angle formed by the surface of the underlying SiO ₂ film 3 and the surface of the tapered Si film 14 end.

  In FIG. 4, the lifetime is shown as a relative value with respect to the lifetime when the channel width is 500 μm, but it can be seen that the reliability is improved when the channel width is 20 μm or less. That is, it can be seen that it is particularly necessary to improve the reliability for TFTs having a channel width of 20 μm or more.

FIG. 5 shows the ratio of the surface area of the Si film at the tapered end b in the active area 4 of the TFT in the active area 4 of the entire active region 4 (hereinafter also referred to as the end area ratio) and the lifetime of the TFT. It is a graph which shows the relationship. Incidentally, in the calculation of the area ratio, the Si film 14, with using only surface not bordered on the upper surface i.e. the underlying SiO ₂ film 3 without including the surface in contact with the face or base SiO ₂ film 3 of the lower, tapered As the area of the end portion, the actual surface area was used instead of the area in the top view. In FIG. 5, the channel length was 5 μm, the channel width was 20 to 500 μm, the taper angle at the end b was 20 to 40 °, and the measurement was performed under the same stress conditions as in FIG. Further, not only a sample having a planar structure as shown in FIG. 2, but also a sample having a planar structure as shown in FIG. 6 was measured. 6 shows a part of the source region 6, the whole LDD region 5 on the source region 6 side, the whole active region 4, the whole LDD region 5 on the drain region 7 side, and the drain region 7 in FIG. A slit 17 (slit region) is formed by cutting the Si film 14 into a slit shape so as to cross a part. This slit 17 is etched so that the cross-sectional shape of the semiconductor layer formed by the slit 17 has an end that is tapered, or has a surface that forms an acute angle with the substrate 1, the underlying SiN film 2, or the underlying SiO ₂ film 3. As long as it is a region formed by

In the slit 17, the entire Si film 14 is removed by etching in the film thickness direction, so that the underlying SiO ₂ film 3 is exposed (or the substrate 1 is exposed by deeper etching. May be) In addition, when the Si film 14 is etched into an island shape so that the end portion is tapered, the slit 17 shares the same resist in the same step and covers a predetermined region of the Si film 14 as a base. It is formed by etching until the SiO ₂ film 3 is reached. Note that the portion of the Si film 14 where the slits 17 are formed is estimated to be excluded from the active region.

  In FIG. 5, the lifetime is shown as a relative value with respect to the lifetime when the channel width is 500 μm and the slit 17 is not formed, but it can be seen that the reliability improves as the end area ratio (ratio) increases. . As shown in FIG. 5, the reliability can be improved by setting the end area ratio to 2% or more, and the effect becomes remarkable when the end area ratio exceeds 10%. This can be explained as follows.

  That is, of the electron / hole pairs generated by impact ionization, the electrons are accelerated to the drain electrode 7 side. On the other hand, holes are accumulated on the body side and raise the potential of the body. As a result, the threshold voltage is lowered by the substrate bias effect, the current is increased, and impact ionization is accelerated. The concentration of holes is determined by the balance between the amount generated by impact ionization and the amount recombined in the active region 4. That is, if the amount of recombination is large, the amount of accumulated holes becomes small and the substrate bias effect can be reduced, so that impact ionization can be suppressed. Carrier recombination is likely to occur through defect levels. Since the end b of the Si layer 4 is exposed to plasma during dry etching, there are many defects, and recombination of holes can be increased by increasing this area. As a result, reliability can be improved.

  Thus, in the present embodiment, the end b is formed in the active region 4 by etching, thereby reducing the accumulation amount of holes generated by impact ionization in the body. Accordingly, variation in transistor characteristics caused by hot carriers can be reduced. Therefore, reliability can be improved.

  In the above description, the TFT having the LDD region 5 (LDD structure) is described as an example of the semiconductor device. However, the TFT is not limited to the LDD structure, and the LDD region 5 is provided as shown in FIGS. Even in a single-drain structure, a GOLD structure having a GOLD (gate-overlapped-LDD) region instead of the LDD region 5, or a structure having both the GOLD region and the LDD region 5 (not shown), Similar effects can be obtained.

  7A to 7C show a method for manufacturing a TFT having a single-drain structure. As shown in FIG. 7, the single-drain structure is advantageous in terms of cost because the process of forming the LDD region 5 is not required as compared with FIG. 8A to 8D show a method for manufacturing a GOLD structure TFT. In this structure, a low concentration impurity region called a GLOD region is implanted into the Si film 14 so as to overlap the gate electrode 9 (although low concentration P is implanted in FIG. 8B, FIG. 8C). , A region in which high concentration P is not implanted) is formed. Alternatively, both the GOLD region 18 and the LDD region 5 may be provided.

  In the above description, the case where one gate electrode 9 is formed in the channel direction has been described. However, the present invention is not limited to this, and the same effect can be obtained when a plurality of gate electrodes 9 are formed in the channel direction. it can.

  In the above description, an n-type TFT has been described as an example of a semiconductor device. However, the present invention is not limited to this, and a p-type TFT can provide the same effect.

  In the above description, the case where the polycrystallized Si film 14 is used as the semiconductor layer has been described. However, the present invention is not limited to this, and the same applies when microcrystalline Si, SiGe, ZnO, or the like is used. An effect can be obtained.

<Embodiment 2>
In the second embodiment, an example of a structure in which the slits 17 are formed will be described in detail with reference to FIGS. In FIG. 6, as described in the first embodiment, a part of the source region 6, the whole LDD region 5 on the source region 6 side, the whole active region 4, and the LDD on the drain region 7 side in the channel direction. A slit 17 is formed across the entire region 5 and a part of the drain region 7.

  FIG. 9 is a graph showing an evaluation of the reliability of the TFT shown in FIG. In FIG. 9, the horizontal axis indicates the number of slits 17 formed in the TFT, and the vertical axis indicates the lifetime of the TFT when stress is applied under a predetermined stress condition.

  As stress conditions, the gate voltage was 1 V, the drain voltage was 15 V, and the source was grounded. Then, the drain current-gate voltage characteristics of the TFT before and after the stress application were measured, and when the gate voltage was 10 V and the drain voltage was 1 V, the stress time when the drain current changed by 10% was estimated as the lifetime. In the evaluated TFT sample, the taper angle of the end b of the active region 4 was 20 °, the channel length was 5 μm, the channel width was 100 μm, and the number of slits 17 was 0 to 39.

  In FIG. 9, the lifetime is shown as a relative value with respect to the lifetime when the slit 17 is not formed, but it can be understood that the reliability is improved by forming the slit 17.

  Thus, in this embodiment, the reliability can be improved by forming the slits 17 in the active region 4 by etching.

  In the above description, referring to FIG. 6, the slit 17 has a part of the source region 6, the entire LDD region 5 on the source region 6 side, the entire active region 4, and the LDD region 5 on the drain region 7 side in the channel direction. However, the present invention is not limited to this. For example, as shown in FIG. 10, all of the source region 6, all of the LDD region 5 on the source region 6 side, all of the active region 4, all of the LDD region 5 on the drain region 7 side, and the drain region 7 in the channel direction. The same effect can be obtained even if the slits 17 are formed so as to cross all of them.

  In the structure as shown in FIG. 6, when the channel length, the length of the source region 5 in the channel direction, and the length of the drain region 6 in the channel direction are set short in order to reduce the size of the TFT, The margin between the end and the end b of the Si film 14 is reduced. The structure as shown in FIG. 10 has an advantage that it is not necessary to consider a margin.

  For the structure shown in FIG. 10, a TFT having an active region 4 with an end b of taper angle of 20 °, a channel length of 5 μm, a channel width of 100 μm, and a number of slits 17 of 19 is fabricated to evaluate reliability. As a result, it was confirmed that the same level of reliability as in the case of FIG. 6 was obtained.

  6 or 10, or the slit 17 crosses the entire active region 4 without crossing the source region 6 and the drain region 7 from the LDD region 5 on the source region 6 side to the drain region 7 side. Even if it is formed so as to reach the LDD region 5, the same effect can be obtained. However, since the length of the LDD region 5 in the channel direction is usually as small as 1 μm or less, there is a problem that such a configuration is difficult. Further, the same effect can be obtained by forming not only one slit but also a plurality of slits 17 in the channel direction. However, when the channel length is short, there is a problem that it is difficult to form a plurality of slits 17 in a line.

  Further, as shown in FIG. 11, the slit 17 may be formed so as to cross only a part of the active region 4 in the channel direction (that is, only in the active region 4).

  FIG. 12 shows the structure shown in FIG. 11, in which a TFT having an end b of the active region 4 having a taper angle of 20 °, a channel length of 5 μm, a channel width of 100 μm, and 19 slits 17 is fabricated and reliability is evaluated. It is a graph which shows the result of having performed. In the structure of FIG. 11, it can be seen that the reliability is slightly improved compared to the structure of FIG. 6 (in FIG. 12, the lifetime is shown as a relative value to the lifetime in the case of having the structure of FIG. 6). This is presumably because by forming the slit 17 in the active region 4, that is, in the channel, the end portion of the slit 17 in the channel width direction is also formed in the channel and contributes to the improvement of reliability.

<Embodiment 3>
In the third embodiment, another example of the structure in which the slits 17 are formed will be described in detail with reference to FIGS.

  FIG. 13 is a cross-sectional view showing the structure of a TFT as a semiconductor device according to this embodiment. FIG. 13 shows the slit 17 formed in FIG. 6 so as to cross a part of the active region 4, the whole LDD region 5 on the drain region 7 side, and a part of the drain region 7 in the channel direction. . That is, in FIG. 13, the center of the slit 17 is arranged to be biased toward the drain region 7 with respect to the center of the active region 4 as compared with FIG. 6.

  FIG. 14 is a graph showing an evaluation of the reliability of the TFT shown in FIG. FIG. 14 shows the lifetime of the TFT when stress is applied under a predetermined stress condition in the case of the structure shown in FIGS.

  As stress conditions, the gate voltage was 1 V, the drain voltage was 15 V, and the source was grounded. Then, the drain current-gate voltage characteristics of the TFT before and after the stress application were measured, and when the gate voltage was 10 V and the drain voltage was 1 V, the stress time when the drain current changed by 10% was estimated as the lifetime. Further, in the evaluated TFT sample, the taper angle of the end b of the active region 4 is 20 °, the channel length is 5 μm, the channel width is 100 μm, the number of slits 17 is 19, the end of the gate electrode 9 and the slit 17 are The distance was 1 μm.

  In FIG. 14, the lifetime is shown as a relative value with respect to the lifetime in the case of having the structure of FIG. 6, but by providing a slit 17 on the drain region 7 side to which a voltage is applied, on the source region 6 side to be grounded. It can be seen that even if the slit 17 is not provided, the same reliability as when the slit 17 is provided on the source region 6 side can be obtained. This can be explained as follows.

  That is, when a high voltage is applied to the drain region 7 side, electron / hole pairs are generated by impact ionization on the drain region 7 side. By forming the slit 17 that promotes the recombination of holes on the drain region 7 side where recombination is generated, the reliability improvement effect equivalent to the case where the slit 17 is provided on the source region 7 side can be obtained. it can.

  The slit 17 or the (tapered end b) of the (island-like) Si film 14 affects the static characteristics of the TFT. When a voltage is applied to the gate electrode 9, carriers are also induced in the slit 17 or the end portion b of the Si film 14 and contribute to the conduction of electrons between the source and the drain. A decrease in voltage is observed. This is explained as follows.

  At the end of the slit 17 or the Si film 14, since the polycrystalline Si film is thin, the expansion of the depletion layer in the film thickness direction is limited, and the threshold voltage is lowered. In addition, since the electric field concentration tends to occur at the end portion, the threshold voltage is lowered. As a result, the static characteristics of the TFT are obtained by adding the static characteristics of the normal TFT to the static characteristics at the end of the slit 17 or the Si film 14 having a lower threshold. As a result, the structure shown in FIG. 6 has a problem that the drain current changes irregularly with respect to the gate voltage, as shown in FIG. On the other hand, since the slit 17 is not provided in the source region 6 in the structure of FIG. 13, there is an advantage that the influence of the end of the slit 17 can be reduced as shown in FIG. In addition, there is an effect of reducing the current density on the source region 6 side. Thereby, the drain current can be stabilized.

  Thus, in this embodiment, the reliability can be improved by forming the slits 17 in the active region 4 by etching.

  In the above description, the case where the slit 17 is formed so as to reach the drain region 7 from the active region 4 is described with reference to FIG. 13, but the present invention is not limited to this. That is, even if the slit 17 is formed only in the active region 4 as shown in FIG. 11 or formed so as to cross the entire drain region 7 as shown in FIG. Can be obtained.

<Embodiment 4>
In the fourth embodiment, the relationship between the taper angle of the end b of the Si film 14 in the structure of FIG. 6 and the reliability of the TFT, that is, the lifetime will be described in detail with reference to FIGS.

  Hereinafter, a method of controlling the taper angle will be described with reference to FIG.

  As shown in FIG. 17A, when the polycrystalline island-shaped Si film 14 is formed, first, a resist 15 is applied and baked on the Si film 14, and then exposed and developed. Thus, a resist pattern is formed. By using the halftone mask 19 at the time of exposure, the exposure amount at the edge of the resist pattern can be continuously changed.

  As a result, as shown in FIG. 17B, a cross-sectional shape of the resist 15 can be obtained such that the film thickness of the resist 15 decreases as the end of the pattern is approached. This cross-sectional shape can be controlled by the design of the halftone mask 19. The Si film 14 is dry etched using the resist 15 as a mask.

  As shown in FIG. 17C, when the Si film 14 is dry-etched, the resist 15 is also slightly etched. The selection ratio of the resist 15 is generally about 10. Since the film thickness of the resist 15 is thin at the end of the pattern, the resist 15 gradually disappears from the end as etching progresses, and etching of the underlying Si film 14 occurs. As a result, an island-like Si film 14 having a tapered end can be formed. The taper angle of the end b of the Si film 14 can be changed by the cross-sectional shape of the end of the resist 15. That is, it can be controlled by the design of the halftone mask 19. The taper angle also depends on the etching selectivity.

  FIG. 18 is a graph showing an evaluation of the reliability of the TFT shown in FIG. In FIG. 18, the horizontal axis indicates the taper angle of the end of the slit 17 in the active region 4 of the TFT or the end b of the polycrystalline island-like Si film 14, and the vertical axis indicates a predetermined stress condition. The lifetime of the TFT when stressed is shown respectively.

  As stress conditions, the gate voltage was 1 V, the drain voltage was 15 V, and the source was grounded. Then, the drain current-gate voltage characteristics of the TFT 100 before and after stress application were measured, and the stress time when the drain current changed by 10% when the gate voltage was 10 V and the drain voltage was 1 V was estimated as the lifetime. In the evaluated TFT sample, the taper angle was 15 to 60 °, the channel length was 5 μm, the channel width was 100 μm, and the number of slits 17 was 19.

  In FIG. 18, the life is shown as a relative value with respect to the life when the taper angle is 20 °, but it can be seen that the reliability increases as the taper angle decreases.

  From the above, it can be seen that the reliability can be improved by reducing the taper angle of the end portion of the slit 17 in the active region 4 or the end portion b of the polycrystalline island-like Si film 14. Although the TFT of FIG. 6 provided with the slit 17 has been described this time, the present invention is not limited to this, and a similar effect can be obtained even in a TFT without the slit 17.

  The taper angle at the end of the slit 17 does not need to be the same value for all TFTs, and can be controlled as necessary.

  Further, as described above in the second embodiment, the reliability can be improved by providing the slits 17 in the active region 4, and the reliability is improved as the number of the slits 17 is increased. However, if the number of the slits 17 is increased, the TFT is increased. There is a problem that the occupied area of the increases. By reducing the taper angle, even when the number of slits 17 is small, the same reliability as when the number of slits 17 is large can be obtained, and there is an advantage that the area occupied by the TFT can be reduced. Such an effect becomes remarkable particularly in a TFT having a large channel width. Conversely, a TFT with a small channel width has already achieved high reliability, and there is no need to reduce the taper angle. Thus, by reducing the taper angle in accordance with the channel width, the area occupied by the TFT can be effectively reduced and the load of the mask design can be reduced.

  As described above, in this embodiment, by defining the taper angle of the end portion according to the channel width, it is possible to improve the reliability while reducing the mask design load.

  In the above description, the case where the taper angle is changed in the structure of FIG. 6 has been described. However, the taper angle may be changed not only in FIG. 6 but also in the structure of FIG. In the structure of FIG. 16, the taper angle at the end of the slit 17 in the active region 4 is made smaller than the taper angle at the end b of the polycrystalline island-like Si film 14 so that the end is transistor characteristics. Can be further reduced. In the structure of FIG. 6 as well, by making the taper angle of the end of the slit 17 on the drain region 7 side smaller than the taper angle of the end b of the Si film 14, the end similarly affects the transistor characteristics. Can be reduced.

<Embodiment 5>
In the first to fourth embodiments, the description has been given of the case where the TFT is provided with the slit 17 in which the entire Si film 14 is removed by etching in the film thickness direction to increase the reliability. However, not only the slit 17 from which the entire Si film 14 has been etched away in the film thickness direction, but a part of the Si film 14 in the film thickness direction will be described in detail with reference to FIGS. You may provide the recessed area | region recessed in the concave shape by being etched away. Similar to the slit 17, this recessed region has an end portion in which the cross-sectional shape of the semiconductor layer by the recessed region is tapered, or a surface that forms an acute angle with the substrate 1, the underlying SiN film 2, or the underlying SiO ₂ film 3. As long as it is a region formed by etching so as to have

  FIG. 19 is a top view showing a structure of a TFT as a semiconductor device according to the fifth embodiment. FIG. 19 is provided with a recess c in which a part of the Si film 14 is etched away in the film thickness direction instead of the slit 17 in which the entire Si film 14 is etched away in the film thickness direction in FIG. (There are recesses c in the active region recess 4 c provided in the active region 4, the LDD region recess 5 c provided in the LDD region 5, the source region recess 6 c provided in the source region 6, and the drain region 7. The drain region recess 7c formed is a generic name). FIG. 20 is a cross-sectional view taken along the line A-A ′ of FIG. 19.

  Next, a manufacturing method of the TFT shown in FIGS.

First, as in FIG. 3A according to the first embodiment, the base SiN film 2, the base SiO ₂ film 3, and the Si film 14 are sequentially formed on the substrate 1, and the Si film 14 is heat-treated to be polycrystallized. I let you.

  Next, as in FIG. 3A according to the first embodiment, a resist was formed by photolithography, and the Si film 14 was processed into an island shape by dry etching using this resist as a mask. At this time, etching may be performed so that the end of the Si film 14 is tapered by adjusting the cross-sectional shape of the resist. Then, the resist was removed by ashing and chemical treatment.

  Next, a resist having a pattern corresponding to the concave portion c is formed by photolithography, and the concave portion c is formed in the Si film 14 by dry etching the Si film 14 halfway in the film thickness direction using the resist as a mask. did. Then, the resist was removed by ashing and chemical treatment.

  That is, unlike the formation of the slit 17, the formation of the concave portion c needs to be stopped during the dry etching, so it cannot be performed in the same process as the formation of the end portion b in common with the same resist. It is necessary to separately form a resist having a pattern corresponding to the recess c.

  In addition, this time, the two photoengraving for the etching is performed by performing the exposure process twice. However, the present invention is not limited to this, or the cross-sectional shape of the resist is adjusted using the halftone mask 19. Thus, when the Si film 14 is processed into an island shape and the end portion is tapered, the recess c may be formed at the same time. As a result, the number of exposure processes can be reduced to one.

  Next, from the formation of the gate insulating film 8 to the formation of the passivation film 13 as in FIGS. 3A to 3D according to the first embodiment.

  FIG. 21 is a graph showing the evaluation of the reliability of the TFT formed by the above process. In FIG. 21, on the horizontal axis, the ratio of the surface area of the Si film of the tapered end portion b and the recess c to the surface area of the Si film of the entire active region 4 (hereinafter also referred to as an end recess area ratio) The vertical axis indicates the lifetime of the TFT when stress is applied under a predetermined stress condition.

  As stress conditions, the gate voltage was 1 V, the drain voltage was 15 V, and the source was grounded. Then, the drain current-gate voltage characteristics of the TFT before and after the stress application were measured, and when the gate voltage was 10 V and the drain voltage was 1 V, the stress time when the drain current changed by 10% was estimated as the lifetime. In the evaluated TFT sample, the taper angle of the end b of the active region 4 is 60 °, the channel length is 5 μm, the channel width is 100 to 500 μm, the recess c is 3 μm, and the number of the recesses c is 1 to 30. Met. Note that the portion of the Si film 14 where the recess c is formed is estimated by excluding it from the channel width.

  In FIG. 21, the lifetime is shown as a relative value with respect to the lifetime when the channel width is 500 μm and the recess c is not formed, but it can be seen that the reliability improves as the end recess area ratio increases. As shown in FIG. 21, the reliability can be improved by setting the end recess area ratio to 2% or more, and the effect becomes remarkable when the end recess area ratio exceeds 10%.

  Thus, in the present embodiment, the reliability can be improved by forming the recess c in the active region 4 by etching.

  In the above description, the TFT having the LDD region 5 (LDD structure) is described as an example of the semiconductor device. However, the TFT is not limited to the LDD structure, and the LDD region 5 is formed as shown in FIGS. The same effect can be obtained also in a single-drain structure that does not have, a GOLD structure having the GOLD region 18 instead of the LDD region 5, or a structure having both the GOLD region 18 and the LDD region 5.

  In the above description, the case where one gate electrode 9 is formed in the channel direction has been described. However, the present invention is not limited to this, and the same effect can be obtained when a plurality of gate electrodes 9 are formed in the channel direction. it can.

  In the above description, an n-type TFT has been described as an example of a semiconductor device. However, the present invention is not limited to this, and a p-type TFT can provide the same effect.

  In the above description, the case where the polycrystallized Si film 14 is used as the semiconductor layer has been described. However, the present invention is not limited to this, and the same applies when microcrystalline Si, SiGe, ZnO, or the like is used. An effect can be obtained.

<Embodiment 6>
In the sixth embodiment, the relationship between the number of recesses c of the Si film 14 in the structure of FIG. 19 and the reliability of the TFT, that is, the lifetime will be described in detail with reference to FIGS.

  In FIG. 22, the horizontal axis indicates the number of recesses c of the Si film 14 of the TFT, and the vertical axis indicates the lifetime of the TFT when stress is applied under a predetermined stress condition.

  As stress conditions, the gate voltage was 1 V, the drain voltage was 15 V, and the source was grounded. Then, the drain current-gate voltage characteristics of the TFT 100 before and after stress application were measured, and the stress time when the drain current changed by 10% when the gate voltage was 10 V and the drain voltage was 1 V was estimated as the lifetime. In the evaluated TFT sample, the taper angle of the end b of the active region 4 is 60 °, the channel length is 5 μm, the channel width is 100 μm, the width of the recess c is 3 μm, and the number of the recesses c is 0 to 6. It was.

  In FIG. 22, the lifetime is shown as a relative value with respect to the lifetime when the concave portion c is not formed, but it can be seen that the reliability is improved as the number of the concave portions c is increased.

  In the above description, referring to FIG. 19, the recess c has a part of the source region 6, the entire LDD region 5 on the source region 6 side, the entire active region 4, and the LDD region 5 on the drain region 7 side in the channel direction. However, the present invention is not limited to this. For example, as shown in FIG. 23, the entire source region 6, the entire LDD region 5 on the source region 6 side, the entire active region 4, the entire LDD region 5 on the drain region 7 side, and the drain region 7 in the channel direction. The same effect can be obtained even if the concave portion c is formed so as to cross the whole.

  In the structure as shown in FIG. 19, when the channel length, the length of the source region 5 in the channel direction, and the length of the drain region 6 in the channel direction are set short in order to reduce the size of the TFT, The margin between the end and the end b of the Si film 14 is reduced. The structure as shown in FIG. 23 has an advantage that it is not necessary to consider a margin.

  For the structure of FIG. 23, a TFT having an active region 4 with an end b of taper angle of 60 °, a channel length of 5 μm, a channel width of 100 μm, a recess c of 3 μm, and a number of recesses c of 4 is fabricated. As a result of evaluating the reliability, it was confirmed that the same level of reliability as in the case of FIG. 19 was obtained.

  19 and 23, or as shown in FIG. 24, the recess c crosses the entire active region 4 without crossing the source region 6 and the drain region 7, and the LDD on the source region 6 side. Similar effects can be obtained by forming the region 5 so as to reach the LDD region 5 on the drain region 7 side. However, since the length of the LDD region 5 in the channel direction is usually as small as 1 μm or less, there is a problem that such a configuration is difficult. Further, as shown in FIG. 25, the same effect can be obtained even when a plurality of recesses c are formed in the channel direction without being limited to one.

  In addition, as shown in FIG. 26, the recess c may be formed so as to cross only a part of the active region 4 in the channel direction (that is, only in the active region 4).

  Thus, in the present embodiment, the reliability can be improved by forming the recess c in the active region 4 by etching.

<Embodiment 7>
In the seventh embodiment, another example of the structure in which the recess c is formed will be described in detail with reference to FIGS. 27 and the like are obtained by forming a recess c in place of the slit 17 in FIG. 13 and the like according to the third embodiment.

  FIG. 27 is a top view showing a structure of a TFT as a semiconductor device according to the present embodiment. In FIG. 27, the recess c is formed in FIG. 19 so as to cross part of the active region 4, all of the LDD region 5 on the drain region 7 side, and part of the drain region 7 in the channel direction. . In other words, in FIG. 27, the center of the recess c is arranged to be biased toward the drain region 7 with respect to the center of the active region 4 as compared with FIG.

  FIG. 28 is a graph showing an evaluation of the reliability of the TFT shown in FIG. FIG. 28 shows the lifetime of the TFT when stress is applied under a predetermined stress condition in the case of the structure shown in FIGS.

  As stress conditions, the gate voltage was 1 V, the drain voltage was 15 V, and the source was grounded. Then, the drain current-gate voltage characteristics of the TFT before and after the stress application were measured, and when the gate voltage was 10 V and the drain voltage was 1 V, the stress time when the drain current changed by 10% was estimated as the lifetime. In the evaluated TFT sample, the taper angle of the end b of the active region 4 is 60 °, the channel length is 5 μm, the channel width is 100 μm, the width of the recess c is 3 μm, the number of the recesses c is 4, and the gate electrode 9 The distance between the end of each of the two and the recess c was 1 μm.

  In FIG. 28, the lifetime is shown as a relative value with respect to the lifetime in the case of having the structure of FIG. 19, but by providing a concave portion c on the drain region 7 side to which a voltage is applied, on the source region 6 side to be grounded. It can be seen that the same reliability as that obtained when the recess c is provided on the source region 6 side can be obtained without providing the recess c. This can be explained as follows.

  That is, when a high voltage is applied to the drain region 7 side, electron / hole pairs are generated by impact ionization on the drain region 7 side. By forming the concave portion c that promotes the recombination of holes on the drain region 7 side where recombination is generated, the reliability improvement effect equivalent to the case where the concave portion c is provided on the source region 7 side can be obtained. it can.

  Such a recess c or (tapered end b) of the (island-like) Si film 14 affects the static characteristics of the TFT. When a voltage is applied to the gate electrode 9, carriers are also induced in the recess c or the end b of the Si film 14 and contribute to the conduction of electrons between the source and the drain. A decrease in voltage is observed. This is explained as follows.

  At the end of the recess c or the Si film 14, since the polycrystalline Si film is thin, the expansion of the depletion layer in the film thickness direction is limited, and the threshold voltage is lowered. In addition, since the electric field concentration tends to occur at the end portion, the threshold voltage is lowered. As a result, the static characteristics of the TFT are obtained by adding the static characteristics of the normal TFT and the static characteristics at the end of the recess c or the Si film 14 having a lower threshold. As a result, the structure of FIG. 19 has a problem that the change of the drain current with respect to the gate voltage becomes irregular. On the other hand, the structure of FIG. 27 has an advantage that the influence of the recess c can be reduced because the recess c is not provided in the source region 6. In addition, there is an effect of reducing the current density on the source region 6 side. Thereby, the drain current can be stabilized.

  Thus, in the present embodiment, the reliability can be improved by forming the recess c in the active region 4 by etching.

  In the above description, the case where the concave portion c is formed so as to reach the drain region 7 from the active region 4 is described with reference to FIG. 27, but the present invention is not limited to this. That is, even if the recess c is formed only in the active region 4 as shown in FIG. 26 or formed so as to cross the entire drain region 7, the same effect can be obtained.

<Eighth embodiment>
In the first embodiment, the manufacturing method of one n-type TFT has been described with reference to FIG. 3, but in the eighth embodiment, a plurality of n-type and p-type are referred to with reference to FIGS. A method for manufacturing the TFT will be described.

First, referring to FIG. 29, similarly to FIG. 3A according to the first embodiment, a base SiN film 2, a base SiO ₂ film 3, and a Si film 14 are sequentially formed on a substrate 1 to form a Si film. 14 was heat-treated to be polycrystallized.

Next, a resist (not shown) was formed by photolithography, and the Si film 14 was processed into an island shape by dry etching using this resist as a mask. At this time, the etching process was performed so that the end of the Si film 14 was tapered by adjusting the cross-sectional shape of the resist. In the Si film 14 where a plurality of TFTs are formed, in the region where the n-type TFT having a channel width exceeding 20 μm is formed, the same resist is shared in the same process, A slit 17 was formed by etching a predetermined region until it reached the underlying SiO ₂ film 3. Then, the resist was removed by ashing and chemical treatment.

Next, a gate insulating film 8 made of a 100 nm SiO ₂ film was formed on the Si film 14 by plasma CVD. TEOS and O ₂ were used as raw materials for the plasma CVD method.

Next, B was implanted into the island-like Si film 14 in order to control the threshold value. As the injection conditions, the injection amount was 1E12 atom / cm ² and the acceleration energy was 60 eV. Note that this step may be omitted as necessary.

  Next, referring to FIG. 30, 200 nm of Cr was formed on the entire surface of gate insulating film 8 by sputtering. Then, a resist 15a was formed by photolithography, and Cr was wet etched using the resist 15a as a mask, thereby forming a gate electrode 9 for p-type TFT. The channel length of the p-type TFT is determined by the width of the gate electrode 9, but this time the width of the gate electrode 9 is set to 5 μm. Note that the entire region where the n-type TFT is formed is covered with Cr.

Next, referring to FIG. 31, after removing resist 15a by ashing and chemical processing, B was implanted into Si film 14 using gate electrode 9 (that is, Cr) as a mask. As the injection conditions, the injection amount was 1E15 atom / cm ² and the acceleration energy was 60 eV. As a result, the source region 6 and the drain region 7 for the p-type TFT having a relatively high impurity concentration could be formed in the Si film 14. Note that since the entire surface of the region where the n-type TFT is formed is covered with Cr, B is not implanted.

  Next, referring to FIG. 32, a resist 15b is formed by photolithography, and Cr is wet-etched using resist 15b as a mask, thereby forming gate electrode 9 for n-type TFT. The channel length of the n-type TFT is determined by the width of the gate electrode 9, but this time the width of the gate electrode 9 is set to 5 μm. Note that the entire surface of the region where the p-type TFT is formed is covered with the resist 15b.

Next, referring to FIG. 33, after removing resist 15b by ashing and chemical processing, P is implanted into Si film 14 using gate electrode 9 as a mask. As the injection conditions, the injection amount was 1E13 atom / cm ² and the acceleration energy was 80 eV. This implantation is called LDD implantation, and the impurity concentration of the LDD region 5 formed in a later process is determined by the impurity concentration at this time. At this time, P is also implanted into the source region 6 and the drain region 7 for the p-type TFT. However, since the concentration of P is lower than the implanted B concentration, there is no influence.

Next, referring to FIG. 34, resist 15c is formed by photolithography, and P is implanted into Si film 14 using resist 15c as a mask. As the injection conditions, the injection amount was 1E14 atom / cm ² and the acceleration energy was 80 eV. Thereby, in the Si film 14, the source region 6 and the drain region 7 for the n-type TFT having a relatively high impurity concentration (P is implanted) and the impurity concentration is relatively low (P is not implanted). The LDD region 5 for the n-type TFT could be formed. This time, the LDD length was set to 1 μm. Note that, in the region where the p-type TFT is formed, P is not implanted because the entire surface is covered with the resist 15c.

Next, referring to FIG. 35, after removing resist 15c by ashing and chemical processing, an interlayer insulating film made of a SiO ₂ film of 400 nm so as to cover gate insulating film 8 and gate electrode 9 by plasma CVD. 10 was formed. Then, referring to FIG. 36, a resist (not shown) is formed by photolithography, and by using this resist as a mask, interlayer insulating film 10 and gate insulating film 8 are dry-etched to form connection holes. Further, a laminated film of Cr and Al was formed, and photolithography and wet etching were performed on the laminated film, thereby forming the connection portion 16, the source electrode 11, and the drain electrode 12.

  Finally, referring to FIG. 37, passivation film 13 made of 200 nm SiN was formed by plasma CVD.

  Through the above process, a plurality of n-type and p-type TFTs could be formed on the substrate 1. In an n-type TFT, the reliability can be improved by setting the end area ratio to 2% or more.

  The end area ratio may be 2% or more for all n-type TFTs, or 2% or more only for n-type TFTs to which a high voltage is applied between the source and drain. Also good.

  For example, a TFT array substrate for a liquid crystal display is roughly divided into a pixel portion, a source driver portion, a gate driver portion, and a logic circuit portion. Among these, since the image signal is input to the pixel portion and the source driver portion, the voltage applied between the source and the drain is a low voltage. On the other hand, since the gate driver unit outputs a gate signal, the voltage applied between the source and the drain is a high voltage. Therefore, the TFT according to the present invention may be applied to the gate driver portion, and a normal TFT may be applied to the pixel portion and the source driver portion. The logic circuit is normally driven at a low voltage in consideration of power consumption and the like. However, in this case, it is necessary to prepare two types of power supplies. When one type of power supply line is used, the logic circuit is also driven at a high voltage, so that a high voltage is applied between the source and drain. In such a case, the TFT according to the present invention may be applied to the logic circuit.

  As described above, since the voltage to be handled differs depending on the circuit block, by using the TFT according to the present invention appropriately, it is possible to improve the reliability and minimize the increase in the area occupied by the TFT.

  Thus, in this embodiment, the reliability can be improved by forming the slit 17 in the active region 4 by etching in the plurality of TFTs.

  In the above description, in the method for manufacturing a plurality of n-type and p-type TFTs, a region in which an n-type TFT having a channel width exceeding 20 μm is formed in the Si film 14 on which the plurality of TFTs are formed. A case has been described in which the slit 17 in which the entire Si film 14 is etched away in the film thickness direction is formed. However, instead of the slits 17, the reliability may be improved by forming a recess c in which the Si film 14 is etched and removed halfway in the film thickness direction. The recess c can be formed by applying the process described above in the fifth embodiment to a region where an n-type TFT having a channel width exceeding 20 μm is formed. However, as described above in the fifth embodiment, the formation of the recess c is different from the formation of the slit 17 and it is necessary to stop dry etching halfway, so the same resist is formed in the same process as the formation of the end b. However, it is necessary to separately form a resist having a pattern corresponding to the recess c.

1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment. 1 is a top view illustrating a structure of a semiconductor device according to a first embodiment. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a graph showing an evaluation of the reliability of the semiconductor device according to the first embodiment. 4 is a graph showing an evaluation of the reliability of the semiconductor device according to the first embodiment. 1 is a top view illustrating a structure of a semiconductor device according to a first embodiment. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a graph showing an evaluation of the reliability of the semiconductor device according to the second embodiment. FIG. 6 is a top view showing a structure of a semiconductor device according to a second embodiment. FIG. 6 is a top view showing a structure of a semiconductor device according to a second embodiment. 10 is a graph showing an evaluation of the reliability of the semiconductor device according to the second embodiment. FIG. 6 is a top view showing a structure of a semiconductor device according to a third embodiment. 10 is a graph showing evaluation of reliability of the semiconductor device according to the third embodiment. 10 is a graph showing changes in drain current of the semiconductor device according to the third embodiment. FIG. 6 is a top view showing a structure of a semiconductor device according to a third embodiment. FIG. 10 is a cross-sectional view showing a technique for controlling a taper angle in a method for manufacturing a semiconductor device according to a fourth embodiment. 10 is a graph showing an evaluation of the reliability of a semiconductor device according to a fourth embodiment. FIG. 10 is a top view showing a structure of a semiconductor device according to a fifth embodiment. FIG. 9 is a cross-sectional view showing a structure of a semiconductor device according to a fifth embodiment. 10 is a graph showing an evaluation of the reliability of a semiconductor device according to a fifth embodiment. 10 is a graph showing an evaluation of reliability of a semiconductor device according to a sixth embodiment. FIG. 10 is a top view showing a structure of a semiconductor device according to a sixth embodiment. FIG. 10 is a top view showing a structure of a semiconductor device according to a sixth embodiment. FIG. 10 is a top view showing a structure of a semiconductor device according to a sixth embodiment. FIG. 10 is a top view showing a structure of a semiconductor device according to a sixth embodiment. FIG. 10 is a top view showing a structure of a semiconductor device according to a seventh embodiment. 10 is a graph showing evaluation of reliability of a semiconductor device according to a seventh embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the eighth embodiment.

Explanation of symbols

1 substrate, 2 base SiN film, 3 base SiO ₂ film, 4 active region, 4a active region main body, 4b active region end, 4c active region recess, 5 LDD region, 5a LDD region main body, 5b LDD region end, 5c LDD region recess, 6 source region, 6a source region body, 6b source region end, 6c source region recess, 7 drain region, 7a drain region body, 7b drain region end, 7c drain region recess, 8 gate insulating film, 9 Gate electrode, 10 interlayer insulating film, 11 source electrode, 12 drain electrode, 13 passivation film, 14 Si film, 15 resist, 16 connecting portion, 17 slit, 18 GOLD region, 19 halftone mask.

Claims (10)

A semiconductor layer having at least first and second impurity regions on both sides of the active region and the active region, respectively, and disposed on the insulating substrate or insulating film;
A gate electrode disposed in contact with the active region through a gate insulating film to apply a gate voltage to the active region;
A first electrode and a second electrode arranged to be in contact with the first and second impurity regions, respectively, in order to pass a current between the first and second impurity regions through a channel according to the gate voltage; A semiconductor device comprising:
The active region includes a predetermined region provided by etching,
The ratio of the surface area of the predetermined region to the surface area of the active region is 2% or more. The semiconductor device according to claim 1,
The predetermined region includes a semiconductor device including an end region located at an end of the active region. The semiconductor device according to claim 1 or 2, wherein
The predetermined region includes a recessed region in which the active region is recessed in a concave shape. A semiconductor device according to any one of claims 1 to 3,
The predetermined area includes a slit region in which the active region is cut into a slit shape. The semiconductor device according to claim 1,
The ratio of the surface area of the said predetermined area | region among the surface areas of the said active region is a semiconductor device which is 10% or more. The semiconductor device according to claim 3 or 4, wherein
The semiconductor device in which the concave region or the slit region is disposed only in the active region. The semiconductor device according to claim 3 or 4, wherein
The semiconductor device in which the concave region or the slit region is disposed so as to be biased to one of the first and second impurity regions with respect to the center of the active region. The semiconductor device according to claim 2,
The end region has a tapered cross-sectional shape,
The taper angle in the end region is a semiconductor device determined according to the width of the channel. A semiconductor device according to any one of claims 1 to 5,
A semiconductor device having a channel width of 20 μm or more. Forming an active region and a semiconductor layer having at least first and second impurity regions on both sides of the active region on an insulating substrate or insulating film, respectively;
Forming a gate electrode in contact with the active region through a gate insulating film to apply a gate voltage to the active region;
Forming first and second electrodes so as to be in contact with the first and second impurity regions, respectively, in order to cause a current to flow between the first and second impurity regions through a channel according to the gate voltage; A method of manufacturing a semiconductor device comprising:
A method for manufacturing a semiconductor device, comprising: forming a predetermined region in the active region by etching so that a ratio of a surface area of the predetermined region to a surface area of the active region is 2% or more.

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