JP2008153416A - Display device and manufacturing method - Google Patents

Display device and manufacturing method Download PDF

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JP2008153416A
JP2008153416A JP2006339462A JP2006339462A JP2008153416A JP 2008153416 A JP2008153416 A JP 2008153416A JP 2006339462 A JP2006339462 A JP 2006339462A JP 2006339462 A JP2006339462 A JP 2006339462A JP 2008153416 A JP2008153416 A JP 2008153416A
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channel
display device
edge portion
active layer
island
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JP2006339462A
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Japanese (ja)
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Takuo Kaito
Eiji Oue
栄司 大植
拓生 海東
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Hitachi Displays Ltd
株式会社 日立ディスプレイズ
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Priority to JP2006339462A priority Critical patent/JP2008153416A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1296Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • H01L29/458Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high quality image display by restricting failure and leakage failure of circuit operation resulting from hump in behavior of thin film transistor at a channel edge portion. <P>SOLUTION: An edge portion 302 of a polysilicon layer 301 that becomes a channel layer, becomes an amorphous region or a microcrystal region. Since silicon semiconductor film of channel edge portion 302 is in a microcrystal or an amorphous state, current is extremely small or is not caused to flow. In this way, there is almost no effect on behavior of the whole thin film transistor, even if threshold voltages Vth in channel center portion and in channel edge portion differ from each other, and thereby indication failure resulting from the hump can be avoided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device having a thin film transistor, and more particularly, to a display device using a substrate having a thin film transistor in which a channel is formed of a low-temperature polysilicon semiconductor film and a method for manufacturing the same.

For example, a thin film transistor (LTPS-TFT) formed of a low-temperature polysilicon semiconductor film has transistor characteristics with different threshold voltages Vth depending on the location where the current flows between the central portion of the channel and its edge portion. This is mainly due to the film thickness distribution of the gate insulating film. In LTPS-TFT, a gate insulating film (mainly SiO 2 -based film) is formed by CVD, so it is greatly affected by the shape of the underlying polysilicon (p-Si) layer and compared to a flat part. At the edge portion (step portion), the film thickness becomes thin due to the coverage characteristics of the film formation.

  As a result, a difference occurs in the electric field applied to the channel due to a difference in film thickness, and a difference occurs in the threshold voltage Vth. The channel edge portion has a lower threshold voltage Vth (depletion direction) than the channel center portion (flat portion). For this reason, the characteristic which becomes a hump in the gate voltage-drain current characteristic (Vg-Id characteristic) is shown. Since the channel edge portion exhibits a depletion characteristic, a defect such as a leak occurs in the product.

  In addition, there is a difference in film thickness between the channel edge part and the channel center part (flat part), and when the gate insulating film is used as a through film in an implantation process (hereinafter referred to as an implantation process), This difference in film thickness causes a difference in effective dose. Therefore, as described above, the threshold voltage Vth differs between the channel edge portion and the channel center portion (flat portion), resulting in poor characteristics.

  As a countermeasure, a countermeasure for increasing the dose amount to the channel (so as to be in the enhancement direction) can be considered. However, with such a countermeasure, the threshold voltage Vth of the channel main portion (flat portion, center region) is further enhanced, which causes characteristic defects such as insufficient on-current.

  FIG. 28 is an explanatory diagram of an LTPS-TFT (n-MOS) manufactured by the process flow of the prior art, FIG. 28 (a) is a plan view, and FIG. 28 (b) is an AA ′ of FIG. 28 (a). It is sectional drawing along a line. FIG. 29 is a diagram illustrating gate voltage-drain current (Vg-Id) characteristics measured using the LTPS-TFT illustrated in FIG.

  In FIG. 28, a gate electrode 202 is formed on a polysilicon (p-Si) layer 201 that is a channel layer via a gate insulating film 205. An aluminum (Al) wiring 203 serving as a source / drain electrode is disposed on the polysilicon layer 201 at a position sandwiching the gate electrode 202, and is connected to the polysilicon layer 201 through a contact hole 204.

  In the thin film transistor having such a structure, a voltage is applied to the aluminum wiring 203 serving as a source / drain electrode. In FIG. 28, when a positive voltage is applied to the gate electrode 202, a drain current 206 and a drain current 207 flow through the polysilicon layer 201 serving as a channel in the direction of the arrow.

  The drain current 206 flowing through the center of the channel and the drain current current 207 flowing through the channel edge have different transistor characteristics with respect to the gate electrode potential. The drain current 207 flowing through the channel edge portion flows through a portion 209 in which the film thickness of the gate insulating film 205 shown in FIG. Therefore, the transistor characteristics of the channel edge portion are stronger in the electric field applied to the channel than the channel center portion.

  From the transistor characteristics shown in FIG. 29, the current starts flowing from the low value of the gate voltage Vg in the channel edge portion and is limited to the current flowing only in the channel edge portion, so no current increase proportional to the gate voltage Vg is seen. 211 (channel edge transistor characteristics).

  On the other hand, in the center portion of the channel, a curve 210 in which current flows out when Vg = 0 V or more due to the effect of the channel implantation for controlling the threshold voltage Vth and the drain current increases in proportion to the gate voltage Vg (transistor characteristics in the center portion of the channel). The characteristics are as follows.

  Therefore, the Vg-Id characteristic of the entire transistor is a curve 212 (transistor characteristic of the entire channel) obtained by combining the curve 210 at the center of the channel and the curve 211 at the channel edge. A curve 212 which is the Vg-Id characteristic of the entire transistor shown in FIG. 29 shows a hump 213 due to the transistor characteristic of the channel edge portion, and shows the same characteristic as the depleted transistor. The current of the hump 213 causes a circuit operation failure or a leakage failure.

As countermeasures against this hump, Patent Documents 1 and 2 disclose a technique in which a high-concentration impurity is implanted into the channel edge portion and the transistor characteristics of the edge portion are intentionally shifted in the enhancement direction. Patent Document 1 and Patent Document 2 are different in that the mask at the time of implantation is diverted from the resist at the time of channel processing, or a photo process is independently added, but an impurity is injected into the channel edge portion to take countermeasures. The point is the same.
JP 2003-258262 A JP 2003-273362 A

  When the dose amount of the channel implantation is increased, the characteristics of the center portion of the channel are shifted in the same manner as the enhancement direction shift of the channel edge portion, so that a defect due to insufficient on-current occurs. As a result, in a display device using this thin film transistor, it is difficult to obtain pixel display with uniform luminance over the entire display region. Further, in the case of a thin film transistor having a CMOS structure, impurities having different polarities are implanted into n-type and p-type, respectively, so that the process becomes complicated, such as impurity separation and addition of a photo process for region selection. This is one of the factors that hinder the reduction of manufacturing costs.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of displaying a high-quality image by suppressing a circuit operation failure or leakage failure of a thin film transistor due to a hump caused by transistor characteristics of a channel edge portion, and a manufacturing method thereof. is there.

  In order to achieve the above object, in the display device of the present invention, a thin film transistor having an active layer having different crystallinity or different damage at a channel edge portion and a channel central portion is formed on a thin film transistor formed over an insulating substrate. Use. In the method for manufacturing a display device of the present invention, after processing (etching) the channel layer using a resist as a mask, the resist is used to perform impurity implantation such as argon (Ar) on the channel edge portion of the active layer. By performing Ar implantation or the like, the crystal is intentionally damaged, and the crystallinity of the channel edge portion is deteriorated. Through the above process, polysilicon (p-Si) is transformed into a further microcrystalline silicon film, typically amorphous silicon (a-Si).

  By deteriorating the crystallinity of the channel edge portion or by making it amorphous as compared with the center portion of the channel, the carrier mobility is lowered and the current hardly flows. As a result, even when the threshold voltage Vth is different between the channel center portion and the channel edge portion, no current flows through the channel edge portion, so that the occurrence of depletion and leakage current is suppressed.

  Since the resist mask used for processing the active layer for the channel is diverted to the implantation mask, it can be dealt with by adding an implantation process for deteriorating crystallinity without adding a photolithography process. Further, since the threshold voltage Vth of the channel edge portion is not controlled by impurity implantation, there is no increase in the implantation process and the photo process even when applied to the CMOS configuration, and only the addition of the implantation process that deteriorates the crystallinity. Correspondence becomes possible.

  Since no current flows in the channel edge portion, the implantation amount for controlling the threshold voltage Vth can be determined by paying attention only to the characteristics of the channel center portion. Therefore, it is not necessary to match the dose amount of the channel implantation to the channel edge portion where the threshold voltage Vth is depleted unlike the conventional case, and the dose amount can be reduced. Furthermore, since the threshold voltage Vth at the center of the channel can be optimized, it is possible to prevent an on-current drop failure.

  The present invention can be applied to liquid crystal display devices, organic EL display devices, and other display devices using various display principles.

  Hereinafter, the display device of the present invention will be described with reference to examples of manufacturing processes. This manufacturing process also reveals the structure.

  FIGS. 1 to 25 are diagrams for sequentially explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. In FIG. 1 to FIG. A plan view (b) is shown. The cross-sectional view corresponds to a portion along the line AA ′ in the plan view.

FIG. 1: SiN (silicon nitride) 102, SiO 2 (silicon oxide) 103, and amorphous silicon (a-Si) 104 are formed on a glass substrate 101 by plasma CVD. Hydrogen in the amorphous silicon (a-Si) 104 is desorbed by heat treatment. SiN (silicon nitride) 102 and SiO 2 (silicon oxide) 103 are base films.

  FIG. 2: Amorphous silicon (a-Si) 104 is irradiated with an excimer laser 105 to be polycrystallized. The average grain size is around 2 μm (1 to 3 μm).

  FIG. 3: A polysilicon (p-Si) layer 106 is formed.

  FIG. 4: A photo process is performed on the polysilicon (p-Si) layer 106, and a photoresist 107 is disposed.

  FIG. 5: The polysilicon (p-Si) layer 106 is processed into an island shape by dry etching.

  FIG. 6: After dry etching, an ashing process 108 or the like is performed to reduce (retract) the photoresist 107 to expose the edge portion of the polysilicon layer.

  FIG. 7: After the resist recedes, the exposed edge 110 is damaged by using an argon implanter 109. With this damage, the polysilicon is microcrystallized or amorphized. The average particle diameter when microcrystallized is ˜several 100 nm.

  FIG. 8: The pattern of the processed polysilicon layer after removing the photoresist remains the polysilicon (p-Si) layer 106 in the center portion, and the edge portion 110 has a microcrystalline region or an amorphous region due to implantation damage. It is formed. The width of the microcrystalline region or the non-crystalline region is about 1 μm inward from the edge of the island pattern.

FIG. 9: A SiO 2 film 111 is formed as a gate insulating film on the island-shaped silicon semiconductor film (polysilicon (p-Si) layer 106 and edge portion 110) subjected to the island-shaped processing by a plasma CVD method.

FIG. 10: Channel implantation (B + ) 112 for controlling the threshold voltage Vth is performed.

  FIG. 11: A gate metal layer 113 to be a gate wiring and a capacitor line is formed.

  FIG. 12: A photoresist 114 is formed by a photo process.

  FIG. 13: The gate metal layer 113 is processed by etching, and a processed gate metal layer 115 is formed. At this time, the dimension of the processed gate metal layer 115 is made smaller than that of the photoresist 114 by performing side etching.

FIG. 14: Impurities (P + ) 116 for forming source / drain regions are formed.

  FIG. 15: A source / drain electrode 117 is formed.

FIG. 16: In order to fabricate an LDD (Lightly Doped Drain) region, low concentration P + 118 is entirely implanted using the processed gate metal layer 115 as a mask.

  FIG. 17: The LDD portion 119 is formed.

  FIG. 18: Interlayer insulating film 120 is formed. Annealing is performed to activate the implanted impurities.

  FIG. 19: The contact hole 121 is processed by a photo-etching process.

  FIG. 20: A source / drain wiring (barrier layer 122, Al layer 123, cap layer 124) is formed.

  FIG. 21: Source / drain wiring (barrier layer 122, Al layer 123, cap layer 124) is processed by a photo-etching process.

  FIG. 22: Passivation film 125 is formed by plasma CVD. A hydrogen termination process is performed to complete the thin film transistor.

  FIG. 23: A planarizing film 126 is applied to improve display characteristics, and a contact hole 127 is formed using a photo-etching process.

  FIG. 24: The passivation film 125 in the region of the contact hole 127 by the planarization film is dry-etched to form a contact hole 128 with ITO and an opening for PAD.

  FIG. 25: ITO 129 to be a pixel electrode is formed and processed.

  26A and 26B are explanatory diagrams of an LTPS-TFT (n-MOS) manufactured by the process flow of the present invention. FIG. 26A is a plan view and FIG. 26B is an AA ′ line in FIG. It is sectional drawing along a line. FIG. 27 is a diagram showing gate voltage-drain current (Vg-Id) characteristics measured using the LTPS-TFT shown in FIG.

  In FIG. 26, a gate electrode 303 is formed on a polysilicon (p-Si) layer 301 that is a channel layer via a gate insulating film 306. An aluminum (Al) wiring 304 serving as a source / drain electrode is disposed above the polysilicon (p-Si) layer 301 and sandwiching the gate electrode 303, and polysilicon (p-Si) is formed in the contact hole 305. Connected to layer 301.

  The edge portion 302 of the polysilicon (p-Si) layer 301 serving as a channel layer becomes the above-described amorphous region or microcrystalline region. Since the thickness 310 of the gate insulating film 306 in the edge portion 302 is smaller than the thickness 319 of the gate insulating film 306 in the center of the channel, the threshold voltage Vth is low.

  The drain current 308 flowing through the edge portion 302 is lower in gate voltage (Vth) from which current flows because the gate insulating film 306 is thinner than the drain current 307 flowing through the center of the channel.

  However, since the silicon semiconductor film in the edge portion 302 is in a microcrystalline or non-crystalline state, the drain current 308 flowing in the edge portion 302 is extremely small (or does not flow) compared to the drain current 307 flowing in the center portion of the channel. .

  In FIG. 27, a curve 311 represents the Vg-Id characteristic at the center of the channel, and a curve 312 represents the Vg-Id characteristic at the channel edge. Although the drain current starts flowing out at the channel edge portion at a lower gate voltage, the amount of flowing current is small. Therefore, even if the threshold voltage Vth differs between the channel center and the channel edge, there is almost no effect on the curve 313 that is the overall characteristics of the transistor, and there is no hump as shown in FIG. .

  As a result, the above-described problem due to depletion does not occur. Further, since the amount of channel implantation for controlling the threshold voltage Vth can be adjusted by paying attention only to the characteristics at the center of the channel, current shortage occurs due to the threshold voltage Vth shift of the thin film transistor at the center of the channel. do not do. Therefore, it is possible to provide a display device and a method for manufacturing the same that can suppress high-quality image display by suppressing circuit operation failure and leakage failure due to hump caused by transistor characteristics of the channel edge portion.

It is a figure explaining the flow of the manufacturing process of the n-MOS top gate TFT by this invention. It is a figure following FIG. 1 explaining the flow of the manufacturing process of the n-MOS top gate TFT by this invention. FIG. 3 is a diagram continued from FIG. 2 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 4 is a diagram subsequent to FIG. 3 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 5 is a diagram continued from FIG. 4 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 6 is a diagram continued from FIG. 5 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 7 is a diagram following FIG. 6 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 8 is a diagram continued from FIG. 7 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 9 is a diagram continued from FIG. 8 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 10 is a diagram subsequent to FIG. 9 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 11 is a diagram continued from FIG. 10 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 12 is a diagram continued from FIG. 11 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 13 is a diagram continued from FIG. 12 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. It is a figure following FIG. 13 explaining the flow of the manufacturing process of the n-MOS top gate TFT by this invention. FIG. 15 is a diagram continued from FIG. 14 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 16 is a diagram continued from FIG. 15 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 17 is a diagram continued from FIG. 16 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 18 is a diagram continued from FIG. 17 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 19 is a diagram continued from FIG. 18 for describing the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 20 is a diagram subsequent to FIG. 19 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 21 is a diagram continued from FIG. 20 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 22 is a diagram continued from FIG. 21 for describing the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 23 is a diagram continued from FIG. 22 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 24 is a diagram continued from FIG. 23 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. FIG. 25 is a diagram continued from FIG. 24 for explaining the flow of the manufacturing process of the n-MOS top gate TFT according to the present invention. It is explanatory drawing of LTPS-TFT (n-MOS) produced with the process flow of this invention. It is a figure which shows the gate voltage-drain current (Vg-Id) characteristic measured using LTPS-TFT shown in FIG. It is explanatory drawing of LTPS-TFT (n-MOS) produced with the process flow of the prior art. It is a figure which shows the gate voltage-drain current (Vg-Id) characteristic measured using LTPS-TFT shown in FIG.

Explanation of symbols

101 ... glass substrate, 104 ... amorphous silicon, 106 ... polysilicon layer, 107 ... photoresist, 111 ... SiO 2 film, 113 ... gate metal layer, 117 ... Source Drain electrode, 120 ... Interlayer insulating film, 122 ... Barrier layer, 123 ... Al layer, 124 ... Cap layer, 125 ... Passivation film, 126 ... Planarization film, 129 ... -ITO.

Claims (10)

  1. A display device having a thin film transistor formed on an insulating substrate,
    In the thin film transistor, an active layer forming a channel is a silicon semiconductor film,
    The channel has a channel center part and a channel edge part which is an edge part in the width direction of the channel,
    A display device, wherein the crystallinity of the silicon semiconductor layer is different between the channel center portion and the channel edge portion.
  2. In claim 1,
    The display device characterized in that the carrier mobility differs by one digit or more between the channel center portion and the channel edge portion.
  3. In claim 1 or claim 2,
    A display device, wherein the channel central portion is a polycrystalline silicon film and the channel edge portion is a microcrystalline silicon film.
  4. In claim 3,
    The average crystal grain size of the polycrystalline silicon film is about 1 μm to 3 μm, and the average grain size of the microcrystalline silicon film is about several tens nm to several hundreds nm.
  5. In claim 1 or claim 2,
    The display device according to claim 1, wherein the channel central portion is a polycrystalline silicon film and the channel edge portion is an amorphous silicon film.
  6. In claim 1 or claim 2,
    A display device, wherein the channel central portion and the channel edge portion have different crystal defects.
  7. A method of manufacturing a display device having a thin film transistor formed on an insulating substrate,
    Forming a polycrystalline silicon film on the insulating substrate;
    Applying a photosensitive resist film for processing the island-shaped active layer forming the channel of the thin film transistor, exposing and developing to form a resist film having a pattern of the island-shaped active layer;
    Etching the polycrystalline silicon film using the resist film of the island-shaped active layer pattern as a mask, and processing the island-shaped active layer;
    Ashing the resist film used for processing the island-shaped active layer, reducing a side edge thereof, retreating from the side edge, and exposing the island-shaped active layer of the channel edge portion;
    Performing impurity implantation on the exposed portion of the island active layer;
    A method for manufacturing a display device, comprising:
  8. In claim 7,
    The method for manufacturing a display device, wherein the impurity is argon.
  9. In claim 7 or 8,
    A method of manufacturing a display device, wherein the exposed portion of the island-like active layer is microcrystallized by the impurity implantation.
  10. In claim 7 or 8,
    A method of manufacturing a display device, wherein the exposed portion of the island-like active layer is amorphized by the impurity implantation.
JP2006339462A 2006-12-18 2006-12-18 Display device and manufacturing method Pending JP2008153416A (en)

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GB2479150B (en) 2010-03-30 2013-05-15 Pragmatic Printing Ltd Transistor and its method of manufacture
US8859330B2 (en) * 2011-03-23 2014-10-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR20160055563A (en) * 2014-11-10 2016-05-18 삼성디스플레이 주식회사 Method for manufacturing thin film transistor, thin film transistor, and display apparatus comprising the same
CN105428243B (en) * 2016-01-11 2017-10-24 京东方科技集团股份有限公司 A kind of thin film transistor (TFT) and preparation method, array base palte and display device

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