WO2020115604A1 - Semiconductor device, and semiconductor device fabrication method - Google Patents

Semiconductor device, and semiconductor device fabrication method Download PDF

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Publication number
WO2020115604A1
WO2020115604A1 PCT/IB2019/060104 IB2019060104W WO2020115604A1 WO 2020115604 A1 WO2020115604 A1 WO 2020115604A1 IB 2019060104 W IB2019060104 W IB 2019060104W WO 2020115604 A1 WO2020115604 A1 WO 2020115604A1
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Prior art keywords
insulator
oxide
conductor
transistor
film
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PCT/IB2019/060104
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French (fr)
Japanese (ja)
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山崎舜平
菅谷健太郎
方堂涼太
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株式会社半導体エネルギー研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one mode of the semiconductor device.
  • a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like can be said to have a semiconductor device. ..
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • the CPU is an assembly of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes which are connection terminals.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of various electronic device components.
  • transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • a transistor using an oxide semiconductor has an extremely small leak current in a non-conducting state.
  • a low-power-consumption CPU or the like is disclosed in which a transistor including an oxide semiconductor has a low leak current (see Patent Document 1).
  • a memory device or the like which can hold stored data for a long time by applying the characteristic of a transistor including an oxide semiconductor, which has low leakage current, is disclosed (see Patent Document 2).
  • One object of one embodiment of the present invention is to provide a semiconductor device having favorable electric characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device having normally-off electrical characteristics. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device with high productivity.
  • One object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time.
  • One object of one embodiment of the present invention is to provide a semiconductor device in which data writing speed is high.
  • One object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility.
  • One object of one embodiment of the present invention is to provide a semiconductor device in which power consumption can be suppressed.
  • One object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention includes a first oxide, a first conductor and a second conductor over the first oxide, a first insulator over the first conductor, and a second insulator over the second conductor.
  • the carrier concentration of the region in contact with the insulator is higher than the carrier concentration of the region of the first oxide in contact with the second oxide, and the carrier concentration of the region of the first oxide in contact with the fifth insulator is:
  • the semiconductor device has a higher carrier concentration than the region of the first oxide which is in contact with the second oxide.
  • the fourth insulator is less likely to transmit oxygen than the third insulator, the fourth insulator is more likely to transmit oxygen than the first insulator, and the fifth insulator is It is preferable that oxygen is less likely to permeate oxygen than the third insulator, and that the fifth insulator is more likely to permeate oxygen than the second insulator.
  • the film density of the fourth insulator is preferably lower than that of the first insulator, and the film density of the fifth insulator is preferably lower than that of the second insulator.
  • the fourth insulator and the fifth insulator include any one of aluminum, magnesium, and tantalum.
  • the first insulator, the second insulator, the fourth insulator, and the fifth insulator are aluminum oxide.
  • Another embodiment of the present invention is that a first oxide film, a first conductive film, a first insulating film, and a second conductive film are sequentially formed over a substrate to form a first oxide film.
  • the first conductive film, the first insulating film, and the second conductive film are processed to form a first oxide, a first conductor layer, a first insulator layer, and a second conductor.
  • the film is anisotropically etched to form a first insulator in contact with at least a side surface of the first oxide and a side surface of the first conductor layer, and removing the second conductor layer, A first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, and a first insulating layer.
  • the first conductor, the second conductor, the second insulator, the third insulator, and the fourth insulator By forming the second insulating film, the fifth insulating film, the sixth insulating film, the second oxide film, the fourth insulating film, and the third conductive film in that order, and performing a planarization treatment.
  • the second oxide film, the fourth insulating film, and the third conductive film are removed until a part of the sixth insulator is exposed, and the second oxide, the seventh insulator, and the third conductor are removed. Is formed, and a fifth insulating film is formed over the sixth insulator, the second oxide, the seventh insulator, and the third conductor, which is a method for manufacturing a semiconductor device.
  • a semiconductor device having favorable electric characteristics can be provided.
  • a semiconductor device having normally-off electrical characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a highly productive semiconductor device can be provided.
  • a semiconductor device capable of holding data for a long period can be provided.
  • a semiconductor device in which data writing speed is high can be provided.
  • a semiconductor device with high design flexibility can be provided.
  • a semiconductor device which can reduce power consumption can be provided.
  • a novel semiconductor device can be provided.
  • FIG. 1A is a top view of a semiconductor device according to one embodiment of the present invention.
  • 1B to 1D are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 3A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 3B to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 4B to 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 18A is a top view of a semiconductor device according to one embodiment of the present invention.
  • 18B to 18D are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 19A is a top view of a semiconductor device according to one embodiment of the present invention.
  • 19B to 19D are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 20A and 20B are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • 21 is a cross-sectional view illustrating the structure of the memory device according to one embodiment of the present invention.
  • FIG. 22 is a cross-sectional view illustrating the structure of the memory device according to one embodiment of the present invention.
  • FIG. 23A is a block diagram illustrating a structural example of a storage device according to one embodiment of the present invention.
  • FIG. 23B is a diagram showing a configuration of a storage device according to one embodiment of the present invention.
  • 24A to 24H are circuit diagrams each illustrating a structural example of a memory device according to one embodiment of the present invention.
  • FIG. 25A is a block diagram of a semiconductor device according to one embodiment of the present invention.
  • FIG. 25B is a schematic diagram of a semiconductor device according to one embodiment of the present invention.
  • 26A to 26E are schematic views of a memory device according to one embodiment of the present invention.
  • 27A to 27F are diagrams illustrating electronic devices according to one embodiment of the present invention.
  • FIG. 28A is a STEM image of a sample according to an example of the present invention.
  • FIG. 28B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
  • FIG. 29A is a STEM image of a sample according to an example of the present invention.
  • FIG. 29B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
  • FIG. 30A is a STEM image of a sample according to an example of the present invention.
  • FIG. 30B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
  • FIG. 31A is a STEM image of a sample according to an example of the present invention.
  • FIG. 31B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
  • the size, the layer thickness, or the region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.
  • a layer, a resist mask, or the like may be unintentionally reduced due to a process such as etching, but may not be reflected in the drawings for easy understanding.
  • the same reference numerals are commonly used in different drawings for the same portions or portions having similar functions, and repeated description thereof may be omitted.
  • the hatch pattern may be the same and may not be given a reference numeral.
  • top view also referred to as “plan view”
  • perspective view some of the constituent elements may be omitted for easier understanding of the invention.
  • description of some hidden lines may be omitted.
  • the ordinal numbers given as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, “first” can be replaced with “second” or “third” as appropriate.
  • the ordinal numbers in this specification and the like and the ordinal numbers used to specify one embodiment of the present invention may not match.
  • connection relation for example, the connection relation shown in the drawing or the text, and other than the connection relation shown in the drawing or the text is also disclosed in the drawing or the text.
  • X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • the functions of the source and drain may be switched when adopting transistors of different polarities or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be interchanged in some cases.
  • a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) and a top view of the transistor depending on the structure of the transistor.
  • the indicated channel width (hereinafter, also referred to as “apparent channel width”) may be different.
  • the effective channel width becomes larger than the apparent channel width, and the effect thereof may not be negligible.
  • the proportion of a channel formation region formed in the side surface of the semiconductor might be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width when simply described as channel width, it may indicate an apparent channel width.
  • channel width may refer to an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the impurities of a semiconductor refer to, for example, components other than the main constituents of the semiconductor.
  • an element whose concentration is less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example, the DOS (Density of States) of the semiconductor may be increased and the crystallinity may be decreased.
  • the semiconductor is an oxide semiconductor
  • examples of impurities that change the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
  • the impurities that change the characteristics of the semiconductor include, for example, a Group 1 element other than oxygen and hydrogen, a Group 2 element, a Group 13 element, and a Group 15 element.
  • silicon oxynitride has a higher oxygen content than nitrogen as its composition. Further, silicon oxynitride has a composition containing more nitrogen than oxygen.
  • the term “insulator” can be restated as an insulating film or an insulating layer.
  • the term “conductor” can be referred to as a conductive film or a conductive layer.
  • the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 degrees to 10 degrees. Therefore, a case of -5 degrees or more and 5 degrees or less is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • a barrier film refers to a film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, and when the barrier film has conductivity, it is referred to as a conductive barrier film. May be called.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the term “OS FET” or “OS transistor” is used, it can be referred to as a transistor including an oxide or an oxide semiconductor.
  • normally-off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the current per channel width of 1 ⁇ m flowing in the transistor is 1 ⁇ 10 ⁇ 20 at room temperature. A or less, 1 ⁇ 10 ⁇ 18 A or less at 85° C., or 1 ⁇ 10 ⁇ 16 A or less at 125° C.
  • Example of configuration of semiconductor device> 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention and a periphery of the transistor 200.
  • FIG. 1A is a top view of a semiconductor device having a transistor 200.
  • 1B and 1C are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of a portion indicated by dashed-dotted line A1-A2 in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel length direction.
  • 1C is a cross-sectional view of a portion indicated by dashed-dotted line A3-A4 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 1D is a cross-sectional view of a portion indicated by a chain line of A5-A6 in FIG. 1A. In the top view of FIG. 1A, some elements are omitted for the sake of clarity.
  • a semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, and an insulator 280 over the transistor 200.
  • the insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, and the insulator 274 function as an interlayer film.
  • a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and serves as a plug is included.
  • the insulator 241 (the insulator 241a and the insulator 241b) is provided in contact with the side surface of the conductor 240 which functions as a plug.
  • a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and serves as a wiring is provided over the insulator 274 and the conductor 240.
  • an insulator 241a is provided in contact with the inner walls of the openings of the insulator 272, the insulator 280, the insulator 282, the insulator 283, and the insulator 274, and the first conductor of the conductor 240a is provided in contact with the side surface thereof. Is provided, and the second conductor of the conductor 240a is further provided inside.
  • an insulator 241b is provided in contact with the inner walls of the openings of the insulator 272, the insulator 280, the insulator 282, the insulator 283, and the insulator 274, and the first conductor of the conductor 240b is provided in contact with the side surface thereof.
  • a second conductor of the conductor 240b is further provided inside.
  • the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 274 can be approximately the same.
  • the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this.
  • the conductor 240 may have a single-layer structure or a stacked structure including three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
  • the transistor 200 described in this embodiment be formed over an insulator 212 and have an upper surface and a side surface covered with the insulator 283. Further, in a top view, the insulator 283 and the insulator 212 are in contact with each other outside the transistor 200, and the transistor 200 is preferably sealed with the insulator 283 and the insulator 212.
  • the transistor 200 includes an insulator 216 over an insulator 214, a conductor 205 (a conductor 205 a, and a conductor 205 b) which is arranged so as to be embedded in the insulator 216 and an insulator 216.
  • An insulator 222 over the conductor 205, an insulator 224 over the insulator 222, an oxide 230a over the insulator 224, an oxide 230b over the oxide 230a, and an oxide over the oxide 230b.
  • the conductor 242a on the oxide 243a the conductor 242b on the oxide 243b
  • the insulator 272a on the conductor 242a the insulator 272b on the conductor 242b
  • the insulator 272b on the conductor 242b the conductor 242b
  • An insulator 273a which is located above and is in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243a, and the side surface of the conductor 242a;
  • a conductor 260 (a conductor 260a and a conductor 260b) which is located over the body 250 and overlaps with the oxide 230c.
  • the oxide 230c is in contact with the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, and the side surface of the conductor 242b, respectively.
  • the conductor 260 has a conductor 260a and a conductor 260b, and the conductor 260a is arranged so as to cover the bottom surface and the side surface of the conductor 260b.
  • the upper surface of the conductor 260 is arranged so as to substantially coincide with the upper surfaces of the insulator 250 and the oxide 230c.
  • the insulator 282 is in contact with the top surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280, respectively.
  • the oxide 243a and the oxide 243b may be collectively referred to as the oxide 243.
  • the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242.
  • the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242.
  • the insulator 272a and the insulator 272b may be collectively referred to as an insulator 272.
  • the insulator 273a and the insulator 273b may be collectively referred to as an insulator 273.
  • the conductor 260 functions as a gate of the transistor, and the conductors 242a and 242b function as a source electrode and a drain electrode, respectively.
  • the transistor 200 is formed in a self-aligned manner so that the conductor 260 functioning as a gate fills an opening formed by the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without alignment.
  • At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 is hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, or the like) or a diffusion of water molecules. It is preferable to have a function of suppressing In particular, the insulator 212 and the insulator 283 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules) or water molecules.
  • At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 suppresses diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules). It is preferable to have a function.
  • at least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 has lower permeability of one or both of oxygen and hydrogen than the insulator 224. preferable.
  • At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 preferably has lower permeability of one or both of oxygen and hydrogen than the insulator 250. At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 preferably has lower permeability of one or both of oxygen and hydrogen than the insulator 280.
  • the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or oxynitride is used. Silicon or the like can be used. In particular, as the insulator 212 and the insulator 283, silicon nitride or silicon nitride oxide, which has a higher hydrogen barrier property, is preferably used.
  • the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 are patterned.
  • the insulator 283 has a structure that covers them. That is, the insulator 283 includes a top surface of the insulator 282, a side surface of the insulator 282, a side surface of the insulator 280, a side surface of the insulator 224, a side surface of the insulator 222, a side surface of the insulator 216, a side surface of the insulator 214, and It contacts the upper surface of the insulator 212, respectively.
  • the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 including the oxide 230 and the like are isolated from the outside by the insulator 283 and the insulator 212. ..
  • the oxide 230 includes an oxide 230a over the insulator 224, an oxide 230b over the oxide 230a, and an oxide 230c which is disposed over the oxide 230b and at least part of which is in contact with the top surface of the oxide 230b. It is preferable to have Here, the side surface of the oxide 230c is preferably provided in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272a, the insulator 272b, and the insulator 280.
  • the transistor 200 has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in the channel formation region and the vicinity thereof, the present invention is not limited to this. ..
  • a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided.
  • the oxide 230c may have a two-layer structure and a four-layer stacked structure may be provided.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is used for the oxide 230 including the channel formation region (the oxide 230a, the oxide 230b, and the oxide 230c).
  • an oxide semiconductor an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used.
  • an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium).
  • the element M is preferably aluminum, gallium, yttrium, or tin.
  • an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used as the oxide 230.
  • the oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b.
  • the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a into the oxide 230b can be suppressed.
  • the oxide 230c over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.
  • the oxide 230 preferably has a laminated structure of a plurality of oxide layers in which the atomic ratio of each metal atom is different.
  • the atomic ratio of the element M in the constituent elements is higher than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230c a metal oxide which can be used for the oxide 230a or the oxide 230b can be used.
  • the above metal oxide may be used.
  • gallium oxide and In:Ga:Zn 4:2:3 [atomic ratio].
  • the oxide 230b preferably has crystallinity.
  • a CAAC-OS c-axis aligned crystalline oxide semiconductor
  • An oxide having crystallinity such as CAAC-OS has few impurities and defects (such as oxygen vacancies), has high crystallinity, and has a dense structure. Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even if heat treatment is performed, oxygen extraction from the oxide 230b can be reduced, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in a manufacturing process.
  • the energy at the bottom of the conduction band of the oxides 230a and 230c be higher than the energy at the bottom of the conduction band of the oxide 230b.
  • the electron affinity of the oxide 230a and the oxide 230c be smaller than the electron affinity of the oxide 230b.
  • the electron affinity or the energy level Ec at the bottom of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg.
  • the ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) device.
  • the energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.
  • the energy level at the bottom of the conduction band changes gently at the junction of the oxide 230a, the oxide 230b, and the oxide 230c.
  • the energy level at the bottom of the conduction band in the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously joined.
  • the main carrier path is the oxide 230b.
  • the oxide 230a and the oxide 230c having the above structures, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can have high on-state current and high frequency characteristics.
  • an oxide semiconductor having a low carrier concentration for the oxide 230 eg, the oxide 230b.
  • the concentration of impurities in the oxide semiconductor may be lowered and the density of defect states may be lowered.
  • low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
  • hydrogen contained in an oxide semiconductor reacts with oxygen which is bonded to a metal atom to be water, which might cause oxygen deficiency (also referred to as V 2 O :oxygenvacancy) in the oxide semiconductor.
  • a defect in which hydrogen is contained in an oxygen vacancy (hereinafter, also referred to as V OH ) may function as a donor and an electron which is a carrier may be generated.
  • part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor which contains a large amount of hydrogen is likely to have normally-on characteristics. Further, hydrogen in an oxide semiconductor is likely to move due to stress such as heat and an electric field; therefore, when a large amount of hydrogen is contained in the oxide semiconductor, reliability of the transistor might be deteriorated.
  • V OH can function as a donor of the oxide semiconductor.
  • the oxide semiconductor may be evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, a carrier concentration which is assumed to be a state where no electric field is applied may be used as a parameter of the oxide semiconductor, instead of the donor concentration. That is, the “carrier concentration” described in this specification and the like can be called the “donor concentration” in some cases.
  • the V O H to obtain a sufficiently reduced oxide semiconductor the moisture in the oxide semiconductor, to remove impurities such as hydrogen (dehydration, may be described as dehydrogenation.)
  • it is important to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygenation treatment).
  • the V O H oxide semiconductor impurity is sufficiently reduced such by using a channel formation region of the transistor, it is possible to have stable electrical characteristics.
  • the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or lower, and 1 ⁇ 10 17 cm ⁇ 3. Is less than 1 ⁇ 10 16 cm ⁇ 3 , more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , further preferably less than 1 ⁇ 10 12 cm ⁇ 3. More preferable. Note that there is no particular limitation on the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region, but it can be set to, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • an interlayer insulating film (insulator 216, insulator 274, insulator 280, and the like) and a gate insulating film (insulator 224, using a source gas which does not contain hydrogen atoms or has a low hydrogen atom content).
  • insulator 216, insulator 274, insulator 280, and the like an interlayer insulating film
  • insulator 224 using a source gas which does not contain hydrogen atoms or has a low hydrogen atom content
  • a gas containing molecules containing silicon atoms is mainly used as a film forming gas.
  • the number of hydrogen atoms contained in the molecule containing the silicon atom be small, and it is more preferable that the molecule containing the silicon atom contain no hydrogen atom.
  • the film-forming gas other than the gas having a molecule containing a silicon atom preferably contains a small number of hydrogen atoms, and more preferably does not contain a hydrogen atom.
  • a molecule containing a silicon atom for example, tetraisocyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate silane, octaisocyanate silane, etc. can be used.
  • a molecule in which the same type of functional group is bonded to a silicon atom is illustrated, but the present embodiment is not limited to this. You may make it the structure which a different kind of functional group couple
  • halogen Cl, Br, I, or F
  • the functional group R may be used as the functional group R.
  • halogen Cl, Br, I, or F
  • 1 ⁇ x ⁇ 2 and 1 ⁇ y ⁇ 6 As such a molecule containing a silicon atom, for example, tetrachlorosilane (SiCl 4 ) or hexachlorodisilane (Si 2 Cl 6 ) can be used.
  • halogen other than chlorine such as bromine, iodine or fluorine
  • a structure in which different kinds of halogens are bonded to silicon atoms may be adopted.
  • the insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 are formed by chemical vapor deposition (CVD) using a gas having a molecule containing a silicon atom as described above. Deposition) method. Since the CVD method has a relatively high film formation rate, it is suitable for forming the insulator 280, the insulator 274, and the insulator 216 which have large film thicknesses.
  • CVD chemical vapor deposition
  • CVD plasma CVD
  • TCVD Thermal CVD
  • APCVD Atmospheric Pressure CVD
  • LPCVD Low
  • an oxidizer is preferably used.
  • a gas containing no hydrogen atom such as O 2 , O 3 , NO, NO 2 , N 2 O, N 2 O 3 , N 2 O 4 , N 2 O 5 , CO, or CO 2 is used.
  • a gas containing no hydrogen atom such as O 2 , O 3 , NO, NO 2 , N 2 O, N 2 O 3 , N 2 O 4 , N 2 O 5 , CO, or CO 2 is used.
  • a gas containing no hydrogen atom such as O 2 , O 3 , NO, NO 2 , N 2 O, N 2 O 3 , N 2 O 4 , N 2 O 5 , CO, or CO 2 is used.
  • a gas containing no hydrogen atom such as O 2 , O 3 , NO, NO 2 , N 2 O, N 2 O 3 , N 2 O 4 , N 2 O 5 , CO, or CO 2 is used.
  • CO or CO 2
  • the insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 may be formed by an ALD (Atomic Layer Deposition) method.
  • ALD Atomic Layer Deposition
  • a first source gas for reaction hereinafter referred to as a precursor. It can also be referred to as a precursor or a metal precursor
  • a second source gas hereinafter referred to as a reactant.
  • Reactant, non-metal Can also be referred to as a precursor.
  • the ALD method allows atoms to be deposited one by one by utilizing the self-controllability, which is the property of atoms, by forming films while switching the source gas. Therefore, the ALD method can perform film formation with an extremely thin film thickness, film formation on a structure with a high aspect ratio, film formation with few defects such as pinholes, and film formation with excellent coverage. Therefore, the ALD method is suitable for forming the insulator 250 and the insulator 224.
  • a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactant is performed only with thermal energy may be used, or a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant may be used.
  • a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant may be used.
  • a gas having a molecule containing the silicon atom may be used as a precursor, and the oxidant may be used as a reactant. Accordingly, the amount of hydrogen taken into the insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 can be significantly reduced.
  • a molecule including a silicon atom does not include a hydrogen atom
  • this embodiment is not limited to this.
  • the molecule containing a silicon atom a part of the functional group bonded to the silicon atom may be replaced with a hydrogen atom.
  • the number of hydrogen atoms contained in the molecule containing a silicon atom is smaller than that of silane (SiH 4 ). That is, it is preferable that the molecule containing a silicon atom has 3 or less hydrogen atoms per silicon atom. Further, it is more preferable that the gas having a molecule containing a silicon atom has 3 or less hydrogen atoms per silicon atom.
  • the insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 is formed by a film formation method using a gas in which hydrogen atoms are reduced or removed.
  • the amount of hydrogen contained in these insulating films can be reduced.
  • the insulator 216, the insulator 224, the insulator 280, and the insulator 250 which are formed in the region sealed with the insulator 283 and the insulator 212 together with the oxide 230 are formed by the above film formation method. This is more preferable because the hydrogen concentration in the sealed region can be reduced and hydrogen mixed from the outside can be reduced by the insulator 283 and the insulator 212.
  • the transistor 200 has a structure in which an insulator 282 and an insulator 250 are in direct contact with each other, as shown in FIGS. 1B and 1C and 1D.
  • oxygen contained in the insulator 280 is less likely to be absorbed by the conductor 260. Therefore, oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b through the oxide 230c, so that oxygen vacancies in the oxide 230a and the oxide 230b are reduced. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.
  • impurities such as hydrogen contained in the insulator 280 can be prevented from entering the insulator 250, so that the hydrogen concentrations of the insulator 250 and the oxide 230 can be further reduced. Therefore, an adverse effect on the electrical characteristics and reliability of the transistor 200 can be suppressed.
  • silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used as the insulator 282
  • a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.
  • a semiconductor device having normally-off electrical characteristics can be provided.
  • a semiconductor device including a transistor with high on-state current can be provided.
  • a semiconductor device including a transistor having high frequency characteristics can be provided.
  • a semiconductor device including a transistor with low off-state current can be provided.
  • the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260.
  • the conductor 205 is preferably embedded in the insulator 214 and the insulator 216.
  • the conductor 260 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode.
  • Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260, without changing the potential.
  • Vth of the transistor 200 can be higher than 0 V and off-state current can be reduced. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, as compared to the case where no potential is applied.
  • the conductor 205 is preferably provided larger than the size of a region of the oxide 230 which does not overlap with the conductors 242a and 242b.
  • the conductor 205 is preferably extended also in a region outside the end portion of the oxide 230 which intersects with the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with the insulator provided outside the side surface of the oxide 230 in the channel width direction.
  • local charging (called charge-up) can be alleviated in a treatment using plasma in a manufacturing process after the formation of the conductor 205.
  • charge-up local charging
  • the conductor 205 may overlap with at least the oxide 230 located between the conductor 242a and the conductor 242b.
  • the height of the bottom surface of the conductor 260 in a region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is lower than the height of the bottom surface of the oxide 230b with reference to the bottom surface of the insulator 224.
  • the difference between the height of the bottom surface of the conductor 260 in a region where the oxide 230b and the conductor 260 do not overlap with each other and the height of the bottom surface of the oxide 230b is 0 nm to 100 nm, preferably 3 nm to 50 nm.
  • the thickness is more preferably 5 nm or more and 20 nm or less.
  • the conductor 260 functioning as a gate has a structure in which the side surface and the top surface of the oxide 230b in the channel formation region are covered with the oxide 230c and the insulator 250, so that the electric field of the conductor 260 is formed into a channel. It becomes easy to act on the entire oxide 230b in the region. Therefore, the on-state current of the transistor 200 can be increased and frequency characteristics can be improved.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.
  • the conductor 205a is preferably a conductor that suppresses permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen.
  • titanium, titanium nitride, tantalum, or tantalum nitride can be used.
  • the conductor 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component.
  • the conductor 205 is illustrated as having two layers, it may have a multilayer structure of three or more layers.
  • the oxide semiconductor, the insulator or the conductor located in the lower layer of the oxide semiconductor, and the insulator or the conductor located in the upper layer of the oxide semiconductor are formed into different films without being exposed to the atmosphere. It is preferable to continuously form the seeds because an oxide semiconductor film with substantially high purity and intrinsic concentration in which impurities (in particular, hydrogen and water) are reduced can be formed.
  • At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 has impurities such as water or hydrogen mixed in the transistor 200 from the substrate side or from above. It is preferable that the barrier insulating film functions as a barrier insulating film. Therefore, at least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule.
  • an insulating material N 2 O, NO, NO 2, etc.
  • a material having a function of suppressing the diffusion of impurities such as copper atoms
  • an insulating material having a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules
  • silicon nitride, silicon nitride oxide, or the like is used for the insulator 212 and the insulator 283, and aluminum oxide, hafnium oxide, or the like is used for the insulator 214, the insulator 222, the insulator 272, and the insulator 282. preferable. Accordingly, impurities such as water or hydrogen can be suppressed from diffusing from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side through the insulator 212 and the insulator 214.
  • the transistor 200 includes the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 which has a function of suppressing diffusion of impurities such as water or hydrogen and oxygen.
  • a surrounding structure is preferable.
  • the resistivity of the insulator 212 and the insulator 283 may be preferable to reduce the resistivity of the insulator 212 and the insulator 283.
  • the resistivity of the insulator 212 and the insulator 283 is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 216, the insulator 280, and the insulator 274 preferably have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide containing fluorine, silicon oxide containing carbon, carbon, or nitrogen is added. Silicon oxide, silicon oxide having holes, or the like may be used as appropriate.
  • the insulator 222 and the insulator 224 have a function as a gate insulator.
  • the insulator 224 in contact with the oxide 230 desorb oxygen by heating.
  • oxygen released by heating may be referred to as excess oxygen.
  • the insulator 224 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator 224.
  • the oxide that desorbs oxygen by heating means that the desorption amount of oxygen molecules is 1.0 ⁇ 10 18 molecules/cm 3 or more, preferably by thermal desorption gas analysis (TDS (Thermal Desorption Spectroscopy) analysis).
  • TDS Thermal Desorption gas analysis
  • the surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.
  • the insulator 222 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side.
  • the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 222 has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to permeate).
  • the insulator 222 preferably has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 have a function of suppressing diffusion of oxygen and impurities because oxygen in the oxide 230 can be prevented from diffusing below the insulator 222.
  • the conductor 205 can be prevented from reacting with the insulator 224 and oxygen contained in the oxide 230.
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials, may be used.
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.
  • the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator and used.
  • the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3 (BST).
  • the insulating material may be used as a single layer or a stacked layer. As transistors become finer and more highly integrated, thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the oxide 243 (the oxide 243a and the oxide 243b) may be provided between the oxide 230b and the conductor 242 (the conductor 242a and the conductor 242b) which functions as a source electrode or a drain electrode. .. Since the conductor 242 and the oxide 230 are not in contact with each other, the conductor 242 can be prevented from absorbing oxygen in the oxide 230. That is, by preventing the conductor 242 from being oxidized, it is possible to suppress the decrease in the conductivity of the conductor 242. Therefore, the oxide 243 preferably has a function of suppressing oxidation of the conductor 242.
  • the oxide 243 preferably has a function of suppressing the permeation of oxygen.
  • the oxide 243 having a function of suppressing permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, electrical conductivity between the conductor 242 and the oxide 230b can be obtained. It is preferable because the resistance is reduced. With such a structure, electric characteristics of the transistor 200 and reliability of the transistor 200 can be improved.
  • a metal oxide containing the element M may be used.
  • the element M is preferably aluminum, gallium, yttrium, or tin.
  • the oxide 243 preferably has a higher concentration of the element M than the oxide 230b.
  • gallium oxide may be used as the oxide 243.
  • a metal oxide such as an In-M-Zn oxide may be used.
  • the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, release of oxygen in the oxide 230 can be suppressed appropriately. For example, if the oxide 243 has a hexagonal crystal structure or the like, release of oxygen in the oxide 230 can be suppressed in some cases.
  • the oxide 243 does not necessarily have to be provided. In that case, when the conductor 242 (the conductor 242a and the conductor 242b) is in contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 242 and the conductor 242 may be oxidized. Oxidation of the conductor 242 is likely to reduce the conductivity of the conductor 242. Note that diffusion of oxygen in the oxide 230 into the conductor 242 can be restated as absorption of oxygen in the oxide 230 by the conductor 242.
  • oxygen in the oxide 230 diffuses into the conductor 242 (the conductor 242a and the conductor 242b), so that the conductor 242a and the oxide 230b are separated from each other and the conductor 242b and the oxide 230b are separated from each other.
  • Different layers may be formed between them. Since the different layer contains more oxygen than the conductor 242, it is estimated that the different layer has an insulating property.
  • the three-layer structure of the conductor 242, the different layer, and the oxide 230b can be regarded as a three-layer structure including a metal-insulator-semiconductor and a MIS (Metal-Insulator-Semiconductor) structure. In some cases, it may be referred to as a diode junction structure mainly including the MIS structure.
  • the different layer is not limited to being formed between the conductor 242 and the oxide 230b.
  • the different layer is formed between the conductor 242 and the oxide 230c, It may be formed between the body 242 and the oxide 230b and between the conductor 242 and the oxide 230c.
  • the conductor 242 (the conductor 242a and the conductor 242b) functioning as a source electrode and a drain electrode is provided over the oxide 243.
  • the thickness of the conductor 242 may be, for example, 1 nm to 50 nm inclusive, preferably 2 nm to 25 nm inclusive.
  • the conductor 242 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even when absorbing oxygen is preferable.
  • the insulator 272 is provided in contact with the top surface of the conductor 242 and preferably functions as a barrier layer. With such a structure, absorption of excess oxygen included in the insulator 280 by the conductor 242 can be suppressed. Further, by suppressing the oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can have favorable electrical characteristics and reliability.
  • the insulator 272 has a function of suppressing diffusion of oxygen.
  • the insulator 272 preferably has a function of suppressing diffusion of oxygen as compared with the insulator 280.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed.
  • an insulator containing aluminum nitride may be used.
  • FIG. 2 shows a cross-sectional view corresponding to a portion indicated by a dashed line A7-A8 in FIG. 1A.
  • the insulator 273b is in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243b, and the side surface of the conductor 242b.
  • the insulator 273a is in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243a, and the side surface of the conductor 242a.
  • the insulator 273b may be in contact with the side surface of the insulator 272b.
  • the insulator 273a may be in contact with the side surface of the insulator 272a.
  • a metal oxide for the insulator 273 (insulator 273a and insulator 273b).
  • the metal contained in the insulator 273 is embedded in the interface between the insulator 273 and the oxide 230a and in the vicinity of the interface, whereby the interface between the insulator 273 and the oxide 230a and the vicinity of the interface can be made n-type.
  • the metal contained in the insulator 273 is embedded in the interface between the insulator 273 and the oxide 230b and in the vicinity of the interface, so that the interface between the insulator 273 and the oxide 230b and in the vicinity of the interface are made n-type. You can In FIG. 2, an n-type region of the oxide 230a and an n-type region of the oxide 230b are shown as a region 230n.
  • the on-state current of the transistor 200 can be increased.
  • the insulator 273 preferably has higher oxygen permeability than the insulator 272 and lower oxygen permeability than the insulator 280.
  • the film density of the insulator 273 is preferably lower than the film density of the insulator 272. This is preferable because oxygen contained in the insulator 280 can be injected into the oxides 230a and 230b in an appropriate amount and oxygen vacancies in the oxides 230a and 230b can be repaired. Further, since oxygen does not excessively enter the oxide 230a and the oxide 230b, reliability of the transistor 200 can be improved.
  • an oxide film containing one or more elements selected from aluminum, magnesium, and tantalum can be preferably used.
  • aluminum oxide, magnesium oxide, or tantalum oxide can be used.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably placed in contact with the top surface of the oxide 230c.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon-nitrogen-added silicon oxide, or silicon oxide having holes is used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • an insulator from which oxygen is released by heating As the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b.
  • the concentration of impurities such as water or hydrogen in the insulator 250 be reduced.
  • the thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 250 and the conductor 260.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260.
  • diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed.
  • oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.
  • the metal oxide may have a function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a high-k material with a high relative dielectric constant. When the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure which is stable to heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator.
  • EOT equivalent oxide film thickness
  • a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like may be used. it can.
  • the metal oxide may have a function as a part of the gate.
  • a conductive material containing oxygen may be provided on the channel formation region side.
  • a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen as a conductor functioning as a gate.
  • a conductive material containing the above metal element and nitrogen may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the conductor 260 is shown as a two-layer structure in FIG. 1, it may have a single-layer structure or a laminated structure of three or more layers.
  • the conductor 260a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.), and copper atoms. It is preferable to use materials. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.
  • the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to suppress the conductivity of the conductor 260b from being reduced due to the oxygen contained in the insulator 250 from oxidizing the conductor 260b.
  • the conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • a conductive material containing tungsten, copper, or aluminum as a main component for the conductor 260b. Since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used.
  • the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having holes is used. It is preferable to have.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • a material such as silicon oxide, silicon oxynitride, or silicon oxide having pores is preferable because a region containing oxygen which is released by heating can be easily formed.
  • the insulator 280 may have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by a sputtering method and silicon oxynitride formed over the silicon oxide by a CVD method. do it.
  • silicon nitride may be stacked further thereon.
  • the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Further, the upper surface of the insulator 280 may be flattened.
  • the insulator 282 and the insulator 283 preferably function as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulator 280 from above. Further, the insulator 282 and the insulator 283 preferably function as a barrier insulating film which suppresses oxygen permeation.
  • an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example.
  • aluminum oxide having a high barrier property against oxygen may be used as the insulator 282
  • silicon nitride or silicon nitride oxide having a high barrier property to hydrogen may be used as the insulator 283.
  • the insulator 274 functioning as an interlayer film on the insulator 283.
  • the insulator 274 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • the conductor 240a and the conductor 240b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 240a and the conductor 240b may have a stacked structure. Although the conductor 240a and the conductor 240b are circular in a top view in FIG. 1A, they are not limited to this. For example, the conductors 240a and 240b may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.
  • the insulator 274, the insulator 283, the insulator 282, the insulator 280, and the conductor in contact with the insulator 272 have impurities such as water or hydrogen and oxygen permeation in the conductor.
  • a conductive material having a function of suppressing For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like.
  • the conductive material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen may be used as a single layer or a stacked layer.
  • impurities such as water or hydrogen that diffuse from the insulator 280 and the like can be further reduced from entering the oxide 230 through the conductors 240a and 240b.
  • oxygen added to the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 274, the insulator 283, the insulator 282, the insulator 280, and the insulator 272, impurities such as water or hydrogen from the insulator 280 and the like can be conducted. Mixing into the oxide 230 through the body 240a and the conductor 240b can be suppressed.
  • silicon nitride is suitable because it has a high blocking property against hydrogen.
  • oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.
  • the conductor 246 (the conductor 246a and the conductor 246b) which functions as wiring may be arranged in contact with the top surface of the conductor 240a and the top surface of the conductor 240b.
  • the conductor 246 is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component.
  • the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in the opening provided in the insulator.
  • a substrate for forming the transistor 200 for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulating region inside the above-described semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate including a metal nitride, a substrate including a metal oxide, or the like can be given.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • a substrate provided with an element may be used.
  • the elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
  • the insulator examples include an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide.
  • the gate insulator may cause problems such as leakage current.
  • a high-k material for the insulator functioning as a gate insulator it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness.
  • a material having a low relative dielectric constant for the insulator functioning as the interlayer film it is possible to reduce the parasitic capacitance generated between the wirings. Therefore, the material should be selected according to the function of the insulator.
  • gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, silicon and hafnium, can be used. And the like, or a nitride containing silicon and hafnium.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or a hole is included.
  • examples include silicon oxide and resin.
  • a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium.
  • the insulator containing lanthanum, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, a metal oxide such as tantalum oxide, a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is released by heating.
  • the structure where silicon oxide or silicon oxynitride having a region containing oxygen which is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
  • Conductor aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, and the like.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even when absorbing oxygen is preferable.
  • a semiconductor having high electric conductivity which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed of the above materials may be laminated and used.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.
  • a stacked-layer structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate.
  • a conductive material containing oxygen may be provided on the channel formation region side.
  • a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen as a conductor functioning as a gate.
  • a conductive material containing the above metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • a metal oxide which functions as an oxide semiconductor is preferably used.
  • the metal oxide applicable to the oxide 230 according to the present invention will be described below.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained.
  • the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.
  • a combination of the above-mentioned elements may be used as the element M.
  • metal oxides having nitrogen may be collectively referred to as metal oxides. Further, the metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • the oxide semiconductor (metal oxide) is divided into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), and an amorphous oxide. There are things like semiconductors.
  • CAAC-OS has a crystal structure having a c-axis orientation, and a plurality of nanocrystals are connected in the ab plane direction to have a strain.
  • the strain refers to a portion in which the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in the region where a plurality of nanocrystals are connected.
  • Nanocrystals are basically hexagonal, but they are not limited to regular hexagons and may be non-regular hexagons.
  • the strain may have a lattice arrangement such as a pentagon and a heptagon.
  • a lattice arrangement such as a pentagon and a heptagon.
  • the CAAC-OS it is difficult to confirm a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of strain. That is, it is understood that the distortion of the lattice arrangement suppresses the formation of crystal grain boundaries. This is because the CAAC-OS can tolerate strain due to a non-dense arrangement of oxygen atoms in the ab plane direction, a change in bond distance between atoms due to substitution with a metal element, or the like. This is because.
  • the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M,Zn) layer) are stacked. It tends to have a structure (also called a layered structure).
  • indium and the element M can be replaced with each other, and when the element M of the (M,Zn) layer is replaced with indium, it can be expressed as an (In,M,Zn) layer.
  • the indium of the In layer is replaced with the element M, it can be expressed as an (In,M) layer.
  • CAAC-OS is a metal oxide with high crystallinity.
  • the CAAC-OS since it is difficult to confirm a clear crystal grain boundary, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur.
  • CAAC-OS impurities and defects oxygen deficiency (V O: also referred to as oxygen vacancy), etc.) with little metal oxide It can be called a thing. Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide including the CAAC-OS is highly heat resistant and highly reliable.
  • Nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Moreover, in the nc-OS, no regularity is found in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
  • IGZO indium-gallium-zinc oxide
  • IGZO indium-gallium-zinc oxide
  • IGZO may have a stable structure by using the above-described nanocrystal.
  • IGZO tends to have difficulty in crystal growth in the atmosphere, and thus a smaller crystal (for example, the above-mentioned nanocrystal) is used than a large crystal (here, a crystal of several mm or a crystal of several cm).
  • a large crystal here, a crystal of several mm or a crystal of several cm.
  • it may be structurally stable.
  • the a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the crystallinity of the a-like OS is lower than that of the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the structure of the oxide semiconductor is not particularly limited, but preferably has crystallinity.
  • the oxide 230 can have a CAAC-OS structure and the oxide 243 can have a hexagonal crystal structure.
  • the oxide 230 and the oxide 243 have the above crystal structure, a highly reliable semiconductor device can be obtained.
  • the oxide 230a, the oxide 230c, and the oxide 243 can have approximately the same composition.
  • the metal oxide contains an alkali metal or an alkaline earth metal
  • a defect level may be formed and a carrier may be generated. Therefore, a transistor including a metal oxide containing an alkali metal or an alkaline earth metal in a channel formation region is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide.
  • the concentration of alkali metal or alkaline earth metal (concentration obtained by SIMS) in the metal oxide is 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less. To do.
  • hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, which may form oxygen deficiency.
  • oxygen vacancies electrons which are carriers may be generated.
  • part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including a metal oxide containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible.
  • a thin film with high crystallinity As the metal oxide used for the semiconductor of the transistor.
  • the thin film By using the thin film, stability or reliability of the transistor can be improved.
  • the thin film include a single crystal metal oxide thin film and a polycrystalline metal oxide thin film.
  • a high temperature or laser heating process is required in order to form a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.
  • a in each drawing shows a top view.
  • B in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 shown in A, and is also a cross-sectional view in the channel length direction of the transistor 200.
  • C in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A3-A4 in A, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • D in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in A.
  • some elements are omitted for clarity of the drawing.
  • a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate.
  • the insulator 212 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method. (Atomic Layer Deposition) method can be used.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, and a photo CVD (Photo CVD) method that uses light. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • atmospheric pressure CVD Atmospheric Pressure CVD
  • LPCVD Low Pressure CVD
  • the plasma CVD method can obtain a high quality film at a relatively low temperature.
  • the thermal CVD method is a film forming method which can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in a semiconductor device might be charged up by receiving electric charge from plasma. At this time, the accumulated charges may damage wirings, electrodes, elements, and the like included in the semiconductor device.
  • the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased.
  • plasma damage does not occur during film formation, so that a film with few defects can be obtained.
  • a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactant is performed only with thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant, and the like can be used.
  • the ALD method uses the self-controlling property of atoms and can deposit atoms one by one, so ultrathin films can be formed, films with high aspect ratios can be formed, pinholes, etc. It is possible to form a film with few defects, to form a film with excellent coverage, and to form a film at a low temperature.
  • the use of plasma may allow film formation at a lower temperature, which is preferable in some cases.
  • some precursors used in the ALD method include impurities such as carbon. Therefore, a film formed by the ALD method may contain a large amount of impurities such as carbon as compared with a film formed by another film formation method.
  • the impurities can be quantified using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, the film forming method is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of the opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gas.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gas.
  • a silicon nitride film is formed as the insulator 212 by a CVD method.
  • a CVD method As described above, by using an insulator such as silicon nitride in which copper is less likely to permeate as the insulator 212, even if a metal such as copper that easily diffuses is used as a conductor in a layer (not shown) below the insulator 212, The metal can be suppressed from diffusing into the upper layer through the insulator 212. Further, by using an insulator such as silicon nitride in which impurities such as water or hydrogen are less likely to permeate, diffusion of impurities such as water or hydrogen from a layer below the insulator 212 can be suppressed.
  • the insulator 214 is formed over the insulator 212.
  • the insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is used as the insulator 214.
  • the insulator 216 is formed over the insulator 214.
  • the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide or silicon oxynitride is used as the insulator 216.
  • the insulator 216 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 216 can be reduced.
  • an opening reaching the insulator 214 is formed in the insulator 216.
  • the openings include, for example, grooves and slits.
  • the area where the opening is formed may be referred to as an opening.
  • the opening may be formed by wet etching, but dry etching is preferable for fine processing.
  • the insulator 214 it is preferable to select an insulator which functions as an etching stopper film when the insulator 216 is etched to form a groove.
  • the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.
  • a conductive film to be the conductor 205a is formed.
  • the conductive film preferably contains a conductor having a function of suppressing permeation of oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used.
  • the conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205a has a multi-layer structure.
  • a tantalum nitride film is formed by a sputtering method, and titanium nitride is laminated on the tantalum nitride film.
  • a conductive film to be the conductor 205b is formed.
  • the conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as copper is formed as a conductive film to be the conductor 205b.
  • a CMP process (Chemical Mechanical Polishing) is performed to remove the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b, so that the insulator 216 is exposed.
  • the conductors 205a and 205b remain only in the openings.
  • the conductor 205 having a flat upper surface can be formed.
  • part of the insulator 216 may be removed by the CMP treatment (see FIG. 20).
  • the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but the present embodiment is not limited to this.
  • the conductor 205 is formed over the insulator 214, the insulator 216 is formed over the conductor 205, and the insulator 216 is subjected to CMP treatment so that part of the insulator 216 is removed and the conductor 216 is removed.
  • the surface of 205 may be exposed.
  • the insulator 222 is formed over the insulator 216 and the conductor 205.
  • an insulator containing one or both oxides of aluminum and hafnium may be formed.
  • the insulator containing one or both oxides of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water.
  • the insulator 222 having a barrier property against hydrogen and water suppresses diffusion of hydrogen and water contained in the structure provided around the transistor 200 to the inside of the transistor 200 through the insulator 222. The generation of oxygen vacancies in the oxide 230 can be suppressed.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 224 is formed over the insulator 222.
  • the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide or silicon oxynitride is used as the insulator 224.
  • the insulator 224 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 224 can be reduced. Since the insulator 224 becomes the insulator 224 that is in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.
  • the heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 300 °C to 500 °C inclusive, and more preferably 320 °C to 450 °C inclusive.
  • the heat treatment is performed in a nitrogen or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in a nitrogen or inert gas atmosphere and then in an atmosphere containing an oxidizing gas in an amount of 10 ppm or higher, 1% or higher, or 10% or higher in order to supplement desorbed oxygen. Good.
  • a treatment for 1 hour at a temperature of 400° C. is continuously performed in an oxygen atmosphere.
  • impurities such as water and hydrogen contained in the insulator 224 can be removed.
  • the heat treatment may be performed after the insulator 222 is formed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • plasma treatment containing oxygen may be performed under reduced pressure.
  • an apparatus having a power source for generating high-density plasma using microwaves for example.
  • a power source for applying a high frequency wave such as RF may be provided on the substrate side.
  • high-density plasma high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently introduced into the insulator 224. it can.
  • plasma treatment containing oxygen may be performed in order to supplement desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by selecting appropriate conditions for the plasma treatment. In that case, heat treatment may not be performed.
  • aluminum oxide may be formed on the insulator 224 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 224.
  • CMP chemical vapor deposition
  • the surface of the insulator 224 can be planarized and the surface of the insulator 224 can be smoothed.
  • the end point of CMP can be easily detected.
  • part of the insulator 224 is polished by CMP and the thickness of the insulator 224 is reduced in some cases, the thickness may be adjusted when the insulator 224 is formed.
  • oxygen can be added to the insulator 224 by depositing aluminum oxide over the insulator 224 by a sputtering method, which is preferable.
  • an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see FIG. 3).
  • the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • a sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased.
  • the above oxide film is formed by the sputtering method, the above In-M-Zn oxide target can be used.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A is 70% or higher, preferably 80% or higher, more preferably 100%.
  • the oxide film 230B is formed by a sputtering method
  • the proportion of oxygen contained in the sputtering gas is 1% to 30% inclusive, preferably 5% to 20% inclusive, an oxygen-deficient oxide semiconductor is obtained. It is formed.
  • a transistor including an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility. Further, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.
  • one embodiment of the present invention is not limited to this.
  • the oxide film 230B is formed by a sputtering method
  • the proportion of oxygen contained in the sputtering gas is greater than 30% and 100% or less, preferably 70% or more and 100% or less
  • the oxygen-excess oxide semiconductor is formed. Is formed.
  • a transistor including an oxygen-excess type oxide semiconductor in a channel formation region has relatively high reliability.
  • a film is formed using a target of 4 [atomic ratio].
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed.
  • treatment is continuously performed at a temperature of 400° C. for 1 hour in an oxygen atmosphere.
  • an oxide film 243A is formed on the oxide film 230B (see FIG. 3).
  • the oxide film 243A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 243A preferably has an atomic ratio of Ga to In that is larger than an atomic ratio of Ga to In of the oxide film 230B.
  • the conductive film 242A is formed on the oxide film 243A (see FIG. 3).
  • the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film 272A is formed on the conductive film 242A (see FIG. 3).
  • the insulating film 272A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • As the insulating film 272A it is preferable to use an insulating film having a function of suppressing permeation of oxygen.
  • aluminum oxide, silicon nitride, silicon oxide, or gallium oxide may be formed by a sputtering method or an ALD method.
  • a conductive film 247A is formed over the insulating film 272A (see FIG. 3).
  • the conductive film 247A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 272A, and the conductive film 247A are processed into an island shape by a lithography method to form the oxide 230a, the oxide 230b, and the oxide film.
  • the object layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are formed (see FIG. 4).
  • the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are formed so that at least part of them overlaps with the conductor 205.
  • a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing. Note that in this step, the thickness of a region of the insulator 224 which does not overlap with the oxide 230a may be thin.
  • the resist is exposed through a mask.
  • the exposed region is removed or left using a developing solution to form a resist mask.
  • the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the above-mentioned light.
  • the resist mask can be removed by performing dry etching treatment such as ashing, performing wet etching treatment, performing wet etching treatment after dry etching treatment, or performing dry etching treatment after wet etching treatment.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • a hard mask an insulating film or a conductive film serving as a hard mask material is formed over the conductive film 242A, a resist mask is formed thereover, and the hard mask material is etched to form a hard mask having a desired shape. can do.
  • Etching of the conductive film 242A or the like may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the conductive film 242A or the like, the hard mask may be removed by etching.
  • the insulator layer 272B and the conductor layer 247B are used as a hard mask.
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as the dry etching device.
  • the capacitively coupled plasma etching apparatus having the parallel plate electrodes may have a configuration in which a high frequency power source is applied to one of the parallel plate electrodes.
  • a plurality of different high frequency power supplies may be applied to one of the parallel plate electrodes.
  • a high frequency power source having the same frequency may be applied to each of the parallel plate electrodes.
  • a configuration may be adopted in which high frequency power supplies having different frequencies are applied to the parallel plate electrodes.
  • a dry etching apparatus having a high density plasma source can be used.
  • an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus can be used as a dry etching apparatus having a high-density plasma source.
  • the conductor layer 242B has a curved surface between the side surface and the top surface as illustrated in FIGS. 4C and 4D. do not do.
  • the conductor 242a and the conductor 242b shown in FIG. 1 have angular end portions where the side surfaces and the upper surface intersect. Since the end portion where the side surface and the upper surface of the conductor 242 intersect is angular, the cross-sectional area of the conductor 242 is larger than that in the case where the end portion has a curved surface. Accordingly, the resistance of the conductor 242 is reduced, so that the on-state current of the transistor 200 can be increased.
  • the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are substantially perpendicular to the top surface of the insulator 222, the plurality of transistors can be formed. When 200 is provided, the area can be reduced and the density can be increased.
  • the invention is not limited thereto, and the angle formed between the side surface of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B and the top surface of the insulator 222 is low. It may be configured as follows.
  • the insulating film 273A is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B (see FIG. 5). ).
  • the insulating film 273A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 273A is anisotropically etched to remove the insulating film 273A on the conductor layer 247B and the insulating film 273A on the insulator 224.
  • the conductor layer 247B is removed, so that the insulator layer 273B is formed.
  • the insulator layer 273B is preferably formed so as to be in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide layer 243B, and the side surface of the conductor layer 242B (see FIG. 6).
  • an insulating film to be the insulator 280 is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the insulator layer 273B. ..
  • the insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film may be formed by a sputtering method and a silicon oxide film may be formed thereover by a PEALD method or a thermal ALD method.
  • the insulating film to be the insulator 280 is preferably formed by the above-described film forming method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 280 can be reduced.
  • the insulator 280 is subjected to CMP treatment to form the insulator 280 having a flat upper surface (see FIG. 7).
  • aluminum oxide may be formed over the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.
  • the insulator 280, the oxide 230b, and the oxide 230a may be irradiated with microwaves or high frequencies such as RF. Irradiated microwaves or high frequencies such as RF penetrate into the insulator 280, the oxide 230b, and the oxide 230a, and remove hydrogen in these.
  • Irradiated microwaves or high frequencies such as RF penetrate into the insulator 280, the oxide 230b, and the oxide 230a, and remove hydrogen in these.
  • happening reactions coupling VoH is disconnected, when other words happening reaction of "V O H ⁇ Vo + H"
  • Part of the hydrogen generated at this time may be removed from the oxide 230 and the insulator 280 as H 2 O by combining with oxygen. Further, part of hydrogen may be gettered to the conductor 242 in some cases.
  • irradiation with microwaves or high frequencies such as RF can reduce the hydrogen concentration in the insulator 280, the oxide 230b, and the oxide 230a.
  • irradiation with microwaves or high frequencies such as RF may be performed before the CMP treatment.
  • oxygen radicals may be formed by converting oxygen gas into plasma by microwaves or high frequencies such as RF. That is, plasma treatment may be performed in an atmosphere in which the insulator 280, the oxide 230b, and the oxide 230a contain oxygen. Hereinafter, such a process may be referred to as an oxygen plasma process. Further, oxygen can be supplied to the insulator 280, the oxide 230b, and the oxide 230a by the formed oxygen radical. In the case where plasma treatment is performed on the insulator 280, the oxide 230b, and the oxide 230a in an atmosphere containing oxygen, the oxide 230 may be less likely to be irradiated with microwaves or high frequencies such as RF.
  • the microwave processing apparatus may have a power source for applying RF on the substrate side.
  • high density plasma high density oxygen radicals can be generated.
  • RF radio frequency
  • oxygen ions generated by high-density plasma can be efficiently introduced into the insulator 280 and the oxide 230.
  • the oxygen plasma treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, still more preferably 400 Pa or higher.
  • the oxygen flow rate ratio (O 2 /O 2 +Ar) is 50% or less, preferably 10% or more and 30% or less.
  • the processing temperature may be about 400° C., for example. Further, after the oxygen plasma treatment is performed, the heat treatment may be continuously performed without being exposed to the outside air.
  • part of the insulator 280, part of the insulator layer 272B, part of the insulator layer 273B, part of the conductor layer 242B, and part of the oxide layer 243B are processed to form the oxide 230b.
  • the opening is preferably formed so as to overlap with the conductor 205.
  • the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272a, the insulator 272b, the insulator 273a, and the insulator 273b are formed.
  • the etching of part of the insulator 280, part of the insulator layer 272B, part of the insulator layer 273B, part of the conductor layer 242B, and part of the oxide layer 243B is performed by a dry etching method or a wet etching method. be able to. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 280 is processed by dry etching, part of the insulator layer 272B is processed by wet etching, the insulator layer 273B is processed by dry etching, and the oxide layer 243B and the conductive layer A part of the body layer 242B may be processed by a dry etching method.
  • Impurities resulting from the etching gas and the like may adhere or diffuse to the surface or inside of the oxides 230a and 230b by performing the processes such as the dry etching so far.
  • impurities include fluorine and chlorine.
  • cleaning method include wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, or heat treatment, or the like, and the above cleaning may be performed in appropriate combination.
  • the wet cleaning may be performed using an aqueous solution prepared by diluting oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, etc. with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.
  • a heat treatment may be performed after the etching or the cleaning.
  • the heat treatment may be performed at 100 °C to 450 °C inclusive, more preferably 350 °C to 400 °C inclusive, for example.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 230a and oxides 230b, it is possible to reduce the oxygen vacancies V O.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the air.
  • an oxide film 230C is formed (see FIG. 9).
  • Heat treatment may be performed before the oxide film 230C is formed, and the heat treatment is preferably performed under reduced pressure and the oxide film 230C is continuously formed without being exposed to the air. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b or the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced.
  • the temperature of the heat treatment is preferably 100°C or higher and 400°C or lower, and more preferably 150°C or higher and 350°C or lower. In this embodiment mode, heat treatment is performed at a temperature of 200° C. under reduced pressure.
  • the oxide film 230C includes at least a part of a side surface of the oxide 230a, a part of a side surface and a part of an upper surface of the oxide 230b, a part of a side surface of the oxide 243, a part of a side surface of the conductor 242. It is preferably provided so as to be in contact with part of a side surface of the insulator 272 and a side surface of the insulator 280. Since the conductor 242 is surrounded by the oxide 243, the insulator 272, the insulator 273, and the oxide film 230C, the decrease in conductivity due to the oxidation of the conductor 242 in the subsequent steps can be suppressed.
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the atomic ratio of Ga to In is preferably larger than the atomic ratio of Ga to In of the oxide film 230B.
  • the oxide film 230C may be a laminated layer.
  • a film ratio may be used for the target formation.
  • part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 280 when the oxide film 230C is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or higher, preferably 80% or higher, more preferably 100%.
  • heat treatment may be performed.
  • the heat treatment may be performed under reduced pressure, and the insulating film 250A may be continuously formed without being exposed to the air.
  • moisture and hydrogen adsorbed on the surface of the oxide film 230C or the like can be removed, and moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. it can.
  • the temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment mode, the temperature of the heat treatment is 200° C.
  • an insulating film 250A is formed on the oxide film 230C (see FIG. 9).
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by the above-described film forming method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250 that comes into contact with the oxide 230c in a later step, it is preferable that the hydrogen concentration be reduced in this manner. Note that after the insulating film 250A is formed, irradiation with microwaves or high frequencies such as RF or oxygen plasma treatment which is performed after forming the insulator 280 may be performed.
  • the conductive film 260Aa and the conductive film 260Ab are formed (see FIG. 10).
  • the conductive film 260Aa and the conductive film 260Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 260Aa is formed by an ALD method and the conductive film 260Ab is formed by a CVD method.
  • the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and the conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, whereby the oxide 230c, the insulator 250, and the conductive material 260 (the conductive material 260a). And a conductor 260b) are formed (see FIG. 11).
  • heat treatment may be performed.
  • the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere.
  • moisture concentration and hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
  • the insulator 282 may be continuously formed without being exposed to the air.
  • an insulator 282 is formed over the conductor 260, the oxide 230c, the insulator 250, and the insulator 280.
  • the insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 12).
  • oxygen can be added to the insulator 280 while forming the film. At this time, it is preferable to form the insulator 282 while heating the substrate.
  • oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 260 in heat treatment performed later, which is preferable. ..
  • part of the insulator 282, part of the insulator 280, part of the insulator 224, part of the insulator 222, part of the insulator 216, and part of the insulator 214 are processed.
  • An opening reaching the insulator 212 is formed (see FIG. 13).
  • the opening may be formed so as to surround the transistor 200.
  • the opening may be formed so as to surround the plurality of transistors 200. Therefore, in the opening, part of the side surface of the insulator 282, part of the side surface of the insulator 280, part of the side surface of the insulator 224, part of the side surface of the insulator 222, part of the side surface of the insulator 216. , And a part of the side surface of the insulator 214 is exposed.
  • Part of the insulator 282, part of the insulator 280, part of the insulator 224, part of the insulator 222, part of the insulator 216, and part of the insulator 214 are processed by a dry etching method.
  • a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions.
  • the insulator 280 or the like may be irradiated with microwaves or high frequencies such as RF.
  • the irradiated microwave or high frequency waves such as RF may penetrate into the insulator 280, the oxide 230b, the oxide 230a, and the like, so that hydrogen in these can be removed.
  • happening reactions coupling VoH is disconnected, when other words happening reaction of "V O H ⁇ Vo + H", will be dehydrogenated.
  • Part of the hydrogen generated at this time may be removed from the oxide 230 and the insulator 280 as H 2 O by combining with oxygen. Further, part of hydrogen may be gettered to the conductor 242 in some cases.
  • the insulator 283 is formed by covering the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 (see FIG. 14). As shown in FIG. 14, the insulator 283 is in contact with the insulator 212 on the bottom surface of the opening. That is, the top surface and the side surface of the transistor 200 are covered with the insulator 283, and the bottom surface is covered with the insulator 212. In this manner, by wrapping the transistor 200 with the insulator 283 and the insulator 212 having a high barrier property, moisture and hydrogen can be prevented from entering from the outside.
  • the insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • heat treatment may be performed.
  • the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere.
  • oxygen added by forming the insulator 282 can be diffused into the insulator 280 and further supplied to the oxide 230a and the oxide 230b through the oxide 230c.
  • oxygen vacancies in the oxide 230 oxygen vacancies in the oxide 230 (oxide 230b) can be repaired by oxygen, that is, a reaction of “Vo+O ⁇ null” can be promoted. it can.
  • oxygen supplied as hydrogen reacts with hydrogen remaining in the oxide 230, whereby the hydrogen can be removed (dehydrated) as H 2 O.
  • the hydrogen remained in the oxide 230 can be prevented from recombine V O H is formed by oxygen vacancies.
  • the heat treatment is not limited to after the insulator 283 is formed and may be performed after the insulator 282 is formed.
  • an insulating film to be the insulator 274 is formed over the insulator 283.
  • the insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film to be the insulator 274 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulating film which serves as the insulator 274 can be reduced.
  • the insulating film to be the insulator 274 is subjected to CMP treatment to form the insulator 274 having a flat upper surface (see FIG. 15).
  • the insulator 272a, the insulator 280, the insulator 282, the insulator 283, and the insulator 274 are provided with an opening 255a reaching the conductor 242a, an insulator 272b, an insulator 280, an insulator 282, an insulator 283, Then, an opening 255b reaching the conductor 242b is formed in the insulator 274 (see FIG. 15).
  • the opening may be formed by using a lithography method. Note that although the opening 255a and the opening 255b are circular in a top view in FIG. 15A, the shape is not limited to this.
  • the openings 255a and 255b may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 16).
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film serving as the insulator 241 an insulating film having a function of suppressing permeation of oxygen is preferably used.
  • a silicon nitride film similarly to the above-described film formation of the insulator 283, it is preferable to form a silicon nitride film by using a PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.
  • a dry etching method may be used as the anisotropic etching of the insulating film that becomes the insulator 241.
  • a dry etching method may be used.
  • oxygen permeation from the outside can be suppressed and oxidation of the conductor 240a and the conductor 240b which are formed next can be prevented.
  • impurities such as water and hydrogen can be prevented from diffusing outside from the conductor 240a and the conductor 240b.
  • a conductive film to be the conductor 240a and the conductor 240b is formed.
  • the conductive films to be the conductor 240a and the conductor 240b preferably have a stacked-layer structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.
  • a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used.
  • the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed to remove a part of the conductive film to be the conductors 240a and 240b and expose the upper surface of the insulator 274.
  • the conductor 240a and the conductor 240b whose top surfaces are flat can be formed by leaving the conductive film only in the openings 255a and 255b (see FIG. 17).
  • part of the upper surface of the insulator 274 may be removed by the CMP treatment.
  • the conductive film to be the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 246 is processed by a lithography method to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b (see FIG. 1).
  • a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured.
  • the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment.
  • FIGS. 18 to 20 structures having the same functions as the structures included in the semiconductor device (see FIG. 1) illustrated in ⁇ Structure example of semiconductor device> are denoted by the same reference numerals. Note that in this item, as the constituent material of the transistor 200, the material described in detail in ⁇ Structure example of semiconductor device> can be used.
  • FIG. 18A is a top view of a semiconductor device including the transistor 200.
  • 18B is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2 in FIG. 18A and also a cross-sectional view in the channel length direction of the transistor 200.
  • 18C is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4 in FIG. 18A and also a cross-sectional view in the channel width direction of the transistor 200.
  • 18D is a cross-sectional view corresponding to the portion indicated by dashed-dotted line A5-A6 in FIG. 18A. Note that in the top view of FIG. 18A, some elements are omitted for clarity.
  • the insulator 214, the insulator 216, the insulator 222, the insulator 224, and the insulator 280 are patterned, and the insulator 282 and the insulator 212 have a structure in which they are sealed. 1 is different from the transistor 200 shown in FIG. That is, the insulator 282 includes the upper surface of the insulator 280, the side surface of the insulator 280, the side surface of the insulator 224, the side surface of the insulator 222, the side surface of the insulator 216, the side surface of the insulator 214, and the upper surface of the insulator 212. , Touch each other.
  • an insulator 283 is provided over the insulator 282. Accordingly, the insulator 214, the insulator 216, the insulator 222, the insulator 224, and the insulator 280 including the oxide 230 and the like are separated by the insulator 282, the insulator 283 over the insulator 282, and the insulator 212. , Isolated from the outside.
  • FIG. 19A is a top view of a semiconductor device including the transistor 200.
  • 19B is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2 in FIG. 19A and also a cross-sectional view in the channel length direction of the transistor 200.
  • 19C is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4 in FIG. 19A and also a cross-sectional view in the channel width direction of the transistor 200.
  • FIG. 19D is a cross-sectional view corresponding to the portion indicated by dashed-dotted line A5-A6 in FIG. 19A. In the top view of FIG. 19A, some elements are omitted for clarity.
  • the transistor 200 shown in FIG. 19 is different from the transistor 200 shown in FIG. 1 in that the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 are not patterned.
  • the top surface of the conductor 242 is covered with the insulator 272, and the side surface of the conductor 242, the side surface of the oxide 243, the side surface of the oxide 230a, and the side surface of the oxide 230b are covered with the insulator 273. It is possible to suppress diffusion of impurities such as hydrogen and water and oxygen into the conductor 242 from the side surface of the conductor 242 and the upper surface direction of the conductor 242.
  • the lower surface of the conductor 242 has a structure in contact with the oxide 243, and oxygen in the oxide 230b is blocked by the oxide 243, so that diffusion of oxygen into the conductor 242 is suppressed.
  • the diffusion of oxygen from the periphery of the conductor 242 to the conductor 242 can be suppressed, so that the oxidation of the conductor 242 can be suppressed. Further, diffusion of impurities such as hydrogen and water into the oxide 230a and the oxide 230b from the side surface of the oxide 230a and the side surface of the oxide 230b can be suppressed.
  • 20A and 20B show a structure in which the plurality of transistors 200_1 to 200_n are collectively sealed with an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 20A and 20B, the invention is not limited thereto.
  • the transistors 200_1 to 200_n may be arranged in the channel width direction, may be arranged in a matrix, or may be arranged without regularity.
  • a portion where the insulator 283 and the insulator 212 are in contact with each other (hereinafter, may be referred to as a sealing portion 265) is formed.
  • the sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With such a structure, the plurality of transistors 200_1 to 200_n can be surrounded by the insulator 283 and the insulator 212. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.
  • a dicing line (may be referred to as a scribe line, a dividing line, or a cutting line) may be provided so as to overlap the sealing portion 265. Since the substrate is divided in the dicing line, the transistor group surrounded by the sealing portion 265 is taken out as one chip.
  • FIG. 20A illustrates an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, the present invention is not limited to this.
  • a plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions.
  • the plurality of transistors 200_1 to 200_n are surrounded by the sealing portion 265a and further surrounded by the outer sealing portion 265b.
  • the plurality of transistors 200_1 to 200_n By thus surrounding the plurality of transistors 200_1 to 200_n with the plurality of sealing portions, a portion where the insulator 283 and the insulator 212 are in contact with each other is increased; thus, the adhesion between the insulator 283 and the insulator 212 is increased. It can be further improved. Accordingly, the plurality of transistors 200_1 to 200_n can be sealed more reliably.
  • the dicing line may be provided so as to overlap the sealing portion 265a or the sealing portion 265b, or the dicing line may be provided between the sealing portion 265a and the sealing portion 265b.
  • a semiconductor device having favorable electric characteristics can be provided.
  • a semiconductor device having normally-off electrical characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with high on-state current can be provided.
  • a semiconductor device having high frequency characteristics can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a highly productive semiconductor device can be provided.
  • FIG. 21 illustrates an example of a semiconductor device (memory device) including the capacitor which is one embodiment of the present invention.
  • the transistor 200 is provided above the transistor 300 and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the stored content can be held for a long time by using the transistor 200 in a memory device. That is, the refresh operation is not necessary or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300 and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to a first gate of the transistor 200, and the wiring 1006 is electrically connected to a second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100 and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. ..
  • the memory devices shown in FIG. 21 can be arranged in a matrix to form a memory cell array.
  • the transistor 300 is provided over the substrate 311, and includes a conductor 316 which functions as a gate, an insulator 315 which functions as a gate insulator, a semiconductor region 313 which is part of the substrate 311, and a low region which functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to cover the conductor 316 with the insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material whose work function is adjusted. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator which functions as a mask for forming the protrusion may be provided in contact with the top of the protrusion. Further, although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • transistor 300 illustrated in FIG. 21 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the capacitor 100 is provided above the transistor 200.
  • the capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
  • the conductor 112 provided on the conductor 246 and the conductor 110 can be formed at the same time.
  • the conductor 112 has a function as a plug or a wiring which is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 21, the structure is not limited to this structure and may have a stacked structure of two or more layers.
  • a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between the conductor having barrier property and the conductor having high conductivity.
  • the insulator 130 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Etc. may be used, and they can be provided as a laminated layer or a single layer.
  • the capacitor 100 has an insulator having a high dielectric constant (high-k), whereby sufficient capacitance can be secured, and an insulator having a large dielectric strength improves the dielectric strength and Electrostatic breakdown of the element 100 can be suppressed.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen are used. Examples thereof include added silicon oxide, silicon oxide having pores, or resin.
  • a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design.
  • the conductor having a function as a plug or a wiring may have a plurality of structures collectively given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, part of the conductor may function as a wiring, and part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film over the transistor 300. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are filled with a conductor 328, a conductor 330, and the like which are electrically connected to the capacitor 100 or the transistor 200. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.
  • the insulator functioning as an interlayer film may function as a flattening film that covers the uneven shape below the insulator.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve flatness.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided.
  • a conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or a wiring.
  • a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
  • the conductor 218 has a function as a plug or a wiring which is electrically connected to the capacitor 100 or the transistor 300.
  • an insulator 150 is provided over the conductor 120 and the insulator 130.
  • the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug.
  • the insulator 217 is provided in contact with the inner walls of the openings formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. That is, the insulator 217 is provided between the conductor 218 and the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may be formed in contact with the side surface of the conductor 205 in some cases.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulator 212, the insulator 214, and the insulator 222, impurities such as water or hydrogen from the insulator 210 or the insulator 216 are mixed into the oxide 230 through the conductor 218. Can be suppressed.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Further, oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218.
  • the insulator 217 can be formed by a method similar to that of the insulator 241.
  • a PEALD method may be used to form a silicon nitride film and anisotropic etching may be used to form an opening reaching the conductor 356.
  • the insulator that can be used as the interlayer film there are oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having an insulating property.
  • the material should be selected according to the function of the insulator.
  • the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like have insulators with low relative permittivity.
  • the insulator may include silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon- and nitrogen-added silicon oxide, silicon oxide having holes, or a resin.
  • the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide containing fluorine, silicon oxide containing carbon, silicon oxide containing carbon and nitrogen, or silicon oxide having holes. And a laminated structure of a resin.
  • silicon oxide and silicon oxynitride are thermally stable, by combining with a resin, a laminated structure having thermal stability and a low relative dielectric constant can be obtained.
  • the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.
  • the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium.
  • the insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for the wiring and the plug include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium.
  • a material containing one or more metal elements selected from ruthenium, ruthenium, and the like can be used.
  • a semiconductor having high electric conductivity which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a metal material for example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like formed using any of the above materials.
  • the conductive material of can be used as a single layer or a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
  • the insulator 241 is preferably provided in contact with the side surface of the conductor 240 which functions as a plug.
  • the insulator 241 is formed in contact with the inner walls of the openings formed in the insulator 222, the insulator 224, the insulator 280, the insulator 282, the insulator 283, and the insulator 274.
  • the insulator 241 is provided between the conductor 240 and the insulator 222, the insulator 224, the insulator 280, the insulator 282, the insulator 283, and the insulator 274; Impurities such as water or hydrogen from the body 280 and the insulator 274 can be prevented from entering the oxide 230 through the conductor 240.
  • the insulator 241 oxygen contained in the insulator 224, the insulator 280, and the insulator 274 can be prevented from being absorbed by the conductor 240. Therefore, the amount of hydrogen diffused from the conductor 240 to the conductor 242 and the oxide 230 can be reduced.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen.
  • a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used.
  • the transistor 200 is preferably sealed with the insulator 283 and the insulator 212. With such a structure, hydrogen contained in the insulator 274 can be prevented from entering the insulator 280 or the like.
  • the conductor 240 penetrates the insulator 283 and the conductor 218 penetrates the insulator 212, but as described above, the insulator 241 is provided in contact with the conductor 240 and the insulator 217 conducts. It is provided in contact with the body 218. Accordingly, hydrogen mixed inside the insulator 283 and the insulator 212 through the conductor 240 and the conductor 218 can be reduced. In this manner, the transistor 200 is more reliably sealed with the insulator 283, the insulator 212, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 and the like from the outside of the insulator 283. It is possible to reduce contamination.
  • the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 are formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described in the above embodiment. It is preferably formed. Accordingly, the hydrogen concentration of the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 can be reduced.
  • the insulator 216, the insulator 224, the insulator 280, and the insulator 274 are provided with conductors 240 and 218, which are vias connected to the conductor 242. There is. As described above, by reducing the hydrogen concentration in the insulator 216, the insulator 224, the insulator 280, and the insulator 274, the hydrogen is diffused into the conductor 242 and the oxide 230 through the conductor 240 and the conductor 218. The amount of hydrogen can be further reduced.
  • the hydrogen concentration of the silicon-based insulating film near the transistor 200 can be reduced and the hydrogen concentration of the oxide 230 can be reduced.
  • a dicing line (which may be referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing a large-area substrate into semiconductor elements will be described. ..
  • a dividing method for example, first, a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, and then the semiconductor element is cut along the dicing line to divide (divide) into a plurality of semiconductor devices.
  • a region where the insulator 283 and the insulator 212 are in contact with each other and the dicing line openings are provided in the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 in the vicinity of a region which serves as a dicing line which is provided on the outer edge of the memory cell including the plurality of transistors 200.
  • the insulator 212 and the insulator 283 are in contact with each other in the openings provided in the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214.
  • the insulator 212 and the insulator 283 may be formed using the same material and the same method.
  • adhesion can be improved. For example, it is preferable to use silicon nitride.
  • the transistor 200 can be wrapped with the insulator 212 and the insulator 283. Since the insulator 212 and the insulator 283 have a function of suppressing diffusion of oxygen, hydrogen, and water, the substrate is divided into each circuit region in which the semiconductor element described in this embodiment is formed. Thus, even when processed into a plurality of chips, it is possible to prevent impurities such as hydrogen or water from entering from the side surface direction of the divided substrate and diffusing into the transistor 200.
  • the oxide in which the channel in the transistor 200 is formed can be an oxide semiconductor with low density of defect states and stable characteristics. That is, variation in electric characteristics of the transistor 200 can be suppressed and reliability can be improved.
  • FIG. 22 illustrates an example of a memory device using the semiconductor device which is one embodiment of the present invention.
  • the memory device illustrated in FIG. 22 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.
  • the transistor 400 can control the second gate voltage of the transistor 200.
  • the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200.
  • the negative potential of the second gate of the transistor 200 is held in this structure, the first gate-source voltage and the second gate-source voltage of the transistor 400 are 0V.
  • the second gate voltage of the transistor 200 can be reduced even if power is not supplied to the transistor 200 and the transistor 400.
  • the negative potential can be maintained for a long time. Accordingly, the memory device including the transistor 200 and the transistor 400 can hold the memory content for a long time.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to a gate of the transistor 200, and the wiring 1006 is electrically connected to a back gate of the transistor 200. ..
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100 and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. ..
  • the wiring 1007 is electrically connected to a source of the transistor 400
  • the wiring 1008 is electrically connected to a gate of the transistor 400
  • the wiring 1009 is electrically connected to a back gate of the transistor 400
  • the wiring 1010 is a drain of the transistor 400. Is electrically connected to.
  • the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
  • the memory device shown in FIG. 22 can form a memory cell array by arranging the memory device shown in FIG. 22 in a matrix like the memory device shown in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the transistor 400 may be provided in a smaller number than the transistor 200. Further, in the memory device illustrated in FIG. 22, the transistor 200 and the transistor 400 can be sealed with the insulator 212 and the insulator 283 similarly to the memory device illustrated in FIG.
  • the transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel.
  • the transistor 400 includes a conductor 460 (a conductor 460a and a conductor 460b) which functions as a first gate, a conductor 405 which functions as a second gate, an insulator 222 which functions as a gate insulating layer, and an insulator.
  • 224 an insulator 450, an oxide 430c having a channel formation region, a conductor 442a, an oxide 443a, an oxide 431a, and an oxide 431b which function as a source, and a conductor 442b and an oxide which function as a drain.
  • the conductor 440 that functions as a plug (the conductor 440a and the conductor 440b)
  • the insulator 472 that functions as a barrier insulating film of the conductor 442 (the insulator 472a and The insulator 472b) and the insulator 473 (the insulator 473a and the insulator 473b) are included.
  • the conductor 405 is in the same layer as the conductor 205.
  • the oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b.
  • the conductor 442 is the same layer as the conductor 242.
  • the oxide 443 is the same layer as the oxide 243.
  • the oxide 430c is the same layer as the oxide 230c.
  • the insulator 450 is the same layer as the insulator 250.
  • the conductor 460 is the same layer as the conductor 260.
  • the conductor 440 is the same layer as the conductor 240.
  • the insulator 472 is the same layer as the insulator 272.
  • the insulator 473 is the same layer as the insulator 273.
  • the oxide 430c can be formed by processing an oxide film to be the oxide 230c.
  • the oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water. Accordingly, the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made extremely small.
  • an OS transistor including an oxide as a semiconductor
  • a capacitor according to one embodiment of the present invention
  • the storage device (hereinafter sometimes referred to as an OS memory device) that is installed will be described.
  • An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.
  • FIG. 23A shows an example of the configuration of the OS memory device.
  • the memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 has, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470 and will be described later in detail.
  • the amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440.
  • the row circuit 1420 has a row decoder, a word line driver circuit, and the like, for example, and can select a row to be accessed.
  • a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the memory device 1400 as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400.
  • the address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.
  • the control logic circuit 1460 processes input signals (CE, WE, RE) from the outside and generates control signals for the row decoder and the column decoder.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.
  • the memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the structure of the memory cell MC, the number of memory cells MC in one column, and the like. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in one row, and the like.
  • FIG. 23A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • a memory cell array 1470 may be provided so as to overlap part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap under the memory cell array 1470.
  • FIG. 24 illustrates a configuration example of a memory cell applicable to the above memory cell MC.
  • [DOSRAM] 24A to 24C show examples of circuit configurations of memory cells of DRAM.
  • a DRAM including a 1-OS transistor 1-capacitive element memory cell may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • the memory cell 1471 illustrated in FIG. 24A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a front gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected.
  • the second terminal of the capacitor CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable to apply a low-level potential to the wiring CAL at the time of writing and reading data.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the back gate of the transistor M1 may be connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a transistor having a single-gate structure, that is, a transistor M1 having no back gate, like the memory cell 1473 illustrated in FIG. 24C.
  • the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA.
  • the leak current of the transistor M1 can be made extremely low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-level data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced and the storage capacity of the memory cell can be reduced.
  • [NOSRAM] 24D to 24H show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 1474 illustrated in FIG. 24D includes the transistor M2, the transistor M3, and the capacitor CB.
  • the transistor M2 has a front gate (may be simply referred to as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected.
  • the second terminal of the capacitor CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable to apply a low-level potential to the wiring CAL during data writing, during data retention, and during data reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate.
  • the back gate of the transistor M2 may be connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a transistor having a single gate structure, that is, a transistor M2 having no back gate, like the memory cell 1476 illustrated in FIG. 24F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are integrated into one wiring BIL like the memory cell 1477 illustrated in FIG. 24G.
  • the transistor 200 can be used as the transistor M2
  • the transistor 300 can be used as the transistor M3
  • the capacitor 100 can be used as the capacitor CB.
  • an OS transistor as the transistor M2
  • the leak current of the transistor M2 can be made extremely low. Accordingly, the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-level data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter, also referred to as Si transistor).
  • the conductivity type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be stacked over the transistor M3, so that the area occupied by the memory cell can be reduced and high integration of the memory device can be achieved.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.
  • FIG. 24H shows an example of a gain cell type memory cell having three transistors and one capacitor.
  • the memory cell 1478 illustrated in FIG. 24H includes transistors M4 to M6 and the capacitor CC.
  • the capacitive element CC is provided as appropriate.
  • the memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL.
  • the wiring GNDL is a wiring which gives a low-level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured using only n-type transistors.
  • the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC.
  • the leak current of the transistor M4 can be made extremely low.
  • peripheral circuit 1411 the memory cell array 1470, and the like shown in this embodiment are not limited to the above. Arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.
  • FIGS. 4 An example of a chip 1200 in which a semiconductor device of the present invention is mounted is shown with reference to FIGS.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • the technique of integrating a plurality of circuits (systems) on a single chip in this way may be called a system on chip (SoC).
  • SoC system on chip
  • a chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, and one or more interfaces 1215. , One or a plurality of network circuits 1216 and the like.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • a bump (not shown) is provided on the chip 1200, and is connected to a first surface of a printed circuit board (Printed Circuit Board: PCB) 1201 as shown in FIG. 25B.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the mother board 1203.
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM described in any of the above embodiments can be used as the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory the above-mentioned NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention or a product-sum operation circuit, image processing and product-sum operation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided in the same chip, wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories included in the CPU 1211 and the GPU 1212, Further, after the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog-calculation unit 1213 may be provided with the product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used.
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network).
  • a circuit for network security may be included.
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be called a GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has the chip 1200 using the SoC technology, its size can be reduced. Moreover, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, portable (carry-out) game machines, and the like.
  • a product-sum operation circuit using the GPU 1212 allows deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), self-encoders, deep Boltzmann machines (DBM), deep belief networks ( Since it is possible to execute operations such as DBN), the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural networks
  • CNN convolutional neural networks
  • RNN recurrent neural networks
  • DBM deep Boltzmann machines
  • DBN deep belief networks
  • the semiconductor device described in any of the above embodiments is, for example, a storage device of various electronic devices (eg, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in any of the above embodiments is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, an SSD (solid state drive), or the like.
  • FIG. 26 schematically shows some configuration examples of the removable storage device.
  • the semiconductor device described in any of the above embodiments is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 26A is a schematic diagram of a USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 of the substrate 1104 or the like.
  • FIG. 26B is a schematic diagram of the external appearance of the SD card
  • FIG. 26C is a schematic diagram of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112, and a board 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip having a wireless communication function may be provided over the substrate 1113.
  • the data in the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 of the substrate 1113 or the like.
  • FIG. 26D is a schematic diagram of the external appearance of the SSD
  • FIG. 26E is a schematic diagram of the internal structure of the SSD.
  • the SSD 1150 has a housing 1151, a connector 1152, and a board 1153.
  • the substrate 1153 is housed in the housing 1151.
  • the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 of the substrate 1153 or the like.
  • the semiconductor device can be used for a processor such as a CPU or a GPU, or a chip.
  • FIG. 27 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.
  • the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and relatively large game machines such as pachinko machines.
  • digital signage digital signage
  • game machines such as pachinko machines.
  • electronic devices including screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be given.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one embodiment of the present invention may include an antenna. By receiving the signal with the antenna, images, information, and the like can be displayed on the display portion.
  • the antenna may be used for contactless power transmission.
  • the electronic device includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It has a function of measuring voltage, electric power, radiation, flow rate, humidity, gradient, vibration, odor or infrared light).
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), wireless communication It can have a function, a function of reading a program or data recorded in a recording medium, and the like.
  • FIG. 27 shows examples of electronic devices.
  • FIG. 27A illustrates a mobile phone (smartphone) that is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • a touch panel is provided in the display portion 5511 and a button is provided in the housing 5510 as an input interface.
  • the information terminal 5500 can execute an application utilizing artificial intelligence.
  • an application using artificial intelligence for example, an application for recognizing a conversation and displaying the content of the conversation on the display unit 5511, a character input by a user on a touch panel included in the display unit 5511, a figure, etc. are recognized, An application displayed on the display portion 5511, an application for biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
  • FIG. 27B shows a desktop information terminal 5300.
  • the desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the desktop information terminal 5300, new artificial intelligence can be developed.
  • a smartphone and a desktop information terminal are shown as examples of electronic devices in FIGS. 27A and 27B, but information terminals other than the smartphone and the desktop information terminal can be applied.
  • Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.
  • FIG. 27C shows an electric refrigerator-freezer 5800 which is an example of an electric appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
  • the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 has a function of automatically generating a menu based on the food items stored in the electric refrigerator-freezer 5800, the expiration date of the foodstuff, and the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature according to the food.
  • an electric refrigerator/freezer is described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, a microwave oven, a rice cooker, a water heater, an IH cooker, a water server, an air conditioner including an air conditioner. Examples include appliances, washing machines, dryers and audiovisual equipment.
  • FIG. 27D shows a portable game machine 5200 which is an example of a game machine.
  • the portable game machine has a housing 5201, a display portion 5202, buttons 5203, and the like.
  • the portable game machine 5200 By applying the GPU or the chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced by the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the mobile game machine 5200 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behaviors of the creatures appearing in the game, and the phenomena occurring in the game are determined by the program included in the game.
  • artificial intelligence to the portable game machine 5200, It enables expressions that are not limited to game programs. For example, it is possible to express that the content that the player asks, the progress of the game, the time, and the behavior of the person appearing in the game changes.
  • the artificial intelligence can configure the game player as an anthropomorphic person. You can play games.
  • FIG. 27D illustrates a portable game machine as an example of a game machine
  • the game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited to this.
  • a game machine to which the GPU or chip of one embodiment of the present invention is applied for example, a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), or a sports facility is installed. A pitching machine for batting practice.
  • the GPU or the chip of one embodiment of the present invention can be applied to an automobile that is a moving object and around a driver's seat of the automobile.
  • FIG. 27E1 shows an automobile 5700, which is an example of a moving body
  • FIG. 27E2 is a view showing the windshield and its surroundings in the interior of the automobile.
  • FIG. 27E2 illustrates a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard, and a display panel 5704 attached to a pillar.
  • the display panels 5701 to 5703 can provide various information by displaying speedometers, tachometers, mileage, fuel gauges, gear status, air conditioning settings, and the like. Further, display items and layouts displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
  • the display panels 5701 to 5703 can also be used as a lighting device.
  • the field of view (blind spot) blocked by the pillars can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated and safety can be improved. In addition, by displaying an image that complements the invisible portion, it is possible to confirm the safety more naturally and comfortably.
  • the display panel 5704 can also be used as a lighting device.
  • the chip can be used for an automatic driving system of an automobile 5700, for example.
  • the chip can be used in a system that performs road guidance, risk prediction, and the like. Information such as road guidance and risk prediction may be displayed on the display panels 5701 to 5704.
  • a car is described as an example of the moving body, but the moving body is not limited to a car.
  • the moving object a train, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), or the like can be given, and the chip of one embodiment of the present invention is applied to these moving objects.
  • a system using artificial intelligence can be added.
  • the GPU or chip of one embodiment of the present invention can be applied to a broadcasting system.
  • FIG. 27F schematically shows data transmission in the broadcasting system. Specifically, FIG. 27F shows a path through which a radio wave (broadcast signal) transmitted from the broadcasting station 5680 reaches a television receiver (TV) 5600 in each home.
  • the TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.
  • the antenna 5650 shows a UHF (Ultra High Frequency) antenna, but as the antenna 5650, a BS/110° CS antenna, a CS antenna, or the like can be applied.
  • UHF Ultra High Frequency
  • Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and a radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B.
  • the terrestrial TV broadcast can be viewed on the TV 5600 by receiving the radio wave 5675B with the antenna 5650.
  • the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 27F, and satellite broadcasting using artificial satellites, data broadcasting using optical lines, etc. may be used.
  • the broadcasting system described above may be a broadcasting system using artificial intelligence by applying the chip of one embodiment of the present invention.
  • the encoder compresses the broadcasting data
  • the decoder of the receiving device included in the TV 5600 decodes the broadcasting data. Restore is performed.
  • artificial intelligence it is possible to recognize a display pattern included in a display image in motion compensation prediction, which is one of encoder compression methods. It is also possible to perform intra-frame prediction using artificial intelligence. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, an image interpolation process such as up-conversion can be performed when the decoder restores the broadcast data.
  • the above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.
  • UHDTV ultra-high definition television
  • the TV 5600 may be provided with a recording device having artificial intelligence.
  • the program can be automatically recorded by allowing the recording apparatus to learn the user's preference by artificial intelligence.
  • the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, the effect, and the like can be appropriately combined with the description of other electronic devices.
  • a sample A and a sample B having a source electrode and a drain electrode of the transistor 200 are manufactured, a cross-sectional STEM image of the sample in a channel width direction is taken, and energy dispersive X-ray spectroscopy (EDX: Energy) is performed. Analysis by Dispersive X-ray spectroscopy was performed using "HD-2700" manufactured by Hitachi High-Technologies Corporation.
  • silicon oxynitride was formed into a film with a thickness of 300 nm on a silicon substrate by a CVD method.
  • a first tantalum nitride film was formed to a thickness of 20 nm by a sputtering method.
  • a first aluminum oxide film was formed to a thickness of 5 nm by the ALD method.
  • a second tantalum nitride film was formed to a thickness of 15 nm by the sputtering method.
  • a resist mask is formed by a lithography method, and using the resist mask as an etching mask, a part of the first tantalum nitride, a part of the first aluminum oxide, and a part of the second tantalum nitride are dry-etched. Etched by. Here, the resist mask was removed.
  • sample A a second aluminum oxide film having a thickness of 5 nm was formed by a sputtering method.
  • sample B a second aluminum oxide film having a thickness of 7 nm was formed by a sputtering method.
  • the sample A was divided into the sample A-1 and the sample A-2.
  • the sample B was divided into the sample B-1 and the sample B-2.
  • Samples A-2 and B-2 the second aluminum oxide and the second tantalum nitride were anisotropically etched by the dry etching method.
  • the anisotropic etching times of Sample A-2 and Sample B-2 were set according to the film thickness of the second aluminum oxide.
  • the aluminum distribution was observed by photographing a cross-sectional STEM image of the sample A-1, sample A-2, sample B-1, and sample B-2 in the channel width direction and EDX mapping analysis.
  • FIG. 28A shows a cross-sectional STEM image of Sample A-1
  • FIG. 28B shows the distribution of aluminum by EDX mapping analysis.
  • FIG. 29A shows a cross-sectional STEM image of Sample A-2
  • FIG. 29B shows an aluminum distribution by EDX mapping analysis.
  • FIG. 30A shows a cross-sectional STEM image of Sample B-1
  • FIG. 30B shows the distribution of aluminum by EDX mapping analysis.
  • FIG. 31A shows a cross-sectional STEM image of Sample B-2
  • FIG. 31B shows the distribution of aluminum by EDX mapping analysis.
  • the film thickness of the second aluminum oxide in Sample A-1 is 5 nm, but the first to third oxides on the silicon oxynitride, the first tantalum nitride, the It was found that the aluminum oxide of 1 and the tantalum nitride of the second layer were formed with good coverage.
  • the second aluminum oxide is at least the first to the third. It was confirmed that it was formed so as to be in contact with the side surface of the oxide and the side surface of the first tantalum nitride.
  • the thickness of the second aluminum oxide of Sample B-1 is 7 nm
  • the first to third oxides and the first tantalum nitride on the silicon oxynitride are used. It was found that a film was formed on the laminate of the first aluminum oxide and the second tantalum nitride with good coverage.
  • the second aluminum oxide is at least the first to the third. It was confirmed that it was formed so as to be in contact with the side surface of the oxide and the side surface of the first tantalum nitride.
  • the structure, the method, and the like described in this embodiment can be used in appropriate combination with the structure, the structure, the method, and the like described in other embodiment modes and other examples.

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Abstract

Provided is a semiconductor device having good electrical characteristics. The semiconductor device has a first oxide; a first conductor and a second conductor on the first oxide; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator on the first insulator and the second insulator; a fourth insulator in contact with a side surface of the first oxide and a side surface of the first conductor; a fifth insulator in contact with a side surface of the first oxide and a side surface of the second conductor; a second oxide disposed on the first oxide between the first conductor and the second conductor; a sixth insulator on the second oxide; a third conductor on the sixth insulator; and a seventh insulator respectively in contact with the upper surface of the third insulator, the upper surface of the second oxide, the upper surface of the sixth insulator, and the upper surface of the third conductor. The carrier concentration of a region of the first oxide in contact with the fourth insulator and the fifth insulator is higher than the carrier concentration of a region of the first oxide in contact with the second oxide.

Description

半導体装置、および半導体装置の作製方法Semiconductor device and method for manufacturing semiconductor device
　本発明の一態様は、半導体装置、ならびに半導体装置の作製方法に関する。または、本発明の一態様は、半導体ウエハ、モジュール、および電子機器に関する。 One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
　なお、本明細書等において半導体装置とは、半導体特性を利用することで機能し得る装置全般を指す。トランジスタなどの半導体素子をはじめ、半導体回路、演算装置、記憶装置は、半導体装置の一態様である。表示装置（液晶表示装置、発光表示装置など）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置、および電子機器などは、半導体装置を有すると言える場合がある。 Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one mode of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like can be said to have a semiconductor device. ..
　なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様は、物、方法、または、製造方法に関するものである。または、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物（コンポジション・オブ・マター）に関するものである。 Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
　近年、半導体装置の開発が進められ、ＬＳＩやＣＰＵやメモリが主に用いられている。ＣＰＵは、半導体ウエハから切り離された半導体集積回路（少なくともトランジスタ及びメモリ）を有し、接続端子である電極が形成された半導体素子の集合体である。 In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. The CPU is an assembly of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes which are connection terminals.
　ＬＳＩやＣＰＵやメモリなどの半導体回路（ＩＣチップ）は、回路基板、例えばプリント配線板に実装され、様々な電子機器の部品の一つとして用いられる。 Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of various electronic device components.
　また、絶縁表面を有する基板上に形成された半導体薄膜を用いてトランジスタを構成する技術が注目されている。該トランジスタは集積回路（ＩＣ）や画像表示装置（単に表示装置とも表記する）のような電子デバイスに広く応用されている。トランジスタに適用可能な半導体薄膜としてシリコン系半導体材料が広く知られているが、その他の材料として酸化物半導体が注目されている。 Also, attention is focused on the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
　また、酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流が小さいことが知られている。例えば、酸化物半導体を用いたトランジスタのリーク電流が低いという特性を応用した低消費電力のＣＰＵなどが開示されている（特許文献１参照。）。また、例えば、酸化物半導体を用いたトランジスタのリーク電流が低いという特性を応用して、長期にわたり記憶内容を保持することができる記憶装置などが、開示されている（特許文献２参照。）。 Also, it is known that a transistor using an oxide semiconductor has an extremely small leak current in a non-conducting state. For example, a low-power-consumption CPU or the like is disclosed in which a transistor including an oxide semiconductor has a low leak current (see Patent Document 1). In addition, for example, a memory device or the like which can hold stored data for a long time by applying the characteristic of a transistor including an oxide semiconductor, which has low leakage current, is disclosed (see Patent Document 2).
　また、近年では電子機器の小型化、軽量化に伴い、集積回路のさらなる高密度化への要求が高まっている。また、集積回路を含む半導体装置の生産性の向上が求められている。 Demands for higher density of integrated circuits have also increased in recent years as electronic devices have become smaller and lighter. Further, it is required to improve the productivity of semiconductor devices including integrated circuits.
特開２０１２−２５７１８７号公報JP 2012-257187 A 特開２０１１−１５１３８３号公報JP, 2011-151383, A
　本発明の一態様は、良好な電気特性を有する半導体装置を提供することを課題の一つとする。または、本発明の一態様は、ノーマリーオフの電気特性を有する半導体装置を提供することを課題の一つとする。または、本発明の一態様は、信頼性が良好な半導体装置を提供することを課題の一つとする。または、本発明の一態様は、オン電流が大きい半導体装置を提供することを課題の一つとする。または、本発明の一態様は、高い周波数特性を有する半導体装置を提供することを課題の一つとする。または、本発明の一態様は、微細化または高集積化が可能な半導体装置を提供することを課題の一つとする。または、本発明の一態様は、生産性の高い半導体装置を提供することを課題の一つとする。 One object of one embodiment of the present invention is to provide a semiconductor device having favorable electric characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device having normally-off electrical characteristics. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device with high productivity.
　本発明の一態様は、長期間においてデータの保持が可能な半導体装置を提供することを課題の一つとする。本発明の一態様は、情報の書き込み速度が速い半導体装置を提供することを課題の一つとする。本発明の一態様は、設計自由度が高い半導体装置を提供することを課題の一つとする。本発明の一態様は、消費電力を抑えることができる半導体装置を提供することを課題の一つとする。本発明の一態様は、新規な半導体装置を提供することを課題の一つとする。 One object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time. One object of one embodiment of the present invention is to provide a semiconductor device in which data writing speed is high. One object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. One object of one embodiment of the present invention is to provide a semiconductor device in which power consumption can be suppressed. One object of one embodiment of the present invention is to provide a novel semiconductor device.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。 Note that the description of these issues does not prevent the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. It should be noted that problems other than these are obvious from the description of the specification, drawings, claims, etc., and other problems can be extracted from the description of the specification, drawings, claims, etc. Is.
　本発明の一態様は、第１の酸化物と、第１の酸化物上の第１の導電体および第２の導電体と、第１の導電体上の第１の絶縁体と、第２の導電体上の第２の絶縁体と、第１の絶縁体および第２の絶縁体上の第３の絶縁体と、少なくとも第１の酸化物の側面、および第１の導電体の側面と接する第４の絶縁体と、少なくとも第１の酸化物の側面、および第２の導電体の側面と接する第５の絶縁体と、第１の酸化物上で、第１の導電体と第２の導電体の間に配置される第２の酸化物と、第２の酸化物上の第６の絶縁体と、第６の絶縁体上の第３の導電体と、第３の絶縁体の上面、第２の酸化物の上面、第６の絶縁体の上面、および第３の導電体の上面にそれぞれ接する、第７の絶縁体と、を有し、第１の酸化物の第４の絶縁体と接する領域のキャリア濃度は、第１の酸化物の第２の酸化物と接する領域のキャリア濃度よりも高く、第１の酸化物の第５の絶縁体と接する領域のキャリア濃度は、第１の酸化物の第２の酸化物と接する領域のキャリア濃度よりも高い半導体装置である。 One embodiment of the present invention includes a first oxide, a first conductor and a second conductor over the first oxide, a first insulator over the first conductor, and a second insulator over the second conductor. A second insulator on the conductor, a third insulator on the first insulator and the second insulator, at least a side surface of the first oxide, and a side surface of the first conductor. A fourth insulator which is in contact with the first insulator, a fifth insulator which is in contact with at least the side surface of the first oxide, and a side surface of the second conductor, and the first conductor and the second conductor which are on the first oxide. A second oxide disposed between the conductors of the second oxide, a sixth insulator on the second oxide, a third conductor on the sixth insulator, and a third insulator on the third insulator. A top surface of the first oxide, a top surface of the second oxide, a top surface of the sixth insulator, and a top surface of the third conductor. The carrier concentration of the region in contact with the insulator is higher than the carrier concentration of the region of the first oxide in contact with the second oxide, and the carrier concentration of the region of the first oxide in contact with the fifth insulator is: The semiconductor device has a higher carrier concentration than the region of the first oxide which is in contact with the second oxide.
　また、上記において、第４の絶縁体は、第３の絶縁体よりも酸素を透過し難く、第４の絶縁体は、第１の絶縁体よりも酸素を透過し易く、第５の絶縁体は、第３の絶縁体よりも酸素を透過し難く、第５の絶縁体は、第２の絶縁体よりも酸素を透過し易いことが好ましい。 Further, in the above, the fourth insulator is less likely to transmit oxygen than the third insulator, the fourth insulator is more likely to transmit oxygen than the first insulator, and the fifth insulator is It is preferable that oxygen is less likely to permeate oxygen than the third insulator, and that the fifth insulator is more likely to permeate oxygen than the second insulator.
　また、第４の絶縁体の膜密度は、第１の絶縁体の膜密度より低く、第５の絶縁体の膜密度は、第２の絶縁体の膜密度より低いことが好ましい。 The film density of the fourth insulator is preferably lower than that of the first insulator, and the film density of the fifth insulator is preferably lower than that of the second insulator.
　また、第４の絶縁体、および第５の絶縁体は、アルミニウム、マグネシウム、タンタルのいずれか一を含むことが好ましい。 Moreover, it is preferable that the fourth insulator and the fifth insulator include any one of aluminum, magnesium, and tantalum.
　また、第１の絶縁体、第２の絶縁体、第４の絶縁体、および第５の絶縁体は、酸化アルミニウムであることが好ましい。 Moreover, it is preferable that the first insulator, the second insulator, the fourth insulator, and the fifth insulator are aluminum oxide.
　また、本発明の他の一態様は、基板上に、第１の酸化膜、第１の導電膜、第１の絶縁膜、および第２の導電膜を順に成膜し、第１の酸化膜、第１の導電膜、第１の絶縁膜、および第２の導電膜を加工して、第１の酸化物、第１の導電体層、第１の絶縁体層、および第２の導電体層を形成し、第１の酸化物、第１の導電体層、第１の絶縁体層、および第２の導電体層を覆って、第２の絶縁膜を成膜し、第２の絶縁膜を異方性エッチングすることで、少なくとも第１の酸化物の側面、および第１の導電体層の側面に接する第１の絶縁体を形成し、第２の導電体層を除去し、第１の酸化物、第１の導電体層、および第１の絶縁体層を覆って、第３の絶縁膜を成膜し、第１の導電体層、第１の絶縁体層、第１の絶縁体および第３の絶縁膜に第１の酸化物が露出する開口を形成することで、第１の導電体、第２の導電体、第２の絶縁体、第３の絶縁体、第４の絶縁体、第５の絶縁体および第６の絶縁体を形成し、第２の酸化膜、第４の絶縁膜および第３の導電膜を順に成膜し、平坦化処理を行うことによって、第２の酸化膜、第４の絶縁膜および第３の導電膜を第６の絶縁体の一部が露出するまで除去し、第２の酸化物、第７の絶縁体および第３の導電体を形成し、第６の絶縁体、第２の酸化物、第７の絶縁体、および第３の導電体上に第５の絶縁膜を成膜する、半導体装置の作製方法である。 Another embodiment of the present invention is that a first oxide film, a first conductive film, a first insulating film, and a second conductive film are sequentially formed over a substrate to form a first oxide film. , The first conductive film, the first insulating film, and the second conductive film are processed to form a first oxide, a first conductor layer, a first insulator layer, and a second conductor. Forming a layer, covering the first oxide, the first conductor layer, the first insulator layer, and the second conductor layer, forming a second insulating film, and forming a second insulating film. The film is anisotropically etched to form a first insulator in contact with at least a side surface of the first oxide and a side surface of the first conductor layer, and removing the second conductor layer, A first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, a first insulating layer, and a first insulating layer. By forming an opening in which the first oxide is exposed in the insulator and the third insulating film, the first conductor, the second conductor, the second insulator, the third insulator, and the fourth insulator By forming the second insulating film, the fifth insulating film, the sixth insulating film, the second oxide film, the fourth insulating film, and the third conductive film in that order, and performing a planarization treatment. The second oxide film, the fourth insulating film, and the third conductive film are removed until a part of the sixth insulator is exposed, and the second oxide, the seventh insulator, and the third conductor are removed. Is formed, and a fifth insulating film is formed over the sixth insulator, the second oxide, the seventh insulator, and the third conductor, which is a method for manufacturing a semiconductor device.
　本発明の一態様により、良好な電気特性を有する半導体装置を提供することができる。または、本発明の一態様により、ノーマリーオフの電気特性を有する半導体装置を提供することができる。または、本発明の一態様により、信頼性が良好な半導体装置を提供することができる。または、本発明の一態様により、オン電流が大きい半導体装置を提供することができる。または、本発明の一態様により、高い周波数特性を有する半導体装置を提供することができる。または、本発明の一態様により、微細化または高集積化が可能な半導体装置を提供することができる。または、本発明の一態様により、生産性の高い半導体装置を提供することができる。 According to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having normally-off electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.
　または、長期間においてデータの保持が可能な半導体装置を提供することができる。または、データの書き込み速度が速い半導体装置を提供することができる。または、設計自由度が高い半導体装置を提供することができる。または、消費電力を抑えることができる半導体装置を提供することができる。または、新規な半導体装置を提供することができる。 Alternatively, a semiconductor device capable of holding data for a long period can be provided. Alternatively, a semiconductor device in which data writing speed is high can be provided. Alternatively, a semiconductor device with high design flexibility can be provided. Alternatively, a semiconductor device which can reduce power consumption can be provided. Alternatively, a novel semiconductor device can be provided.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally apparent from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the description of the specification, drawings, claims, etc. Is.
図１Ａは、本発明の一態様に係る半導体装置の上面図である。図１Ｂ乃至図１Ｄは、本発明の一態様に係る半導体装置の断面図である。
図２は本発明の一態様に係る半導体装置の断面図である。
図３Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図３Ｂ乃至図３Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図４Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図４Ｂ乃至図４Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図５Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図５Ｂ乃至図５Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図６Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図６Ｂ乃至図６Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図７Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図７Ｂ乃至図７Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図８Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図８Ｂ乃至図８Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図９Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図９Ｂ乃至図９Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１０Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１０Ｂ乃至図１０Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１１Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１１Ｂ乃至図１１Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１２Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１２Ｂ乃至図１２Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１３Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１３Ｂ乃至図１３Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１４Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１４Ｂ乃至図１４Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１５Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１５Ｂ乃至図１５Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１６Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１６Ｂ乃至図１６Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１７Ａは、本発明の一態様に係る半導体装置の作製方法を示す上面図である。図１７Ｂ乃至図１７Ｄは、本発明の一態様に係る半導体装置の作製方法を示す断面図である。
図１８Ａは、本発明の一態様に係る半導体装置の上面図である。図１８Ｂ乃至図１８Ｄは、本発明の一態様に係る半導体装置の断面図である。
図１９Ａは、本発明の一態様に係る半導体装置の上面図である。図１９Ｂ乃至図１９Ｄは、本発明の一態様に係る半導体装置の断面図である。
図２０Ａおよび図２０Ｂは、本発明の一態様に係る半導体装置の断面図である。
図２１は、本発明の一態様に係る記憶装置の構成を示す断面図である。
図２２は、本発明の一態様に係る記憶装置の構成を示す断面図である。
図２３Ａは、本発明の一態様に係る記憶装置の構成例を示すブロック図である。図２３Ｂは、本発明の一態様に係る記憶装置の構成を示す図である。
図２４Ａ乃至図２４Ｈは、本発明の一態様に係る記憶装置の構成例を示す回路図である。
図２５Ａは、本発明の一態様に係る半導体装置のブロック図である。図２５Ｂは、本発明の一態様に係る半導体装置の模式図である。
図２６Ａ乃至図２６Ｅは、本発明の一態様に係る記憶装置の模式図である。
図２７Ａ乃至図２７Ｆは、本発明の一態様に係る電子機器を示す図である。
図２８Ａは、本発明の実施例に係る試料のＳＴＥＭ像である。図２８Ｂは、本発明の実施例に係る試料のＥＤＸ分析結果を示す図である。
図２９Ａは、本発明の実施例に係る試料のＳＴＥＭ像である。図２９Ｂは、本発明の実施例に係る試料のＥＤＸ分析結果を示す図である。
図３０Ａは、本発明の実施例に係る試料のＳＴＥＭ像である。図３０Ｂは、本発明の実施例に係る試料のＥＤＸ分析結果を示す図である。
図３１Ａは、本発明の実施例に係る試料のＳＴＥＭ像である。図３１Ｂは、本発明の実施例に係る試料のＥＤＸ分析結果を示す図である。 FIG. 1A is a top view of a semiconductor device according to one embodiment of the present invention. 1B to 1D are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
FIG. 3A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 3B to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4B to 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 18A is a top view of a semiconductor device according to one embodiment of the present invention. 18B to 18D are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
FIG. 19A is a top view of a semiconductor device according to one embodiment of the present invention. 19B to 19D are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
20A and 20B are cross-sectional views of a semiconductor device according to one embodiment of the present invention.
21 is a cross-sectional view illustrating the structure of the memory device according to one embodiment of the present invention.
FIG. 22 is a cross-sectional view illustrating the structure of the memory device according to one embodiment of the present invention.
FIG. 23A is a block diagram illustrating a structural example of a storage device according to one embodiment of the present invention. FIG. 23B is a diagram showing a configuration of a storage device according to one embodiment of the present invention.
24A to 24H are circuit diagrams each illustrating a structural example of a memory device according to one embodiment of the present invention.
FIG. 25A is a block diagram of a semiconductor device according to one embodiment of the present invention. FIG. 25B is a schematic diagram of a semiconductor device according to one embodiment of the present invention.
26A to 26E are schematic views of a memory device according to one embodiment of the present invention.
27A to 27F are diagrams illustrating electronic devices according to one embodiment of the present invention.
FIG. 28A is a STEM image of a sample according to an example of the present invention. FIG. 28B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
FIG. 29A is a STEM image of a sample according to an example of the present invention. FIG. 29B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
FIG. 30A is a STEM image of a sample according to an example of the present invention. FIG. 30B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
FIG. 31A is a STEM image of a sample according to an example of the present invention. FIG. 31B is a diagram showing an EDX analysis result of the sample according to the example of the present invention.
　以下、実施の形態について図面を参照しながら説明する。ただし、実施の形態は多くの異なる態様で実施することが可能であり、趣旨およびその範囲から逸脱することなくその形態および詳細を様々に変更し得ることは、当業者であれば容易に理解される。したがって、本発明は、以下の実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiment can be implemented in many different modes, and the form and details thereof can be variously changed without departing from the spirit and the scope thereof. It Therefore, the present invention should not be construed as being limited to the description of the embodiments below.
　また、図面において、大きさ、層の厚さ、または領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。なお、図面は、理想的な例を模式的に示したものであり、図面に示す形状または値などに限定されない。例えば、実際の製造工程において、エッチングなどの処理により層やレジストマスクなどが意図せずに目減りすることがあるが、理解を容易とするために図に反映しないことがある。また、図面において、同一部分または同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する場合がある。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。 Also, in the drawings, the size, the layer thickness, or the region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer, a resist mask, or the like may be unintentionally reduced due to a process such as etching, but may not be reflected in the drawings for easy understanding. In the drawings, the same reference numerals are commonly used in different drawings for the same portions or portions having similar functions, and repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and may not be given a reference numeral.
　また、特に上面図（「平面図」ともいう）や斜視図などにおいて、発明の理解を容易とするため、一部の構成要素の記載を省略する場合がある。また、一部の隠れ線などの記載を省略する場合がある。 Also, in particular, in the top view (also referred to as “plan view”) and perspective view, some of the constituent elements may be omitted for easier understanding of the invention. In addition, description of some hidden lines may be omitted.
　また、本明細書等において、第１、第２等として付される序数詞は便宜上用いるものであり、工程順または積層順を示すものではない。そのため、例えば、「第１の」を「第２の」または「第３の」などと適宜置き換えて説明することができる。また、本明細書等に記載されている序数詞と、本発明の一態様を特定するために用いられる序数詞は一致しない場合がある。 Also, in this specification and the like, the ordinal numbers given as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, “first” can be replaced with “second” or “third” as appropriate. In addition, the ordinal numbers in this specification and the like and the ordinal numbers used to specify one embodiment of the present invention may not match.
　また、本明細書等において、「上に」、「下に」などの配置を示す語句は、構成同士の位置関係を、図面を参照して説明するために、便宜上用いている。また、構成同士の位置関係は、各構成を描写する方向に応じて適宜変化するものである。したがって、明細書で説明した語句に限定されず、状況に応じて適切に言い換えることができる。 In addition, in this specification and the like, terms such as “above” and “below” indicating a layout are used for convenience in order to explain the positional relationship between components with reference to the drawings. Further, the positional relationship between the components changes appropriately depending on the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, but can be paraphrased appropriately according to the situation.
　例えば、本明細書等において、ＸとＹとが接続されている、と明示的に記載されている場合は、ＸとＹとが電気的に接続されている場合と、ＸとＹとが機能的に接続されている場合と、ＸとＹとが直接的に接続されている場合とが、本明細書等に開示されているものとする。したがって、所定の接続関係、例えば、図または文章に示された接続関係に限定されず、図または文章に示された接続関係以外のものも、図または文章に開示されているものとする。 For example, in this specification and the like, when it is explicitly described that X and Y are connected, a case where X and Y are electrically connected and a case where X and Y function And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the drawing or the text, and other than the connection relation shown in the drawing or the text is also disclosed in the drawing or the text.
　ここで、Ｘ、Ｙは、対象物（例えば、装置、素子、回路、配線、電極、端子、導電膜、層、など）であるとする。 Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
　また、ソースやドレインの機能は、異なる極性のトランジスタを採用する場合や、回路動作において電流の方向が変化する場合などには入れ替わることがある。このため、本明細書等においては、ソースやドレインの用語は、入れ替えて用いることができる場合がある。 Also, the functions of the source and drain may be switched when adopting transistors of different polarities or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be interchanged in some cases.
　なお、本明細書等において、トランジスタの構造によっては、実際にチャネルの形成される領域（チャネル形成領域）におけるチャネル幅（以下、「実効的なチャネル幅」ともいう）と、トランジスタの上面図において示されるチャネル幅（以下、「見かけ上のチャネル幅」ともいう）と、が異なる場合がある。例えば、ゲートが半導体の側面を覆う場合、実効的なチャネル幅が、見かけ上のチャネル幅よりも大きくなり、その影響が無視できなくなる場合がある。例えば、微細かつゲートが半導体の側面を覆うトランジスタでは、半導体の側面に形成されるチャネル形成領域の割合が大きくなる場合がある。その場合は、見かけ上のチャネル幅よりも、実効的なチャネル幅の方が大きくなる。 Note that in this specification and the like, a channel width in a region where a channel is actually formed (a channel formation region) (hereinafter also referred to as an “effective channel width”) and a top view of the transistor depending on the structure of the transistor. The indicated channel width (hereinafter, also referred to as “apparent channel width”) may be different. For example, when the gate covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and the effect thereof may not be negligible. For example, in a transistor which is fine and whose gate covers a side surface of a semiconductor, the proportion of a channel formation region formed in the side surface of the semiconductor might be large. In that case, the effective channel width is larger than the apparent channel width.
　このような場合、実効的なチャネル幅の、実測による見積もりが困難となる場合がある。例えば、設計値から実効的なチャネル幅を見積もるためには、半導体の形状が既知という仮定が必要である。したがって、半導体の形状が正確にわからない場合には、実効的なチャネル幅を正確に測定することは困難である。 In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the semiconductor shape is known. Therefore, it is difficult to measure the effective channel width accurately when the shape of the semiconductor is not known accurately.
　本明細書では、単にチャネル幅と記載した場合には、見かけ上のチャネル幅を指す場合がある。または、本明細書では、単にチャネル幅と記載した場合には、実効的なチャネル幅を指す場合がある。なお、チャネル長、チャネル幅、実効的なチャネル幅、見かけ上のチャネル幅などは、断面ＴＥＭ像などを解析することなどによって、値を決定することができる。 In this specification, when simply described as channel width, it may indicate an apparent channel width. Alternatively, in the present specification, the term “channel width” may refer to an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
　なお、半導体の不純物とは、例えば、半導体を構成する主成分以外をいう。例えば、濃度が０．１原子％未満の元素は不純物と言える。不純物が含まれることにより、例えば、半導体のＤＯＳ（Ｄｅｎｓｉｔｙ　ｏｆ　Ｓｔａｔｅｓ）が高くなることや、結晶性が低下することなどが起こる場合がある。半導体が酸化物半導体である場合、半導体の特性を変化させる不純物としては、例えば、第１族元素、第２族元素、第１３族元素、第１４族元素、第１５族元素、および酸化物半導体の主成分以外の遷移金属などがあり、例えば、水素、リチウム、ナトリウム、シリコン、ホウ素、リン、炭素、窒素などがある。酸化物半導体の場合、水も不純物として機能する場合がある。また、酸化物半導体の場合、例えば不純物の混入によって酸素欠損を形成する場合がある。また、半導体がシリコンである場合、半導体の特性を変化させる不純物としては、例えば、酸素、水素を除く第１族元素、第２族元素、第１３族元素、第１５族元素などがある。 Note that the impurities of a semiconductor refer to, for example, components other than the main constituents of the semiconductor. For example, an element whose concentration is less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example, the DOS (Density of States) of the semiconductor may be increased and the crystallinity may be decreased. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed due to the mixture of impurities, for example. When the semiconductor is silicon, the impurities that change the characteristics of the semiconductor include, for example, a Group 1 element other than oxygen and hydrogen, a Group 2 element, a Group 13 element, and a Group 15 element.
　なお、本明細書等において、酸化窒化シリコンとは、その組成として、窒素よりも酸素の含有量が多いものである。また、窒化酸化シリコンとは、その組成として、酸素よりも窒素の含有量が多いものである。 Note that in this specification and the like, silicon oxynitride has a higher oxygen content than nitrogen as its composition. Further, silicon oxynitride has a composition containing more nitrogen than oxygen.
　また、本明細書等において、「絶縁体」という用語を、絶縁膜または絶縁層と言い換えることができる。また、「導電体」という用語を、導電膜または導電層と言い換えることができる。また、「半導体」という用語を、半導体膜または半導体層と言い換えることができる。 In addition, in this specification and the like, the term “insulator” can be restated as an insulating film or an insulating layer. In addition, the term "conductor" can be referred to as a conductive film or a conductive layer. Further, the term "semiconductor" can be restated as a semiconductor film or a semiconductor layer.
　また、本明細書等において、「平行」とは、二つの直線が−１０度以上１０度以下の角度で配置されている状態をいう。したがって、−５度以上５度以下の場合も含まれる。また、「略平行」とは、二つの直線が−３０度以上３０度以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０度以上１００度以下の角度で配置されている状態をいう。したがって、８５度以上９５度以下の場合も含まれる。また、「略垂直」とは、二つの直線が６０度以上１２０度以下の角度で配置されている状態をいう。 Also, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 degrees to 10 degrees. Therefore, a case of -5 degrees or more and 5 degrees or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Further, “vertical” means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
　なお、本明細書において、バリア膜とは、水、水素などの不純物および酸素の透過を抑制する機能を有する膜のことであり、当該バリア膜に導電性を有する場合は、導電性バリア膜と呼ぶことがある。 Note that in this specification, a barrier film refers to a film having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, and when the barrier film has conductivity, it is referred to as a conductive barrier film. May be called.
　本明細書等において、金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）とは、広い意味での金属の酸化物である。金属酸化物は、酸化物絶縁体、酸化物導電体（透明酸化物導電体を含む）、酸化物半導体（Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒまたは単にＯＳともいう）などに分類される。例えば、トランジスタの半導体層に金属酸化物を用いた場合、当該金属酸化物を酸化物半導体と呼称する場合がある。つまり、ＯＳ　ＦＥＴあるいはＯＳトランジスタと記載する場合においては、酸化物または酸化物半導体を有するトランジスタと換言することができる。 In this specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the term “OS FET” or “OS transistor” is used, it can be referred to as a transistor including an oxide or an oxide semiconductor.
　また、本明細書等において、ノーマリーオフとは、ゲートに電位を印加しない、またはゲートに接地電位を与えたときに、トランジスタに流れるチャネル幅１μｍあたりの電流が、室温において１×１０−２０Ａ以下、８５℃において１×１０−１８Ａ以下、または１２５℃において１×１０−１６Ａ以下であることをいう。 In this specification and the like, normally-off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the current per channel width of 1 μm flowing in the transistor is 1×10 −20 at room temperature. A or less, 1×10 −18 A or less at 85° C., or 1×10 −16 A or less at 125° C.
（実施の形態１）
　以下では、本発明の一態様に係るトランジスタ２００を有する半導体装置の一例、およびその作製方法について説明する。 (Embodiment 1)
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described.
＜半導体装置の構成例＞
　図１Ａ、図１Ｂ、図１Ｃ、および図１Ｄは、本発明の一態様に係るトランジスタ２００、およびトランジスタ２００周辺の上面図および断面図である。 <Example of configuration of semiconductor device>
1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention and a periphery of the transistor 200.
　図１Ａは、トランジスタ２００を有する半導体装置の上面図である。また、図１Ｂ、および図１Ｃは、当該半導体装置の断面図である。ここで、図１Ｂは、図１ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、図１Ｃは、図１ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、図１Ｄは、図１ＡにＡ５−Ａ６の一点鎖線で示す部位の断面図である。なお、図１Ａの上面図では、図の明瞭化のために一部の要素を省いている。 FIG. 1A is a top view of a semiconductor device having a transistor 200. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion indicated by dashed-dotted line A1-A2 in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel length direction. 1C is a cross-sectional view of a portion indicated by dashed-dotted line A3-A4 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel width direction. Further, FIG. 1D is a cross-sectional view of a portion indicated by a chain line of A5-A6 in FIG. 1A. In the top view of FIG. 1A, some elements are omitted for the sake of clarity.
　本発明の一態様の半導体装置は、基板（図示せず）上の絶縁体２１２と、絶縁体２１２上の絶縁体２１４と、絶縁体２１４上のトランジスタ２００と、トランジスタ２００上の絶縁体２８０と、絶縁体２８０上の絶縁体２８２と、絶縁体２８２上の絶縁体２８３と、絶縁体２８３上の絶縁体２７４と、を有する。絶縁体２１２、絶縁体２１４、絶縁体２８０、絶縁体２８２、絶縁体２８３、および絶縁体２７４は層間膜として機能する。また、トランジスタ２００と電気的に接続し、プラグとして機能する導電体２４０（導電体２４０ａ、および導電体２４０ｂ）とを有する。なお、プラグとして機能する導電体２４０の側面に接して絶縁体２４１（絶縁体２４１ａ、および絶縁体２４１ｂ）が設けられる。また、絶縁体２７４上、および導電体２４０上には、導電体２４０と電気的に接続し、配線として機能する導電体２４６（導電体２４６ａ、および導電体２４６ｂ）が設けられる。 A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, and an insulator 280 over the transistor 200. , An insulator 282 over the insulator 280, an insulator 283 over the insulator 282, and an insulator 274 over the insulator 283. The insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, and the insulator 274 function as an interlayer film. In addition, a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and serves as a plug is included. Note that the insulator 241 (the insulator 241a and the insulator 241b) is provided in contact with the side surface of the conductor 240 which functions as a plug. Further, a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and serves as a wiring is provided over the insulator 274 and the conductor 240.
　また、絶縁体２７２、絶縁体２８０、絶縁体２８２、絶縁体２８３、および絶縁体２７４の開口の内壁に接して絶縁体２４１ａが設けられ、その側面に接して導電体２４０ａの第１の導電体が設けられ、さらに内側に導電体２４０ａの第２の導電体が設けられている。また、絶縁体２７２、絶縁体２８０、絶縁体２８２、絶縁体２８３、および絶縁体２７４の開口の内壁に接して絶縁体２４１ｂが設けられ、その側面に接して導電体２４０ｂの第１の導電体が設けられ、さらに内側に導電体２４０ｂの第２の導電体が設けられている。ここで、導電体２４０の上面の高さと、絶縁体２７４の上面の高さは同程度にできる。なお、トランジスタ２００では、導電体２４０の第１の導電体および導電体２４０の第２の導電体を積層する構成について示しているが、本発明はこれに限られるものではない。例えば、導電体２４０を単層、または３層以上の積層構造として設ける構成にしてもよい。構造体が積層構造を有する場合、形成順に序数を付与し、区別する場合がある。 Further, an insulator 241a is provided in contact with the inner walls of the openings of the insulator 272, the insulator 280, the insulator 282, the insulator 283, and the insulator 274, and the first conductor of the conductor 240a is provided in contact with the side surface thereof. Is provided, and the second conductor of the conductor 240a is further provided inside. Further, an insulator 241b is provided in contact with the inner walls of the openings of the insulator 272, the insulator 280, the insulator 282, the insulator 283, and the insulator 274, and the first conductor of the conductor 240b is provided in contact with the side surface thereof. And a second conductor of the conductor 240b is further provided inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 274 can be approximately the same. Although the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may have a single-layer structure or a stacked structure including three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
　また、図１に示すように、本実施の形態に示すトランジスタ２００は、絶縁体２１２上に形成され、上面と側面が絶縁体２８３に覆われていることが好ましい。さらに、上面視において、絶縁体２８３と絶縁体２１２は、トランジスタ２００の外側で接している構造とし、絶縁体２８３と絶縁体２１２でトランジスタ２００が封止されていることが好ましい。 Further, as shown in FIG. 1, it is preferable that the transistor 200 described in this embodiment be formed over an insulator 212 and have an upper surface and a side surface covered with the insulator 283. Further, in a top view, the insulator 283 and the insulator 212 are in contact with each other outside the transistor 200, and the transistor 200 is preferably sealed with the insulator 283 and the insulator 212.
［トランジスタ２０］
　図１に示すように、トランジスタ２００は、絶縁体２１４上の絶縁体２１６と、絶縁体２１６に埋め込まれるように配置された導電体２０５（導電体２０５ａ、および導電体２０５ｂ）と、絶縁体２１６上、および導電体２０５上の絶縁体２２２と、絶縁体２２２上の絶縁体２２４と、絶縁体２２４上の酸化物２３０ａと、酸化物２３０ａ上の酸化物２３０ｂと、酸化物２３０ｂ上の酸化物２４３ａおよび酸化物２４３ｂと、酸化物２４３ａ上の導電体２４２ａと、酸化物２４３ｂ上の導電体２４２ｂと、導電体２４２ａ上の絶縁体２７２ａと、導電体２４２ｂ上の絶縁体２７２ｂと、絶縁体２２４上に位置し、少なくとも酸化物２３０ａの側面、酸化物２３０ｂの側面、酸化物２４３ａの側面、および導電体２４２ａの側面にそれぞれ接する絶縁体２７３ａと、絶縁体２２４上に位置し、少なくとも酸化物２３０ａの側面、酸化物２３０ｂの側面、酸化物２４３ｂの側面、および導電体２４２ｂの側面にそれぞれ接する絶縁体２７３ｂと、酸化物２３０ｂ上の酸化物２３０ｃと、酸化物２３０ｃ上の絶縁体２５０と、絶縁体２５０上に位置し、酸化物２３０ｃと重なる導電体２６０（導電体２６０ａ、および導電体２６０ｂ）と、を有する。また、酸化物２３０ｃは、酸化物２４３ａの側面、酸化物２４３ｂの側面、導電体２４２ａの側面および導電体２４２ｂの側面とそれぞれ接する。導電体２６０は、導電体２６０ａおよび導電体２６０ｂを有し、導電体２６０ｂの底面および側面を包むように導電体２６０ａが配置される。ここで、図１Ｂに示すように、導電体２６０の上面は、絶縁体２５０の上面および酸化物２３０ｃの上面と略一致して配置される。また、絶縁体２８２は、導電体２６０、絶縁体２５０、酸化物２３０ｃ、および絶縁体２８０のそれぞれの上面と接する。 [Transistor 20]
As illustrated in FIG. 1, the transistor 200 includes an insulator 216 over an insulator 214, a conductor 205 (a conductor 205 a, and a conductor 205 b) which is arranged so as to be embedded in the insulator 216 and an insulator 216. An insulator 222 over the conductor 205, an insulator 224 over the insulator 222, an oxide 230a over the insulator 224, an oxide 230b over the oxide 230a, and an oxide over the oxide 230b. 243a and the oxide 243b, the conductor 242a on the oxide 243a, the conductor 242b on the oxide 243b, the insulator 272a on the conductor 242a, the insulator 272b on the conductor 242b, and the insulator 224. An insulator 273a which is located above and is in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243a, and the side surface of the conductor 242a; The insulator 273b, the oxide 230b on the oxide 230c, the insulator 230b on the oxide 230b, the insulator 230b on the oxide 230b, and the insulator 250 on the oxide 230c. A conductor 260 (a conductor 260a and a conductor 260b) which is located over the body 250 and overlaps with the oxide 230c. The oxide 230c is in contact with the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, and the side surface of the conductor 242b, respectively. The conductor 260 has a conductor 260a and a conductor 260b, and the conductor 260a is arranged so as to cover the bottom surface and the side surface of the conductor 260b. Here, as shown in FIG. 1B, the upper surface of the conductor 260 is arranged so as to substantially coincide with the upper surfaces of the insulator 250 and the oxide 230c. The insulator 282 is in contact with the top surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280, respectively.
　なお、以下において、酸化物２４３ａと酸化物２４３ｂをまとめて酸化物２４３と呼ぶ場合がある。また、導電体２４２ａと導電体２４２ｂをまとめて導電体２４２と呼ぶ場合がある。また、導電体２４２ａと導電体２４２ｂをまとめて導電体２４２と呼ぶ場合がある。また、絶縁体２７２ａと絶縁体２７２ｂをまとめて絶縁体２７２と呼ぶ場合がある。また、絶縁体２７３ａと絶縁体２７３ｂをまとめて絶縁体２７３と呼ぶ場合がある。 Note that, hereinafter, the oxide 243a and the oxide 243b may be collectively referred to as the oxide 243. Further, the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242. Further, the conductor 242a and the conductor 242b may be collectively referred to as a conductor 242. Further, the insulator 272a and the insulator 272b may be collectively referred to as an insulator 272. Further, the insulator 273a and the insulator 273b may be collectively referred to as an insulator 273.
　トランジスタ２００において、導電体２６０は、トランジスタのゲートとして機能し、導電体２４２ａおよび導電体２４２ｂは、それぞれソース電極またはドレイン電極として機能する。トランジスタ２００は、ゲートとして機能する導電体２６０が、絶縁体２８０などによって形成される開口を埋めるように自己整合的に形成される。導電体２６０をこのように形成することにより、導電体２４２ａと導電体２４２ｂの間の領域に、導電体２６０を位置合わせすることなく確実に配置することができる。 In the transistor 200, the conductor 260 functions as a gate of the transistor, and the conductors 242a and 242b function as a source electrode and a drain electrode, respectively. The transistor 200 is formed in a self-aligned manner so that the conductor 260 functioning as a gate fills an opening formed by the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without alignment.
　また、絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３の少なくとも一は、水素（例えば、水素原子、水素分子などの少なくとも一）または水分子の拡散を抑制する機能を有することが好ましい。特に、絶縁体２１２および絶縁体２８３は、水素（例えば、水素原子、水素分子などの少なくとも一）または水分子の拡散を抑制する機能が高いことが好ましい。また、絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３の少なくとも一は、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有することが好ましい。例えば、絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３の少なくとも一は、絶縁体２２４よりも酸素および水素の一方または双方の透過性が低いことが好ましい。絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３の少なくとも一は、絶縁体２５０よりも酸素および水素の一方または双方の透過性が低いことが好ましい。絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３の少なくとも一は、絶縁体２８０よりも酸素および水素の一方または双方の透過性が低いことが好ましい。 Further, at least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 is hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, or the like) or a diffusion of water molecules. It is preferable to have a function of suppressing In particular, the insulator 212 and the insulator 283 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms and hydrogen molecules) or water molecules. Further, at least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 suppresses diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules). It is preferable to have a function. For example, at least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 has lower permeability of one or both of oxygen and hydrogen than the insulator 224. preferable. At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 preferably has lower permeability of one or both of oxygen and hydrogen than the insulator 250. At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 preferably has lower permeability of one or both of oxygen and hydrogen than the insulator 280.
　絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３としては、例えば、酸化アルミニウム、酸化ハフニウム、酸化ガリウム、インジウムガリウム亜鉛酸化物、窒化シリコン、または窒化酸化シリコンなどを用いることができる。特に、絶縁体２１２および絶縁体２８３としては、より水素バリア性が高い、窒化シリコンまたは窒化酸化シリコンを用いることが好ましい。 As the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or oxynitride is used. Silicon or the like can be used. In particular, as the insulator 212 and the insulator 283, silicon nitride or silicon nitride oxide, which has a higher hydrogen barrier property, is preferably used.
　また、図１に示すように、本実施の形態に示す半導体装置の一態様では、絶縁体２１４、絶縁体２１６、絶縁体２２２、絶縁体２２４、絶縁体２８０、および絶縁体２８２がパターニングされており、絶縁体２８３がこれらを覆う構造になっている。つまり、絶縁体２８３は、絶縁体２８２の上面、絶縁体２８２の側面、絶縁体２８０の側面、絶縁体２２４の側面、絶縁体２２２の側面、絶縁体２１６の側面、絶縁体２１４の側面、および絶縁体２１２の上面にそれぞれ接する。これにより、酸化物２３０などを含む、絶縁体２１４、絶縁体２１６、絶縁体２２２、絶縁体２２４、絶縁体２８０、および絶縁体２８２は、絶縁体２８３と絶縁体２１２によって、外部から隔離される。 Further, as shown in FIG. 1, in one mode of the semiconductor device described in this embodiment, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 are patterned. The insulator 283 has a structure that covers them. That is, the insulator 283 includes a top surface of the insulator 282, a side surface of the insulator 282, a side surface of the insulator 280, a side surface of the insulator 224, a side surface of the insulator 222, a side surface of the insulator 216, a side surface of the insulator 214, and It contacts the upper surface of the insulator 212, respectively. Accordingly, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 including the oxide 230 and the like are isolated from the outside by the insulator 283 and the insulator 212. ..
　また、酸化物２３０は、絶縁体２２４上の酸化物２３０ａと、酸化物２３０ａ上の酸化物２３０ｂと、酸化物２３０ｂ上に配置され、少なくとも一部が酸化物２３０ｂの上面に接する酸化物２３０ｃと、を有することが好ましい。ここで、酸化物２３０ｃの側面は、酸化物２４３ａ、酸化物２４３ｂ、導電体２４２ａ、導電体２４２ｂ、絶縁体２７２ａ、絶縁体２７２ｂ、および絶縁体２８０に接して設けられていることが好ましい。 Further, the oxide 230 includes an oxide 230a over the insulator 224, an oxide 230b over the oxide 230a, and an oxide 230c which is disposed over the oxide 230b and at least part of which is in contact with the top surface of the oxide 230b. It is preferable to have Here, the side surface of the oxide 230c is preferably provided in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272a, the insulator 272b, and the insulator 280.
　なお、トランジスタ２００では、チャネル形成領域と、その近傍において、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃの３層を積層する構成について示しているが、本発明はこれに限られるものではない。例えば、酸化物２３０ｂの単層、酸化物２３０ｂと酸化物２３０ａの２層構造、酸化物２３０ｂと酸化物２３０ｃの２層構造、または４層以上の積層構造を設ける構成にしてもよい。例えば、酸化物２３０ｃを２層構造にして、４層の積層構造を設ける構成にしてもよい。 Although the transistor 200 has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in the channel formation region and the vicinity thereof, the present invention is not limited to this. .. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided. For example, the oxide 230c may have a two-layer structure and a four-layer stacked structure may be provided.
　トランジスタ２００は、チャネル形成領域を含む酸化物２３０（酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃ）に、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう）を用いることが好ましい。例えば、酸化物半導体として機能する金属酸化物は、エネルギーギャップが２ｅＶ以上、好ましくは２．５ｅＶ以上のものを用いることが好ましい。このように、エネルギーギャップの大きい金属酸化物を用いることで、トランジスタ２００の非導通状態におけるリーク電流（オフ電流）を極めて小さくすることができる。このようなトランジスタを用いることで、低消費電力の半導体装置を提供できる。 In the transistor 200, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is used for the oxide 230 including the channel formation region (the oxide 230a, the oxide 230b, and the oxide 230c). preferable. For example, as a metal oxide which functions as an oxide semiconductor, an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used. By using a metal oxide having a large energy gap in this manner, leakage current (off current) in the non-conduction state of the transistor 200 can be extremely reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.
　例えば、酸化物２３０として、Ｉｎ−Ｍ−Ｚｎ酸化物（元素Ｍは、アルミニウム、ガリウム、イットリウム、錫、銅、バナジウム、ベリリウム、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種）等の金属酸化物を用いるとよい。特に、元素Ｍは、アルミニウム、ガリウム、イットリウム、または錫を用いるとよい。また、酸化物２３０として、Ｉｎ−Ｍ酸化物、Ｉｎ−Ｚｎ酸化物、またはＭ−Ｚｎ酸化物を用いてもよい。 For example, as the oxide 230, an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium). , One kind or plural kinds selected from neodymium, hafnium, tantalum, tungsten, magnesium and the like) may be used. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. Alternatively, as the oxide 230, an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used.
　酸化物２３０は、酸化物２３０ａと、酸化物２３０ａ上の酸化物２３０ｂと、酸化物２３０ｂ上の酸化物２３０ｃと、を有する。酸化物２３０ｂ下に酸化物２３０ａを有することで、酸化物２３０ａよりも下方に形成された構造物から、酸化物２３０ｂへの不純物の拡散を抑制することができる。また、酸化物２３０ｂ上に酸化物２３０ｃを有することで、酸化物２３０ｃよりも上方に形成された構造物から、酸化物２３０ｂへの不純物の拡散を抑制することができる。 The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By including the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a into the oxide 230b can be suppressed. Further, by including the oxide 230c over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.
　なお、酸化物２３０は、各金属原子の原子数比が異なる複数の酸化物層の積層構造を有することが好ましい。具体的には、酸化物２３０ａに用いる金属酸化物において、構成元素中の元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、構成元素中の元素Ｍの原子数比より、大きいことが好ましい。また、酸化物２３０ａに用いる金属酸化物において、Ｉｎに対する元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、Ｉｎに対する元素Ｍの原子数比より大きいことが好ましい。また、酸化物２３０ｂに用いる金属酸化物において、元素Ｍに対するＩｎの原子数比が、酸化物２３０ａに用いる金属酸化物における、元素Ｍに対するＩｎの原子数比より大きいことが好ましい。また、酸化物２３０ｃは、酸化物２３０ａまたは酸化物２３０ｂに用いることができる金属酸化物を、用いることができる。 The oxide 230 preferably has a laminated structure of a plurality of oxide layers in which the atomic ratio of each metal atom is different. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is higher than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Preferably. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide which can be used for the oxide 230a or the oxide 230b can be used.
　具体的には、酸化物２３０ａとして、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］、または１：１：０．５［原子数比］の金属酸化物を用いればよい。また、酸化物２３０ｂとして、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３［原子数比］、または１：１：１［原子数比］の金属酸化物を用いればよい。また、酸化物２３０ｃとして、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］、Ｇａ：Ｚｎ＝２：１［原子数比］、またはＧａ：Ｚｎ＝２：５［原子数比］の金属酸化物を用いればよい。また、酸化物２３０ｃを積層構造とする場合の具体例としては、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３［原子数比］と、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］との積層構造、Ｇａ：Ｚｎ＝２：１［原子数比］と、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３［原子数比］との積層構造、Ｇａ：Ｚｎ＝２：５［原子数比］と、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３［原子数比］との積層構造、酸化ガリウムと、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３［原子数比］との積層構造などが挙げられる。 Specifically, a metal oxide of In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used as the oxide 230a. Further, as the oxide 230b, a metal oxide of In:Ga:Zn=4:2:3 [atomic ratio] or 1:1:1 [atomic ratio] may be used. As the oxide 230c, In:Ga:Zn=1:3:4 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio]. The above metal oxide may be used. In addition, as a specific example of the case where the oxide 230c has a stacked structure, In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio]. ], a laminated structure of Ga:Zn=2:1 [atomic ratio] and In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:5 [atomic] Number ratio] and In:Ga:Zn=4:2:3 [atomic ratio], and gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio]. And so on.
　また、酸化物２３０ｂは、結晶性を有することが好ましい。例えば、後述するＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）を用いることが好ましい。ＣＡＡＣ−ＯＳなどの結晶性を有する酸化物は、不純物や欠陥（酸素欠損など）が少なく、結晶性の高い、緻密な構造を有している。よって、ソース電極またはドレイン電極による、酸化物２３０ｂからの酸素の引き抜きを抑制することができる。これにより、加熱処理を行っても、酸化物２３０ｂから酸素が引き抜かれることを低減できるので、トランジスタ２００は、製造工程における高い温度（所謂サーマルバジェット）に対して安定である。 The oxide 230b preferably has crystallinity. For example, it is preferable to use a CAAC-OS (c-axis aligned crystalline oxide semiconductor) described later. An oxide having crystallinity such as CAAC-OS has few impurities and defects (such as oxygen vacancies), has high crystallinity, and has a dense structure. Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even if heat treatment is performed, oxygen extraction from the oxide 230b can be reduced, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in a manufacturing process.
　また、酸化物２３０ａおよび酸化物２３０ｃの伝導帯下端のエネルギーが、酸化物２３０ｂの伝導帯下端のエネルギーより高くなることが好ましい。また、言い換えると、酸化物２３０ａおよび酸化物２３０ｃの電子親和力が、酸化物２３０ｂの電子親和力より小さいことが好ましい。 Further, it is preferable that the energy at the bottom of the conduction band of the oxides 230a and 230c be higher than the energy at the bottom of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c be smaller than the electron affinity of the oxide 230b.
　ここで、電子親和力または伝導帯下端のエネルギー準位Ｅｃは、真空準位と価電子帯上端のエネルギーＥｖとの差であるイオン化ポテンシャルＩｐと、エネルギーギャップＥｇから求めることができる。イオン化ポテンシャルＩｐは、例えば、紫外線光電子分光分析（ＵＰＳ：Ｕｌｔｒａｖｉｏｌｅｔ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）装置を用いて測定することができる。エネルギーギャップＥｇは、例えば、分光エリプソメータを用いて測定することができる。 Here, the electron affinity or the energy level Ec at the bottom of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg. The ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) device. The energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.
　また、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃの接合部において、伝導帯下端のエネルギー準位はなだらかに変化する。換言すると、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃの接合部における伝導帯下端のエネルギー準位は、連続的に変化または連続接合するともいうことができる。このようにするためには、酸化物２３０ａと酸化物２３０ｂとの界面、および酸化物２３０ｂと酸化物２３０ｃとの界面において形成される混合層の欠陥準位密度を低くするとよい。 In addition, the energy level at the bottom of the conduction band changes gently at the junction of the oxide 230a, the oxide 230b, and the oxide 230c. In other words, it can be said that the energy level at the bottom of the conduction band in the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuously changed or continuously joined. In order to do so, it is preferable that the density of defect states in the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c be low.
　また、キャリアの主たる経路は酸化物２３０ｂとなる。酸化物２３０ａ、酸化物２３０ｃを上述の構成とすることで、酸化物２３０ａと酸化物２３０ｂとの界面、および酸化物２３０ｂと酸化物２３０ｃとの界面における欠陥準位密度を低くすることができる。そのため、界面散乱によるキャリア伝導への影響が小さくなり、トランジスタ２００は高いオン電流、および高い周波数特性を得ることができる。 Also, the main carrier path is the oxide 230b. With the oxide 230a and the oxide 230c having the above structures, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can have high on-state current and high frequency characteristics.
　酸化物２３０（例えば、酸化物２３０ｂ）には、キャリア濃度の低い酸化物半導体を用いることが好ましい。酸化物半導体のキャリア濃度を低くする場合においては、酸化物半導体中の不純物濃度を低くし、欠陥準位密度を低くすればよい。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性または実質的に高純度真性という。なお、酸化物半導体中の不純物としては、例えば、水素、窒素、アルカリ金属、アルカリ土類金属、鉄、ニッケル、シリコン等がある。 It is preferable to use an oxide semiconductor having a low carrier concentration for the oxide 230 (eg, the oxide 230b). In the case of reducing the carrier concentration of the oxide semiconductor, the concentration of impurities in the oxide semiconductor may be lowered and the density of defect states may be lowered. In this specification and the like, low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.
　特に、酸化物半導体に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸化物半導体中に酸素欠損（ＶＯ：ｏｘｙｇｅｎ　ｖａｃａｎｃｙともいう）を形成する場合がある。さらに、酸素欠損に水素が入った欠陥（以下、ＶＯＨと呼ぶ場合がある。）はドナーとして機能し、キャリアである電子が生成されることがある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成する場合がある。従って、水素が多く含まれている酸化物半導体を用いたトランジスタは、ノーマリーオン特性となりやすい。また、酸化物半導体中の水素は、熱、電界などのストレスによって動きやすいため、酸化物半導体に多くの水素が含まれると、トランジスタの信頼性が悪化する恐れもある。 In particular, hydrogen contained in an oxide semiconductor reacts with oxygen which is bonded to a metal atom to be water, which might cause oxygen deficiency (also referred to as V 2 O :oxygenvacancy) in the oxide semiconductor. Further, a defect in which hydrogen is contained in an oxygen vacancy (hereinafter, also referred to as V OH ) may function as a donor and an electron which is a carrier may be generated. In addition, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor which contains a large amount of hydrogen is likely to have normally-on characteristics. Further, hydrogen in an oxide semiconductor is likely to move due to stress such as heat and an electric field; therefore, when a large amount of hydrogen is contained in the oxide semiconductor, reliability of the transistor might be deteriorated.
　ＶＯＨは、酸化物半導体のドナーとして機能しうる。しかしながら、当該欠陥を定量的に評価することは困難である。そこで、酸化物半導体においては、ドナー濃度ではなく、キャリア濃度で評価される場合がある。よって、本明細書等では、酸化物半導体のパラメータとして、ドナー濃度ではなく、電界が印加されない状態を想定したキャリア濃度を用いる場合がある。つまり、本明細書等に記載の「キャリア濃度」は、「ドナー濃度」と言い換えることができる場合がある。 V OH can function as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Therefore, the oxide semiconductor may be evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, a carrier concentration which is assumed to be a state where no electric field is applied may be used as a parameter of the oxide semiconductor, instead of the donor concentration. That is, the “carrier concentration” described in this specification and the like can be called the “donor concentration” in some cases.
　以上より、酸化物半導体を酸化物２３０に用いる場合、酸化物２３０中のＶＯＨをできる限り低減し、高純度真性または実質的に高純度真性にすることが好ましい。このように、ＶＯＨが十分低減された酸化物半導体を得るには、酸化物半導体中の水分、水素などの不純物を除去すること（脱水、脱水素化処理と記載する場合がある。）と、酸化物半導体に酸素を供給して酸素欠損を補填すること（加酸素化処理と記載する場合がある。）が重要である。ＶＯＨなどの不純物が十分に低減された酸化物半導体をトランジスタのチャネル形成領域に用いることで、安定した電気特性を付与することができる。 From the above, the case of using an oxide semiconductor in the oxide 230, reduced as much as possible V O H in the oxide 230, it is preferable that the highly purified intrinsic or substantially highly purified intrinsic. Thus, the V O H to obtain a sufficiently reduced oxide semiconductor, the moisture in the oxide semiconductor, to remove impurities such as hydrogen (dehydration, may be described as dehydrogenation.) Then, it is important to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygenation treatment). The V O H oxide semiconductor impurity is sufficiently reduced such by using a channel formation region of the transistor, it is possible to have stable electrical characteristics.
　また、酸化物２３０に酸化物半導体を用いる場合、チャネル形成領域として機能する領域の酸化物半導体のキャリア濃度は、１×１０１８ｃｍ−３以下であることが好ましく、１×１０１７ｃｍ−３未満であることがより好ましく、１×１０１６ｃｍ−３未満であることがさらに好ましく、１×１０１３ｃｍ−３未満であることがさらに好ましく、１×１０１２ｃｍ−３未満であることがさらに好ましい。なお、チャネル形成領域として機能する領域の酸化物半導体のキャリア濃度の下限値については、特に限定は無いが、例えば、１×１０−９ｃｍ−３とすることができる。 In the case where an oxide semiconductor is used for the oxide 230, the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1×10 18 cm −3 or lower, and 1×10 17 cm −3. Is less than 1×10 16 cm −3 , more preferably less than 1×10 13 cm −3 , further preferably less than 1×10 12 cm −3. More preferable. Note that there is no particular limitation on the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region, but it can be set to, for example, 1×10 −9 cm −3 .
　また、水素原子を含まない、または水素原子の含有量が少ない、原料ガスを用いて、層間絶縁膜（絶縁体２１６、絶縁体２７４、絶縁体２８０など）、およびゲート絶縁膜（絶縁体２２４、絶縁体２５０など）を成膜することで、これらの絶縁膜に含まれる水素濃度を低減し、酸化物半導体のチャネル形成領域に混入する水素の低減を図ってもよい。 In addition, an interlayer insulating film (insulator 216, insulator 274, insulator 280, and the like) and a gate insulating film (insulator 224, using a source gas which does not contain hydrogen atoms or has a low hydrogen atom content). By forming a film of the insulator 250 or the like, the concentration of hydrogen contained in these insulating films may be reduced and hydrogen mixed in the channel formation region of the oxide semiconductor may be reduced.
　上記絶縁膜の成膜では、成膜ガスとして、シリコン原子を含む分子を有するガスが主に用いられる。上記絶縁膜に含まれる水素を低減するには、当該シリコン原子を含む分子に含まれる水素原子が少ないことが好ましく、当該シリコン原子を含む分子が水素原子を含まないことがより好ましい。もちろん、シリコン原子を含む分子を有するガス以外の成膜ガスも、含有される水素原子が少ないことが好ましく、水素原子を含まないことがより好ましい。 In forming the insulating film, a gas containing molecules containing silicon atoms is mainly used as a film forming gas. In order to reduce hydrogen contained in the insulating film, it is preferable that the number of hydrogen atoms contained in the molecule containing the silicon atom be small, and it is more preferable that the molecule containing the silicon atom contain no hydrogen atom. Of course, the film-forming gas other than the gas having a molecule containing a silicon atom preferably contains a small number of hydrogen atoms, and more preferably does not contain a hydrogen atom.
　上記のようなシリコン原子を含む分子をＳｉｘ−Ｒｙで表すと、例えば、官能基Ｒとして、イソシアネート基（−Ｎ＝Ｃ＝Ｏ）、シアネート基（−Ｏ−Ｃ≡Ｎ）、シアノ基（−Ｃ≡Ｎ）、ジアゾ基（＝Ｎ２）、アジド基（−Ｎ３）、ニトロソ基（−ＮＯ）、およびニトロ基（−ＮＯ２）の少なくとも一つを用いることができる。例えば、１≦ｘ≦３、１≦ｙ≦８、とすればよい。このようなシリコン原子を含む分子としては、例えば、テトライソシアネートシラン、テトラシアネートシラン、テトラシアノシラン、ヘキサイソシアネートシラン、オクタイソシアネートシラン等を用いることができる。ここでは、シリコン原子に同じ種類の官能基が結合する分子を例示したが、本実施の形態はこれに限られるものではない。シリコン原子に異なる種類の官能基が結合する構成にしてもよい。 When the molecule containing a silicon atom as described above is represented by Si x —R y , for example, as the functional group R, an isocyanate group (—N═C═O), a cyanate group (—O—C≡N), a cyano group, etc. (-C≡N), diazo group (= N 2), azido group (-N 3), it is possible to use at least one nitroso group (-NO), and a nitro group (-NO 2). For example, 1≦x≦3 and 1≦y≦8 may be set. As such a molecule containing a silicon atom, for example, tetraisocyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate silane, octaisocyanate silane, etc. can be used. Here, a molecule in which the same type of functional group is bonded to a silicon atom is illustrated, but the present embodiment is not limited to this. You may make it the structure which a different kind of functional group couple|bonds with a silicon atom.
　また、例えば、官能基Ｒとしてハロゲン（Ｃｌ、Ｂｒ、Ｉ、またはＦ）を用いる構成にしてもよい。例えば、１≦ｘ≦２、１≦ｙ≦６、とすればよい。このようなシリコン原子を含む分子としては、例えば、テトラクロロシラン（ＳｉＣｌ４）、ヘキサクロロジシラン（Ｓｉ２Ｃｌ６）等を用いることができる。塩素を官能基とする例を示したが、塩素以外の、臭素、ヨウ素、フッ素等のハロゲンを官能基として用いてもよい。また、シリコン原子に異なる種類のハロゲンが結合する構成にしてもよい。 Alternatively, for example, halogen (Cl, Br, I, or F) may be used as the functional group R. For example, 1≦x≦2 and 1≦y≦6. As such a molecule containing a silicon atom, for example, tetrachlorosilane (SiCl 4 ) or hexachlorodisilane (Si 2 Cl 6 ) can be used. Although an example in which chlorine is used as the functional group is shown, halogen other than chlorine, such as bromine, iodine or fluorine, may be used as the functional group. Further, a structure in which different kinds of halogens are bonded to silicon atoms may be adopted.
　絶縁体２１６、絶縁体２７４、絶縁体２８０、絶縁体２２４、および絶縁体２５０の成膜は、上記のようなシリコン原子を含む分子を有するガスを用いた、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法によって行えばよい。ＣＶＤ法は、成膜速度が比較的早いので、膜厚が厚い絶縁体２８０、絶縁体２７４、および絶縁体２１６の成膜を行うにあたって好適である。 The insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 are formed by chemical vapor deposition (CVD) using a gas having a molecule containing a silicon atom as described above. Deposition) method. Since the CVD method has a relatively high film formation rate, it is suitable for forming the insulator 280, the insulator 274, and the insulator 216 which have large film thicknesses.
　ＣＶＤ法として、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＣＶＤ）法、または熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ　ＣＶＤ）法、を用いることが好ましい。熱ＣＶＤ法を用いる場合、大気圧下で成膜を行なう常圧ＣＶＤ（ＡＰＣＶＤ：Ａｔｍｏｓｐｈｅｒｉｃ　Ｐｒｅｓｓｕｒｅ　ＣＶＤ）法を用いてもよいし、大気圧より低い減圧状態で成膜を行う減圧ＣＶＤ（ＬＰＣＶＤ：Ｌｏｗ　Ｐｒｅｓｓｕｒｅ　ＣＶＤ）法を用いてもよい。 As the CVD method, it is preferable to use a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma or a thermal CVD (TCVD: Thermal CVD) method using heat. When the thermal CVD method is used, an atmospheric pressure CVD (APCVD: Atmospheric Pressure CVD) method may be used in which the film is formed under atmospheric pressure, or a low pressure CVD (LPCVD: Low) in which the film is formed under a reduced pressure lower than the atmospheric pressure. The Pressure CVD) method may be used.
　ＣＶＤ法を用いて絶縁体２１６、絶縁体２７４、絶縁体２８０、絶縁体２２４、および絶縁体２５０を成膜する場合、酸化剤を用いることが好ましい。酸化剤としては、Ｏ２、Ｏ３、ＮＯ、ＮＯ２、Ｎ２Ｏ、Ｎ２Ｏ３、Ｎ２Ｏ４、Ｎ２Ｏ５、ＣＯ、ＣＯ２、などの水素原子を含まないガスを用いることが好ましい。 When the insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 are formed by a CVD method, an oxidizer is preferably used. As the oxidant, a gas containing no hydrogen atom such as O 2 , O 3 , NO, NO 2 , N 2 O, N 2 O 3 , N 2 O 4 , N 2 O 5 , CO, or CO 2 is used. Preferably.
　また、絶縁体２１６、絶縁体２７４、絶縁体２８０、絶縁体２２４、および絶縁体２５０の成膜は、ＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法によって行ってもよい。ＡＬＤ法では、反応のための第１の原料ガス（以下、プリカーサと呼ぶ。前駆体、金属プリカーサとも呼ぶことができる。）と第２の原料ガス（以下、リアクタントと呼ぶ。反応剤、非金属プリカーサとも呼ぶことができる。）を交互にチャンバーに導入し、これらの原料ガスの導入を繰り返すことで成膜を行う。 The insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 may be formed by an ALD (Atomic Layer Deposition) method. In the ALD method, a first source gas for reaction (hereinafter referred to as a precursor. It can also be referred to as a precursor or a metal precursor) and a second source gas (hereinafter referred to as a reactant. Reactant, non-metal) Can also be referred to as a precursor.) is alternately introduced into the chamber, and the introduction of these source gases is repeated to form a film.
　ＡＬＤ法は、原料ガスを切り替えながら成膜することで、原子の性質である自己制御性を利用し、一層ずつ原子を堆積することができる。よって、ＡＬＤ法は、極薄膜厚の成膜、アスペクト比の高い構造への成膜、ピンホールなどの欠陥の少ない成膜、および被覆性に優れた成膜などを行うことができる。このため、ＡＬＤ法は、絶縁体２５０、および絶縁体２２４の成膜を行うにあたって好適である。 The ALD method allows atoms to be deposited one by one by utilizing the self-controllability, which is the property of atoms, by forming films while switching the source gas. Therefore, the ALD method can perform film formation with an extremely thin film thickness, film formation on a structure with a high aspect ratio, film formation with few defects such as pinholes, and film formation with excellent coverage. Therefore, the ALD method is suitable for forming the insulator 250 and the insulator 224.
　ＡＬＤ法としては、プリカーサ及びリアクタントの反応を熱エネルギーのみで行う熱ＡＬＤ（Ｔｈｅｒｍａｌ　ＡＬＤ）法をもちいてもよいし、プラズマ励起されたリアクタントを用いるＰＥＡＬＤ（Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＡＬＤ）法を用いてもよい。 As the ALD method, a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactant is performed only with thermal energy may be used, or a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant may be used.
　ＡＬＤ法を用いる場合、プリカーサとして、上記シリコン原子を含む分子を有するガスを、リアクタントとして、上記酸化剤を用いればよい。これにより、絶縁体２１６、絶縁体２７４、絶縁体２８０、絶縁体２２４、および絶縁体２５０中に取り込まれる水素の量を大きく低減することができる。 When using the ALD method, a gas having a molecule containing the silicon atom may be used as a precursor, and the oxidant may be used as a reactant. Accordingly, the amount of hydrogen taken into the insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 can be significantly reduced.
　なお、上記では、シリコン原子を含む分子が水素原子を含まない例について示したが、本実施の形態はこれに限られるものではない。上記のシリコン原子を含む分子において、シリコン原子に結合する官能基の一部が水素原子に置換される構成にしてもよい。ただし、上記のシリコン原子を含む分子に含まれる水素原子は、シラン（ＳｉＨ４）より少ないことが好ましい。つまり、上記のシリコン原子を含む分子は、シリコン１原子あたり３原子以下の水素原子を有することが好ましい。また、上記のシリコン原子を含む分子を有するガスが、シリコン１原子あたり３原子以下の水素原子を有すると、より好ましい。 Although an example in which a molecule including a silicon atom does not include a hydrogen atom is described above, this embodiment is not limited to this. In the molecule containing a silicon atom, a part of the functional group bonded to the silicon atom may be replaced with a hydrogen atom. However, it is preferable that the number of hydrogen atoms contained in the molecule containing a silicon atom is smaller than that of silane (SiH 4 ). That is, it is preferable that the molecule containing a silicon atom has 3 or less hydrogen atoms per silicon atom. Further, it is more preferable that the gas having a molecule containing a silicon atom has 3 or less hydrogen atoms per silicon atom.
　以上のように、水素原子が低減または除去されたガスを用いた成膜方法で、絶縁体２１６、絶縁体２７４、絶縁体２８０、絶縁体２２４、および絶縁体２５０の少なくとも一つを成膜することで、これらの絶縁膜に含まれる水素の量を低減することができる。特に、酸化物２３０とともに、絶縁体２８３と絶縁体２１２に封止された領域に形成される、絶縁体２１６、絶縁体２２４、絶縁体２８０、および絶縁体２５０を上記の成膜方法で成膜することで、当該封止された領域内の水素濃度を低減し、さらに外部から混入する水素を、絶縁体２８３および絶縁体２１２によって低減できるのでより好ましい。 As described above, at least one of the insulator 216, the insulator 274, the insulator 280, the insulator 224, and the insulator 250 is formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thus, the amount of hydrogen contained in these insulating films can be reduced. In particular, the insulator 216, the insulator 224, the insulator 280, and the insulator 250 which are formed in the region sealed with the insulator 283 and the insulator 212 together with the oxide 230 are formed by the above film formation method. This is more preferable because the hydrogen concentration in the sealed region can be reduced and hydrogen mixed from the outside can be reduced by the insulator 283 and the insulator 212.
　また、トランジスタ２００は、図１Ｂ、図１Ｃ図１Ｄに示すように、絶縁体２８２と、絶縁体２５０とが、直接接する構造となっている。このような構造とすることで、絶縁体２８０に含まれる酸素が、導電体２６０に吸収され難くなる。従って、絶縁体２８０に含まれる酸素は、酸化物２３０ｃを介して、酸化物２３０ａおよび酸化物２３０ｂへ効率よく供給することができるので、酸化物２３０ａ中および酸化物２３０ｂ中の酸素欠損を低減し、トランジスタ２００の電気特性および信頼性を向上させることができる。また、絶縁体２８０に含まれる水素などの不純物が絶縁体２５０へ混入することを抑えることができるので、さらに、絶縁体２５０および酸化物２３０の水素濃度を低減することができる。よって、トランジスタ２００の電気特性および信頼性への悪影響を抑制することができる。絶縁体２８２としては、窒化シリコン、窒化酸化シリコン、酸化アルミニウム、または酸化ハフニウムを用いることができる。 The transistor 200 has a structure in which an insulator 282 and an insulator 250 are in direct contact with each other, as shown in FIGS. 1B and 1C and 1D. With such a structure, oxygen contained in the insulator 280 is less likely to be absorbed by the conductor 260. Therefore, oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b through the oxide 230c, so that oxygen vacancies in the oxide 230a and the oxide 230b are reduced. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. In addition, impurities such as hydrogen contained in the insulator 280 can be prevented from entering the insulator 250, so that the hydrogen concentrations of the insulator 250 and the oxide 230 can be further reduced. Therefore, an adverse effect on the electrical characteristics and reliability of the transistor 200 can be suppressed. As the insulator 282, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used.
　以上より、電気特性の変動を抑制し、安定した電気特性を有するとともに、信頼性を向上させた半導体装置を提供することができる。または、ノーマリーオフの電気特性を有する半導体装置を提供することができる。または、オン電流が大きいトランジスタを有する半導体装置を提供することができる。または、高い周波数特性を有するトランジスタを有する半導体装置を提供することができる。または、オフ電流が小さいトランジスタを有する半導体装置を提供することができる。 From the above, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability. Alternatively, a semiconductor device having normally-off electrical characteristics can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor having high frequency characteristics can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided.
　以下では、本発明の一態様に係るトランジスタ２００を有する半導体装置の詳細な構成について説明する。 Hereinafter, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.
　導電体２０５は、酸化物２３０、および導電体２６０と、重なるように配置する。また、導電体２０５は、絶縁体２１４および絶縁体２１６に埋め込まれて設けることが好ましい。 The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 214 and the insulator 216.
　ここで、導電体２６０は、第１のゲート（トップゲートともいう）電極として機能する場合がある。また、導電体２０５は、第２のゲート（ボトムゲートともいう）電極として機能する場合がある。その場合、導電体２０５に印加する電位を、導電体２６０に印加する電位と、連動させず、独立して変化させることで、トランジスタ２００のＶｔｈを制御することができる。特に、導電体２０５に負の電位を印加することにより、トランジスタ２００のＶｔｈを０Ｖより大きくし、オフ電流を低減することが可能となる。したがって、導電体２０５に負の電位を印加したほうが、印加しない場合よりも、導電体２６０に印加する電位が０Ｖのときのドレイン電流を小さくすることができる。 Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260, without changing the potential. In particular, by applying a negative potential to the conductor 205, Vth of the transistor 200 can be higher than 0 V and off-state current can be reduced. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, as compared to the case where no potential is applied.
　なお、導電体２０５は、図１Ａに示すように、酸化物２３０の導電体２４２ａおよび導電体２４２ｂと重ならない領域の大きさよりも、大きく設けるとよい。特に、図１Ｃに示すように、導電体２０５は、酸化物２３０のチャネル幅方向と交わる端部よりも外側の領域においても、延伸していることが好ましい。つまり、酸化物２３０のチャネル幅方向における側面の外側において、導電体２０５と、導電体２６０とは、絶縁体を介して重畳していることが好ましい。または、導電体２０５を大きく設けることによって、導電体２０５形成以降の作製工程のプラズマを用いた処理において、局所的なチャージング（チャージアップと言う）の緩和ができる場合がある。ただし、本発明の一態様はこれに限定されない。導電体２０５は、少なくとも導電体２４２ａと、導電体２４２ｂとの間に位置する酸化物２３０と重畳すればよい。 Note that as shown in FIG. 1A, the conductor 205 is preferably provided larger than the size of a region of the oxide 230 which does not overlap with the conductors 242a and 242b. In particular, as illustrated in FIG. 1C, the conductor 205 is preferably extended also in a region outside the end portion of the oxide 230 which intersects with the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with the insulator provided outside the side surface of the oxide 230 in the channel width direction. Alternatively, in some cases, by providing a large conductor 205, local charging (called charge-up) can be alleviated in a treatment using plasma in a manufacturing process after the formation of the conductor 205. However, one embodiment of the present invention is not limited to this. The conductor 205 may overlap with at least the oxide 230 located between the conductor 242a and the conductor 242b.
　また、絶縁体２２４の底面を基準として、酸化物２３０ａおよび酸化物２３０ｂと、導電体２６０とが、重ならない領域における導電体２６０の底面の高さは、酸化物２３０ｂの底面の高さより低い位置に配置されていることが好ましい。また、酸化物２３０ｂと、導電体２６０とが、重ならない領域における導電体２６０の底面の高さと、酸化物２３０ｂの底面の高さと、の差は、０ｎｍ以上１００ｎｍ以下、好ましくは、３ｎｍ以上５０ｎｍ以下、より好ましくは、５ｎｍ以上２０ｎｍ以下とする。 In addition, the height of the bottom surface of the conductor 260 in a region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is lower than the height of the bottom surface of the oxide 230b with reference to the bottom surface of the insulator 224. Are preferably arranged in In addition, the difference between the height of the bottom surface of the conductor 260 in a region where the oxide 230b and the conductor 260 do not overlap with each other and the height of the bottom surface of the oxide 230b is 0 nm to 100 nm, preferably 3 nm to 50 nm. The thickness is more preferably 5 nm or more and 20 nm or less.
　このように、ゲートとして機能する導電体２６０が、チャネル形成領域の酸化物２３０ｂの側面および上面を酸化物２３０ｃおよび絶縁体２５０を介して覆う構成となっており、導電体２６０の電界をチャネル形成領域の酸化物２３０ｂ全体に作用させやすくなる。よって、トランジスタ２００のオン電流を増大させ、周波数特性を向上させることができる。本明細書において、第１のゲート、および第２のゲートの電界によって、チャネル形成領域を電気的に取り囲むトランジスタの構造を、ｓｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（Ｓ−ｃｈａｎｎｅｌ）構造とよぶ。 As described above, the conductor 260 functioning as a gate has a structure in which the side surface and the top surface of the oxide 230b in the channel formation region are covered with the oxide 230c and the insulator 250, so that the electric field of the conductor 260 is formed into a channel. It becomes easy to act on the entire oxide 230b in the region. Therefore, the on-state current of the transistor 200 can be increased and frequency characteristics can be improved. In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.
　また、導電体２０５ａは、水または水素などの不純物および酸素の透過を抑制する導電体が好ましい。例えば、チタン、窒化チタン、タンタル、または窒化タンタルを用いることができる。また、導電体２０５ｂは、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。なお、導電体２０５を２層で図示したが、３層以上の多層構造としてもよい。 Further, the conductor 205a is preferably a conductor that suppresses permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Further, the conductor 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Although the conductor 205 is illustrated as having two layers, it may have a multilayer structure of three or more layers.
　ここで、酸化物半導体と、酸化物半導体の下層に位置する絶縁体、または導電体と、酸化物半導体の上層に位置する絶縁体、または導電体とを、大気開放を行わずに、異なる膜種を連続成膜することで、不純物（特に、水素、水）の濃度が低減された、実質的に高純度真性である酸化物半導体膜を成膜することができるので好ましい。 Here, the oxide semiconductor, the insulator or the conductor located in the lower layer of the oxide semiconductor, and the insulator or the conductor located in the upper layer of the oxide semiconductor are formed into different films without being exposed to the atmosphere. It is preferable to continuously form the seeds because an oxide semiconductor film with substantially high purity and intrinsic concentration in which impurities (in particular, hydrogen and water) are reduced can be formed.
　絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３の少なくとも一つは、水または水素などの不純物が、基板側から、または、上方からトランジスタ２００に混入するのを抑制するバリア絶縁膜として機能することが好ましい。したがって、絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３の少なくとも一つは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい）絶縁性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する（上記酸素が透過しにくい）絶縁性材料を用いることが好ましい。 At least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 has impurities such as water or hydrogen mixed in the transistor 200 from the substrate side or from above. It is preferable that the barrier insulating film functions as a barrier insulating film. Therefore, at least one of the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule. It is preferable to use an insulating material (N 2 O, NO, NO 2, etc.) or a material having a function of suppressing the diffusion of impurities such as copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) (the above oxygen is less likely to permeate).
　例えば、絶縁体２１２、および絶縁体２８３として、窒化シリコンまたは窒化酸化シリコンなどを用い、絶縁体２１４、絶縁体２２２、絶縁体２７２、および絶縁体２８２として、酸化アルミニウムまたは酸化ハフニウムなどを用いることが好ましい。これにより、水または水素などの不純物が絶縁体２１２、および絶縁体２１４を介して、基板側からトランジスタ２００側に拡散するのを抑制することができる。または、絶縁体２２４などに含まれる酸素が、絶縁体２１２、および絶縁体２１４を介して基板側に、拡散するのを抑制することができる。また、水または水素などの不純物が絶縁体２７２、絶縁体２８２、および絶縁体２８３よりも上方に配置されている絶縁体２８０、および絶縁体２７４などからトランジスタ２００側に拡散するのを抑制することができる。このように、トランジスタ２００を、水または水素などの不純物、および酸素の拡散を抑制する機能を有する絶縁体２１２、絶縁体２１４、絶縁体２２２、絶縁体２７２、絶縁体２８２、および絶縁体２８３で取り囲む構造とすることが好ましい。 For example, silicon nitride, silicon nitride oxide, or the like is used for the insulator 212 and the insulator 283, and aluminum oxide, hafnium oxide, or the like is used for the insulator 214, the insulator 222, the insulator 272, and the insulator 282. preferable. Accordingly, impurities such as water or hydrogen can be suppressed from diffusing from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side through the insulator 212 and the insulator 214. Further, it is possible to suppress impurities such as water or hydrogen from diffusing from the insulator 272, the insulator 282, the insulator 280 which is provided above the insulator 283, the insulator 274, and the like to the transistor 200 side. You can As described above, the transistor 200 includes the insulator 212, the insulator 214, the insulator 222, the insulator 272, the insulator 282, and the insulator 283 which has a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. A surrounding structure is preferable.
　また、絶縁体２１２、および絶縁体２８３の抵抗率を低くすることが好ましい場合がある。例えば、絶縁体２１２、および絶縁体２８３の抵抗率を概略１×１０１３Ωｃｍとすることで、半導体装置作製工程のプラズマ等を用いる処理において、絶縁体２１２、および絶縁体２８３が、導電体２０５、導電体２４２または導電体２６０のチャージアップを緩和することができる場合がある。絶縁体２１２、および絶縁体２８３の抵抗率は、好ましくは、１×１０１０Ωｃｍ以上１×１０１５Ωｃｍ以下とする。 Further, it may be preferable to reduce the resistivity of the insulator 212 and the insulator 283. For example, by setting the resistivity of the insulator 212 and the insulator 283 to approximately 1×10 13 Ωcm, the insulator 212 and the insulator 283 can be replaced by the conductor 205 in a process using plasma or the like in a semiconductor device manufacturing process. In some cases, charge-up of the conductor 242 or the conductor 260 can be reduced. The resistivity of the insulator 212 and the insulator 283 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.
　また、絶縁体２１６、絶縁体２８０、および絶縁体２７４は、絶縁体２１４よりも誘電率が低いことが好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。例えば、絶縁体２１６、絶縁体２８０、および絶縁体２７４として、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、または空孔を有する酸化シリコンなどを適宜用いればよい。 Further, the insulator 216, the insulator 280, and the insulator 274 preferably have a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 216, the insulator 280, and the insulator 274, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide containing fluorine, silicon oxide containing carbon, carbon, or nitrogen is added. Silicon oxide, silicon oxide having holes, or the like may be used as appropriate.
　絶縁体２２２、および絶縁体２２４は、ゲート絶縁体としての機能を有する。 The insulator 222 and the insulator 224 have a function as a gate insulator.
　ここで、酸化物２３０と接する絶縁体２２４は、加熱により酸素を脱離することが好ましい。本明細書では、加熱により離脱する酸素を過剰酸素と呼ぶことがある。例えば、絶縁体２２４は、酸化シリコンまたは酸化窒化シリコンなどを適宜用いればよい。酸素を含む絶縁体を酸化物２３０に接して設けることにより、酸化物２３０中の酸素欠損を低減し、トランジスタ２００の信頼性を向上させることができる。 Here, it is preferable that the insulator 224 in contact with the oxide 230 desorb oxygen by heating. In the present specification, oxygen released by heating may be referred to as excess oxygen. For example, the insulator 224 may be formed using silicon oxide, silicon oxynitride, or the like as appropriate. By providing the insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.
　絶縁体２２４として、具体的には、加熱により一部の酸素が脱離する酸化物材料を用いることが好ましい。加熱により酸素を脱離する酸化物とは、昇温脱離ガス分析（ＴＤＳ（Ｔｈｅｒｍａｌ　Ｄｅｓｏｒｐｔｉｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）分析）にて、酸素分子の脱離量が１．０×１０１８ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上、好ましくは１．０×１０１９ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上、さらに好ましくは２．０×１０１９ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上、または３．０×１０２０ｍｏｌｅｃｕｌｅｓ／ｃｍ３以上である酸化物膜である。なお、上記ＴＤＳ分析時における膜の表面温度としては１００℃以上７００℃以下、または１００℃以上４００℃以下の範囲が好ましい。 Specifically, as the insulator 224, an oxide material from which part of oxygen is released by heating is preferably used. The oxide that desorbs oxygen by heating means that the desorption amount of oxygen molecules is 1.0×10 18 molecules/cm 3 or more, preferably by thermal desorption gas analysis (TDS (Thermal Desorption Spectroscopy) analysis). Is an oxide film of 1.0×10 19 molecules/cm 3 or more, more preferably 2.0×10 19 molecules/cm 3 or more, or 3.0×10 20 molecules/cm 3 or more. The surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.
　絶縁体２２２は、水または水素などの不純物が、基板側からトランジスタ２００に混入するのを抑制するバリア絶縁膜として機能することが好ましい。例えば、絶縁体２２２は、絶縁体２２４より水素透過性が低いことが好ましい。絶縁体２２２、および絶縁体２８３によって、絶縁体２２４および酸化物２３０などを囲むことにより、外方から水または水素などの不純物がトランジスタ２００に侵入することを抑制することができる。 The insulator 222 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, and the like with the insulator 222 and the insulator 283, impurities such as water or hydrogen can be prevented from entering the transistor 200 from the outside.
　さらに、絶縁体２２２は、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する（上記酸素が透過しにくい）ことが好ましい。例えば、絶縁体２２２は、絶縁体２２４より酸素透過性が低いことが好ましい。絶縁体２２２が、酸素や不純物の拡散を抑制する機能を有することで、酸化物２３０が有する酸素が、絶縁体２２２より下側へ拡散することを低減できるので、好ましい。また、導電体２０５が、絶縁体２２４や、酸化物２３０が有する酸素と反応することを抑制することができる。 Furthermore, it is preferable that the insulator 222 has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the oxygen is difficult to permeate). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 have a function of suppressing diffusion of oxygen and impurities because oxygen in the oxide 230 can be prevented from diffusing below the insulator 222. In addition, the conductor 205 can be prevented from reacting with the insulator 224 and oxygen contained in the oxide 230.
　絶縁体２２２は、絶縁性材料であるアルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体を用いるとよい。アルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体として、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。このような材料を用いて絶縁体２２２を形成した場合、絶縁体２２２は、酸化物２３０からの酸素の放出や、トランジスタ２００の周辺部から酸化物２３０への水素等の不純物の混入を抑制する層として機能する。 As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230. Functions as a layer.
　または、これらの絶縁体に、例えば、酸化アルミニウム、酸化ビスマス、酸化ゲルマニウム、酸化ニオブ、酸化シリコン、酸化チタン、酸化タングステン、酸化イットリウム、酸化ジルコニウムを添加してもよい。またはこれらの絶縁体を窒化処理してもよい。上記の絶縁体に酸化シリコン、酸化窒化シリコンまたは窒化シリコンを積層して用いてもよい。 Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator and used.
　また、絶縁体２２２は、例えば、酸化アルミニウム、酸化ハフニウム、酸化タンタル、酸化ジルコニウム、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）または（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などを含む絶縁体を単層または積層で用いてもよい。トランジスタの微細化、および高集積化が進むと、ゲート絶縁体の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁体として機能する絶縁体にｈｉｇｈ−ｋ材料を用いることで、物理膜厚を保ちながら、トランジスタ動作時のゲート電位の低減が可能となる。 The insulator 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3 (BST). The insulating material may be used as a single layer or a stacked layer. As transistors become finer and more highly integrated, thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
　なお、絶縁体２２２、および絶縁体２２４が、２層以上の積層構造を有していてもよい。その場合、同じ材料からなる積層構造に限定されず、異なる材料からなる積層構造でもよい。 Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
　また、酸化物２３０ｂと、ソース電極またはドレイン電極として機能する導電体２４２（導電体２４２ａよび導電体２４２ｂ）と、の間に酸化物２４３（酸化物２４３ａおよび酸化物２４３ｂ）を配置してもよい。導電体２４２と、酸化物２３０とが接しない構成となるので、導電体２４２が、酸化物２３０の酸素を吸収することを抑制できる。つまり、導電体２４２の酸化を防止することで、導電体２４２の導電率の低下を抑制することができる。従って、酸化物２４３は、導電体２４２の酸化を抑制する機能を有することが好ましい。 Further, the oxide 243 (the oxide 243a and the oxide 243b) may be provided between the oxide 230b and the conductor 242 (the conductor 242a and the conductor 242b) which functions as a source electrode or a drain electrode. .. Since the conductor 242 and the oxide 230 are not in contact with each other, the conductor 242 can be prevented from absorbing oxygen in the oxide 230. That is, by preventing the conductor 242 from being oxidized, it is possible to suppress the decrease in the conductivity of the conductor 242. Therefore, the oxide 243 preferably has a function of suppressing oxidation of the conductor 242.
　従って、酸化物２４３は、酸素の透過を抑制する機能を有することが好ましい。ソース電極やドレイン電極として機能する導電体２４２と酸化物２３０ｂとの間に酸素の透過を抑制する機能を有する酸化物２４３を配置することで、導電体２４２と、酸化物２３０ｂとの間の電気抵抗が低減されるので好ましい。このような構成とすることで、トランジスタ２００の電気特性およびトランジスタ２００の信頼性を向上させることができる。 Therefore, the oxide 243 preferably has a function of suppressing the permeation of oxygen. By arranging the oxide 243 having a function of suppressing permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, electrical conductivity between the conductor 242 and the oxide 230b can be obtained. It is preferable because the resistance is reduced. With such a structure, electric characteristics of the transistor 200 and reliability of the transistor 200 can be improved.
　酸化物２４３として、元素Ｍを有する金属酸化物を用いてもよい。特に、元素Ｍは、アルミニウム、ガリウム、イットリウム、または錫を用いるとよい。酸化物２４３は、酸化物２３０ｂよりも元素Ｍの濃度が高いことが好ましい。また、酸化物２４３として、酸化ガリウムを用いてもよい。また、酸化物２４３として、Ｉｎ−Ｍ−Ｚｎ酸化物等の金属酸化物を用いてもよい。具体的には、酸化物２４３に用いる金属酸化物において、Ｉｎに対する元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、Ｉｎに対する元素Ｍの原子数比より大きいことが好ましい。また、酸化物２４３の膜厚は、０．５ｎｍ以上５ｎｍ以下が好ましく、より好ましくは、１ｎｍ以上３ｎｍ以下である。また、酸化物２４３は、結晶性を有すると好ましい。酸化物２４３が結晶性を有する場合、酸化物２３０中の酸素の放出を好適に抑制することが出来る。例えば、酸化物２４３としては、六方晶などの結晶構造であれば、酸化物２３０中の酸素の放出を抑制できる場合がある。 As the oxide 243, a metal oxide containing the element M may be used. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. The oxide 243 preferably has a higher concentration of the element M than the oxide 230b. Alternatively, gallium oxide may be used as the oxide 243. Alternatively, as the oxide 243, a metal oxide such as an In-M-Zn oxide may be used. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. The film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, release of oxygen in the oxide 230 can be suppressed appropriately. For example, if the oxide 243 has a hexagonal crystal structure or the like, release of oxygen in the oxide 230 can be suppressed in some cases.
　なお、酸化物２４３は必ずしも設けなくてもよい。その場合、導電体２４２（導電体２４２ａ、および導電体２４２ｂ）と酸化物２３０とが接することで、酸化物２３０中の酸素が導電体２４２へ拡散し、導電体２４２が酸化する場合がある。導電体２４２が酸化することで、導電体２４２の導電率が低下する蓋然性が高い。なお、酸化物２３０中の酸素が導電体２４２へ拡散することを、導電体２４２が酸化物２３０中の酸素を吸収する、と言い換えることができる。 Note that the oxide 243 does not necessarily have to be provided. In that case, when the conductor 242 (the conductor 242a and the conductor 242b) is in contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 242 and the conductor 242 may be oxidized. Oxidation of the conductor 242 is likely to reduce the conductivity of the conductor 242. Note that diffusion of oxygen in the oxide 230 into the conductor 242 can be restated as absorption of oxygen in the oxide 230 by the conductor 242.
　また、酸化物２３０中の酸素が導電体２４２（導電体２４２ａ、および導電体２４２ｂ）へ拡散することで、導電体２４２ａと酸化物２３０ｂとの間、および、導電体２４２ｂと酸化物２３０ｂとの間に異層が形成される場合がある。当該異層は、導電体２４２よりも酸素を多く含むため、当該異層は絶縁性を有すると推定される。このとき、導電体２４２と、当該異層と、酸化物２３０ｂとの３層構造は、金属−絶縁体−半導体からなる３層構造とみなすことができ、ＭＩＳ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構造と呼ぶ、またはＭＩＳ構造を主としたダイオード接合構造と呼ぶ場合がある。 In addition, oxygen in the oxide 230 diffuses into the conductor 242 (the conductor 242a and the conductor 242b), so that the conductor 242a and the oxide 230b are separated from each other and the conductor 242b and the oxide 230b are separated from each other. Different layers may be formed between them. Since the different layer contains more oxygen than the conductor 242, it is estimated that the different layer has an insulating property. At this time, the three-layer structure of the conductor 242, the different layer, and the oxide 230b can be regarded as a three-layer structure including a metal-insulator-semiconductor and a MIS (Metal-Insulator-Semiconductor) structure. In some cases, it may be referred to as a diode junction structure mainly including the MIS structure.
　なお、上記異層は、導電体２４２と酸化物２３０ｂとの間に形成されることに限られず、例えば、異層が、導電体２４２と酸化物２３０ｃとの間に形成される場合や、導電体２４２と酸化物２３０ｂとの間、および導電体２４２と酸化物２３０ｃとの間に形成される場合がある。 Note that the different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, when the different layer is formed between the conductor 242 and the oxide 230c, It may be formed between the body 242 and the oxide 230b and between the conductor 242 and the oxide 230c.
　酸化物２４３上には、ソース電極、およびドレイン電極として機能する導電体２４２（導電体２４２ａ、および導電体２４２ｂ）が設けられる。導電体２４２の膜厚は、例えば、１ｎｍ以上５０ｎｍ以下、好ましくは２ｎｍ以上２５ｎｍ以下、とすればよい。 The conductor 242 (the conductor 242a and the conductor 242b) functioning as a source electrode and a drain electrode is provided over the oxide 243. The thickness of the conductor 242 may be, for example, 1 nm to 50 nm inclusive, preferably 2 nm to 25 nm inclusive.
　導電体２４２としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。 As the conductor 242, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. Preferably. Further, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when absorbing oxygen is preferable.
　絶縁体２７２は、導電体２４２上面に接して設けられており、バリア層として機能することが好ましい。当該構成にすることで、導電体２４２による、絶縁体２８０が有する過剰酸素の吸収を抑制することができる。また、導電体２４２の酸化を抑制することで、トランジスタ２００と配線とのコンタクト抵抗の増加を抑制することができる。よって、トランジスタ２００に良好な電気特性および信頼性を与えることができる。 The insulator 272 is provided in contact with the top surface of the conductor 242 and preferably functions as a barrier layer. With such a structure, absorption of excess oxygen included in the insulator 280 by the conductor 242 can be suppressed. Further, by suppressing the oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can have favorable electrical characteristics and reliability.
　従って、絶縁体２７２は、酸素の拡散を抑制する機能を有することが好ましい。例えば、絶縁体２７２は、絶縁体２８０よりも酸素の拡散を抑制する機能を有することが好ましい。絶縁体２７２としては、例えば、アルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体を成膜するとよい。また、絶縁体２７２としては、例えば、窒化アルミニウムを含む絶縁体を用いればよい。 Therefore, it is preferable that the insulator 272 has a function of suppressing diffusion of oxygen. For example, the insulator 272 preferably has a function of suppressing diffusion of oxygen as compared with the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Further, as the insulator 272, for example, an insulator containing aluminum nitride may be used.
　また、図１ＡのＡ７−Ａ８の一点鎖線で示す部位に対応する断面図を図２に示す。図２に示すように、絶縁体２７３ｂは、少なくとも、酸化物２３０ａの側面、酸化物２３０ｂの側面、酸化物２４３ｂの側面、および導電体２４２ｂの側面と接する。また、図示しないが、絶縁体２７３ａは、少なくとも、酸化物２３０ａの側面、酸化物２３０ｂの側面、酸化物２４３ａの側面、および導電体２４２ａの側面と接する。なお、絶縁体２７３ｂは、絶縁体２７２ｂの側面と接する構成としてもよい。なお、絶縁体２７３ａが、絶縁体２７２ａの側面と接する構成としてもよい。 Further, FIG. 2 shows a cross-sectional view corresponding to a portion indicated by a dashed line A7-A8 in FIG. 1A. As illustrated in FIG. 2, the insulator 273b is in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243b, and the side surface of the conductor 242b. Although not illustrated, the insulator 273a is in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide 243a, and the side surface of the conductor 242a. Note that the insulator 273b may be in contact with the side surface of the insulator 272b. Note that the insulator 273a may be in contact with the side surface of the insulator 272a.
　また、絶縁体２７３（絶縁体２７３ａおよび絶縁体２７３ｂ）は、金属酸化物を用いることが好ましい。絶縁体２７３に含まれる金属が、絶縁体２７３と酸化物２３０ａとの界面および界面近傍に埋め込まれることで、絶縁体２７３と酸化物２３０ａとの界面および界面近傍をｎ型化することができる。同様に、絶縁体２７３に含まれる金属が、絶縁体２７３と酸化物２３０ｂとの界面および界面近傍に埋め込まれることで、絶縁体２７３と酸化物２３０ｂとの界面および界面近傍をｎ型化することができる。図２に、酸化物２３０ａのｎ型化した領域、および酸化物２３０ｂのｎ型化した領域を領域２３０ｎとして示す。 Further, it is preferable to use a metal oxide for the insulator 273 (insulator 273a and insulator 273b). The metal contained in the insulator 273 is embedded in the interface between the insulator 273 and the oxide 230a and in the vicinity of the interface, whereby the interface between the insulator 273 and the oxide 230a and the vicinity of the interface can be made n-type. Similarly, the metal contained in the insulator 273 is embedded in the interface between the insulator 273 and the oxide 230b and in the vicinity of the interface, so that the interface between the insulator 273 and the oxide 230b and in the vicinity of the interface are made n-type. You can In FIG. 2, an n-type region of the oxide 230a and an n-type region of the oxide 230b are shown as a region 230n.
　このように、ソース電極、およびドレイン電極として機能する導電体２４２と重なる酸化物２３０ａの側面および酸化物２３０ｂの側面をｎ型化することで、トランジスタ２００のオン電流を大きくすることができる。 As described above, by making the side surface of the oxide 230a and the side surface of the oxide 230b which overlap with the conductor 242 functioning as a source electrode and a drain electrode n-type, the on-state current of the transistor 200 can be increased.
　また、絶縁体２７３は、絶縁体２７２よりも酸素透過性が高く、絶縁体２８０よりも酸素透過性が低いことが好ましい。または、絶縁体２７３の膜密度は、絶縁体２７２の膜密度よりも低いことが好ましい。このようにすることで、絶縁体２８０に含まれる酸素を酸化物２３０ａおよび酸化物２３０ｂに適量注入することが可能となり、酸化物２３０ａおよび酸化物２３０ｂの酸素欠損を修復することができるので好ましい。また、酸化物２３０ａおよび酸化物２３０ｂに酸素が入り過ぎることがないので、トランジスタ２００の信頼性を向上することができる。絶縁体２７３として、アルミニウム、マグネシウム、およびタンタルの中から選ばれるいずれか一つまたは複数の元素を有する酸化膜を好適に用いることができる。絶縁体２７３としては、代表的には、酸化アルミニウム、酸化マグネシウム、酸化タンタルを用いることができる。 The insulator 273 preferably has higher oxygen permeability than the insulator 272 and lower oxygen permeability than the insulator 280. Alternatively, the film density of the insulator 273 is preferably lower than the film density of the insulator 272. This is preferable because oxygen contained in the insulator 280 can be injected into the oxides 230a and 230b in an appropriate amount and oxygen vacancies in the oxides 230a and 230b can be repaired. Further, since oxygen does not excessively enter the oxide 230a and the oxide 230b, reliability of the transistor 200 can be improved. As the insulator 273, an oxide film containing one or more elements selected from aluminum, magnesium, and tantalum can be preferably used. As the insulator 273, typically, aluminum oxide, magnesium oxide, or tantalum oxide can be used.
　絶縁体２５０は、ゲート絶縁体として機能する。絶縁体２５０は、酸化物２３０ｃの上面に接して配置することが好ましい。絶縁体２５０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコンを用いることができる。特に、酸化シリコン、および酸化窒化シリコンは熱に対し安定であるため好ましい。 The insulator 250 functions as a gate insulator. The insulator 250 is preferably placed in contact with the top surface of the oxide 230c. For the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon-nitrogen-added silicon oxide, or silicon oxide having holes is used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.
　絶縁体２２４と同様に、絶縁体２５０は、加熱により酸素が放出される絶縁体を用いて形成することが好ましい。加熱により酸素が放出される絶縁体を、絶縁体２５０として、酸化物２３０ｃの上面に接して設けることにより、酸化物２３０ｂのチャネル形成領域に効果的に酸素を供給することができる。また、絶縁体２２４と同様に、絶縁体２５０中の水または水素などの不純物濃度が低減されていることが好ましい。絶縁体２５０の膜厚は、１ｎｍ以上２０ｎｍ以下とするのが好ましい。 Like the insulator 224, the insulator 250 is preferably formed using an insulator from which oxygen is released by heating. By providing an insulator from which oxygen is released by heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b. Further, similarly to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 be reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
　また、絶縁体２５０と導電体２６０との間に金属酸化物を設けてもよい。当該金属酸化物は、絶縁体２５０から導電体２６０への酸素拡散を抑制することが好ましい。酸素の拡散を抑制する金属酸化物を設けることで、絶縁体２５０から導電体２６０への酸素の拡散が抑制される。つまり、酸化物２３０へ供給する酸素量の減少を抑制することができる。また、絶縁体２５０の酸素による導電体２６０の酸化を抑制することができる。 A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing the metal oxide which suppresses diffusion of oxygen, diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.
　また、当該金属酸化物は、ゲート絶縁体の一部としての機能を有する場合がある。したがって、絶縁体２５０に酸化シリコンや酸化窒化シリコンなどを用いる場合、当該金属酸化物は、比誘電率が高いｈｉｇｈ−ｋ材料である金属酸化物を用いることが好ましい。ゲート絶縁体を、絶縁体２５０と当該金属酸化物との積層構造とすることで、熱に対して安定、かつ比誘電率の高い積層構造とすることができる。したがって、ゲート絶縁体の物理膜厚を保持したまま、トランジスタ動作時に印加するゲート電位の低減化が可能となる。また、ゲート絶縁体として機能する絶縁体の等価酸化膜厚（ＥＯＴ）の薄膜化が可能となる。 Also, the metal oxide may have a function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a high-k material with a high relative dielectric constant. When the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure which is stable to heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator.
　具体的には、ハフニウム、アルミニウム、ガリウム、イットリウム、ジルコニウム、タングステン、チタン、タンタル、ニッケル、ゲルマニウム、または、マグネシウムなどから選ばれた一種、または二種以上が含まれた金属酸化物を用いることができる。特に、アルミニウム、またはハフニウムの一方または双方の酸化物を含む絶縁体である、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。 Specifically, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like may be used. it can. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing an oxide of one or both of aluminum and hafnium.
　または、当該金属酸化物は、ゲートの一部としての機能を有する場合がある。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から離脱した酸素がチャネル形成領域に供給されやすくなる。 Alternatively, the metal oxide may have a function as a part of the gate. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
　特に、ゲートとして機能する導電体として、チャネルが形成される金属酸化物に含まれる金属元素および酸素を含む導電性材料を用いることが好ましい。また、前述した金属元素および窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、チャネルが形成される金属酸化物に含まれる水素を捕獲することができる場合がある。または、外方の絶縁体などから混入する水素を捕獲することができる場合がある。 In particular, it is preferable to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen as a conductor functioning as a gate. Alternatively, a conductive material containing the above metal element and nitrogen may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed can be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.
　導電体２６０は、図１では２層構造として示しているが、単層構造でもよいし、３層以上の積層構造であってもよい。 Although the conductor 260 is shown as a two-layer structure in FIG. 1, it may have a single-layer structure or a laminated structure of three or more layers.
　導電体２６０ａは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する導電性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する導電性材料を用いることが好ましい。 The conductor 260a has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.), and copper atoms. It is preferable to use materials. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.
　また、導電体２６０ａが酸素の拡散を抑制する機能を持つことにより、絶縁体２５０に含まれる酸素により、導電体２６０ｂが酸化して導電率が低下することを抑制することができる。酸素の拡散を抑制する機能を有する導電性材料としては、例えば、タンタル、窒化タンタル、ルテニウム、または酸化ルテニウムなどを用いることが好ましい。 In addition, since the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to suppress the conductivity of the conductor 260b from being reduced due to the oxygen contained in the insulator 250 from oxidizing the conductor 260b. As the conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
　また、導電体２６０ｂは、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。また、導電体２６０は、配線としても機能するため、導電性が高い導電体を用いることが好ましい。例えば、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることができる。また、導電体２６０ｂは積層構造としてもよく、例えば、チタンまたは窒化チタンと上記導電性材料との積層構造としてもよい。 Further, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the conductor 260b. Since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.
　絶縁体２８０は、例えば、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、または空孔を有する酸化シリコンなどを有することが好ましい。特に、酸化シリコンおよび酸化窒化シリコンは、熱的に安定であるため好ましい。特に、酸化シリコン、酸化窒化シリコン、空孔を有する酸化シリコンなどの材料は、加熱により脱離する酸素を含む領域を容易に形成することができるため好ましい。また、絶縁体２８０は、上記の材料が積層された構造でもよく、例えば、スパッタリング法で成膜した酸化シリコンと、その上に積層されたＣＶＤ法で成膜された酸化窒化シリコンの積層構造とすればよい。また、さらに上に窒化シリコンを積層してもよい。 For the insulator 280, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having holes is used. It is preferable to have. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having pores is preferable because a region containing oxygen which is released by heating can be easily formed. The insulator 280 may have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by a sputtering method and silicon oxynitride formed over the silicon oxide by a CVD method. do it. In addition, silicon nitride may be stacked further thereon.
　絶縁体２８０中の水または水素などの不純物濃度が低減されていることが好ましい。また、絶縁体２８０の上面は、平坦化されていてもよい。 It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Further, the upper surface of the insulator 280 may be flattened.
　絶縁体２８２および絶縁体２８３は、水または水素などの不純物が、上方から絶縁体２８０に混入するのを抑制するバリア絶縁膜として機能することが好ましい。また、絶縁体２８２および絶縁体２８３は、酸素の透過を抑制するバリア絶縁膜として機能することが好ましい。絶縁体２８２および絶縁体２８３としては、例えば、酸化アルミニウム、窒化シリコン、または窒化酸化シリコンなどの絶縁体を用いればよい。例えば、絶縁体２８２として、酸素に対してバリア性が高い酸化アルミニウムを用い、絶縁体２８３として、水素に対してバリア性が高い窒化シリコンまたは窒化酸化シリコンを用いればよい。 The insulator 282 and the insulator 283 preferably function as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulator 280 from above. Further, the insulator 282 and the insulator 283 preferably function as a barrier insulating film which suppresses oxygen permeation. As the insulator 282 and the insulator 283, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example. For example, aluminum oxide having a high barrier property against oxygen may be used as the insulator 282, and silicon nitride or silicon nitride oxide having a high barrier property to hydrogen may be used as the insulator 283.
　また、絶縁体２８３の上に、層間膜として機能する絶縁体２７４を設けることが好ましい。絶縁体２７４は、絶縁体２２４などと同様に、膜中の水または水素などの不純物濃度が低減されていることが好ましい。 Further, it is preferable to provide an insulator 274 functioning as an interlayer film on the insulator 283. Like the insulator 224 and the like, the insulator 274 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
　導電体２４０ａおよび導電体２４０ｂは、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。また、導電体２４０ａおよび導電体２４０ｂは積層構造としてもよい。なお、図１Ａで導電体２４０ａおよび導電体２４０ｂは、上面視において円形状にしているが、これに限られるものではない。例えば、導電体２４０ａおよび導電体２４０ｂが、上面視において、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。 For the conductor 240a and the conductor 240b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 240a and the conductor 240b may have a stacked structure. Although the conductor 240a and the conductor 240b are circular in a top view in FIG. 1A, they are not limited to this. For example, the conductors 240a and 240b may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.
　また、導電体２４０を積層構造とする場合、絶縁体２７４、絶縁体２８３、絶縁体２８２、絶縁体２８０、および絶縁体２７２と接する導電体には、水または水素などの不純物、および酸素の透過を抑制する機能を有する導電性材料を用いることが好ましい。例えば、タンタル、窒化タンタル、チタン、窒化チタン、ルテニウム、または酸化ルテニウムなどを用いることが好ましい。また、水または水素などの不純物、および酸素の透過を抑制する機能を有する導電性材料は、単層または積層で用いてもよい。当該導電性材料を用いることで、絶縁体２８０などから拡散する水または水素などの不純物が、導電体２４０ａおよび導電体２４０ｂを通じて酸化物２３０に混入するのをさらに低減することができる。また、絶縁体２８０に添加された酸素が導電体２４０ａおよび導電体２４０ｂに吸収されるのを防ぐことができる。 In the case where the conductor 240 has a stacked-layer structure, the insulator 274, the insulator 283, the insulator 282, the insulator 280, and the conductor in contact with the insulator 272 have impurities such as water or hydrogen and oxygen permeation in the conductor. It is preferable to use a conductive material having a function of suppressing For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. The conductive material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen may be used as a single layer or a stacked layer. By using the conductive material, impurities such as water or hydrogen that diffuse from the insulator 280 and the like can be further reduced from entering the oxide 230 through the conductors 240a and 240b. In addition, oxygen added to the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.
　絶縁体２４１ａおよび絶縁体２４１ｂとしては、例えば、窒化シリコン、酸化アルミニウム、または窒化酸化シリコンなどの絶縁体を用いればよい。絶縁体２４１ａおよび絶縁体２４１ｂは、絶縁体２７４、絶縁体２８３、絶縁体２８２、絶縁体２８０、および絶縁体２７２に接して設けられるので、絶縁体２８０などから水または水素などの不純物が、導電体２４０ａおよび導電体２４０ｂを通じて酸化物２３０に混入するのを抑制することができる。特に、窒化シリコンは水素に対するブロッキング性が高いので好適である。また、絶縁体２８０に含まれる酸素が導電体２４０ａおよび導電体２４０ｂに吸収されるのを防ぐことができる。 As the insulator 241a and the insulator 241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 274, the insulator 283, the insulator 282, the insulator 280, and the insulator 272, impurities such as water or hydrogen from the insulator 280 and the like can be conducted. Mixing into the oxide 230 through the body 240a and the conductor 240b can be suppressed. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.
　また、導電体２４０ａの上面、および導電体２４０ｂの上面に接して配線として機能する導電体２４６（導電体２４６ａ、および導電体２４６ｂ）を配置してもよい。導電体２４６は、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。また、当該導電体は、積層構造としてもよく、例えば、チタンまたは窒化チタンと上記導電性材料との積層としてもよい。なお、当該導電体は、絶縁体に設けられた開口に埋め込むように形成してもよい。 Further, the conductor 246 (the conductor 246a and the conductor 246b) which functions as wiring may be arranged in contact with the top surface of the conductor 240a and the top surface of the conductor 240b. The conductor 246 is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Further, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in the opening provided in the insulator.
＜半導体装置の構成材料＞
　以下では、半導体装置に用いることができる構成材料について説明する。 <Constituent material of semiconductor device>
The constituent materials that can be used for the semiconductor device will be described below.
＜基板＞
　トランジスタ２００を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 <Substrate>
As a substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulating region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, or the like can be given. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, a substrate provided with an element may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
＜絶縁体＞
　絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 <insulator>
Examples of the insulator include an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide.
　例えば、トランジスタの微細化、および高集積化が進むと、ゲート絶縁体の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁体として機能する絶縁体に、ｈｉｇｈ−ｋ材料を用いることで物理膜厚を保ちながら、トランジスタ動作時の低電圧化が可能となる。一方、層間膜として機能する絶縁体には、比誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。したがって、絶縁体の機能に応じて、材料を選択するとよい。 For example, as transistors become finer and more highly integrated, thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material having a low relative dielectric constant for the insulator functioning as the interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. Therefore, the material should be selected according to the function of the insulator.
　また、比誘電率の高い絶縁体としては、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウムおよびハフニウムを有する酸化物、アルミニウムおよびハフニウムを有する酸化窒化物、シリコンおよびハフニウムを有する酸化物、シリコンおよびハフニウムを有する酸化窒化物、またはシリコンおよびハフニウムを有する窒化物などがある。 As the insulator having a high relative dielectric constant, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, silicon and hafnium, can be used. And the like, or a nitride containing silicon and hafnium.
　また、比誘電率が低い絶縁体としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコン、または樹脂などがある。 As the insulator having a low relative dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or a hole is included. Examples include silicon oxide and resin.
　また、酸化物半導体を用いたトランジスタは、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体で囲うことによって、トランジスタの電気特性を安定にすることができる。水素などの不純物および酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウム、またはタンタルを含む絶縁体を、単層で、または積層で用いればよい。具体的には、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体として、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、または酸化タンタルなどの金属酸化物、窒化アルミニウム、窒化アルミニウムチタン、窒化チタン、窒化酸化シリコンまたは窒化シリコンなどの金属窒化物を用いることができる。 Also, a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium. The insulator containing lanthanum, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, a metal oxide such as tantalum oxide, a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
　また、ゲート絶縁体として機能する絶縁体は、加熱により脱離する酸素を含む領域を有する絶縁体であることが好ましい。例えば、加熱により脱離する酸素を含む領域を有する酸化シリコンまたは酸化窒化シリコンを酸化物２３０と接する構造とすることで、酸化物２３０が有する酸素欠損を補償することができる。 Also, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is released by heating. For example, with the structure where silicon oxide or silicon oxynitride having a region containing oxygen which is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
＜導電体＞
　導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 <Conductor>
As the conductor, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, and the like. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used. Preferably. Further, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize. A conductive material or a material that maintains conductivity even when absorbing oxygen is preferable. Alternatively, a semiconductor having high electric conductivity, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
　また、上記の材料で形成される導電層を複数積層して用いてもよい。例えば、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、酸素を含む導電性材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。 Alternatively, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be used. Further, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be used. Alternatively, a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.
　なお、トランジスタのチャネル形成領域に酸化物を用いる場合において、ゲートとして機能する導電体には、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造を用いることが好ましい。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から離脱した酸素がチャネル形成領域に供給されやすくなる。 Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked-layer structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate. preferable. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
　特に、ゲートとして機能する導電体として、チャネルが形成される金属酸化物に含まれる金属元素および酸素を含む導電性材料を用いることが好ましい。また、前述した金属元素および窒素を含む導電性材料を用いてもよい。例えば、窒化チタン、窒化タンタルなどの窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、チャネルが形成される金属酸化物に含まれる水素を捕獲することができる場合がある。または、外方の絶縁体などから混入する水素を捕獲することができる場合がある。 In particular, it is preferable to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen as a conductor functioning as a gate. Alternatively, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed can be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.
＜金属酸化物＞
　酸化物２３０として、酸化物半導体として機能する金属酸化物を用いることが好ましい。以下では、本発明に係る酸化物２３０に適用可能な金属酸化物について説明する。 <Metal oxide>
As the oxide 230, a metal oxide which functions as an oxide semiconductor is preferably used. The metal oxide applicable to the oxide 230 according to the present invention will be described below.
　金属酸化物は、少なくともインジウムまたは亜鉛を含むことが好ましい。特に、インジウムおよび亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウムまたは錫などが含まれていることが好ましい。また、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれていてもよい。 The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained.
　ここでは、金属酸化物が、インジウム、元素Ｍおよび亜鉛を有するＩｎ−Ｍ−Ｚｎ酸化物である場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウム、または錫などとする。そのほかの元素Ｍに適用可能な元素としては、ホウ素、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどがある。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。 Here, consider the case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium. However, in some cases, a combination of the above-mentioned elements may be used as the element M.
　なお、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 In this specification and the like, metal oxides having nitrogen may be collectively referred to as metal oxides. Further, the metal oxide containing nitrogen may be referred to as a metal oxynitride.
［金属酸化物の構造］
　酸化物半導体（金属酸化物）は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、ＣＡＡＣ−ＯＳ、多結晶酸化物半導体、ｎｃ−ＯＳ、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、および非晶質酸化物半導体などがある。 [Structure of metal oxide]
The oxide semiconductor (metal oxide) is divided into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), and an amorphous oxide. There are things like semiconductors.
　ＣＡＡＣ−ＯＳは、ｃ軸配向性を有し、かつａ−ｂ面方向において複数のナノ結晶が連結し、歪みを有した結晶構造となっている。なお、歪みとは、複数のナノ結晶が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。 CAAC-OS has a crystal structure having a c-axis orientation, and a plurality of nanocrystals are connected in the ab plane direction to have a strain. In addition, the strain refers to a portion in which the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in the region where a plurality of nanocrystals are connected.
　ナノ結晶は、六角形を基本とするが、正六角形状とは限らず、非正六角形状である場合がある。また、歪みにおいて、五角形、および七角形などの格子配列を有する場合がある。なお、ＣＡＡＣ−ＯＳにおいて、歪み近傍においても、明確な結晶粒界（グレインバウンダリーともいう）を確認することは難しい。すなわち、格子配列の歪みによって、結晶粒界の形成が抑制されていることがわかる。これは、ＣＡＡＣ−ＯＳが、ａ−ｂ面方向において酸素原子の配列が稠密でないことや、金属元素が置換することで原子間の結合距離が変化することなどによって、歪みを許容することができるためである。 　Nanocrystals are basically hexagonal, but they are not limited to regular hexagons and may be non-regular hexagons. In addition, the strain may have a lattice arrangement such as a pentagon and a heptagon. Note that in the CAAC-OS, it is difficult to confirm a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of strain. That is, it is understood that the distortion of the lattice arrangement suppresses the formation of crystal grain boundaries. This is because the CAAC-OS can tolerate strain due to a non-dense arrangement of oxygen atoms in the ab plane direction, a change in bond distance between atoms due to substitution with a metal element, or the like. This is because.
　また、ＣＡＡＣ−ＯＳは、インジウム、および酸素を有する層（以下、Ｉｎ層）と、元素Ｍ、亜鉛、および酸素を有する層（以下、（Ｍ，Ｚｎ）層）とが積層した、層状の結晶構造（層状構造ともいう）を有する傾向がある。なお、インジウムと元素Ｍは、互いに置換可能であり、（Ｍ，Ｚｎ）層の元素Ｍがインジウムと置換した場合、（Ｉｎ，Ｍ，Ｚｎ）層と表すこともできる。また、Ｉｎ層のインジウムが元素Ｍと置換した場合、（Ｉｎ，Ｍ）層と表すこともできる。 In addition, the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M,Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M of the (M,Zn) layer is replaced with indium, it can be expressed as an (In,M,Zn) layer. When the indium of the In layer is replaced with the element M, it can be expressed as an (In,M) layer.
　ＣＡＡＣ−ＯＳは結晶性の高い金属酸化物である。一方、ＣＡＡＣ−ＯＳは、明確な結晶粒界を確認することが難しいため、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。また、金属酸化物の結晶性は不純物の混入や欠陥の生成などによって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物や欠陥（酸素欠損（ＶＯ：ｏｘｙｇｅｎ　ｖａｃａｎｃｙともいう）など）の少ない金属酸化物ともいえる。したがって、ＣＡＡＣ−ＯＳを有する金属酸化物は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する金属酸化物は熱に強く、信頼性が高い。 CAAC-OS is a metal oxide with high crystallinity. On the other hand, in the CAAC-OS, since it is difficult to confirm a clear crystal grain boundary, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Moreover, since the crystallinity of the metal oxide that may be reduced by such generation of contamination and defects impurities, CAAC-OS impurities and defects (oxygen deficiency (V O: also referred to as oxygen vacancy), etc.) with little metal oxide It can be called a thing. Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide including the CAAC-OS is highly heat resistant and highly reliable.
　ｎｃ−ＯＳは、微小な領域（例えば、１ｎｍ以上１０ｎｍ以下の領域、特に１ｎｍ以上３ｎｍ以下の領域）において原子配列に周期性を有する。また、ｎｃ−ＯＳは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、ｎｃ−ＯＳは、分析方法によっては、ａ−ｌｉｋｅ　ＯＳや非晶質酸化物半導体と区別が付かない場合がある。 Nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Moreover, in the nc-OS, no regularity is found in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
　なお、インジウムと、ガリウムと、亜鉛と、を有する金属酸化物の一種である、インジウム−ガリウム−亜鉛酸化物（以下、ＩＧＺＯ）は、上述のナノ結晶とすることで安定な構造をとる場合がある。特に、ＩＧＺＯは、大気中では結晶成長がし難い傾向があるため、大きな結晶（ここでは、数ｍｍの結晶、または数ｃｍの結晶）よりも小さな結晶（例えば、上述のナノ結晶）とする方が、構造的に安定となる場合がある。 Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide containing indium, gallium, and zinc, may have a stable structure by using the above-described nanocrystal. is there. In particular, IGZO tends to have difficulty in crystal growth in the atmosphere, and thus a smaller crystal (for example, the above-mentioned nanocrystal) is used than a large crystal (here, a crystal of several mm or a crystal of several cm). However, it may be structurally stable.
　ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳと非晶質酸化物半導体との間の構造を有する金属酸化物である。ａ−ｌｉｋｅ　ＯＳは、鬆または低密度領域を有する。すなわち、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて、結晶性が低い。 The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the crystallinity of the a-like OS is lower than that of the nc-OS and the CAAC-OS.
　酸化物半導体（金属酸化物）は、多様な構造をとり、それぞれが異なる特性を有する。本発明の一態様の酸化物半導体は、非晶質酸化物半導体、多結晶酸化物半導体、ａ−ｌｉｋｅ　ＯＳ、ｎｃ−ＯＳ、ＣＡＡＣ−ＯＳのうち、二種以上を有していてもよい。 Oxide semiconductors (metal oxides) have various structures, and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
　なお、本発明の一態様の半導体装置においては、酸化物半導体（金属酸化物）の構造に特に限定はないが、結晶性を有すると好ましい。例えば、酸化物２３０をＣＡＡＣ−ＯＳ構造とし、酸化物２４３を六方晶の結晶構造とすることが出来る。酸化物２３０、及び酸化物２４３を上記の結晶構造とすることで、高い信頼性を有する半導体装置とすることができる。また、酸化物２３０ａ、酸化物２３０ｃ、および酸化物２４３を概略同じ組成とすることができる。 Note that in the semiconductor device of one embodiment of the present invention, the structure of the oxide semiconductor (metal oxide) is not particularly limited, but preferably has crystallinity. For example, the oxide 230 can have a CAAC-OS structure and the oxide 243 can have a hexagonal crystal structure. When the oxide 230 and the oxide 243 have the above crystal structure, a highly reliable semiconductor device can be obtained. Further, the oxide 230a, the oxide 230c, and the oxide 243 can have approximately the same composition.
［不純物］
　ここで、金属酸化物中における各不純物の影響について説明する。 [impurities]
Here, the influence of each impurity in the metal oxide will be described.
　また、金属酸化物にアルカリ金属またはアルカリ土類金属が含まれると、欠陥準位を形成し、キャリアを生成する場合がある。したがって、アルカリ金属またはアルカリ土類金属が含まれている金属酸化物をチャネル形成領域に用いたトランジスタはノーマリーオン特性となりやすい。このため、金属酸化物中のアルカリ金属またはアルカリ土類金属の濃度を低減することが好ましい。具体的には、金属酸化物中のアルカリ金属またはアルカリ土類金属の濃度（ＳＩＭＳにより得られる濃度）を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。 Further, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and a carrier may be generated. Therefore, a transistor including a metal oxide containing an alkali metal or an alkaline earth metal in a channel formation region is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of alkali metal or alkaline earth metal (concentration obtained by SIMS) in the metal oxide is 1×10 18 atoms/cm 3 or less, preferably 2×10 16 atoms/cm 3 or less. To do.
　また、金属酸化物に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。当該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。従って、水素が含まれている金属酸化物を用いたトランジスタは、ノーマリーオン特性となりやすい。このため、金属酸化物中の水素はできる限り低減されていることが好ましい。 Also, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, which may form oxygen deficiency. When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. Further, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including a metal oxide containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible.
　トランジスタの半導体に用いる金属酸化物として、結晶性の高い薄膜を用いることが好ましい。該薄膜を用いることで、トランジスタの安定性または信頼性を向上させることができる。該薄膜として、例えば、単結晶金属酸化物の薄膜または多結晶金属酸化物の薄膜が挙げられる。しかしながら、単結晶金属酸化物の薄膜または多結晶金属酸化物の薄膜を基板上に形成するには、高温またはレーザー加熱の工程が必要とされる。よって、製造工程のコストが増加し、さらに、スループットも低下してしまう。 It is preferable to use a thin film with high crystallinity as the metal oxide used for the semiconductor of the transistor. By using the thin film, stability or reliability of the transistor can be improved. Examples of the thin film include a single crystal metal oxide thin film and a polycrystalline metal oxide thin film. However, in order to form a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate, a high temperature or laser heating process is required. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.
＜半導体装置の作製方法＞
　次に、図１に示す、本発明に係るトランジスタ２００を有する半導体装置について、作製方法を図３乃至図１７を用いて説明する。また、図３乃至図１７において、各図のＡは上面図を示す。また、各図のＢは、Ａに示すＡ１−Ａ２の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、各図のＣは、ＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、各図のＤは、ＡにＡ５−Ａ６の一点鎖線で示す部位に対応する断面図である。なお、各図のＡの上面図では、図の明瞭化のために一部の要素を省いている。 <Method for manufacturing semiconductor device>
Next, a method for manufacturing the semiconductor device including the transistor 200 of the present invention shown in FIGS. 1A to 1C will be described with reference to FIGS. Further, in FIGS. 3 to 17, A in each drawing shows a top view. In addition, B in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 shown in A, and is also a cross-sectional view in the channel length direction of the transistor 200. In addition, C in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A3-A4 in A, and is also a cross-sectional view in the channel width direction of the transistor 200. Further, D in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in A. In addition, in the top view of A of each drawing, some elements are omitted for clarity of the drawing.
　まず、基板（図示しない）を準備し、当該基板上に絶縁体２１２を成膜する。絶縁体２１２の成膜は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法、パルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、またはＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などを用いて行うことができる。 First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate. The insulator 212 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method. (Atomic Layer Deposition) method can be used.
　なお、ＣＶＤ法は、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＣＶＤ）法、熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ　ＣＶＤ）法、光を利用する光ＣＶＤ（Ｐｈｏｔｏ　ＣＶＤ）法などに分類できる。さらに用いる原料ガスによって金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ　ＣＶＤ）法、有機金属ＣＶＤ（ＭＯＣＶＤ：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　ＣＶＤ）法に分けることができる。また、成膜時の圧力によって、大気圧下で成膜を行なう常圧ＣＶＤ（ＡＰＣＶＤ：Ａｔｍｏｓｐｈｅｒｉｃ　Ｐｒｅｓｓｕｒｅ　ＣＶＤ）法、大気圧より低い減圧状態で成膜を行う減圧ＣＶＤ（ＬＰＣＶＤ：Ｌｏｗ　Ｐｒｅｓｓｕｒｅ　ＣＶＤ）法、に分けることができる。 The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, and a photo CVD (Photo CVD) method that uses light. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used. In addition, depending on the pressure at the time of film formation, atmospheric pressure CVD (APCVD: Atmospheric Pressure CVD) method for forming a film under atmospheric pressure, and low pressure CVD (LPCVD: Low Pressure CVD) method for forming a film under a reduced pressure lower than atmospheric pressure , Can be divided into
　プラズマＣＶＤ法は、比較的低温で高品質の膜が得られる。また、熱ＣＶＤ法は、プラズマを用いないため、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。例えば、半導体装置に含まれる配線、電極、素子（トランジスタ、容量素子など）などは、プラズマから電荷を受け取ることでチャージアップする場合がある。このとき、蓄積した電荷によって、半導体装置に含まれる配線、電極、素子などが破壊される場合がある。一方、プラズマを用いない熱ＣＶＤ法の場合、こういったプラズマダメージが生じないため、半導体装置の歩留まりを高くすることができる。また、熱ＣＶＤ法では、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。 The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, the thermal CVD method is a film forming method which can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in a semiconductor device might be charged up by receiving electric charge from plasma. At this time, the accumulated charges may damage wirings, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, plasma damage does not occur during film formation, so that a film with few defects can be obtained.
　また、ＡＬＤ法としては、プリカーサ及びリアクタントの反応を熱エネルギーのみで行う熱ＡＬＤ（Ｔｈｅｒｍａｌ　ＡＬＤ）法、プラズマ励起されたリアクタントを用いるＰＥＡＬＤ（Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＡＬＤ）法などを用いることができる。 Further, as the ALD method, a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactant is performed only with thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant, and the like can be used.
　ＡＬＤ法は、原子の性質である自己制御性を利用し、一層ずつ原子を堆積することができるので、極薄の成膜が可能、アスペクト比の高い構造への成膜が可能、ピンホールなどの欠陥の少ない成膜が可能、被覆性に優れた成膜が可能、および低温での成膜が可能、などの効果がある。ＰＥＡＬＤ法では、プラズマを利用することで、より低温での成膜が可能となり好ましい場合がある。なお、ＡＬＤ法で用いるプリカーサには炭素などの不純物を含むものがある。このため、ＡＬＤ法により設けられた膜は、他の成膜法により設けられた膜と比較して、炭素などの不純物を多く含む場合がある。なお、不純物の定量は、Ｘ線光電子分光法（ＸＰＳ：Ｘ−ｒａｙ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて行うことができる。 The ALD method uses the self-controlling property of atoms and can deposit atoms one by one, so ultrathin films can be formed, films with high aspect ratios can be formed, pinholes, etc. It is possible to form a film with few defects, to form a film with excellent coverage, and to form a film at a low temperature. In the PEALD method, the use of plasma may allow film formation at a lower temperature, which is preferable in some cases. Note that some precursors used in the ALD method include impurities such as carbon. Therefore, a film formed by the ALD method may contain a large amount of impurities such as carbon as compared with a film formed by another film formation method. The impurities can be quantified using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
　ＣＶＤ法およびＡＬＤ法は、ターゲットなどから放出される粒子が堆積する成膜方法とは異なり、被処理物の表面における反応により膜が形成される成膜方法である。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。 The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, the film forming method is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of the opening having a high aspect ratio. However, since the ALD method has a relatively low film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.
　ＣＶＤ法およびＡＬＤ法は、原料ガスの流量比によって、得られる膜の組成を制御することができる。例えば、ＣＶＤ法およびＡＬＤ法では、原料ガスの流量比によって、任意の組成の膜を成膜することができる。また、例えば、ＣＶＤ法およびＡＬＤ法では、成膜しながら原料ガスの流量比を変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスの流量比を変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送や圧力調整に掛かる時間を要さない分、成膜に掛かる時間を短くすることができる。したがって、半導体装置の生産性を高めることができる場合がある。 In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gas. Further, for example, in the CVD method and the ALD method, it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of the raw material gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for transfer and pressure adjustment is less than in the case of film formation using multiple film formation chambers. can do. Therefore, it may be possible to improve the productivity of the semiconductor device.
　本実施の形態では、絶縁体２１２として、ＣＶＤ法によって窒化シリコンを成膜する。このように、絶縁体２１２として、窒化シリコンなどの銅が透過しにくい絶縁体を用いることにより、絶縁体２１２より下層（図示せず）の導電体に銅など拡散しやすい金属を用いても、当該金属が絶縁体２１２を介して上の層に拡散するのを抑制することができる。また、窒化シリコンのように水または水素などの不純物が透過しにくい絶縁体を用いることにより絶縁体２１２より下層から水または水素などの不純物の拡散を抑制することができる。 In this embodiment mode, a silicon nitride film is formed as the insulator 212 by a CVD method. As described above, by using an insulator such as silicon nitride in which copper is less likely to permeate as the insulator 212, even if a metal such as copper that easily diffuses is used as a conductor in a layer (not shown) below the insulator 212, The metal can be suppressed from diffusing into the upper layer through the insulator 212. Further, by using an insulator such as silicon nitride in which impurities such as water or hydrogen are less likely to permeate, diffusion of impurities such as water or hydrogen from a layer below the insulator 212 can be suppressed.
　次に、絶縁体２１２上に絶縁体２１４を成膜する。絶縁体２１４の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２１４として、酸化アルミニウムを用いる。 Next, the insulator 214 is formed over the insulator 212. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.
　次に、絶縁体２１４上に絶縁体２１６を成膜する。絶縁体２１６の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２１６として、酸化シリコンまたは酸化窒化シリコンを用いる。また、絶縁体２１６は、上述の水素原子が低減または除去されたガスを用いた成膜方法で成膜することが好ましい。これにより、絶縁体２１６の水素濃度を低減することができる。 Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. In addition, the insulator 216 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 216 can be reduced.
　次に、絶縁体２１６に絶縁体２１４に達する開口を形成する。開口とは、例えば、溝やスリットなども含まれる。また、開口が形成された領域を指して開口部とする場合がある。開口の形成はウェットエッチングを用いてもよいが、ドライエッチングを用いるほうが微細加工には好ましい。また、絶縁体２１４は、絶縁体２１６をエッチングして溝を形成する際のエッチングストッパ膜として機能する絶縁体を選択することが好ましい。例えば、溝を形成する絶縁体２１６に酸化シリコン膜または酸化窒化シリコン膜を用いた場合は、絶縁体２１４は窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜を用いるとよい。 Next, an opening reaching the insulator 214 is formed in the insulator 216. The openings include, for example, grooves and slits. In addition, the area where the opening is formed may be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. Further, as the insulator 214, it is preferable to select an insulator which functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when a silicon oxide film or a silicon oxynitride film is used for the insulator 216 which forms the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.
　開口の形成後に、導電体２０５ａとなる導電膜を成膜する。該導電膜は、酸素の透過を抑制する機能を有する導電体を含むことが望ましい。たとえば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。またはタンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。導電体２０５ａとなる導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 After forming the opening, a conductive film to be the conductor 205a is formed. The conductive film preferably contains a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. The conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　本実施の形態では、導電体２０５ａとなる導電膜を多層構造とする。まず、スパッタリング法によって窒化タンタルを成膜し、当該窒化タンタルの上に窒化チタンを積層する。このような金属窒化物を導電体２０５ｂの下層に用いることにより、後述する導電体２０５ｂとなる導電膜として銅などの拡散しやすい金属を用いても、当該金属が導電体２０５ａから外に拡散するのを防ぐことができる。 In this embodiment, the conductive film to be the conductor 205a has a multi-layer structure. First, a tantalum nitride film is formed by a sputtering method, and titanium nitride is laminated on the tantalum nitride film. By using such a metal nitride in the lower layer of the conductor 205b, even if a metal such as copper that easily diffuses is used as a conductive film to be the conductor 205b described later, the metal diffuses out from the conductor 205a. Can be prevented.
　次に、導電体２０５ｂとなる導電膜を成膜する。該導電膜の成膜は、メッキ法、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。本実施の形態では、導電体２０５ｂとなる導電膜として、銅などの低抵抗導電性材料を成膜する。 Next, a conductive film to be the conductor 205b is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a low-resistance conductive material such as copper is formed as a conductive film to be the conductor 205b.
　次に、ＣＭＰ処理（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）を行うことで、導電体２０５ａとなる導電膜、ならびに導電体２０５ｂとなる導電膜の一部を除去し、絶縁体２１６を露出する。その結果、開口部のみに、導電体２０５ａ及び導電体２０５ｂが残存する。これにより、上面が平坦な、導電体２０５を形成することができる。なお、当該ＣＭＰ処理により、絶縁体２１６の一部が除去される場合がある（図２０参照）。 Next, a CMP process (Chemical Mechanical Polishing) is performed to remove the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b, so that the insulator 216 is exposed. As a result, the conductors 205a and 205b remain only in the openings. Thus, the conductor 205 having a flat upper surface can be formed. Note that part of the insulator 216 may be removed by the CMP treatment (see FIG. 20).
　なお、上記においては、導電体２０５を絶縁体２１６の開口に埋め込むように形成したが、本実施の形態はこれに限られるものではない。例えば、絶縁体２１４上に導電体２０５を形成し、導電体２０５上に絶縁体２１６を成膜し、絶縁体２１６にＣＭＰ処理を行うことで、絶縁体２１６の一部を除去し、導電体２０５の表面を露出させてもよい。 In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but the present embodiment is not limited to this. For example, the conductor 205 is formed over the insulator 214, the insulator 216 is formed over the conductor 205, and the insulator 216 is subjected to CMP treatment so that part of the insulator 216 is removed and the conductor 216 is removed. The surface of 205 may be exposed.
　次に、絶縁体２１６、および導電体２０５上に絶縁体２２２を成膜する。絶縁体２２２として、アルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体を成膜するとよい。なお、アルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体として、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。アルミニウムおよびハフニウムの一方または双方の酸化物を含む絶縁体は、酸素、水素、および水に対するバリア性を有する。絶縁体２２２が、水素および水に対するバリア性を有することで、トランジスタ２００の周辺に設けられた構造体に含まれる水素、および水が、絶縁体２２２を通じてトランジスタ２００の内側へ拡散することが抑制され、酸化物２３０中の酸素欠損の生成を抑制することができる。 Next, the insulator 222 is formed over the insulator 216 and the conductor 205. As the insulator 222, an insulator containing one or both oxides of aluminum and hafnium may be formed. As the insulator containing one or both oxides of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. The insulator 222 having a barrier property against hydrogen and water suppresses diffusion of hydrogen and water contained in the structure provided around the transistor 200 to the inside of the transistor 200 through the insulator 222. The generation of oxygen vacancies in the oxide 230 can be suppressed.
　絶縁体２２２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。 The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、絶縁体２２２上に絶縁体２２４を成膜する。絶縁体２２４の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２２４として、酸化シリコンまたは酸化窒化シリコンを用いる。また、絶縁体２２４は、上述の水素原子が低減または除去されたガスを用いた成膜方法で成膜することが好ましい。これにより、絶縁体２２４の水素濃度を低減することができる。絶縁体２２４は、後の工程で酸化物２３０ａと接する絶縁体２２４となるので、このように水素濃度が低減されていることが好適である。 Next, the insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 224. The insulator 224 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 224 can be reduced. Since the insulator 224 becomes the insulator 224 that is in contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.
　続いて、加熱処理を行うことが好ましい。加熱処理は、２５０℃以上６５０℃以下、好ましくは３００℃以上５００℃以下、さらに好ましくは３２０℃以上４５０℃以下で行えばよい。なお、加熱処理は、窒素または不活性ガス雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上、もしくは１０％以上含む雰囲気で行う。また、加熱処理は減圧状態で行ってもよい。または、加熱処理は、窒素または不活性ガス雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上、または１０％以上含む雰囲気で加熱処理を行ってもよい。 Next, it is preferable to perform heat treatment. The heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 300 °C to 500 °C inclusive, and more preferably 320 °C to 450 °C inclusive. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere and then in an atmosphere containing an oxidizing gas in an amount of 10 ppm or higher, 1% or higher, or 10% or higher in order to supplement desorbed oxygen. Good.
　本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行った後に、連続して酸素雰囲気にて４００℃の温度で１時間の処理を行う。当該加熱処理によって、絶縁体２２４に含まれる水、水素などの不純物を除去することができる。 In the present embodiment, after performing a treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, a treatment for 1 hour at a temperature of 400° C. is continuously performed in an oxygen atmosphere. By the heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.
　また、加熱処理は、絶縁体２２２の成膜後に行ってもよい。当該加熱処理は、上述した加熱処理条件を用いることができる。 Alternatively, the heat treatment may be performed after the insulator 222 is formed. The heat treatment conditions described above can be used for the heat treatment.
　ここで、絶縁体２２４に過剰酸素領域を形成するために、減圧状態で酸素を含むプラズマ処理を行ってもよい。酸素を含むプラズマ処理は、例えばマイクロ波を用いた高密度プラズマを発生させる電源を有する装置を用いることが好ましい。または、基板側にＲＦなどの高周波を印加する電源を有してもよい。高密度プラズマを用いることより、高密度の酸素ラジカルを生成することができ、基板側にＲＦを印加することで、高密度プラズマによって生成された酸素ラジカルを効率よく絶縁体２２４内に導くことができる。または、この装置を用いて不活性ガスを含むプラズマ処理を行った後に、脱離した酸素を補うために酸素を含むプラズマ処理を行ってもよい。なお、当該プラズマ処理の条件を適宜選択することにより、絶縁体２２４に含まれる水、水素などの不純物を除去することができる。その場合、加熱処理は行わなくてもよい。 Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves, for example. Alternatively, a power source for applying a high frequency wave such as RF may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently introduced into the insulator 224. it can. Alternatively, after performing plasma treatment containing an inert gas using this apparatus, plasma treatment containing oxygen may be performed in order to supplement desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by selecting appropriate conditions for the plasma treatment. In that case, heat treatment may not be performed.
　ここで、絶縁体２２４上に、例えば、スパッタリング法によって、酸化アルミニウムを成膜し、該酸化アルミニウムを絶縁体２２４に達するまで、ＣＭＰを行ってもよい。当該ＣＭＰを行うことで絶縁体２２４表面の平坦化および絶縁体２２４表面の平滑化を行うことができる。当該酸化アルミニウムを絶縁体２２４上に配置してＣＭＰを行うことで、ＣＭＰの終点検出が容易となる。また、ＣＭＰによって、絶縁体２２４の一部が研磨されて、絶縁体２２４の膜厚が薄くなることがあるが、絶縁体２２４の成膜時に膜厚を調整すればよい。絶縁体２２４表面の平坦化および平滑化を行うことで、後に成膜する酸化物の被覆率の悪化を防止し、半導体装置の歩留りの低下を防ぐことができる場合がある。また、絶縁体２２４上に、スパッタリング法によって、酸化アルミニウムを成膜することにより、絶縁体２２４に酸素を添加することができるので好ましい。 Here, aluminum oxide may be formed on the insulator 224 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 224. By performing the CMP, the surface of the insulator 224 can be planarized and the surface of the insulator 224 can be smoothed. By disposing the aluminum oxide on the insulator 224 and performing CMP, the end point of CMP can be easily detected. Further, although part of the insulator 224 is polished by CMP and the thickness of the insulator 224 is reduced in some cases, the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, deterioration in coverage of an oxide film to be formed later can be prevented in some cases and reduction in yield of semiconductor devices can be prevented. In addition, oxygen can be added to the insulator 224 by depositing aluminum oxide over the insulator 224 by a sputtering method, which is preferable.
　次に、絶縁体２２４上に、酸化膜２３０Ａ、酸化膜２３０Ｂを順に成膜する（図３参照）。なお、上記酸化膜は、大気環境にさらさずに連続して成膜することが好ましい。大気開放せずに成膜することで、酸化膜２３０Ａ、および酸化膜２３０Ｂ上に大気環境からの不純物または水分が付着することを防ぐことができ、酸化膜２３０Ａと酸化膜２３０Ｂとの界面近傍を清浄に保つことができる。 Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see FIG. 3). The oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
　酸化膜２３０Ａおよび、酸化膜２３０Ｂの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。 The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　例えば、酸化膜２３０Ａ、および酸化膜２３０Ｂをスパッタリング法によって成膜する場合は、スパッタリングガスとして酸素、または、酸素と希ガスの混合ガスを用いる。スパッタリングガスに含まれる酸素の割合を高めることで、成膜される酸化膜中の過剰酸素を増やすことができる。また、上記の酸化膜をスパッタリング法によって成膜する場合は、上記のＩｎ−Ｍ−Ｚｎ酸化物ターゲットを用いることができる。 For example, when forming the oxide film 230A and the oxide film 230B by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. When the above oxide film is formed by the sputtering method, the above In-M-Zn oxide target can be used.
　特に、酸化膜２３０Ａの成膜時に、スパッタリングガスに含まれる酸素の一部が絶縁体２２４に供給される場合がある。したがって、酸化膜２３０Ａのスパッタリングガスに含まれる酸素の割合は７０％以上、好ましくは８０％以上、より好ましくは１００％とすればよい。 In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A is 70% or higher, preferably 80% or higher, more preferably 100%.
　また、酸化膜２３０Ｂをスパッタリング法で形成する場合、スパッタリングガスに含まれる酸素の割合を１％以上３０％以下、好ましくは５％以上２０％以下として成膜すると、酸素欠乏型の酸化物半導体が形成される。酸素欠乏型の酸化物半導体をチャネル形成領域に用いたトランジスタは、比較的高い電界効果移動度が得られる。また、基板を加熱しながら成膜を行うことによって、当該酸化膜の結晶性を向上させることができる。ただし、本発明の一態様はこれに限定されない。酸化膜２３０Ｂをスパッタリング法で形成する場合、スパッタリングガスに含まれる酸素の割合を、３０％を超えて１００％以下、好ましくは７０％以上１００％以下として成膜すると、酸素過剰型の酸化物半導体が形成される。酸素過剰型の酸化物半導体をチャネル形成領域に用いたトランジスタは、比較的高い信頼性が得られる。 In the case where the oxide film 230B is formed by a sputtering method, if the proportion of oxygen contained in the sputtering gas is 1% to 30% inclusive, preferably 5% to 20% inclusive, an oxygen-deficient oxide semiconductor is obtained. It is formed. A transistor including an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility. Further, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved. However, one embodiment of the present invention is not limited to this. In the case where the oxide film 230B is formed by a sputtering method, if the proportion of oxygen contained in the sputtering gas is greater than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen-excess oxide semiconductor is formed. Is formed. A transistor including an oxygen-excess type oxide semiconductor in a channel formation region has relatively high reliability.
　本実施の形態では、酸化膜２３０Ａとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：１：０．５［原子数比］（２：２：１［原子数比］）、あるいは１：３：４［原子数比］のターゲットを用いて成膜する。また、酸化膜２３０Ｂとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］、あるいは１：１：１［原子数比］のターゲットを用いて成膜する。なお、各酸化膜は、成膜条件、および原子数比を適宜選択することで、酸化物２３０に求める特性に合わせて形成するとよい。 In this embodiment, as the oxide film 230A, In:Ga:Zn=1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or 1:3 by a sputtering method. : A film is formed using a target of 4 [atomic ratio]. Further, the oxide film 230B is formed by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] or 1:1:1 [atomic ratio]. Note that each oxide film may be formed in accordance with characteristics required for the oxide 230 by appropriately selecting film formation conditions and atomic ratio.
　次に、加熱処理を行ってもよい。加熱処理は、上述した加熱処理条件を用いることができる。加熱処理によって、酸化膜２３０Ａ、および酸化膜２３０Ｂ中の水、水素などの不純物を除去することなどができる。本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行った後に、連続して酸素雰囲気にて４００℃の温度で１時間の処理を行う。 Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In this embodiment mode, after performing treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, treatment is continuously performed at a temperature of 400° C. for 1 hour in an oxygen atmosphere.
　次に、酸化膜２３０Ｂ上に酸化膜２４３Ａを成膜する（図３参照）。酸化膜２４３Ａの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。酸化膜２４３Ａは、Ｉｎに対するＧａの原子数比が、酸化膜２３０ＢのＩｎに対するＧａの原子数比より大きいことが好ましい。本実施の形態では、酸化膜２４３Ａとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜する。 Next, an oxide film 243A is formed on the oxide film 230B (see FIG. 3). The oxide film 243A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 243A preferably has an atomic ratio of Ga to In that is larger than an atomic ratio of Ga to In of the oxide film 230B. In this embodiment mode, the oxide film 243A is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio].
　次に、酸化膜２４３Ａ上に導電膜２４２Ａを成膜する（図３参照）。導電膜２４２Ａの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。 Next, a conductive film 242A is formed on the oxide film 243A (see FIG. 3). The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、導電膜２４２Ａ上に絶縁膜２７２Ａを成膜する（図３参照）。絶縁膜２７２Ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。絶縁膜２７２Ａは、酸素の透過を抑制する機能を有する絶縁膜を用いることが好ましい。例えば、スパッタリング法またはＡＬＤ法によって、酸化アルミニウム、窒化シリコン、酸化シリコン、または、酸化ガリウムを成膜してもよい。 Next, an insulating film 272A is formed on the conductive film 242A (see FIG. 3). The insulating film 272A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 272A, it is preferable to use an insulating film having a function of suppressing permeation of oxygen. For example, aluminum oxide, silicon nitride, silicon oxide, or gallium oxide may be formed by a sputtering method or an ALD method.
　次に、絶縁膜２７２Ａ上に導電膜２４７Ａを成膜する（図３参照）。導電膜２４７Ａの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。 Next, a conductive film 247A is formed over the insulating film 272A (see FIG. 3). The conductive film 247A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、リソグラフィー法を用いて、酸化膜２３０Ａ、酸化膜２３０Ｂ、酸化膜２４３Ａ、導電膜２４２Ａ、絶縁膜２７２Ａ、および導電膜２４７Ａを島状に加工して、酸化物２３０ａ、酸化物２３０ｂ、酸化物層２４３Ｂ、導電体層２４２Ｂ、絶縁体層２７２Ｂ、および導電体層２４７Ｂを形成する（図４参照）。ここで、酸化物２３０ａ、酸化物２３０ｂ、酸化物層２４３Ｂ、導電体層２４２Ｂ、絶縁体層２７２Ｂ、および導電体層２４７Ｂは、少なくとも一部が導電体２０５と重なるように形成する。また、当該加工はドライエッチング法やウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。なお、当該工程において、絶縁体２２４の酸化物２３０ａと重ならない領域の膜厚が薄くなることがある。 Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 272A, and the conductive film 247A are processed into an island shape by a lithography method to form the oxide 230a, the oxide 230b, and the oxide film. The object layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are formed (see FIG. 4). Here, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are formed so that at least part of them overlaps with the conductor 205. Further, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing. Note that in this step, the thickness of a region of the insulator 224 which does not overlap with the oxide 230a may be thin.
　なお、リソグラフィー法では、まず、マスクを介してレジストを露光する。次に、露光された領域を、現像液を用いて除去または残存させてレジストマスクを形成する。次に、当該レジストマスクを介してエッチング処理することで導電体、半導体または絶縁体などを所望の形状に加工することができる。例えば、ＫｒＦエキシマレーザ光、ＡｒＦエキシマレーザ光、ＥＵＶ（Ｅｘｔｒｅｍｅ　Ｕｌｔｒａｖｉｏｌｅｔ）光などを用いて、レジストを露光することでレジストマスクを形成すればよい。また、基板と投影レンズとの間に液体（例えば水）を満たして露光する、液浸技術を用いてもよい。また、前述した光に代えて、電子ビームやイオンビームを用いてもよい。なお、電子ビームやイオンビームを用いる場合には、マスクは不要となる。なお、レジストマスクの除去には、アッシングなどのドライエッチング処理を行う、ウェットエッチング処理を行う、ドライエッチング処理後にウェットエッチング処理を行う、またはウェットエッチング処理後にドライエッチング処理を行うことができる。 In the lithography method, first, the resist is exposed through a mask. Next, the exposed region is removed or left using a developing solution to form a resist mask. Next, the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, an electron beam or an ion beam may be used instead of the above-mentioned light. If an electron beam or an ion beam is used, no mask is needed. Note that the resist mask can be removed by performing dry etching treatment such as ashing, performing wet etching treatment, performing wet etching treatment after dry etching treatment, or performing dry etching treatment after wet etching treatment.
　また、レジストマスクの代わりに絶縁体や導電体からなるハードマスクを用いてもよい。ハードマスクを用いる場合、導電膜２４２Ａ上にハードマスク材料となる絶縁膜や導電膜を形成し、その上にレジストマスクを形成し、ハードマスク材料をエッチングすることで所望の形状のハードマスクを形成することができる。導電膜２４２Ａなどのエッチングは、レジストマスクを除去してから行っても良いし、レジストマスクを残したまま行っても良い。後者の場合、エッチング中にレジストマスクが消失することがある。導電膜２４２Ａなどのエッチング後にハードマスクをエッチングにより除去しても良い。一方、ハードマスクの材料が後工程に影響が無い、あるいは後工程で利用できる場合、必ずしもハードマスクを除去する必要は無い。本実施の形態では、絶縁体層２７２Ｂ、および導電体層２４７Ｂをハードマスクとして用いる。 Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material is formed over the conductive film 242A, a resist mask is formed thereover, and the hard mask material is etched to form a hard mask having a desired shape. can do. Etching of the conductive film 242A or the like may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the conductive film 242A or the like, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask. In this embodiment, the insulator layer 272B and the conductor layer 247B are used as a hard mask.
　ドライエッチング装置としては、平行平板型電極を有する容量結合型プラズマ（ＣＣＰ：Ｃａｐａｃｉｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置を用いることができる。平行平板型電極を有する容量結合型プラズマエッチング装置は、平行平板型電極の一方の電極に高周波電源を印加する構成でもよい。または平行平板型電極の一方の電極に複数の異なった高周波電源を印加する構成でもよい。または平行平板型電極それぞれに同じ周波数の高周波電源を印加する構成でもよい。または平行平板型電極それぞれに周波数の異なる高周波電源を印加する構成でもよい。または高密度プラズマ源を有するドライエッチング装置を用いることができる。高密度プラズマ源を有するドライエッチング装置は、例えば、誘導結合型プラズマ（ＩＣＰ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置などを用いることができる。 As the dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having the parallel plate electrodes may have a configuration in which a high frequency power source is applied to one of the parallel plate electrodes. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate electrodes. Alternatively, a high frequency power source having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a configuration may be adopted in which high frequency power supplies having different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus can be used.
　ここで、絶縁体層２７２Ｂ、および導電体層２４７Ｂが導電体層２４２Ｂのマスクとして機能するので、図４Ｃ、図４Ｄに示すように、導電体層２４２Ｂは側面と上面の間に湾曲面を有しない。これにより、図１に示す導電体２４２ａおよび導電体２４２ｂは、側面と上面が交わる端部が角状になる。導電体２４２の側面と上面が交わる端部が角状になることで、当該端部が曲面を有する場合に比べて、導電体２４２の断面積が大きくなる。これにより、導電体２４２の抵抗が低減されるので、トランジスタ２００のオン電流を大きくすることができる。 Here, since the insulator layer 272B and the conductor layer 247B function as a mask of the conductor layer 242B, the conductor layer 242B has a curved surface between the side surface and the top surface as illustrated in FIGS. 4C and 4D. do not do. As a result, the conductor 242a and the conductor 242b shown in FIG. 1 have angular end portions where the side surfaces and the upper surface intersect. Since the end portion where the side surface and the upper surface of the conductor 242 intersect is angular, the cross-sectional area of the conductor 242 is larger than that in the case where the end portion has a curved surface. Accordingly, the resistance of the conductor 242 is reduced, so that the on-state current of the transistor 200 can be increased.
　また、酸化物２３０ａ、酸化物２３０ｂ、酸化物層２４３Ｂ、導電体層２４２Ｂ、絶縁体層２７２Ｂ、および導電体層２４７Ｂの側面は、絶縁体２２２の上面に対し、概略垂直であることが好ましい。酸化物２３０ａ、酸化物２３０ｂ、酸化物層２４３Ｂ、導電体層２４２Ｂ、絶縁体層２７２Ｂ、および導電体層２４７Ｂの側面が、絶縁体２２２の上面に対し、概略垂直であることで、複数のトランジスタ２００を設ける際に、小面積化、高密度化が可能となる。ただし、これに限られず、酸化物２３０ａ、酸化物２３０ｂ、酸化物層２４３Ｂ、導電体層２４２Ｂ、絶縁体層２７２Ｂ、および導電体層２４７Ｂの側面と絶縁体２２２の上面のなす角が低い角度になる構成にしてもよい。 Further, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B are substantially perpendicular to the top surface of the insulator 222, the plurality of transistors can be formed. When 200 is provided, the area can be reduced and the density can be increased. However, the invention is not limited thereto, and the angle formed between the side surface of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B and the top surface of the insulator 222 is low. It may be configured as follows.
　次に、絶縁体２２４、酸化物２３０ａ、酸化物２３０ｂ、酸化物層２４３Ｂ、導電体層２４２Ｂ、絶縁体層２７２Ｂ、および導電体層２４７Ｂの上に、絶縁膜２７３Ａを成膜する（図５参照）。絶縁膜２７３Ａの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 Next, the insulating film 273A is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the conductor layer 247B (see FIG. 5). ). The insulating film 273A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、絶縁膜２７３Ａを異方性エッチングすることで、導電体層２４７Ｂ上の絶縁膜２７３Ａ、および絶縁体２２４上の絶縁膜２７３Ａを除去する。次に、導電体層２４７Ｂを除去することで、絶縁体層２７３Ｂを形成する。絶縁体層２７３Ｂは、少なくとも酸化物２３０ａの側面、酸化物２３０ｂの側面、酸化物層２４３Ｂの側面、および導電体層２４２Ｂの側面と接するように形成することが好ましい（図６参照）。 Next, the insulating film 273A is anisotropically etched to remove the insulating film 273A on the conductor layer 247B and the insulating film 273A on the insulator 224. Next, the conductor layer 247B is removed, so that the insulator layer 273B is formed. The insulator layer 273B is preferably formed so as to be in contact with at least the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the oxide layer 243B, and the side surface of the conductor layer 242B (see FIG. 6).
　次に、絶縁体２２４、酸化物２３０ａ、酸化物２３０ｂ、酸化物層２４３Ｂ、導電体層２４２Ｂ、絶縁体層２７２Ｂ、および絶縁体層２７３Ｂの上に、絶縁体２８０となる絶縁膜を成膜する。絶縁体２８０となる絶縁膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。例えば、絶縁体２８０として、スパッタリング法を用いて酸化シリコン膜を成膜し、その上にＰＥＡＬＤ法またはサーマルＡＬＤ法を用いて酸化シリコン膜を成膜すればよい。また、絶縁体２８０となる絶縁膜は、上述の水素原子が低減または除去されたガスを用いた成膜方法で成膜することが好ましい。これにより、絶縁体２８０の水素濃度を低減することができる。 Next, an insulating film to be the insulator 280 is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, the insulator layer 272B, and the insulator layer 273B. .. The insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulator 280, a silicon oxide film may be formed by a sputtering method and a silicon oxide film may be formed thereover by a PEALD method or a thermal ALD method. Further, the insulating film to be the insulator 280 is preferably formed by the above-described film forming method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulator 280 can be reduced.
　次に、絶縁体２８０にＣＭＰ処理を行い、上面が平坦な絶縁体２８０を形成する（図７参照）。なお、絶縁体２２４と同様に、絶縁体２８０上に、例えば、スパッタリング法によって、酸化アルミニウムを成膜し、該酸化アルミニウムを絶縁体２８０に達するまで、ＣＭＰを行ってもよい。 Next, the insulator 280 is subjected to CMP treatment to form the insulator 280 having a flat upper surface (see FIG. 7). Note that similarly to the insulator 224, aluminum oxide may be formed over the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.
　次に、マイクロ波、またはＲＦ等の高周波を絶縁体２８０、酸化物２３０ｂ、および酸化物２３０ａに照射してもよい。照射されたマイクロ波、またはＲＦ等の高周波は絶縁体２８０、酸化物２３０ｂ、および酸化物２３０ａ中に浸透して、これらの中の水素を除去する。特に、酸化物２３０ａおよび酸化物２３０ｂにおいては、ＶｏＨの結合が切断される反応が起きて、別言すると「ＶＯＨ→Ｖｏ＋Ｈ」という反応が起きて、脱水素化されることになる。このとき発生した水素の一部は、酸素と結合してＨ２Ｏとして、酸化物２３０、および絶縁体２８０から除去される場合がある。また、水素の一部は、導電体２４２にゲッタリングされる場合がある。このように、マイクロ波、またはＲＦ等の高周波を照射することで、絶縁体２８０、酸化物２３０ｂ、および酸化物２３０ａ中の水素濃度を低減することができる。なお、マイクロ波、またはＲＦ等の高周波の照射は、上記ＣＭＰ処理の前に行ってもよい。 Next, the insulator 280, the oxide 230b, and the oxide 230a may be irradiated with microwaves or high frequencies such as RF. Irradiated microwaves or high frequencies such as RF penetrate into the insulator 280, the oxide 230b, and the oxide 230a, and remove hydrogen in these. In particular, in the oxide 230a and oxides 230b, happening reactions coupling VoH is disconnected, when other words happening reaction of "V O H → Vo + H", will be dehydrogenated. Part of the hydrogen generated at this time may be removed from the oxide 230 and the insulator 280 as H 2 O by combining with oxygen. Further, part of hydrogen may be gettered to the conductor 242 in some cases. Thus, irradiation with microwaves or high frequencies such as RF can reduce the hydrogen concentration in the insulator 280, the oxide 230b, and the oxide 230a. Note that irradiation with microwaves or high frequencies such as RF may be performed before the CMP treatment.
　また、マイクロ波、またはＲＦ等の高周波によって酸素ガスをプラズマ化し、酸素ラジカルを形成してもよい。つまり、絶縁体２８０、酸化物２３０ｂ、および酸化物２３０ａに酸素を有する雰囲気でプラズマ処理を行ってもよい。このような処理を以下において、酸素プラズマ処理という場合がある。また、形成した酸素ラジカルによって、絶縁体２８０、酸化物２３０ｂ、および酸化物２３０ａ中に酸素を供給することができる。また、絶縁体２８０、酸化物２３０ｂ、および酸化物２３０ａに酸素を有する雰囲気でプラズマ処理を行う場合、酸化物２３０にマイクロ波、またはＲＦ等の高周波が照射されにくい構成にしてもよい。 Alternatively, oxygen radicals may be formed by converting oxygen gas into plasma by microwaves or high frequencies such as RF. That is, plasma treatment may be performed in an atmosphere in which the insulator 280, the oxide 230b, and the oxide 230a contain oxygen. Hereinafter, such a process may be referred to as an oxygen plasma process. Further, oxygen can be supplied to the insulator 280, the oxide 230b, and the oxide 230a by the formed oxygen radical. In the case where plasma treatment is performed on the insulator 280, the oxide 230b, and the oxide 230a in an atmosphere containing oxygen, the oxide 230 may be less likely to be irradiated with microwaves or high frequencies such as RF.
　なお、酸素プラズマ処理は、例えばマイクロ波を用いた高密度プラズマを発生させる電源を有する、マイクロ波処理装置を用いることが好ましい。また、マイクロ波処理装置は基板側にＲＦを印加する電源を有してもよい。高密度プラズマを用いることより、高密度の酸素ラジカルを生成することができる。また、基板側にＲＦを印加することで、高密度プラズマによって生成された酸素イオンを、効率よく絶縁体２８０および酸化物２３０中に導くことができる。また、上記酸素プラズマ処理は、減圧下で行うことが好ましく、圧力を６０Ｐａ以上、好ましくは１３３Ｐａ以上、より好ましくは２００Ｐａ以上、さらに好ましくは４００Ｐａ以上とすればよい。また、酸素流量比（Ｏ２／Ｏ２＋Ａｒ）が５０％以下、好ましくは１０％以上３０％以下で行うとよい。また、処理温度は、例えば４００℃程度で行えばよい。また、酸素プラズマ処理を行った後に、外気に曝すことなく、連続して熱処理を行ってもよい。 For the oxygen plasma treatment, it is preferable to use a microwave treatment apparatus having a power source for generating high-density plasma using microwaves, for example. Further, the microwave processing apparatus may have a power source for applying RF on the substrate side. By using high density plasma, high density oxygen radicals can be generated. Further, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the insulator 280 and the oxide 230. The oxygen plasma treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, still more preferably 400 Pa or higher. The oxygen flow rate ratio (O 2 /O 2 +Ar) is 50% or less, preferably 10% or more and 30% or less. Further, the processing temperature may be about 400° C., for example. Further, after the oxygen plasma treatment is performed, the heat treatment may be continuously performed without being exposed to the outside air.
　次に、絶縁体２８０の一部、絶縁体層２７２Ｂの一部、絶縁体層２７３Ｂの一部、導電体層２４２Ｂの一部、および酸化物層２４３Ｂの一部を加工して、酸化物２３０ｂに達する開口を形成する（図８参照）。該開口は、導電体２０５と重なるように形成することが好ましい。該開口の形成によって、酸化物２４３ａ、酸化物２４３ｂ、導電体２４２ａ、導電体２４２ｂ、絶縁体２７２ａ、絶縁体２７２ｂ、絶縁体２７３ａ、および絶縁体２７３ｂを形成する。 Next, part of the insulator 280, part of the insulator layer 272B, part of the insulator layer 273B, part of the conductor layer 242B, and part of the oxide layer 243B are processed to form the oxide 230b. (See FIG. 8). The opening is preferably formed so as to overlap with the conductor 205. By forming the opening, the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272a, the insulator 272b, the insulator 273a, and the insulator 273b are formed.
　絶縁体２８０の一部、絶縁体層２７２Ｂの一部、絶縁体層２７３Ｂの一部、導電体層２４２Ｂ、および酸化物層２４３Ｂの一部の加工は、ドライエッチング法、またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。また、当該加工は、それぞれ異なる条件で加工してもよい。例えば、絶縁体２８０の一部をドライエッチング法で加工し、絶縁体層２７２Ｂの一部をウェットエッチング法で加工し、絶縁体層２７３Ｂをドライエッチング法で加工し、酸化物層２４３Ｂ、および導電体層２４２Ｂの一部をドライエッチング法で加工してもよい。 The etching of part of the insulator 280, part of the insulator layer 272B, part of the insulator layer 273B, part of the conductor layer 242B, and part of the oxide layer 243B is performed by a dry etching method or a wet etching method. be able to. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions. For example, part of the insulator 280 is processed by dry etching, part of the insulator layer 272B is processed by wet etching, the insulator layer 273B is processed by dry etching, and the oxide layer 243B and the conductive layer A part of the body layer 242B may be processed by a dry etching method.
　これまでのドライエッチングなどの処理を行うことによって、エッチングガスなどに起因した不純物が酸化物２３０ａ、および酸化物２３０ｂなどの表面または内部に付着または拡散することがある。不純物としては、例えば、フッ素または塩素などがある。 Impurities resulting from the etching gas and the like may adhere or diffuse to the surface or inside of the oxides 230a and 230b by performing the processes such as the dry etching so far. Examples of impurities include fluorine and chlorine.
　上記の不純物などを除去するために、洗浄を行う。洗浄方法としては、洗浄液など用いたウェット洗浄、プラズマを用いたプラズマ処理、または加熱処理による洗浄などがあり、上記洗浄を適宜組み合わせて行ってもよい。 -Perform cleaning to remove the above impurities. Examples of the cleaning method include wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, or heat treatment, or the like, and the above cleaning may be performed in appropriate combination.
　ウェット洗浄としては、シュウ酸、リン酸、アンモニア水、またはフッ化水素酸などを炭酸水または純水で希釈した水溶液を用いて洗浄処理を行ってもよい。または、純水または炭酸水を用いた超音波洗浄を行ってもよい。 The wet cleaning may be performed using an aqueous solution prepared by diluting oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, etc. with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.
　上記エッチング後、または上記洗浄後に加熱処理を行ってもよい。加熱処理は、例えば、１００℃以上４５０℃以下、より好ましくは３５０℃以上４００℃以下で行えばよい。なお、加熱処理は、窒素ガスもしくは不活性ガスの雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上、もしくは１０％以上含む雰囲気で行う。例えば、加熱処理は酸素雰囲気で行うことが好ましい。これにより、酸化物２３０ａおよび酸化物２３０ｂに酸素を供給して、酸素欠損ＶＯの低減を図ることができる。また、加熱処理は減圧状態で行ってもよい。または、酸素雰囲気で加熱処理した後に、大気に露出せずに連続して窒素雰囲気で加熱処理を行ってもよい。 A heat treatment may be performed after the etching or the cleaning. The heat treatment may be performed at 100 °C to 450 °C inclusive, more preferably 350 °C to 400 °C inclusive, for example. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas in an amount of 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 230a and oxides 230b, it is possible to reduce the oxygen vacancies V O. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the air.
　次に、酸化膜２３０Ｃを成膜する（図９参照）。酸化膜２３０Ｃの成膜前に加熱処理を行っても良く、当該加熱処理は、減圧下で行い、大気に暴露することなく、連続して酸化膜２３０Ｃを成膜することが好ましい。また、当該加熱処理は、酸素を含む雰囲気で行うことが好ましい。このような処理を行うことによって、酸化物２３０ｂの表面などに吸着している水分および水素を除去し、さらに酸化物２３０ａおよび酸化物２３０ｂ中の水分濃度および水素濃度を低減させることができる。加熱処理の温度は、１００℃以上４００℃以下が好ましく、さらに好ましくは１５０℃以上３５０℃以下である。本実施の形態では、加熱処理の温度を２００℃とし、減圧下で行う。 Next, an oxide film 230C is formed (see FIG. 9). Heat treatment may be performed before the oxide film 230C is formed, and the heat treatment is preferably performed under reduced pressure and the oxide film 230C is continuously formed without being exposed to the air. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b or the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower, and more preferably 150°C or higher and 350°C or lower. In this embodiment mode, heat treatment is performed at a temperature of 200° C. under reduced pressure.
　ここで、酸化膜２３０Ｃは、少なくとも酸化物２３０ａの側面の一部、酸化物２３０ｂの側面の一部および上面の一部、酸化物２４３の側面の一部、導電体２４２の側面の一部、絶縁体２７２の側面の一部、および絶縁体２８０の側面と接するように設けられることが好ましい。導電体２４２は、酸化物２４３、絶縁体２７２、絶縁体２７３、および酸化膜２３０Ｃに囲まれることで、以降の工程において導電体２４２の酸化による導電率の低下を抑制することができる。 Here, the oxide film 230C includes at least a part of a side surface of the oxide 230a, a part of a side surface and a part of an upper surface of the oxide 230b, a part of a side surface of the oxide 243, a part of a side surface of the conductor 242. It is preferably provided so as to be in contact with part of a side surface of the insulator 272 and a side surface of the insulator 280. Since the conductor 242 is surrounded by the oxide 243, the insulator 272, the insulator 273, and the oxide film 230C, the decrease in conductivity due to the oxidation of the conductor 242 in the subsequent steps can be suppressed.
　酸化膜２３０Ｃの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。酸化膜２３０Ｃとして、Ｉｎに対するＧａの原子数比が、酸化膜２３０ＢのＩｎに対するＧａの原子数比より大きいことが好ましい。本実施の形態では、酸化膜２３０Ｃとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜する。 The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the oxide film 230C, the atomic ratio of Ga to In is preferably larger than the atomic ratio of Ga to In of the oxide film 230B. In this embodiment, the oxide film 230C is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio].
　尚、酸化膜２３０Ｃは、積層としてもよい。例えば、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のターゲットを用いて成膜して、連続してＩｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜してもよい。 Note that the oxide film 230C may be a laminated layer. For example, a film is formed by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio], and In:Ga:Zn=1:3:4 [atoms] are continuously formed. A film ratio may be used for the target formation.
　酸化膜２３０Ｃの成膜時に、スパッタリングガスに含まれる酸素の一部が酸化物２３０ａおよび酸化物２３０ｂに供給される場合がある。または、酸化膜２３０Ｃの成膜時に、スパッタリングガスに含まれる酸素の一部が絶縁体２８０に供給される場合がある。したがって、酸化膜２３０Ｃのスパッタリングガスに含まれる酸素の割合は７０％以上、好ましくは８０％以上、より好ましくは１００％とすればよい。 When forming the oxide film 230C, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, part of oxygen contained in the sputtering gas may be supplied to the insulator 280 when the oxide film 230C is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or higher, preferably 80% or higher, more preferably 100%.
　次に、加熱処理を行っても良い。また、当該加熱処理を減圧下で行い、大気に暴露することなく、連続して、絶縁膜２５０Ａの成膜を行ってもよい。当該加熱処理を行うことによって、酸化膜２３０Ｃの表面などに吸着している水分および水素を除去し、さらに酸化物２３０ａ、酸化物２３０ｂおよび酸化膜２３０Ｃ中の水分濃度および水素濃度を低減させることができる。加熱処理の温度は、１００℃以上４００℃以下が好ましい。本実施の形態では、加熱処理の温度を２００℃とする。 Next, heat treatment may be performed. Alternatively, the heat treatment may be performed under reduced pressure, and the insulating film 250A may be continuously formed without being exposed to the air. By performing the heat treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C or the like can be removed, and moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. it can. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment mode, the temperature of the heat treatment is 200° C.
　次に、酸化膜２３０Ｃ上に絶縁膜２５０Ａを成膜する（図９参照）。絶縁膜２５０Ａは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて成膜することができる。また、絶縁膜２５０Ａは、上述の水素原子が低減または除去されたガスを用いた成膜方法で成膜することが好ましい。これにより、絶縁膜２５０Ａの水素濃度を低減することができる。絶縁膜２５０Ａは、後の工程で酸化物２３０ｃと接する絶縁体２５０となるので、このように水素濃度が低減されていることが好適である。なお、絶縁膜２５０Ａの成膜後に、絶縁体２８０成膜後に行ったマイクロ波、またはＲＦ等の高周波の照射または酸素プラズマ処理を行ってもよい。 Next, an insulating film 250A is formed on the oxide film 230C (see FIG. 9). The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by the above-described film forming method using a gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250 that comes into contact with the oxide 230c in a later step, it is preferable that the hydrogen concentration be reduced in this manner. Note that after the insulating film 250A is formed, irradiation with microwaves or high frequencies such as RF or oxygen plasma treatment which is performed after forming the insulator 280 may be performed.
　次に、導電膜２６０Ａａおよび導電膜２６０Ａｂを成膜する（図１０参照）。導電膜２６０Ａａおよび導電膜２６０Ａｂの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。例えば、ＣＶＤ法を用いることが好ましい。本実施の形態では、ＡＬＤ法を用いて、導電膜２６０Ａａを成膜し、ＣＶＤ法を用いて導電膜２６０Ａｂを成膜する。 Next, the conductive film 260Aa and the conductive film 260Ab are formed (see FIG. 10). The conductive film 260Aa and the conductive film 260Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use the CVD method. In this embodiment mode, the conductive film 260Aa is formed by an ALD method and the conductive film 260Ab is formed by a CVD method.
　次に、ＣＭＰ処理によって、酸化膜２３０Ｃ、絶縁膜２５０Ａ、導電膜２６０Ａａおよび導電膜２６０Ａｂを絶縁体２８０が露出するまで研磨することによって、酸化物２３０ｃ、絶縁体２５０および導電体２６０（導電体２６０ａおよび導電体２６０ｂ）を形成する（図１１参照）。 Next, the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and the conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, whereby the oxide 230c, the insulator 250, and the conductive material 260 (the conductive material 260a). And a conductor 260b) are formed (see FIG. 11).
　次に、加熱処理を行ってもよい。本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行う。該加熱処理によって、絶縁体２５０および絶縁体２８０中の水分濃度および水素濃度を低減させることができる。なお、上記加熱処理後、大気に曝すことなく連続して、絶縁体２８２の成膜を行ってもよい。 Next, heat treatment may be performed. In this embodiment mode, the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere. By the heat treatment, moisture concentration and hydrogen concentration in the insulator 250 and the insulator 280 can be reduced. Note that after the heat treatment, the insulator 282 may be continuously formed without being exposed to the air.
　次に、導電体２６０上、酸化物２３０ｃ上、絶縁体２５０上、および絶縁体２８０上に、絶縁体２８２を形成する。絶縁体２８２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる（図１２参照）。絶縁体２８２となる絶縁膜としては、例えば、スパッタリング法によって、酸化アルミニウムを成膜することが好ましい。スパッタリング法を用いて、酸素を含む雰囲気で絶縁体２８２の成膜を行うことで、成膜しながら、絶縁体２８０に酸素を添加することができる。このとき、基板加熱を行いながら、絶縁体２８２を成膜することが好ましい。また、導電体２６０の上面に接して、絶縁体２８２を形成することで、この後の加熱処理において、絶縁体２８０が有する酸素が導電体２６０へ吸収されることを抑制することができるので好ましい。 Next, an insulator 282 is formed over the conductor 260, the oxide 230c, the insulator 250, and the insulator 280. The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 12). As the insulating film to be the insulator 282, it is preferable to form aluminum oxide by a sputtering method, for example. By forming the insulator 282 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulator 280 while forming the film. At this time, it is preferable to form the insulator 282 while heating the substrate. In addition, by forming the insulator 282 in contact with the top surface of the conductor 260, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 260 in heat treatment performed later, which is preferable. ..
　次に、絶縁体２８２の一部、絶縁体２８０の一部、絶縁体２２４の一部、絶縁体２２２の一部、絶縁体２１６の一部、および絶縁体２１４の一部、を加工して、絶縁体２１２に達する開口を形成する（図１３参照）。該開口は、トランジスタ２００が囲まれるように形成される場合がある。または、該開口は、複数のトランジスタ２００が囲まれるように形成される場合がある。よって、該開口において、絶縁体２８２の側面の一部、絶縁体２８０の側面の一部、絶縁体２２４の側面の一部、絶縁体２２２の側面の一部、絶縁体２１６の側面の一部、および絶縁体２１４の側面の一部が露出する。 Next, part of the insulator 282, part of the insulator 280, part of the insulator 224, part of the insulator 222, part of the insulator 216, and part of the insulator 214 are processed. , An opening reaching the insulator 212 is formed (see FIG. 13). The opening may be formed so as to surround the transistor 200. Alternatively, the opening may be formed so as to surround the plurality of transistors 200. Therefore, in the opening, part of the side surface of the insulator 282, part of the side surface of the insulator 280, part of the side surface of the insulator 224, part of the side surface of the insulator 222, part of the side surface of the insulator 216. , And a part of the side surface of the insulator 214 is exposed.
　絶縁体２８２の一部、絶縁体２８０の一部、絶縁体２２４の一部、絶縁体２２２の一部、絶縁体２１６の一部、および絶縁体２１４の一部の加工は、ドライエッチング法、またはウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。また、当該加工は、それぞれ異なる条件で加工してもよい。 Part of the insulator 282, part of the insulator 280, part of the insulator 224, part of the insulator 222, part of the insulator 216, and part of the insulator 214 are processed by a dry etching method. Alternatively, a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Further, the processing may be performed under different conditions.
　また、このとき、マイクロ波、またはＲＦ等の高周波を絶縁体２８０などに照射してもよい。照射されたマイクロ波、またはＲＦ等の高周波は絶縁体２８０、酸化物２３０ｂ、および酸化物２３０ａなどに浸透して、これらの中の水素を除去できることがある。例えば、酸化物２３０ａおよび酸化物２３０ｂにおいては、ＶｏＨの結合が切断される反応が起きて、別言すると「ＶＯＨ→Ｖｏ＋Ｈ」という反応が起きて、脱水素化されることになる。このとき発生した水素の一部は、酸素と結合してＨ２Ｏとして、酸化物２３０、および絶縁体２８０から除去される場合がある。また、水素の一部は、導電体２４２にゲッタリングされる場合がある。 At this time, the insulator 280 or the like may be irradiated with microwaves or high frequencies such as RF. The irradiated microwave or high frequency waves such as RF may penetrate into the insulator 280, the oxide 230b, the oxide 230a, and the like, so that hydrogen in these can be removed. For example, in the oxide 230a and oxides 230b, happening reactions coupling VoH is disconnected, when other words happening reaction of "V O H → Vo + H", will be dehydrogenated. Part of the hydrogen generated at this time may be removed from the oxide 230 and the insulator 280 as H 2 O by combining with oxygen. Further, part of hydrogen may be gettered to the conductor 242 in some cases.
　次に、絶縁体２８２、絶縁体２８０、絶縁体２２４、絶縁体２２２、絶縁体２１６、および絶縁体２１４を覆って、絶縁体２８３を形成する（図１４参照）。図１４に示すように、絶縁体２８３は、上記開口の底面において、絶縁体２１２と接する。つまり、トランジスタ２００は、上面及び側面が絶縁体２８３に、下面が絶縁体２１２に包み込まれることになる。このように、バリア性の高い絶縁体２８３および絶縁体２１２でトランジスタ２００を包み込むことで、外部から水分、および水素が侵入するのを防止することができる。 Next, the insulator 283 is formed by covering the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 (see FIG. 14). As shown in FIG. 14, the insulator 283 is in contact with the insulator 212 on the bottom surface of the opening. That is, the top surface and the side surface of the transistor 200 are covered with the insulator 283, and the bottom surface is covered with the insulator 212. In this manner, by wrapping the transistor 200 with the insulator 283 and the insulator 212 having a high barrier property, moisture and hydrogen can be prevented from entering from the outside.
　絶縁体２８３の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。 The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、加熱処理を行ってもよい。本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行う。当該加熱処理によって、絶縁体２８２の成膜によって添加された酸素を絶縁体２８０へ拡散させ、さらに酸化物２３０ｃを介して、酸化物２３０ａ、および酸化物２３０ｂへ供給することができる。このように、酸化物２３０に加酸素化処理を行うことで、酸化物２３０（酸化物２３０ｂ）中の酸素欠損を酸素により修復させる、別言すると「Ｖｏ＋Ｏ→ｎｕｌｌ」という反応を促進させることができる。さらに、酸化物２３０中に残存した水素に供給された酸素が反応することで、当該水素をＨ２Ｏとして除去する（脱水化する）ことができる。これにより、酸化物２３０中に残存していた水素が酸素欠損に再結合してＶＯＨが形成されるのを抑制することができる。なお、当該加熱処理は、絶縁体２８３の成膜後に限らず、絶縁体２８２の成膜後に行ってもよい。 Next, heat treatment may be performed. In this embodiment mode, the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere. By the heat treatment, oxygen added by forming the insulator 282 can be diffused into the insulator 280 and further supplied to the oxide 230a and the oxide 230b through the oxide 230c. In this manner, by performing oxygenation treatment on the oxide 230, oxygen vacancies in the oxide 230 (oxide 230b) can be repaired by oxygen, that is, a reaction of “Vo+O→null” can be promoted. it can. Further, oxygen supplied as hydrogen reacts with hydrogen remaining in the oxide 230, whereby the hydrogen can be removed (dehydrated) as H 2 O. Thus, the hydrogen remained in the oxide 230 can be prevented from recombine V O H is formed by oxygen vacancies. Note that the heat treatment is not limited to after the insulator 283 is formed and may be performed after the insulator 282 is formed.
　次に絶縁体２８３上に、絶縁体２７４となる絶縁膜を成膜する。絶縁体２７４となる絶縁膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。また、絶縁体２７４となる絶縁膜は、上述の水素原子が低減または除去されたガスを用いた成膜方法で成膜することが好ましい。これにより、絶縁体２７４となる絶縁膜の水素濃度を低減することができる。 Next, an insulating film to be the insulator 274 is formed over the insulator 283. The insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In addition, the insulating film to be the insulator 274 is preferably formed by a film formation method using the above-described gas in which hydrogen atoms are reduced or removed. Accordingly, the hydrogen concentration of the insulating film which serves as the insulator 274 can be reduced.
　次に、絶縁体２７４となる絶縁膜にＣＭＰ処理を行い、上面が平坦な絶縁体２７４を形成する（図１５参照）。 Next, the insulating film to be the insulator 274 is subjected to CMP treatment to form the insulator 274 having a flat upper surface (see FIG. 15).
　次に、絶縁体２７２ａ、絶縁体２８０、絶縁体２８２、絶縁体２８３、および絶縁体２７４に、導電体２４２ａに達する開口２５５ａを、絶縁体２７２ｂ、絶縁体２８０、絶縁体２８２、絶縁体２８３、および絶縁体２７４に、導電体２４２ｂに達する開口２５５ｂを形成する（図１５参照）。当該開口の形成は、リソグラフィー法を用いて行えばよい。なお、図１５Ａで開口２５５ａおよび開口２５５ｂは、上面視において円形状にしているが、これに限られるものではない。例えば、開口２５５ａおよび開口２５５ｂが、上面視において、楕円などの略円形状、四角形などの多角形状、四角形等の多角形の角部を丸めた形状になっていてもよい。 Next, the insulator 272a, the insulator 280, the insulator 282, the insulator 283, and the insulator 274 are provided with an opening 255a reaching the conductor 242a, an insulator 272b, an insulator 280, an insulator 282, an insulator 283, Then, an opening 255b reaching the conductor 242b is formed in the insulator 274 (see FIG. 15). The opening may be formed by using a lithography method. Note that although the opening 255a and the opening 255b are circular in a top view in FIG. 15A, the shape is not limited to this. For example, the openings 255a and 255b may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.
　次に、絶縁体２４１となる絶縁膜を成膜し、当該絶縁膜を異方性エッチングして絶縁体２４１を形成する（図１６参照）。当該導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、またはＡＬＤ法などを用いて行うことができる。絶縁体２４１となる絶縁膜としては、酸素の透過を抑制する機能を有する絶縁膜を用いることが好ましい。例えば、上記の絶縁体２８３の成膜と同様に、ＰＥＡＬＤ法を用いて、窒化シリコンを成膜することが好ましい。窒化シリコンは水素に対するブロッキング性が高いので好ましい。 Next, an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 16). The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film serving as the insulator 241, an insulating film having a function of suppressing permeation of oxygen is preferably used. For example, similarly to the above-described film formation of the insulator 283, it is preferable to form a silicon nitride film by using a PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.
　また、絶縁体２４１となる絶縁膜の異方性エッチングとしては、例えばドライエッチング法などを用いればよい。開口の側壁部に絶縁体２４１を設けることで、外方からの酸素の透過を抑制し、次に形成する導電体２４０ａおよび導電体２４０ｂの酸化を防止することができる。また、導電体２４０ａおよび導電体２４０ｂから、水、水素などの不純物が外部に拡散することを防ぐことができる。 As the anisotropic etching of the insulating film that becomes the insulator 241, for example, a dry etching method may be used. By providing the insulator 241 on the sidewall portion of the opening, oxygen permeation from the outside can be suppressed and oxidation of the conductor 240a and the conductor 240b which are formed next can be prevented. Further, impurities such as water and hydrogen can be prevented from diffusing outside from the conductor 240a and the conductor 240b.
　次に、導電体２４０ａおよび導電体２４０ｂとなる導電膜を成膜する。導電体２４０ａおよび導電体２４０ｂとなる導電膜は、水、水素など不純物の透過を抑制する機能を有する導電体を含む積層構造とすることが望ましい。たとえば、窒化タンタル、窒化チタンなどと、タングステン、モリブデン、銅など、と、の積層とすることができる。導電体２４０となる導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 Next, a conductive film to be the conductor 240a and the conductor 240b is formed. The conductive films to be the conductor 240a and the conductor 240b preferably have a stacked-layer structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used. The conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、ＣＭＰ処理を行うことで、導電体２４０ａおよび導電体２４０ｂとなる導電膜の一部を除去し、絶縁体２７４の上面を露出する。その結果、開口２５５ａおよび開口２５５ｂのみに、当該導電膜が残存することで上面が平坦な導電体２４０ａおよび導電体２４０ｂを形成することができる（図１７参照）。なお、当該ＣＭＰ処理により、絶縁体２７４の上面の一部が除去される場合がある。 Next, CMP treatment is performed to remove a part of the conductive film to be the conductors 240a and 240b and expose the upper surface of the insulator 274. As a result, the conductor 240a and the conductor 240b whose top surfaces are flat can be formed by leaving the conductive film only in the openings 255a and 255b (see FIG. 17). Note that part of the upper surface of the insulator 274 may be removed by the CMP treatment.
　次に、導電体２４６となる導電膜を成膜する。導電体２４６となる導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 Next, a conductive film to be the conductor 246 is formed. The conductive film to be the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、導電体２４６となる導電膜をリソグラフィー法によって加工し、導電体２４０ａの上面と接する導電体２４６ａおよび導電体２４０ｂの上面と接する導電体２４６ｂを形成する（図１参照）。 Next, the conductive film to be the conductor 246 is processed by a lithography method to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b (see FIG. 1).
　以上により、図１に示すトランジスタ２００を有する半導体装置を作製することができる。図３乃至図１７に示すように、本実施の形態に示す半導体装置の作製方法を用いることで、トランジスタ２００を作製することができる。 Through the above steps, a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured. As illustrated in FIGS. 3 to 17, the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment.
＜半導体装置の変形例＞
　以下では、図１８乃至図２０を用いて、先の＜半導体装置の構成例＞で示したものとは異なる、本発明の一態様に係るトランジスタ２００を有する半導体装置の一例について説明する。なお、図１８乃至図２０に示す半導体装置において、＜半導体装置の構成例＞に示した半導体装置（図１参照。）を構成する構造と同機能を有する構造には、同符号を付記する。なお、本項目において、トランジスタ２００の構成材料については＜半導体装置の構成例＞で詳細に説明した材料を用いることができる。 <Modification of semiconductor device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the above-described <Structural example of semiconductor device>, is described with reference to FIGS. Note that in the semiconductor devices illustrated in FIGS. 18 to 20, structures having the same functions as the structures included in the semiconductor device (see FIG. 1) illustrated in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that in this item, as the constituent material of the transistor 200, the material described in detail in <Structure example of semiconductor device> can be used.
＜半導体装置の変形例１＞
　図１８Ａは、トランジスタ２００を有する半導体装置の上面図である。また、図１８Ｂは、図１８Ａに示すＡ１−Ａ２の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、図１８Ｃは、図１８ＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、図１８Ｄは、図１８ＡにＡ５−Ａ６の一点鎖線で示す部位に対応する断面図である。なお、図１８Ａの上面図では、図の明瞭化のために一部の要素を省いて図示している。 <Modification 1 of semiconductor device>
FIG. 18A is a top view of a semiconductor device including the transistor 200. 18B is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2 in FIG. 18A and also a cross-sectional view in the channel length direction of the transistor 200. 18C is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4 in FIG. 18A and also a cross-sectional view in the channel width direction of the transistor 200. 18D is a cross-sectional view corresponding to the portion indicated by dashed-dotted line A5-A6 in FIG. 18A. Note that in the top view of FIG. 18A, some elements are omitted for clarity.
　図１８に示すトランジスタ２００は、絶縁体２１４、絶縁体２１６、絶縁体２２２、絶縁体２２４、絶縁体２８０がパターニングされており、絶縁体２８２と絶縁体２１２がこれらを封止する構造になっている点において、図１に示すトランジスタ２００と異なる。つまり、絶縁体２８２は、絶縁体２８０の上面、絶縁体２８０の側面、絶縁体２２４の側面、絶縁体２２２の側面、絶縁体２１６の側面、絶縁体２１４の側面、および絶縁体２１２の上面と、それぞれ接する。また、絶縁体２８２上に絶縁体２８３を有する構成となっている。これにより、酸化物２３０などを含む、絶縁体２１４、絶縁体２１６、絶縁体２２２、絶縁体２２４、および絶縁体２８０は、絶縁体２８２および絶縁体２８２上の絶縁体２８３と、絶縁体２１２によって、外部から隔離される。 In the transistor 200 illustrated in FIG. 18, the insulator 214, the insulator 216, the insulator 222, the insulator 224, and the insulator 280 are patterned, and the insulator 282 and the insulator 212 have a structure in which they are sealed. 1 is different from the transistor 200 shown in FIG. That is, the insulator 282 includes the upper surface of the insulator 280, the side surface of the insulator 280, the side surface of the insulator 224, the side surface of the insulator 222, the side surface of the insulator 216, the side surface of the insulator 214, and the upper surface of the insulator 212. , Touch each other. In addition, an insulator 283 is provided over the insulator 282. Accordingly, the insulator 214, the insulator 216, the insulator 222, the insulator 224, and the insulator 280 including the oxide 230 and the like are separated by the insulator 282, the insulator 283 over the insulator 282, and the insulator 212. , Isolated from the outside.
＜半導体装置の変形例２＞
　図１９Ａは、トランジスタ２００を有する半導体装置の上面図である。また、図１９Ｂは、図１９Ａに示すＡ１−Ａ２の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、図１９Ｃは、図１９ＡにＡ３−Ａ４の一点鎖線で示す部位に対応する断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、図１９Ｄは、図１９ＡにＡ５−Ａ６の一点鎖線で示す部位に対応する断面図である。なお、図１９Ａの上面図では、図の明瞭化のために一部の要素を省いて図示している。 <Second Modification of Semiconductor Device>
FIG. 19A is a top view of a semiconductor device including the transistor 200. 19B is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2 in FIG. 19A and also a cross-sectional view in the channel length direction of the transistor 200. 19C is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4 in FIG. 19A and also a cross-sectional view in the channel width direction of the transistor 200. Further, FIG. 19D is a cross-sectional view corresponding to the portion indicated by dashed-dotted line A5-A6 in FIG. 19A. In the top view of FIG. 19A, some elements are omitted for clarity.
　図１９に示すトランジスタ２００は、絶縁体２１４、絶縁体２１６、絶縁体２２２、絶縁体２２４、絶縁体２８０、および絶縁体２８２がパターニングされていない点、において、図１に示すトランジスタ２００と異なる。 The transistor 200 shown in FIG. 19 is different from the transistor 200 shown in FIG. 1 in that the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 are not patterned.
　このような構造にすることで、絶縁体２１４、絶縁体２１６、絶縁体２２２、絶縁体２２４、絶縁体２８０、および絶縁体２８２をパターニングする必要がなくなるので、工程を簡略化し、半導体装置の生産性向上を図ることができる。 With such a structure, it is not necessary to pattern the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282, so that the process is simplified and the semiconductor device is manufactured. It is possible to improve the property.
　導電体２４２の上面は、絶縁体２７２が覆い、導電体２４２の側面、酸化物２４３の側面、酸化物２３０ａの側面、および酸化物２３０ｂの側面は、絶縁体２７３で覆う構造となっているので、導電体２４２の側面および導電体２４２の上面方向から導電体２４２への水素や水などの不純物および酸素の拡散を抑制することができる。また、導電体２４２の下面は酸化物２４３と接する構造となっており、酸化物２３０ｂの酸素は、酸化物２４３によってブロックされるので導電体２４２へ拡散することを抑制する。従って、導電体２４２の周囲からの導電体２４２への酸素の拡散を抑制することができるので、導電体２４２の酸化を抑制することができる。また、酸化物２３０ａの側面、および酸化物２３０ｂの側面方向から酸化物２３０ａおよび酸化物２３０ｂへの水素や水などの不純物の拡散を抑制することができる。 The top surface of the conductor 242 is covered with the insulator 272, and the side surface of the conductor 242, the side surface of the oxide 243, the side surface of the oxide 230a, and the side surface of the oxide 230b are covered with the insulator 273. It is possible to suppress diffusion of impurities such as hydrogen and water and oxygen into the conductor 242 from the side surface of the conductor 242 and the upper surface direction of the conductor 242. In addition, the lower surface of the conductor 242 has a structure in contact with the oxide 243, and oxygen in the oxide 230b is blocked by the oxide 243, so that diffusion of oxygen into the conductor 242 is suppressed. Therefore, the diffusion of oxygen from the periphery of the conductor 242 to the conductor 242 can be suppressed, so that the oxidation of the conductor 242 can be suppressed. Further, diffusion of impurities such as hydrogen and water into the oxide 230a and the oxide 230b from the side surface of the oxide 230a and the side surface of the oxide 230b can be suppressed.
＜半導体装置の変形例３＞
　図２０Ａおよび図２０Ｂに、複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを、絶縁体２８３と絶縁体２１２で、包括して封止した構成について示す。なお、図２０Ａおよび図２０Ｂにおいて、トランジスタ２００＿１乃至トランジスタ２００＿ｎは、チャネル長方向に並んでいるように見えるが、これにかぎられるものではない。トランジスタ２００＿１乃至トランジスタ２００＿ｎは、チャネル幅方向に並んでいてもよいし、マトリクス状に配置されていてもよいし、規則性を持たずに配置されていてもよい。 <Modification 3 of Semiconductor Device>
20A and 20B show a structure in which the plurality of transistors 200_1 to 200_n are collectively sealed with an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 20A and 20B, the invention is not limited thereto. The transistors 200_1 to 200_n may be arranged in the channel width direction, may be arranged in a matrix, or may be arranged without regularity.
　図２０Ａに示すように、複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎの外側において、絶縁体２８３と絶縁体２１２が接する部分（以下、封止部２６５と呼ぶ場合がある。）が形成されている。封止部２６５は、複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを囲むように形成されている。このような構造にすることで、複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを絶縁体２８３と絶縁体２１２で包み込むことができる。よって封止部２６５に囲まれたトランジスタ群が、基板上に複数設けられることになる。 As shown in FIG. 20A, outside the plurality of transistors 200_1 to 200_n, a portion where the insulator 283 and the insulator 212 are in contact with each other (hereinafter, may be referred to as a sealing portion 265) is formed. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With such a structure, the plurality of transistors 200_1 to 200_n can be surrounded by the insulator 283 and the insulator 212. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.
　また、封止部２６５に重ねてダイシングライン（スクライブライン、分断ライン、又は切断ラインと呼ぶ場合がある）を設けてもよい。上記基板はダイシングラインにおいて分断されるので、封止部２６５に囲まれたトランジスタ群が１チップとして取り出されることになる。 Further, a dicing line (may be referred to as a scribe line, a dividing line, or a cutting line) may be provided so as to overlap the sealing portion 265. Since the substrate is divided in the dicing line, the transistor group surrounded by the sealing portion 265 is taken out as one chip.
　また、図２０Ａでは、複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを一つの封止部２６５で囲む例について示したが、これに限られるものではない。図２０Ｂに示すように、複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを複数の封止部で囲む構成にしてもよい。図２０Ｂでは、複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを封止部２６５ａで囲み、さらに外側の封止部２６５ｂでも囲む構成にしている。 20A illustrates an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, the present invention is not limited to this. As illustrated in FIG. 20B, a plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In FIG. 20B, the plurality of transistors 200_1 to 200_n are surrounded by the sealing portion 265a and further surrounded by the outer sealing portion 265b.
　このように、複数の封止部で複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを囲む構成にすることで、絶縁体２８３と絶縁体２１２が接する部分が増えるので、絶縁体２８３と絶縁体２１２の密着性をより向上させることができる。これにより、より確実に複数のトランジスタ２００＿１乃至トランジスタ２００＿ｎを封止することができる。 By thus surrounding the plurality of transistors 200_1 to 200_n with the plurality of sealing portions, a portion where the insulator 283 and the insulator 212 are in contact with each other is increased; thus, the adhesion between the insulator 283 and the insulator 212 is increased. It can be further improved. Accordingly, the plurality of transistors 200_1 to 200_n can be sealed more reliably.
　この場合、封止部２６５ａまたは封止部２６５ｂに重ねてダイシングラインを設けてもよいし、封止部２６５ａと封止部２６５ｂの間にダイシングラインを設けてもよい。 In this case, the dicing line may be provided so as to overlap the sealing portion 265a or the sealing portion 265b, or the dicing line may be provided between the sealing portion 265a and the sealing portion 265b.
　本発明の一態様により、良好な電気特性を有する半導体装置を提供することができる。または、本発明の一態様により、ノーマリーオフの電気特性を有する半導体装置を提供することができる。または、本発明の一態様により、信頼性が良好な半導体装置を提供することができる。本発明の一態様により、オン電流の大きい半導体装置を提供することができる。または、本発明の一態様により、高い周波数特性を有する半導体装置を提供することができる。または、本発明の一態様により、微細化または高集積化が可能な半導体装置を提供することができる。または、本発明の一態様により、オフ電流の小さい半導体装置を提供することができる。または、本発明の一態様により、消費電力が低減された半導体装置を提供することができる。または、本発明の一態様により、生産性の高い半導体装置を提供することができる。 According to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having normally-off electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.
（実施の形態２）
　本実施の形態では、半導体装置の一形態を、図２１および図２２を用いて説明する。 (Embodiment 2)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.
［記憶装置１］
　本発明の一態様である容量素子を使用した、半導体装置（記憶装置）の一例を図２１に示す。本発明の一態様の半導体装置は、トランジスタ２００はトランジスタ３００の上方に設けられ、容量素子１００はトランジスタ３００、およびトランジスタ２００の上方に設けられている。なお、トランジスタ２００として、先の実施の形態で説明したトランジスタ２００を用いることができる。 [Memory device 1]
FIG. 21 illustrates an example of a semiconductor device (memory device) including the capacitor which is one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300 and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.
　トランジスタ２００は、酸化物半導体を有する半導体層にチャネルが形成されるトランジスタである。トランジスタ２００は、オフ電流が小さいため、これを記憶装置に用いることにより長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、あるいは、リフレッシュ動作の頻度が極めて低いため、記憶装置の消費電力を十分に低減することができる。 The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the stored content can be held for a long time by using the transistor 200 in a memory device. That is, the refresh operation is not necessary or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.
　図２１に示す半導体装置において、配線１００１はトランジスタ３００のソースと電気的に接続され、配線１００２はトランジスタ３００のドレインと電気的に接続されている。また、配線１００３はトランジスタ２００のソースおよびドレインの一方と電気的に接続され、配線１００４はトランジスタ２００の第１のゲートと電気的に接続され、配線１００６はトランジスタ２００の第２のゲートと電気的に接続されている。そして、トランジスタ３００のゲート、およびトランジスタ２００のソースおよびドレインの他方は、容量素子１００の電極の一方と電気的に接続され、配線１００５は容量素子１００の電極の他方と電気的に接続されている。 In the semiconductor device illustrated in FIG. 21, the wiring 1001 is electrically connected to the source of the transistor 300 and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to a first gate of the transistor 200, and the wiring 1006 is electrically connected to a second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100 and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. ..
　また、図２１に示す記憶装置は、マトリクス状に配置することで、メモリセルアレイを構成することができる。 The memory devices shown in FIG. 21 can be arranged in a matrix to form a memory cell array.
＜トランジスタ３００＞
　トランジスタ３００は、基板３１１上に設けられ、ゲートとして機能する導電体３１６、ゲート絶縁体として機能する絶縁体３１５、基板３１１の一部からなる半導体領域３１３、およびソース領域またはドレイン領域として機能する低抵抗領域３１４ａ、および低抵抗領域３１４ｂを有する。トランジスタ３００は、ｐチャネル型、あるいはｎチャネル型のいずれでもよい。 <Transistor 300>
The transistor 300 is provided over the substrate 311, and includes a conductor 316 which functions as a gate, an insulator 315 which functions as a gate insulator, a semiconductor region 313 which is part of the substrate 311, and a low region which functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b. The transistor 300 may be either a p-channel type or an n-channel type.
　ここで、図２１に示すトランジスタ３００はチャネルが形成される半導体領域３１３（基板３１１の一部）が凸形状を有する。また、半導体領域３１３の側面および上面を、絶縁体３１５を介して、導電体３１６が覆うように設けられている。なお、導電体３１６は仕事関数を調整する材料を用いてもよい。このようなトランジスタ３００は半導体基板の凸部を利用していることからＦＩＮ型トランジスタとも呼ばれる。なお、凸部の上部に接して、凸部を形成するためのマスクとして機能する絶縁体を有していてもよい。また、ここでは半導体基板の一部を加工して凸部を形成する場合を示したが、ＳＯＩ基板を加工して凸形状を有する半導体膜を形成してもよい。 Here, in the transistor 300 illustrated in FIG. 21, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to cover the conductor 316 with the insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material whose work function is adjusted. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator which functions as a mask for forming the protrusion may be provided in contact with the top of the protrusion. Further, although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
　なお、図２１に示すトランジスタ３００は一例であり、その構造に限定されず、回路構成や駆動方法に応じて適切なトランジスタを用いればよい。 Note that the transistor 300 illustrated in FIG. 21 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
＜容量素子１００＞
　容量素子１００は、トランジスタ２００の上方に設けられる。容量素子１００は、第１の電極として機能する導電体１１０と、第２の電極として機能する導電体１２０、および誘電体として機能する絶縁体１３０とを有する。 <Capacitance element 100>
The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
　また、例えば、導電体２４６上に設けた導電体１１２と、導電体１１０は、同時に形成することができる。なお、導電体１１２は、容量素子１００、トランジスタ２００、またはトランジスタ３００と電気的に接続するプラグ、または配線としての機能を有する。 Further, for example, the conductor 112 provided on the conductor 246 and the conductor 110 can be formed at the same time. Note that the conductor 112 has a function as a plug or a wiring which is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
　図２１では、導電体１１２、および導電体１１０は単層構造を示したが、当該構成に限定されず、２層以上の積層構造でもよい。例えば、バリア性を有する導電体と導電性が高い導電体との間に、バリア性を有する導電体、および導電性が高い導電体に対して密着性が高い導電体を形成してもよい。 Although the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 21, the structure is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between the conductor having barrier property and the conductor having high conductivity.
　また、絶縁体１３０は、例えば、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、窒化アルミニウム、酸化ハフニウム、酸化窒化ハフニウム、窒化酸化ハフニウム、窒化ハフニウムなどを用いればよく、積層または単層で設けることができる。 The insulator 130 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Etc. may be used, and they can be provided as a laminated layer or a single layer.
　例えば、絶縁体１３０には、酸化窒化シリコンなどの絶縁耐力が大きい材料と、高誘電率（ｈｉｇｈ−ｋ）材料との積層構造を用いることが好ましい。当該構成により、容量素子１００は、高誘電率（ｈｉｇｈ−ｋ）の絶縁体を有することで、十分な容量を確保でき、絶縁耐力が大きい絶縁体を有することで、絶縁耐力が向上し、容量素子１００の静電破壊を抑制することができる。 For example, it is preferable to use, for the insulator 130, a laminated structure of a material having a high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material. With this structure, the capacitor 100 has an insulator having a high dielectric constant (high-k), whereby sufficient capacitance can be secured, and an insulator having a large dielectric strength improves the dielectric strength and Electrostatic breakdown of the element 100 can be suppressed.
　なお、高誘電率（ｈｉｇｈ−ｋ）材料（高い比誘電率の材料）の絶縁体としては、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウムおよびハフニウムを有する酸化物、アルミニウムおよびハフニウムを有する酸化窒化物、シリコンおよびハフニウムを有する酸化物、シリコンおよびハフニウムを有する酸化窒化物またはシリコンおよびハフニウムを有する窒化物などがある。 Note that as an insulator of a high dielectric constant (high-k) material (a material having a high relative dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, is used. , An oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.
　一方、絶縁耐力が大きい材料（低い比誘電率の材料）としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコンまたは樹脂などがある。 On the other hand, as a material having a high dielectric strength (a material having a low relative dielectric constant), silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen are used. Examples thereof include added silicon oxide, silicon oxide having pores, or resin.
＜配線層＞
　各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。 <Wiring layer>
A wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design. Here, the conductor having a function as a plug or a wiring may have a plurality of structures collectively given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, part of the conductor may function as a wiring, and part of the conductor may function as a plug.
　例えば、トランジスタ３００上には、層間膜として、絶縁体３２０、絶縁体３２２、絶縁体３２４、および絶縁体３２６が順に積層して設けられている。また、絶縁体３２０、絶縁体３２２、絶縁体３２４、および絶縁体３２６には容量素子１００、またはトランジスタ２００と電気的に接続する導電体３２８、および導電体３３０等が埋め込まれている。なお、導電体３２８、および導電体３３０はプラグ、または配線として機能する。 For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film over the transistor 300. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are filled with a conductor 328, a conductor 330, and the like which are electrically connected to the capacitor 100 or the transistor 200. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.
　また、層間膜として機能する絶縁体は、その下方の凹凸形状を被覆する平坦化膜として機能してもよい。例えば、絶縁体３２２の上面は、平坦性を高めるために化学機械研磨（ＣＭＰ）法等を用いた平坦化処理により平坦化されていてもよい。 Also, the insulator functioning as an interlayer film may function as a flattening film that covers the uneven shape below the insulator. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve flatness.
　絶縁体３２６、および導電体３３０上に、配線層を設けてもよい。例えば、図２１において、絶縁体３５０、絶縁体３５２、及び絶縁体３５４が順に積層して設けられている。また、絶縁体３５０、絶縁体３５２、及び絶縁体３５４には、導電体３５６が形成されている。導電体３５６は、プラグ、または配線として機能する。 A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 21, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided. Further, a conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.
　同様に、絶縁体２１０、絶縁体２１２、絶縁体２１４、および絶縁体２１６には、導電体２１８、及びトランジスタ２００を構成する導電体（導電体２０５）等が埋め込まれている。なお、導電体２１８は、容量素子１００、またはトランジスタ３００と電気的に接続するプラグ、または配線としての機能を有する。さらに、導電体１２０、および絶縁体１３０上には、絶縁体１５０が設けられている。 Similarly, a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 has a function as a plug or a wiring which is electrically connected to the capacitor 100 or the transistor 300. Further, an insulator 150 is provided over the conductor 120 and the insulator 130.
　ここで、上記実施の形態に示す絶縁体２４１と同様に、プラグとして機能する導電体２１８の側面に接して絶縁体２１７が設けられる。絶縁体２１７は、絶縁体２１０、絶縁体２１２、絶縁体２１４、および絶縁体２１６に形成された開口の内壁に接して設けられている。つまり、絶縁体２１７は、導電体２１８と、絶縁体２１０、絶縁体２１２、絶縁体２１４、および絶縁体２１６と、の間に設けられている。なお、導電体２０５は導電体２１８と並行して形成することができるので、導電体２０５の側面に接して絶縁体２１７が形成される場合もある。 Here, similarly to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner walls of the openings formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. That is, the insulator 217 is provided between the conductor 218 and the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may be formed in contact with the side surface of the conductor 205 in some cases.
　絶縁体２１７としては、例えば、窒化シリコン、酸化アルミニウム、または窒化酸化シリコンなどの絶縁体を用いればよい。絶縁体２１７は、絶縁体２１２、絶縁体２１４、および絶縁体２２２に接して設けられるので、絶縁体２１０または絶縁体２１６などから水または水素などの不純物が、導電体２１８を通じて酸化物２３０に混入するのを抑制することができる。特に、窒化シリコンは水素に対するブロッキング性が高いので好適である。また、絶縁体２１０または絶縁体２１６に含まれる酸素が導電体２１８に吸収されるのを防ぐことができる。 As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulator 212, the insulator 214, and the insulator 222, impurities such as water or hydrogen from the insulator 210 or the insulator 216 are mixed into the oxide 230 through the conductor 218. Can be suppressed. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. Further, oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218.
　絶縁体２１７は、絶縁体２４１と同様の方法で形成することができる。例えば、ＰＥＡＬＤ法を用いて、窒化シリコンを成膜し、異方性エッチングを用いて導電体３５６に達する開口を形成すればよい。 The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a PEALD method may be used to form a silicon nitride film and anisotropic etching may be used to form an opening reaching the conductor 356.
　層間膜として用いることができる絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 As the insulator that can be used as the interlayer film, there are oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having an insulating property.
　例えば、層間膜として機能する絶縁体には、比誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。したがって、絶縁体の機能に応じて、材料を選択するとよい。 For example, by using a material having a low relative dielectric constant for the insulator functioning as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, the material should be selected according to the function of the insulator.
　例えば、絶縁体１５０、絶縁体２１０、絶縁体３５２、および絶縁体３５４等には、比誘電率の低い絶縁体を有することが好ましい。例えば、当該絶縁体は、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコンまたは樹脂などを有することが好ましい。または、当該絶縁体は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコンまたは空孔を有する酸化シリコンと、樹脂との積層構造を有することが好ましい。酸化シリコンおよび酸化窒化シリコンは、熱的に安定であるため、樹脂と組み合わせることで、熱的に安定かつ比誘電率の低い積層構造とすることができる。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネートまたはアクリルなどがある。 For example, it is preferable that the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like have insulators with low relative permittivity. For example, the insulator may include silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon- and nitrogen-added silicon oxide, silicon oxide having holes, or a resin. preferable. Alternatively, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide containing fluorine, silicon oxide containing carbon, silicon oxide containing carbon and nitrogen, or silicon oxide having holes. And a laminated structure of a resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining with a resin, a laminated structure having thermal stability and a low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
　また、酸化物半導体を用いたトランジスタは、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体で囲うことによって、トランジスタの電気特性を安定にすることができる。従って、絶縁体２１４、絶縁体２１２および絶縁体３５０等には、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体を用いればよい。 Also, a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.
　水素などの不純物および酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。具体的には、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体として、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムまたは酸化タンタルなどの金属酸化物、窒化酸化シリコンまたは窒化シリコンなどを用いることができる。 As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium. The insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
　配線、プラグに用いることができる導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を１種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 Conductors that can be used for the wiring and the plug include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium. A material containing one or more metal elements selected from ruthenium, ruthenium, and the like can be used. Alternatively, a semiconductor having high electric conductivity, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
　例えば、導電体３２８、導電体３３０、導電体３５６、導電体２１８、および導電体１１２等としては、上記の材料で形成される金属材料、合金材料、金属窒化物材料、または金属酸化物材料などの導電性材料を、単層または積層して用いることができる。耐熱性と導電性を両立するタングステンやモリブデンなどの高融点材料を用いることが好ましく、タングステンを用いることが好ましい。または、アルミニウムや銅などの低抵抗導電性材料で形成することが好ましい。低抵抗導電性材料を用いることで配線抵抗を低くすることができる。 For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like formed using any of the above materials. The conductive material of can be used as a single layer or a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.
＜酸化物半導体が設けられた層のプラグ＞
　上記実施の形態に示すように、プラグとして機能する導電体２４０の側面に接して、絶縁体２４１を設けることが好ましい。絶縁体２４１は、絶縁体２２２、絶縁体２２４、絶縁体２８０、絶縁体２８２、絶縁体２８３および絶縁体２７４に形成された開口の内壁に接して形成されている。つまり、絶縁体２４１は、導電体２４０と絶縁体２２２、絶縁体２２４、絶縁体２８０、絶縁体２８２、絶縁体２８３および絶縁体２７４と、の間に設けられているので、絶縁体２２４、絶縁体２８０、および絶縁体２７４などから水または水素などの不純物が、導電体２４０を通じて酸化物２３０に混入するのを抑制することができる。また、絶縁体２４１を形成することで、絶縁体２２４、絶縁体２８０、および絶縁体２７４に含まれる酸素が導電体２４０に吸収されるのを防ぐことができる。よって、導電体２４０から導電体２４２および酸化物２３０に拡散する水素の量を低減することができる。 <Plug of layer provided with oxide semiconductor>
As shown in the above embodiment mode, the insulator 241 is preferably provided in contact with the side surface of the conductor 240 which functions as a plug. The insulator 241 is formed in contact with the inner walls of the openings formed in the insulator 222, the insulator 224, the insulator 280, the insulator 282, the insulator 283, and the insulator 274. That is, the insulator 241 is provided between the conductor 240 and the insulator 222, the insulator 224, the insulator 280, the insulator 282, the insulator 283, and the insulator 274; Impurities such as water or hydrogen from the body 280 and the insulator 274 can be prevented from entering the oxide 230 through the conductor 240. In addition, by forming the insulator 241, oxygen contained in the insulator 224, the insulator 280, and the insulator 274 can be prevented from being absorbed by the conductor 240. Therefore, the amount of hydrogen diffused from the conductor 240 to the conductor 242 and the oxide 230 can be reduced.
　絶縁体２４１は、水または水素などの不純物、および酸素の拡散を抑制する機能を有する絶縁性材料を用いるとよい。例えば、窒化シリコン、窒化酸化シリコン、酸化アルミニウムまたは酸化ハフニウムなどを用いることが好ましい。特に、窒化シリコンは水素に対するブロッキング性が高いため好ましい。また、他にも、例えば、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジムまたは酸化タンタルなどの金属酸化物などを用いることができる。 For the insulator 241, it is preferable to use an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. Besides, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used.
　また、上記実施の形態と同様に、トランジスタ２００は絶縁体２８３と絶縁体２１２で封止されることが好ましい。このような構成とすることで、絶縁体２７４に含まれる水素が絶縁体２８０などに混入するのを低減することができる。 Further, similarly to the above embodiment mode, the transistor 200 is preferably sealed with the insulator 283 and the insulator 212. With such a structure, hydrogen contained in the insulator 274 can be prevented from entering the insulator 280 or the like.
　ここで、絶縁体２８３には導電体２４０が、絶縁体２１２には導電体２１８が貫通しているが、上記の通り、絶縁体２４１が導電体２４０に接して設けられ、絶縁体２１７が導電体２１８に接して設けられている。これにより、導電体２４０および導電体２１８を介して絶縁体２８３および絶縁体２１２の内側に混入する水素も低減することができる。このようにして、絶縁体２８３、絶縁体２１２、絶縁体２４１、および絶縁体２１７でトランジスタ２００をより確実に封止し、絶縁体２７４等に含まれる水素などの不純物が絶縁体２８３より外側から混入するのを低減することができる。 Here, the conductor 240 penetrates the insulator 283 and the conductor 218 penetrates the insulator 212, but as described above, the insulator 241 is provided in contact with the conductor 240 and the insulator 217 conducts. It is provided in contact with the body 218. Accordingly, hydrogen mixed inside the insulator 283 and the insulator 212 through the conductor 240 and the conductor 218 can be reduced. In this manner, the transistor 200 is more reliably sealed with the insulator 283, the insulator 212, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 and the like from the outside of the insulator 283. It is possible to reduce contamination.
　また、絶縁体２１６、絶縁体２２４、絶縁体２８０、絶縁体２５０、および絶縁体２７４は、先の実施の形態に示すように、水素原子が低減または除去されたガスを用いた成膜方法で形成されることが好ましい。これにより、絶縁体２１６、絶縁体２２４、絶縁体２８０、絶縁体２５０、および絶縁体２７４の水素濃度を低減することができる。 Further, the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 are formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described in the above embodiment. It is preferably formed. Accordingly, the hydrogen concentration of the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 can be reduced.
　また、図２１に示すように、絶縁体２１６、絶縁体２２４、絶縁体２８０、および絶縁体２７４には、導電体２４２に接続されるビアである、導電体２４０および導電体２１８が配置されている。上記のように、絶縁体２１６、絶縁体２２４、絶縁体２８０、および絶縁体２７４の水素濃度を低減することで、導電体２４０および導電体２１８を介して導電体２４２および酸化物２３０に拡散する水素量をさらに低減することができる。 As shown in FIG. 21, the insulator 216, the insulator 224, the insulator 280, and the insulator 274 are provided with conductors 240 and 218, which are vias connected to the conductor 242. There is. As described above, by reducing the hydrogen concentration in the insulator 216, the insulator 224, the insulator 280, and the insulator 274, the hydrogen is diffused into the conductor 242 and the oxide 230 through the conductor 240 and the conductor 218. The amount of hydrogen can be further reduced.
　このようにして、トランジスタ２００近傍のシリコン系絶縁膜の水素濃度を低減し、酸化物２３０の水素濃度を低減することができる。 In this way, the hydrogen concentration of the silicon-based insulating film near the transistor 200 can be reduced and the hydrogen concentration of the oxide 230 can be reduced.
＜ダイシングライン＞
　以下では、大面積基板を半導体素子ごとに分断することによって、複数の半導体装置をチップ状で取り出す場合に設けられるダイシングライン（スクライブライン、分断ライン、又は切断ラインと呼ぶ場合がある）について説明する。分断方法としては、例えば、まず、基板に半導体素子を分断するための溝（ダイシングライン）を形成した後、ダイシングラインにおいて切断し、複数の半導体装置に分断（分割）する場合がある。 <Dicing line>
Hereinafter, a dicing line (which may be referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing a large-area substrate into semiconductor elements will be described. .. As a dividing method, for example, first, a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, and then the semiconductor element is cut along the dicing line to divide (divide) into a plurality of semiconductor devices.
　ここで、例えば、図２１に示すように、絶縁体２８３と、絶縁体２１２とが接する領域がダイシングラインと重なるように設計することが好ましい。つまり、複数のトランジスタ２００を有するメモリセルの外縁に設けられるダイシングラインとなる領域近傍において、絶縁体２８０、絶縁体２２４、絶縁体２２２、絶縁体２１６、および絶縁体２１４に開口を設ける。 Here, for example, as shown in FIG. 21, it is preferable to design so that a region where the insulator 283 and the insulator 212 are in contact with each other and the dicing line. That is, openings are provided in the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 in the vicinity of a region which serves as a dicing line which is provided on the outer edge of the memory cell including the plurality of transistors 200.
　つまり、上記絶縁体２８２、絶縁体２８０、絶縁体２２４、絶縁体２２２、絶縁体２１６、および絶縁体２１４に設けた開口において、絶縁体２１２と、絶縁体２８３とが接する。例えば、このとき、絶縁体２１２と、絶縁体２８３とを同材料及び同方法を用いて形成してもよい。絶縁体２１２、および絶縁体２８３を、同材料、および同方法で設けることで、密着性を高めることができる。例えば、窒化シリコンを用いることが好ましい。 That is, the insulator 212 and the insulator 283 are in contact with each other in the openings provided in the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214. For example, at this time, the insulator 212 and the insulator 283 may be formed using the same material and the same method. By providing the insulator 212 and the insulator 283 with the same material and the same method, adhesion can be improved. For example, it is preferable to use silicon nitride.
　当該構造により、絶縁体２１２、および絶縁体２８３で、トランジスタ２００を包み込むことができる。絶縁体２１２、および絶縁体２８３は、酸素、水素、及び水の拡散を抑制する機能を有しているため、本実施の形態に示す半導体素子が形成された回路領域ごとに、基板を分断することにより、複数のチップに加工しても、分断した基板の側面方向から、水素又は水などの不純物が混入し、トランジスタ２００に拡散することを防ぐことができる。 With the structure, the transistor 200 can be wrapped with the insulator 212 and the insulator 283. Since the insulator 212 and the insulator 283 have a function of suppressing diffusion of oxygen, hydrogen, and water, the substrate is divided into each circuit region in which the semiconductor element described in this embodiment is formed. Thus, even when processed into a plurality of chips, it is possible to prevent impurities such as hydrogen or water from entering from the side surface direction of the divided substrate and diffusing into the transistor 200.
　また、当該構造により、絶縁体２８０、および絶縁体２２４の過剰酸素が外部に拡散することを防ぐことができる。従って、絶縁体２８０、および絶縁体２２４の過剰酸素は、効率的にトランジスタ２００におけるチャネルが形成される酸化物に供給される。当該酸素により、トランジスタ２００におけるチャネルが形成される酸化物の酸素欠損を低減することができる。これにより、トランジスタ２００におけるチャネルが形成される酸化物を欠陥準位密度が低い、安定な特性を有する酸化物半導体とすることができる。つまり、トランジスタ２００の電気特性の変動を抑制すると共に、信頼性を向上させることができる。 Further, with the structure, excess oxygen in the insulator 280 and the insulator 224 can be prevented from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide forming the channel in the transistor 200. With the oxygen, oxygen vacancies in the oxide forming the channel in the transistor 200 can be reduced. Thus, the oxide in which the channel in the transistor 200 is formed can be an oxide semiconductor with low density of defect states and stable characteristics. That is, variation in electric characteristics of the transistor 200 can be suppressed and reliability can be improved.
　以上が構成例についての説明である。本構成を用いることで、酸化物半導体を有するトランジスタを用いた半導体装置において、電気特性の変動を抑制すると共に、信頼性を向上させることができる。または、オン電流が大きい酸化物半導体を有するトランジスタを提供することができる。または、オフ電流が小さい酸化物半導体を有するトランジスタを提供することができる。または、消費電力が低減された半導体装置を提供することができる。 The above is a description of the configuration example. By using this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.
［記憶装置２］
　本発明の一態様である半導体装置を使用した、記憶装置の一例を図２２に示す。図２２に示す記憶装置は、図２１で示したトランジスタ２００、トランジスタ３００、および容量素子１００を有する半導体装置に加え、トランジスタ４００を有している。 [Memory device 2]
FIG. 22 illustrates an example of a memory device using the semiconductor device which is one embodiment of the present invention. The memory device illustrated in FIG. 22 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.
　トランジスタ４００は、トランジスタ２００の第２のゲート電圧を制御することができる。例えば、トランジスタ４００の第１のゲート及び第２のゲートをソースとダイオード接続し、トランジスタ４００のソースと、トランジスタ２００の第２のゲートを接続する構成とする。当該構成でトランジスタ２００の第２のゲートの負電位を保持するとき、トランジスタ４００の第１のゲートーソース間の電圧および、第２のゲートーソース間の電圧は、０Ｖになる。トランジスタ４００において、第２のゲート電圧及び第１のゲート電圧が０Ｖのときのドレイン電流が非常に小さいため、トランジスタ２００およびトランジスタ４００に電源供給をしなくても、トランジスタ２００の第２のゲートの負電位を長時間維持することができる。これにより、トランジスタ２００、およびトランジスタ４００を有する記憶装置は、長期にわたり記憶内容を保持することが可能である。 The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held in this structure, the first gate-source voltage and the second gate-source voltage of the transistor 400 are 0V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0 V is extremely small, the second gate voltage of the transistor 200 can be reduced even if power is not supplied to the transistor 200 and the transistor 400. The negative potential can be maintained for a long time. Accordingly, the memory device including the transistor 200 and the transistor 400 can hold the memory content for a long time.
　従って、図２２において、配線１００１はトランジスタ３００のソースと電気的に接続され、配線１００２はトランジスタ３００のドレインと電気的に接続されている。また、配線１００３はトランジスタ２００のソースおよびドレインの一方と電気的に接続され、配線１００４はトランジスタ２００のゲートと電気的に接続され、配線１００６はトランジスタ２００のバックゲートと電気的に接続されている。そして、トランジスタ３００のゲート、およびトランジスタ２００のソースおよびドレインの他方は、容量素子１００の電極の一方と電気的に接続され、配線１００５は容量素子１００の電極の他方と電気的に接続されている。配線１００７はトランジスタ４００のソースと電気的に接続され、配線１００８はトランジスタ４００のゲートと電気的に接続され、配線１００９はトランジスタ４００のバックゲートと電気的に接続され、配線１０１０はトランジスタ４００のドレインと電気的に接続されている。ここで、配線１００６、配線１００７、配線１００８、及び配線１００９が電気的に接続されている。 Therefore, in FIG. 22, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to a gate of the transistor 200, and the wiring 1006 is electrically connected to a back gate of the transistor 200. .. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100 and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .. The wiring 1007 is electrically connected to a source of the transistor 400, the wiring 1008 is electrically connected to a gate of the transistor 400, the wiring 1009 is electrically connected to a back gate of the transistor 400, and the wiring 1010 is a drain of the transistor 400. Is electrically connected to. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
　また、図２２に示す記憶装置は、図２１に示す記憶装置と同様に、マトリクス状に配置することで、メモリセルアレイを構成することができる。なお、１個のトランジスタ４００は、複数のトランジスタ２００の第２のゲート電圧を制御することができる。そのため、トランジスタ４００は、トランジスタ２００よりも、少ない個数を設けるとよい。また、また、図２２に示す記憶装置は、図２１に示す記憶装置と同様に、トランジスタ２００、およびトランジスタ４００を絶縁体２１２と絶縁体２８３で封止することができる。 The memory device shown in FIG. 22 can form a memory cell array by arranging the memory device shown in FIG. 22 in a matrix like the memory device shown in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the transistor 400 may be provided in a smaller number than the transistor 200. Further, in the memory device illustrated in FIG. 22, the transistor 200 and the transistor 400 can be sealed with the insulator 212 and the insulator 283 similarly to the memory device illustrated in FIG.
＜トランジスタ４００＞
　トランジスタ４００は、トランジスタ２００と、同じ層に形成されており、並行して作製することができるトランジスタである。トランジスタ４００は、第１のゲートとして機能する導電体４６０（導電体４６０ａ、および導電体４６０ｂ）と、第２のゲートとして機能する導電体４０５と、ゲート絶縁層として機能する絶縁体２２２、絶縁体２２４、および絶縁体４５０と、チャネル形成領域を有する酸化物４３０ｃと、ソースとして機能する導電体４４２ａ、酸化物４４３ａ、酸化物４３１ａ、および酸化物４３１ｂと、ドレインとして機能する導電体４４２ｂ、酸化物４４３ｂ、酸化物４３２ａ、および酸化物４３２ｂと、プラグとして機能する導電体４４０（導電体４４０ａ、および導電体４４０ｂ）と、導電体４４２のバリア絶縁膜として機能する絶縁体４７２（絶縁体４７２ａ、および絶縁体４７２ｂ）と、絶縁体４７３（絶縁体４７３ａ、および絶縁体４７３ｂ）と、を有する。 <Transistor 400>
The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460a and a conductor 460b) which functions as a first gate, a conductor 405 which functions as a second gate, an insulator 222 which functions as a gate insulating layer, and an insulator. 224, an insulator 450, an oxide 430c having a channel formation region, a conductor 442a, an oxide 443a, an oxide 431a, and an oxide 431b which function as a source, and a conductor 442b and an oxide which function as a drain. 443b, the oxide 432a, and the oxide 432b, the conductor 440 that functions as a plug (the conductor 440a and the conductor 440b), and the insulator 472 that functions as a barrier insulating film of the conductor 442 (the insulator 472a and The insulator 472b) and the insulator 473 (the insulator 473a and the insulator 473b) are included.
　トランジスタ４００において、導電体４０５は、導電体２０５と、同じ層である。酸化物４３１ａ、および酸化物４３２ａは、酸化物２３０ａと、同じ層であり、酸化物４３１ｂ、および酸化物４３２ｂは、酸化物２３０ｂと、同じ層である。導電体４４２は、導電体２４２と、同じ層である。酸化物４４３は、酸化物２４３と、同じ層である。酸化物４３０ｃは、酸化物２３０ｃと、同じ層である。絶縁体４５０は、絶縁体２５０と、同じ層である。導電体４６０は、導電体２６０と、同じ層である。導電体４４０は、導電体２４０と、同じ層である。絶縁体４７２は、絶縁体２７２と、同じ層である。絶縁体４７３は、絶縁体２７３と、同じ層である。 In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b. The conductor 442 is the same layer as the conductor 242. The oxide 443 is the same layer as the oxide 243. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260. The conductor 440 is the same layer as the conductor 240. The insulator 472 is the same layer as the insulator 272. The insulator 473 is the same layer as the insulator 273.
　なお、同じ層に形成された構造体は、同時に形成することができる。例えば、酸化物４３０ｃは、酸化物２３０ｃとなる酸化膜を加工することで、形成することができる。 Note that structures formed in the same layer can be formed at the same time. For example, the oxide 430c can be formed by processing an oxide film to be the oxide 230c.
　トランジスタ４００の活性層として機能する酸化物４３０ｃは、酸化物２３０などと同様に、酸素欠損が低減され、水素または水などの不純物が低減されている。これにより、トランジスタ４００のしきい値電圧を０Ｖより大きくし、オフ電流を低減し、第２のゲート電圧及び第１のゲート電圧が０Ｖのときのドレイン電流を非常に小さくすることができる。 Like the oxide 230, the oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water. Accordingly, the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made extremely small.
　本実施の形態に示す構成、方法などは、他の実施の形態および他の実施例に示す構成、構造、方法などと適宜組み合わせて用いることができる。 The configurations, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments and examples.
（実施の形態３）
　本実施の形態では、図２３および図２４を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ（以下、ＯＳトランジスタと呼ぶ場合がある）、および容量素子が適用されている記憶装置（以下、ＯＳメモリ装置と呼ぶ場合がある）について説明する。ＯＳメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するＯＳトランジスタを有する記憶装置である。ＯＳトランジスタのオフ電流は極めて小さいので、ＯＳメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。 (Embodiment 3)
In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied with reference to FIGS. The storage device (hereinafter sometimes referred to as an OS memory device) that is installed will be described. An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.
＜記憶装置の構成例＞
　図２３ＡにＯＳメモリ装置の構成の一例を示す。記憶装置１４００は、周辺回路１４１１、およびメモリセルアレイ１４７０を有する。周辺回路１４１１は、行回路１４２０、列回路１４３０、出力回路１４４０、コントロールロジック回路１４６０を有する。 <Structure example of storage device>
FIG. 23A shows an example of the configuration of the OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
　列回路１４３０は、例えば、列デコーダ、プリチャージ回路、センスアンプ、および書き込み回路等を有する。プリチャージ回路は、配線をプリチャージする機能を有する。センスアンプは、メモリセルから読み出されたデータ信号を増幅する機能を有する。なお、上記配線は、メモリセルアレイ１４７０が有するメモリセルに接続されている配線であり、詳しくは後述する。増幅されたデータ信号は、出力回路１４４０を介して、データ信号ＲＤＡＴＡとして記憶装置１４００の外部に出力される。また、行回路１４２０は、例えば、行デコーダ、ワード線ドライバ回路等を有し、アクセスする行を選択することができる。 The column circuit 1430 has, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470 and will be described later in detail. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. Further, the row circuit 1420 has a row decoder, a word line driver circuit, and the like, for example, and can select a row to be accessed.
　記憶装置１４００には、外部から電源電圧として低電源電圧（ＶＳＳ）、周辺回路１４１１用の高電源電圧（ＶＤＤ）、メモリセルアレイ１４７０用の高電源電圧（ＶＩＬ）が供給される。また、記憶装置１４００には、制御信号（ＣＥ、ＷＥ、ＲＥ）、アドレス信号ＡＤＤＲ、データ信号ＷＤＡＴＡが外部から入力される。アドレス信号ＡＤＤＲは、行デコーダおよび列デコーダに入力され、ＷＤＡＴＡは書き込み回路に入力される。 A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the memory device 1400 as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.
　コントロールロジック回路１４６０は、外部からの入力信号（ＣＥ、ＷＥ、ＲＥ）を処理して、行デコーダ、列デコーダの制御信号を生成する。ＣＥは、チップイネーブル信号であり、ＷＥは、書き込みイネーブル信号であり、ＲＥは、読み出しイネーブル信号である。コントロールロジック回路１４６０が処理する信号は、これに限定されるものではなく、必要に応じて、他の制御信号を入力すればよい。 The control logic circuit 1460 processes input signals (CE, WE, RE) from the outside and generates control signals for the row decoder and the column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.
　メモリセルアレイ１４７０は、行列状に配置された、複数個のメモリセルＭＣと、複数の配線を有する。なお、メモリセルアレイ１４７０と行回路１４２０とを接続している配線の数は、メモリセルＭＣの構成、一列に有するメモリセルＭＣの数などによって決まる。また、メモリセルアレイ１４７０と列回路１４３０とを接続している配線の数は、メモリセルＭＣの構成、一行に有するメモリセルＭＣの数などによって決まる。 The memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the structure of the memory cell MC, the number of memory cells MC in one column, and the like. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in one row, and the like.
　なお、図２３Ａにおいて、周辺回路１４１１とメモリセルアレイ１４７０を同一平面上に形成する例について示したが、本実施の形態はこれに限られるものではない。例えば、図２３Ｂに示すように、周辺回路１４１１の一部の上に、メモリセルアレイ１４７０が重なるように設けられてもよい。例えば、メモリセルアレイ１４７０の下に重なるように、センスアンプを設ける構成にしてもよい。 Although FIG. 23A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited to this. For example, as shown in FIG. 23B, a memory cell array 1470 may be provided so as to overlap part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.
　図２４に上述のメモリセルＭＣに適用できるメモリセルの構成例について説明する。 FIG. 24 illustrates a configuration example of a memory cell applicable to the above memory cell MC.
［ＤＯＳＲＡＭ］
　図２４Ａ乃至図２４Ｃに、ＤＲＡＭのメモリセルの回路構成例を示す。本明細書等において、１ＯＳトランジスタ１容量素子型のメモリセルを用いたＤＲＡＭを、ＤＯＳＲＡＭ（Ｄｙｎａｍｉｃ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）と呼ぶ場合がある。図２４Ａに示す、メモリセル１４７１は、トランジスタＭ１と、容量素子ＣＡと、を有する。なお、トランジスタＭ１は、ゲート（フロントゲートと呼ぶ場合がある）、及びバックゲートを有する。 [DOSRAM]
24A to 24C show examples of circuit configurations of memory cells of DRAM. In this specification and the like, a DRAM including a 1-OS transistor 1-capacitive element memory cell may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 illustrated in FIG. 24A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a front gate) and a back gate.
　トランジスタＭ１の第１端子は、容量素子ＣＡの第１端子と接続され、トランジスタＭ１の第２端子は、配線ＢＩＬと接続され、トランジスタＭ１のゲートは、配線ＷＯＬと接続され、トランジスタＭ１のバックゲートは、配線ＢＧＬと接続されている。容量素子ＣＡの第２端子は、配線ＣＡＬと接続されている。 The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected. Are connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.
　配線ＢＩＬは、ビット線として機能し、配線ＷＯＬは、ワード線として機能する。配線ＣＡＬは、容量素子ＣＡの第２端子に所定の電位を印加するための配線として機能する。データの書き込み時、及び読み出し時において、配線ＣＡＬには、低レベル電位を印加するのが好ましい。配線ＢＧＬは、トランジスタＭ１のバックゲートに電位を印加するための配線として機能する。配線ＢＧＬに任意の電位を印加することによって、トランジスタＭ１のしきい値電圧を増減することができる。 The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable to apply a low-level potential to the wiring CAL at the time of writing and reading data. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
　また、メモリセルＭＣは、メモリセル１４７１に限定されず、回路構成の変更を行うことができる。例えば、メモリセルＭＣは、図２４Ｂに示すメモリセル１４７２のように、トランジスタＭ１のバックゲートが、配線ＢＧＬでなく、配線ＷＯＬと接続される構成にしてもよい。また、例えば、メモリセルＭＣは、図２４Ｃに示すメモリセル１４７３のように、シングルゲート構造のトランジスタ、つまりバックゲートを有さないトランジスタＭ１で構成されたメモリセルとしてもよい。 Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, in the memory cell MC, like the memory cell 1472 illustrated in FIG. 24B, the back gate of the transistor M1 may be connected to the wiring WOL instead of the wiring BGL. Further, for example, the memory cell MC may be a memory cell including a transistor having a single-gate structure, that is, a transistor M1 having no back gate, like the memory cell 1473 illustrated in FIG. 24C.
　上記実施の形態に示す半導体装置をメモリセル１４７１等に用いる場合、トランジスタＭ１としてトランジスタ２００を用い、容量素子ＣＡとして容量素子１００を用いることができる。トランジスタＭ１としてＯＳトランジスタを用いることによって、トランジスタＭ１のリーク電流を非常に低くすることができる。つまり、書き込んだデータをトランジスタＭ１によって長時間保持することができるため、メモリセルのリフレッシュの頻度を少なくすることができる。また、メモリセルのリフレッシュ動作を不要にすることができる。また、リーク電流が非常に低いため、メモリセル１４７１、メモリセル１４７２、メモリセル１４７３に対して多値データ、又はアナログデータを保持することができる。 When the semiconductor device described in any of the above embodiments is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leak current of the transistor M1 can be made extremely low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-level data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
　また、ＤＯＳＲＡＭにおいて、上記のように、メモリセルアレイ１４７０の下に重なるように、センスアンプを設ける構成にすると、ビット線を短くすることができる。これにより、ビット線容量が小さくなり、メモリセルの保持容量を低減することができる。 Further, in the DOSRAM, if the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced and the storage capacity of the memory cell can be reduced.
［ＮＯＳＲＡＭ］
　図２４Ｄ乃至図２４Ｈに、２トランジスタ１容量素子のゲインセル型のメモリセルの回路構成例を示す。図２４Ｄに示す、メモリセル１４７４は、トランジスタＭ２と、トランジスタＭ３と、容量素子ＣＢと、を有する。なお、トランジスタＭ２は、フロントゲート（単にゲートと呼ぶ場合がある）、及びバックゲートを有する。本明細書等において、トランジスタＭ２にＯＳトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、ＮＯＳＲＡＭ（Ｎｏｎｖｏｌａｔｉｌｅ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ）と呼ぶ場合がある。 [NOSRAM]
24D to 24H show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 illustrated in FIG. 24D includes the transistor M2, the transistor M3, and the capacitor CB. Note that the transistor M2 has a front gate (may be simply referred to as a gate) and a back gate. In this specification and the like, a memory device including a gain cell type memory cell in which an OS transistor is used as the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).
　トランジスタＭ２の第１端子は、容量素子ＣＢの第１端子と接続され、トランジスタＭ２の第２端子は、配線ＷＢＬと接続され、トランジスタＭ２のゲートは、配線ＷＯＬと接続され、トランジスタＭ２のバックゲートは、配線ＢＧＬと接続されている。容量素子ＣＢの第２端子は、配線ＣＡＬと接続されている。トランジスタＭ３の第１端子は、配線ＲＢＬと接続され、トランジスタＭ３の第２端子は、配線ＳＬと接続され、トランジスタＭ３のゲートは、容量素子ＣＢの第１端子と接続されている。 The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected. Are connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
　配線ＷＢＬは、書き込みビット線として機能し、配線ＲＢＬは、読み出しビット線として機能し、配線ＷＯＬは、ワード線として機能する。配線ＣＡＬは、容量素子ＣＢの第２端子に所定の電位を印加するための配線として機能する。データの書き込み時、データ保持の最中、データの読み出し時において、配線ＣＡＬには、低レベル電位を印加するのが好ましい。配線ＢＧＬは、トランジスタＭ２のバックゲートに電位を印加するための配線として機能する。配線ＢＧＬに任意の電位を印加することによって、トランジスタＭ２のしきい値電圧を増減することができる。 The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable to apply a low-level potential to the wiring CAL during data writing, during data retention, and during data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
　また、メモリセルＭＣは、メモリセル１４７４に限定されず、回路の構成を適宜変更することができる。例えば、メモリセルＭＣは、図２４Ｅに示すメモリセル１４７５のように、トランジスタＭ２のバックゲートが、配線ＢＧＬでなく、配線ＷＯＬと接続される構成にしてもよい。また、例えば、メモリセルＭＣは、図２４Ｆに示すメモリセル１４７６のように、シングルゲート構造のトランジスタ、つまりバックゲートを有さないトランジスタＭ２で構成されたメモリセルとしてもよい。また、例えば、メモリセルＭＣは、図２４Ｇに示すメモリセル１４７７のように、配線ＷＢＬと配線ＲＢＬを一本の配線ＢＩＬとしてまとめた構成であってもよい。 The memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, in the memory cell MC, like the memory cell 1475 illustrated in FIG. 24E, the back gate of the transistor M2 may be connected to the wiring WOL instead of the wiring BGL. Further, for example, the memory cell MC may be a memory cell including a transistor having a single gate structure, that is, a transistor M2 having no back gate, like the memory cell 1476 illustrated in FIG. 24F. Further, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are integrated into one wiring BIL like the memory cell 1477 illustrated in FIG. 24G.
　上記実施の形態に示す半導体装置をメモリセル１４７４等に用いる場合、トランジスタＭ２としてトランジスタ２００を用い、トランジスタＭ３としてトランジスタ３００を用い、容量素子ＣＢとして容量素子１００を用いることができる。トランジスタＭ２としてＯＳトランジスタを用いることによって、トランジスタＭ２のリーク電流を非常に低くすることができる。これにより、書き込んだデータをトランジスタＭ２によって長時間保持することができるため、メモリセルのリフレッシュの頻度を少なくすることができる。また、メモリセルのリフレッシュ動作を不要にすることができる。また、リーク電流が非常に低いため、メモリセル１４７４に多値データ、又はアナログデータを保持することができる。メモリセル１４７５乃至１４７７も同様である。 When the semiconductor device described in any of the above embodiments is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leak current of the transistor M2 can be made extremely low. Accordingly, the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-level data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
　なお、トランジスタＭ３は、チャネル形成領域にシリコンを有するトランジスタ（以下、Ｓｉトランジスタと呼ぶ場合がある）であってもよい。Ｓｉトランジスタの導電型は、ｎチャネル型としてもよいし、ｐチャネル型としてもよい。Ｓｉトランジスタは、ＯＳトランジスタよりも電界効果移動度が高くなる場合がある。よって、読み出しトランジスタとして機能するトランジスタＭ３として、Ｓｉトランジスタを用いてもよい。また、トランジスタＭ３にＳｉトランジスタを用いることで、トランジスタＭ３の上に積層してトランジスタＭ２を設けることができるので、メモリセルの占有面積を低減し、記憶装置の高集積化を図ることができる。 Note that the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter, also referred to as Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be stacked over the transistor M3, so that the area occupied by the memory cell can be reduced and high integration of the memory device can be achieved.
　また、トランジスタＭ３はＯＳトランジスタであってもよい。トランジスタＭ２、Ｍ３にＯＳトランジスタを用いた場合、メモリセルアレイ１４７０をｎ型トランジスタのみを用いて回路を構成することができる。 Also, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.
　また、図２４Ｈに３トランジスタ１容量素子のゲインセル型のメモリセルの一例を示す。図２４Ｈに示すメモリセル１４７８は、トランジスタＭ４乃至Ｍ６、および容量素子ＣＣを有する。容量素子ＣＣは適宜設けられる。メモリセル１４７８は、配線ＢＩＬ、ＲＷＬ、ＷＷＬ、ＢＧＬ、およびＧＮＤＬに電気的に接続されている。配線ＧＮＤＬは低レベル電位を与える配線である。なお、メモリセル１４７８を、配線ＢＩＬに代えて、配線ＲＢＬ、ＷＢＬに電気的に接続してもよい。 Further, FIG. 24H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 illustrated in FIG. 24H includes transistors M4 to M6 and the capacitor CC. The capacitive element CC is provided as appropriate. The memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring which gives a low-level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
　トランジスタＭ４は、バックゲートを有するＯＳトランジスタであり、バックゲートは配線ＢＧＬに電気的に接続されている。なお、トランジスタＭ４のバックゲートとゲートとを互いに電気的に接続してもよい。あるいは、トランジスタＭ４はバックゲートを有さなくてもよい。 The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
　なお、トランジスタＭ５、Ｍ６はそれぞれ、ｎチャネル型Ｓｉトランジスタまたはｐチャネル型Ｓｉトランジスタでもよい。或いは、トランジスタＭ４乃至Ｍ６がＯＳトランジスタでもよい、この場合、メモリセルアレイ１４７０をｎ型トランジスタのみを用いて回路を構成することができる。 The transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-type transistors.
　上記実施の形態に示す半導体装置をメモリセル１４７８に用いる場合、トランジスタＭ４としてトランジスタ２００を用い、トランジスタＭ５、Ｍ６としてトランジスタ３００を用い、容量素子ＣＣとして容量素子１００を用いることができる。トランジスタＭ４としてＯＳトランジスタを用いることによって、トランジスタＭ４のリーク電流を非常に低くすることができる。 When the semiconductor device described in any of the above embodiments is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leak current of the transistor M4 can be made extremely low.
　なお、本実施の形態に示す、周辺回路１４１１、およびメモリセルアレイ１４７０等の構成は、上記に限定されるものではない。これらの回路、および当該回路に接続される配線、回路素子等の、配置または機能は、必要に応じて、変更、削除、または追加してもよい。 Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to the above. Arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.
　本実施の形態に示す構成、方法などは、他の実施の形態および他の実施例に示す構成、構造、方法などと適宜組み合わせて用いることができる。 The configurations, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments and examples.
（実施の形態４）
　本実施の形態では、図２５を用いて、本発明の半導体装置が実装されたチップ１２００の一例を示す。チップ１２００には、複数の回路（システム）が実装されている。このように、複数の回路（システム）を一つのチップに集積する技術を、システムオンチップ（Ｓｙｓｔｅｍ　ｏｎ　Ｃｈｉｐ：ＳｏＣ）と呼ぶ場合がある。 (Embodiment 4)
In this embodiment mode, an example of a chip 1200 in which a semiconductor device of the present invention is mounted is shown with reference to FIGS. A plurality of circuits (systems) are mounted on the chip 1200. The technique of integrating a plurality of circuits (systems) on a single chip in this way may be called a system on chip (SoC).
　図２５Ａに示すように、チップ１２００は、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）１２１１、ＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）１２１２、一または複数のアナログ演算部１２１３、一または複数のメモリコントローラ１２１４、一または複数のインターフェース１２１５、一または複数のネットワーク回路１２１６等を有する。 As shown in FIG. 25A, a chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, and one or more interfaces 1215. , One or a plurality of network circuits 1216 and the like.
　チップ１２００には、バンプ（図示しない）が設けられ、図２５Ｂに示すように、プリント基板（Ｐｒｉｎｔｅｄ　Ｃｉｒｃｕｉｔ　Ｂｏａｒｄ：ＰＣＢ）１２０１の第１の面と接続する。また、ＰＣＢ１２０１の第１の面の裏面には、複数のバンプ１２０２が設けられており、マザーボード１２０３と接続する。 A bump (not shown) is provided on the chip 1200, and is connected to a first surface of a printed circuit board (Printed Circuit Board: PCB) 1201 as shown in FIG. 25B. A plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the mother board 1203.
　マザーボード１２０３には、ＤＲＡＭ１２２１、フラッシュメモリ１２２２等の記憶装置が設けられていてもよい。例えば、ＤＲＡＭ１２２１に先の実施の形態に示すＤＯＳＲＡＭを用いることができる。また、例えば、フラッシュメモリ１２２２に先の実施の形態に示すＮＯＳＲＡＭを用いることができる。 The motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in any of the above embodiments can be used as the DRAM 1221. Further, for example, the NOSRAM described in the above embodiment can be used for the flash memory 1222.
　ＣＰＵ１２１１は、複数のＣＰＵコアを有することが好ましい。また、ＧＰＵ１２１２は、複数のＧＰＵコアを有することが好ましい。また、ＣＰＵ１２１１、およびＧＰＵ１２１２は、それぞれ一時的にデータを格納するメモリを有していてもよい。または、ＣＰＵ１２１１、およびＧＰＵ１２１２に共通のメモリが、チップ１２００に設けられていてもよい。該メモリには、前述したＮＯＳＲＡＭや、ＤＯＳＲＡＭを用いることができる。また、ＧＰＵ１２１２は、多数のデータの並列計算に適しており、画像処理や積和演算に用いることができる。ＧＰＵ１２１２に、本発明の酸化物半導体を用いた画像処理回路や、積和演算回路を設けることで、画像処理、および積和演算を低消費電力で実行することが可能になる。 The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the above-mentioned NOSRAM or DOSRAM can be used. Further, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention or a product-sum operation circuit, image processing and product-sum operation can be performed with low power consumption.
　また、ＣＰＵ１２１１、およびＧＰＵ１２１２が同一チップに設けられていることで、ＣＰＵ１２１１およびＧＰＵ１２１２間の配線を短くすることができ、ＣＰＵ１２１１からＧＰＵ１２１２へのデータ転送、ＣＰＵ１２１１、およびＧＰＵ１２１２が有するメモリ間のデータ転送、およびＧＰＵ１２１２での演算後に、ＧＰＵ１２１２からＣＰＵ１２１１への演算結果の転送を高速に行うことができる。 Since the CPU 1211 and the GPU 1212 are provided in the same chip, wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories included in the CPU 1211 and the GPU 1212, Further, after the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
　アナログ演算部１２１３はＡ／Ｄ（アナログ／デジタル）変換回路、およびＤ／Ａ（デジタル／アナログ）変換回路の一、または両方を有する。また、アナログ演算部１２１３に上記積和演算回路を設けてもよい。 The analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog-calculation unit 1213 may be provided with the product-sum calculation circuit.
　メモリコントローラ１２１４は、ＤＲＡＭ１２２１のコントローラとして機能する回路、およびフラッシュメモリ１２２２のインターフェースとして機能する回路を有する。 The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
　インターフェース１２１５は、表示装置、スピーカー、マイクロフォン、カメラ、コントローラなどの外部接続機器とのインターフェース回路を有する。コントローラとは、マウス、キーボード、ゲーム用コントローラなどを含む。このようなインターフェースとして、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＨＤＭＩ（登録商標）（Ｈｉｇｈ−Ｄｅｆｉｎｉｔｉｏｎ　Ｍｕｌｔｉｍｅｄｉａ　Ｉｎｔｅｒｆａｃｅ）などを用いることができる。 The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used.
　ネットワーク回路１２１６は、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）などのネットワーク回路を有する。また、ネットワークセキュリティー用の回路を有してもよい。 The network circuit 1216 has a network circuit such as a LAN (Local Area Network). In addition, a circuit for network security may be included.
　チップ１２００には、上記回路（システム）を同一の製造プロセスで形成することが可能である。そのため、チップ１２００に必要な回路の数が増えても、製造プロセスを増やす必要が無く、チップ１２００を低コストで作製することができる。 The above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
　ＧＰＵ１２１２を有するチップ１２００が設けられたＰＣＢ１２０１、ＤＲＡＭ１２２１、およびフラッシュメモリ１２２２が設けられたマザーボード１２０３は、ＧＰＵモジュール１２０４と呼ぶことができる。 The PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be called a GPU module 1204.
　ＧＰＵモジュール１２０４は、ＳｏＣ技術を用いたチップ１２００を有しているため、そのサイズを小さくすることができる。また、画像処理に優れていることから、スマートフォン、タブレット端末、ラップトップＰＣ、携帯型（持ち出し可能な）ゲーム機などの携帯型電子機器に用いることが好適である。また、ＧＰＵ１２１２を用いた積和演算回路により、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの演算を実行することができるため、チップ１２００をＡＩチップ、またはＧＰＵモジュール１２０４をＡＩシステムモジュールとして用いることができる。 Since the GPU module 1204 has the chip 1200 using the SoC technology, its size can be reduced. Moreover, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, portable (carry-out) game machines, and the like. In addition, a product-sum operation circuit using the GPU 1212 allows deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), self-encoders, deep Boltzmann machines (DBM), deep belief networks ( Since it is possible to execute operations such as DBN), the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
　本実施の形態に示す構成、方法などは、他の実施の形態および他の実施例に示す構成、構造、方法などと適宜組み合わせて用いることができる。 The configurations, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments and examples.
（実施の形態５）
　本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器（例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ（ビデオカメラも含む）、録画再生装置、ナビゲーションシステムなど）の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータや、ノート型のコンピュータや、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード（例えば、ＳＤカード）、ＵＳＢメモリ、ＳＳＤ（ソリッド・ステート・ドライブ）等の各種のリムーバブル記憶装置に適用される。図２６にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。 (Embodiment 5)
In this embodiment, an application example of a memory device including the semiconductor device described in any of the above embodiments will be described. The semiconductor device described in any of the above embodiments is, for example, a storage device of various electronic devices (eg, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, etc.). Applicable to Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in any of the above embodiments is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, an SSD (solid state drive), or the like. FIG. 26 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device described in any of the above embodiments is processed into a packaged memory chip and used for various storage devices and removable memories.
　図２６ＡはＵＳＢメモリの模式図である。ＵＳＢメモリ１１００は、筐体１１０１、キャップ１１０２、ＵＳＢコネクタ１１０３および基板１１０４を有する。基板１１０４は、筐体１１０１に収納されている。例えば、基板１１０４には、メモリチップ１１０５、コントローラチップ１１０６が取り付けられている。基板１１０４のメモリチップ１１０５などに先の実施の形態に示す半導体装置を組み込むことができる。 FIG. 26A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 of the substrate 1104 or the like.
　図２６ＢはＳＤカードの外観の模式図であり、図２６Ｃは、ＳＤカードの内部構造の模式図である。ＳＤカード１１１０は、筐体１１１１、コネクタ１１１２および基板１１１３を有する。基板１１１３は筐体１１１１に収納されている。例えば、基板１１１３には、メモリチップ１１１４、コントローラチップ１１１５が取り付けられている。基板１１１３の裏面側にもメモリチップ１１１４を設けることで、ＳＤカード１１１０の容量を増やすことができる。また、無線通信機能を備えた無線チップを基板１１１３に設けてもよい。これによって、ホスト装置とＳＤカード１１１０間の無線通信によって、メモリチップ１１１４のデータの読み出し、書き込みが可能となる。基板１１１３のメモリチップ１１１４などに先の実施の形態に示す半導体装置を組み込むことができる。 FIG. 26B is a schematic diagram of the external appearance of the SD card, and FIG. 26C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back surface side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided over the substrate 1113. As a result, the data in the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 of the substrate 1113 or the like.
　図２６ＤはＳＳＤの外観の模式図であり、図２６Ｅは、ＳＳＤの内部構造の模式図である。ＳＳＤ１１５０は、筐体１１５１、コネクタ１１５２および基板１１５３を有する。基板１１５３は筐体１１５１に収納されている。例えば、基板１１５３には、メモリチップ１１５４、メモリチップ１１５５、コントローラチップ１１５６が取り付けられている。メモリチップ１１５５はコントローラチップ１１５６のワークメモリであり、例えばＤＯＳＲＡＭチップを用いればよい。基板１１５３の裏面側にもメモリチップ１１５４を設けることで、ＳＳＤ１１５０の容量を増やすことができる。基板１１５３のメモリチップ１１５４などに先の実施の形態に示す半導体装置を組み込むことができる。 FIG. 26D is a schematic diagram of the external appearance of the SSD, and FIG. 26E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 of the substrate 1153 or the like.
　本実施の形態に示す構成、方法などは、他の実施の形態および他の実施例に示す構成、構造、方法などと適宜組み合わせて用いることができる。 The configurations, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments and examples.
（実施の形態６）
　本実施の形態では、本発明の一態様の半導体装置に適用可能な電子機器の具体例について図２７を用いて説明する。 (Embodiment 6)
In this embodiment, specific examples of electronic devices which can be applied to the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.
　より具体的には、本発明の一態様に係る半導体装置は、ＣＰＵやＧＰＵなどのプロセッサ、またはチップに用いることができる。図２７に、本発明の一態様に係るＣＰＵやＧＰＵなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。 More specifically, the semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. FIG. 27 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.
＜電子機器・システム＞
　本発明の一態様に係るＧＰＵ又はチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用などのモニタ、デジタルサイネージ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｇｅ：電子看板）、パチンコ機などの大型ゲーム機などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係る集積回路又はチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。 <Electronic devices and systems>
The GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and relatively large game machines such as pachinko machines. In addition to electronic devices including screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be given. By providing the electronic device with the integrated circuit or the chip of one embodiment of the present invention, artificial intelligence can be mounted on the electronic device.
　本発明の一態様の電子機器は、アンテナを有していてもよい。アンテナで信号を受信することで、表示部で映像や情報等の表示を行うことができる。また、電子機器がアンテナ及び二次電池を有する場合、アンテナを、非接触電力伝送に用いてもよい。 The electronic device of one embodiment of the present invention may include an antenna. By receiving the signal with the antenna, images, information, and the like can be displayed on the display portion. When the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.
　本発明の一態様の電子機器は、センサ（力、変位、位置、速度、加速度、角速度、回転数、距離、光、液、磁気、温度、化学物質、音声、時間、硬度、電場、電流、電圧、電力、放射線、流量、湿度、傾度、振動、においまたは赤外線を測定する機能を含むもの）を有していてもよい。 The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It has a function of measuring voltage, electric power, radiation, flow rate, humidity, gradient, vibration, odor or infrared light).
　本発明の一態様の電子機器は、様々な機能を有することができる。例えば、様々な情報（静止画、動画、テキスト画像など）を表示部に表示する機能、タッチパネル機能、カレンダー、日付または時刻などを表示する機能、様々なソフトウェア（プログラム）を実行する機能、無線通信機能、記録媒体に記録されているプログラムまたはデータを読み出す機能等を有することができる。図２７に、電子機器の例を示す。 The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), wireless communication It can have a function, a function of reading a program or data recorded in a recording medium, and the like. FIG. 27 shows examples of electronic devices.
［携帯電話］
　図２７Ａには、情報端末の一種である携帯電話（スマートフォン）が図示されている。情報端末５５００は、筐体５５１０と、表示部５５１１と、を有しており、入力用インターフェースとして、タッチパネルが表示部５５１１に備えられ、ボタンが筐体５５１０に備えられている。 [mobile phone]
FIG. 27A illustrates a mobile phone (smartphone) that is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display portion 5511. A touch panel is provided in the display portion 5511 and a button is provided in the housing 5510 as an input interface.
　情報端末５５００は、本発明の一態様のチップを適用することで、人工知能を利用したアプリケーションを実行することができる。人工知能を利用したアプリケーションとしては、例えば、会話を認識してその会話内容を表示部５５１１に表示するアプリケーション、表示部５５１１に備えるタッチパネルに対してユーザが入力した文字、図形などを認識して、表示部５５１１に表示するアプリケーション、指紋や声紋などの生体認証を行うアプリケーションなどが挙げられる。 By applying the chip of one embodiment of the present invention, the information terminal 5500 can execute an application utilizing artificial intelligence. As an application using artificial intelligence, for example, an application for recognizing a conversation and displaying the content of the conversation on the display unit 5511, a character input by a user on a touch panel included in the display unit 5511, a figure, etc. are recognized, An application displayed on the display portion 5511, an application for biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
［情報端末１］
　図２７Ｂには、デスクトップ型情報端末５３００が図示されている。デスクトップ型情報端末５３００は、情報端末の本体５３０１と、ディスプレイ５３０２と、キーボード５３０３と、を有する。 [Information terminal 1]
FIG. 27B shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
　デスクトップ型情報端末５３００は、先述した情報端末５５００と同様に、本発明の一態様のチップを適用することで、人工知能を利用したアプリケーションを実行することができる。人工知能を利用したアプリケーションとしては、例えば、設計支援ソフトウェア、文章添削ソフトウェア、献立自動生成ソフトウェアなどが挙げられる。また、デスクトップ型情報端末５３００を用いることで、新規の人工知能の開発を行うことができる。 Like the information terminal 5500 described above, the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the desktop information terminal 5300, new artificial intelligence can be developed.
　なお、上述では、電子機器としてスマートフォン、及びデスクトップ用情報端末を例として、それぞれ図２７Ａ、図２７Ｂに図示したが、スマートフォン、及びデスクトップ用情報端末以外の情報端末を適用することができる。スマートフォン、及びデスクトップ用情報端末以外の情報端末としては、例えば、ＰＤＡ（Ｐｅｒｓｏｎａｌ　Ｄｉｇｉｔａｌ　Ａｓｓｉｓｔａｎｔ）、ノート型情報端末、ワークステーションなどが挙げられる。 Note that, in the above description, a smartphone and a desktop information terminal are shown as examples of electronic devices in FIGS. 27A and 27B, but information terminals other than the smartphone and the desktop information terminal can be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.
［電化製品］
　図２７Ｃは、電化製品の一例である電気冷凍冷蔵庫５８００を示している。電気冷凍冷蔵庫５８００は、筐体５８０１、冷蔵室用扉５８０２、冷凍室用扉５８０３等を有する。 [Electronics]
FIG. 27C shows an electric refrigerator-freezer 5800 which is an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
　電気冷凍冷蔵庫５８００に本発明の一態様のチップを適用することによって、人工知能を有する電気冷凍冷蔵庫５８００を実現することができる。人工知能を利用することによって電気冷凍冷蔵庫５８００は、電気冷凍冷蔵庫５８００に保存されている食材、その食材の消費期限などを基に献立を自動生成する機能や、電気冷凍冷蔵庫５８００に保存されている食材に合わせた温度に自動的に調節する機能などを有することができる。 By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 has a function of automatically generating a menu based on the food items stored in the electric refrigerator-freezer 5800, the expiration date of the foodstuff, and the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature according to the food.
　本一例では、電化製品として電気冷凍冷蔵庫について説明したが、その他の電化製品としては、例えば、掃除機、電子レンジ、電子オーブン、炊飯器、湯沸かし器、ＩＨ調理器、ウォーターサーバ、エアーコンディショナーを含む冷暖房器具、洗濯機、乾燥機、オーディオビジュアル機器などが挙げられる。 In this example, an electric refrigerator/freezer is described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, a microwave oven, a rice cooker, a water heater, an IH cooker, a water server, an air conditioner including an air conditioner. Examples include appliances, washing machines, dryers and audiovisual equipment.
［ゲーム機］
　図２７Ｄは、ゲーム機の一例である携帯ゲーム機５２００を示している。携帯ゲーム機は、筐体５２０１、表示部５２０２、ボタン５２０３等を有する。 [game machine]
FIG. 27D shows a portable game machine 5200 which is an example of a game machine. The portable game machine has a housing 5201, a display portion 5202, buttons 5203, and the like.
　携帯ゲーム機５２００に本発明の一態様のＧＰＵ又はチップを適用することによって、低消費電力の携帯ゲーム機５２００を実現することができる。また、低消費電力により、回路からの発熱を低減することができるため、発熱によるその回路自体、周辺回路、及びモジュールへの影響を少なくすることができる。 By applying the GPU or the chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced by the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
　更に、携帯ゲーム機５２００に本発明の一態様のＧＰＵ又はチップを適用することによって、人工知能を有する携帯ゲーム機５２００を実現することができる。 Further, by applying the GPU or the chip of one embodiment of the present invention to the mobile game machine 5200, the mobile game machine 5200 having artificial intelligence can be realized.
　本来、ゲームの進行、ゲーム上に登場する生物の言動、ゲーム上で発生する現象などの表現は、そのゲームが有するプログラムによって定められているが、携帯ゲーム機５２００に人工知能を適用することにより、ゲームのプログラムに限定されない表現が可能になる。例えば、プレイヤーが問いかける内容、ゲームの進行状況、時刻、ゲーム上に登場する人物の言動が変化するといった表現が可能となる。 Originally, expressions such as the progress of the game, the behaviors of the creatures appearing in the game, and the phenomena occurring in the game are determined by the program included in the game. However, by applying artificial intelligence to the portable game machine 5200, It enables expressions that are not limited to game programs. For example, it is possible to express that the content that the player asks, the progress of the game, the time, and the behavior of the person appearing in the game changes.
　また、携帯ゲーム機５２００で複数のプレイヤーが必要なゲームを行う場合、人工知能によって擬人的にゲームプレイヤーを構成することができるため、対戦相手を人工知能によるゲームプレイヤーとすることによって、１人でもゲームを行うことができる。 Further, when a plurality of players play a necessary game on the portable game machine 5200, the artificial intelligence can configure the game player as an anthropomorphic person. You can play games.
　図２７Ｄでは、ゲーム機の一例として携帯ゲーム機を図示しているが、本発明の一態様のＧＰＵ又はチップを適用するゲーム機はこれに限定されない。本発明の一態様のＧＰＵ又はチップを適用するゲーム機としては、例えば、家庭用の据え置き型ゲーム機、娯楽施設（ゲームセンター、遊園地など）に設置されるアーケードゲーム機、スポーツ施設に設置されるバッティング練習用の投球マシンなどが挙げられる。 27D illustrates a portable game machine as an example of a game machine, the game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited to this. As a game machine to which the GPU or chip of one embodiment of the present invention is applied, for example, a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), or a sports facility is installed. A pitching machine for batting practice.
［移動体］
　本発明の一態様のＧＰＵ又はチップは、移動体である自動車、及び自動車の運転席周辺に適用することができる。 [Mobile]
The GPU or the chip of one embodiment of the present invention can be applied to an automobile that is a moving object and around a driver's seat of the automobile.
　図２７Ｅ１は移動体の一例である自動車５７００を示し、図２７Ｅ２は、自動車の室内におけるフロントガラス周辺を示す図である。図２７Ｅ２では、ダッシュボードに取り付けられた表示パネル５７０１、表示パネル５７０２、表示パネル５７０３の他、ピラーに取り付けられた表示パネル５７０４を図示している。 27E1 shows an automobile 5700, which is an example of a moving body, and FIG. 27E2 is a view showing the windshield and its surroundings in the interior of the automobile. FIG. 27E2 illustrates a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard, and a display panel 5704 attached to a pillar.
　表示パネル５７０１乃至表示パネル５７０３は、スピードメーターやタコメーター、走行距離、燃料計、ギア状態、空調の設定などを表示することで、様々な情報を提供することができる。また、表示パネルに表示される表示項目やレイアウトなどは、ユーザの好みに合わせて適宜変更することができ、デザイン性を高めることが可能である。表示パネル５７０１乃至表示パネル５７０３は、照明装置として用いることも可能である。 The display panels 5701 to 5703 can provide various information by displaying speedometers, tachometers, mileage, fuel gauges, gear status, air conditioning settings, and the like. Further, display items and layouts displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as a lighting device.
　表示パネル５７０４には、自動車５７００に設けられた撮像装置（図示しない）からの映像を映し出すことによって、ピラーで遮られた視界（死角）を補完することができる。すなわち、自動車５７００の外側に設けられた撮像装置からの画像を表示することによって、死角を補い、安全性を高めることができる。また、見えない部分を補完する映像を映すことによって、より自然に違和感なく安全確認を行うことができる。表示パネル５７０４は、照明装置として用いることもできる。 By displaying an image from an image pickup device (not shown) provided on the automobile 5700 on the display panel 5704, the field of view (blind spot) blocked by the pillars can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated and safety can be improved. In addition, by displaying an image that complements the invisible portion, it is possible to confirm the safety more naturally and comfortably. The display panel 5704 can also be used as a lighting device.
　本発明の一態様のＧＰＵ又はチップは人工知能の構成要素として適用できるため、例えば、当該チップを自動車５７００の自動運転システムに用いることができる。また、当該チップを道路案内、危険予測などを行うシステムに用いることができる。表示パネル５７０１乃至表示パネル５７０４には、道路案内、危険予測などの情報を表示する構成としてもよい。 Since the GPU or the chip of one embodiment of the present invention can be applied as a component of artificial intelligence, the chip can be used for an automatic driving system of an automobile 5700, for example. In addition, the chip can be used in a system that performs road guidance, risk prediction, and the like. Information such as road guidance and risk prediction may be displayed on the display panels 5701 to 5704.
　なお、上述では、移動体の一例として自動車について説明しているが、移動体は自動車に限定されない。例えば、移動体としては、電車、モノレール、船、飛行体（ヘリコプター、無人航空機（ドローン）、飛行機、ロケット）なども挙げることができ、これらの移動体に本発明の一態様のチップを適用して、人工知能を利用したシステムを付与することができる。 In the above description, a car is described as an example of the moving body, but the moving body is not limited to a car. For example, as the moving object, a train, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), or the like can be given, and the chip of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be added.
［放送システム］
　本発明の一態様のＧＰＵ又はチップは、放送システムに適用することができる。 [Broadcast system]
The GPU or chip of one embodiment of the present invention can be applied to a broadcasting system.
　図２７Ｆは、放送システムにおけるデータ伝送を模式的に示している。具体的には、図２７Ｆは、放送局５６８０から送信された電波（放送信号）が、各家庭のテレビジョン受信装置（ＴＶ）５６００に届くまでの経路を示している。ＴＶ５６００は、受信装置を備え（図示しない）、アンテナ５６５０で受信された放送信号は、当該受信装置を介して、ＴＶ５６００に送信される。 FIG. 27F schematically shows data transmission in the broadcasting system. Specifically, FIG. 27F shows a path through which a radio wave (broadcast signal) transmitted from the broadcasting station 5680 reaches a television receiver (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.
　図２７Ｆでは、アンテナ５６５０は、ＵＨＦ（Ｕｌｔｒａ　Ｈｉｇｈ　Ｆｒｅｑｕｅｎｃｙ）アンテナを図示しているが、アンテナ５６５０としては、ＢＳ・１１０°ＣＳアンテナ、ＣＳアンテナなども適用できる。 In FIG. 27F, the antenna 5650 shows a UHF (Ultra High Frequency) antenna, but as the antenna 5650, a BS/110° CS antenna, a CS antenna, or the like can be applied.
　電波５６７５Ａ、電波５６７５Ｂは地上波放送用の放送信号であり、電波塔５６７０は受信した電波５６７５Ａを増幅して、電波５６７５Ｂの送信を行う。各家庭では、アンテナ５６５０で電波５６７５Ｂを受信することで、ＴＶ５６００で地上波ＴＶ放送を視聴することができる。なお、放送システムは、図２７Ｆに示す地上波放送に限定せず、人工衛星を用いた衛星放送、光回線によるデータ放送などとしてもよい。 Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and a radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. In each home, the terrestrial TV broadcast can be viewed on the TV 5600 by receiving the radio wave 5675B with the antenna 5650. Note that the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 27F, and satellite broadcasting using artificial satellites, data broadcasting using optical lines, etc. may be used.
　上述した放送システムは、本発明の一態様のチップを適用して、人工知能を利用した放送システムとしてもよい。放送局５６８０から各家庭のＴＶ５６００に放送データを送信するとき、エンコーダによって放送データの圧縮が行われ、アンテナ５６５０が当該放送データを受信したとき、ＴＶ５６００に含まれる受信装置のデコーダによって当該放送データの復元が行われる。人工知能を利用することによって、例えば、エンコーダの圧縮方法の一である動き補償予測において、表示画像に含まれる表示パターンの認識を行うことができる。また、人工知能を利用したフレーム内予測などを行うこともできる。また、例えば、解像度の低い放送データを受信して、解像度の高いＴＶ５６００で当該放送データの表示を行うとき、デコーダによる放送データの復元において、アップコンバートなどの画像の補間処理を行うことができる。 The broadcasting system described above may be a broadcasting system using artificial intelligence by applying the chip of one embodiment of the present invention. When broadcasting data is transmitted from the broadcasting station 5680 to the home TV 5600, the encoder compresses the broadcasting data, and when the antenna 5650 receives the broadcasting data, the decoder of the receiving device included in the TV 5600 decodes the broadcasting data. Restore is performed. By using artificial intelligence, it is possible to recognize a display pattern included in a display image in motion compensation prediction, which is one of encoder compression methods. It is also possible to perform intra-frame prediction using artificial intelligence. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, an image interpolation process such as up-conversion can be performed when the decoder restores the broadcast data.
　上述した人工知能を利用した放送システムは、放送データの量が増大する超高精細度テレビジョン（ＵＨＤＴＶ：４Ｋ、８Ｋ）放送に対して好適である。 The above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.
　また、ＴＶ５６００側における人工知能の応用として、例えば、ＴＶ５６００に人工知能を有する録画装置を設けてもよい。このような構成にすることによって、当該録画装置にユーザの好みを人工知能に学習させることで、ユーザの好みにあった番組を自動的に録画することができる。 As an application of artificial intelligence on the TV 5600 side, for example, the TV 5600 may be provided with a recording device having artificial intelligence. With such a configuration, the program can be automatically recorded by allowing the recording apparatus to learn the user's preference by artificial intelligence.
　本実施の形態で説明した電子機器、その電子機器の機能、人工知能の応用例、その効果などは、他の電子機器の記載と適宜組み合わせることができる。 The electronic device described in this embodiment, the function of the electronic device, the application example of artificial intelligence, the effect, and the like can be appropriately combined with the description of other electronic devices.
　本実施の形態に示す構成、方法などは、他の実施の形態および他の実施例に示す構成、構造、方法などと適宜組み合わせて用いることができる。 The configurations, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments and examples.
　本実施例では、トランジスタ２００のソース電極、およびドレイン電極を有する試料Ａおよび試料Ｂを作製し、当該試料のチャネル幅方向の断面ＳＴＥＭ像の撮影と、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　ｓｐｅｃｔｒｏｓｃｏｐｙ）による分析を日立ハイテクノロジーズ製「ＨＤ−２７００」を用いて、行った。 In this embodiment, a sample A and a sample B having a source electrode and a drain electrode of the transistor 200 are manufactured, a cross-sectional STEM image of the sample in a channel width direction is taken, and energy dispersive X-ray spectroscopy (EDX: Energy) is performed. Analysis by Dispersive X-ray spectroscopy was performed using "HD-2700" manufactured by Hitachi High-Technologies Corporation.
　試料の作製方法について説明する。まず、シリコン基板上に、ＣＶＤ法により、酸化窒化シリコンを３００ｎｍの膜厚で成膜した。次に、スパッタリング法により、第１の酸化物として、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて、膜厚５ｎｍで成膜した。次に、第２の酸化物として、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のターゲットを用いて、膜厚１５ｎｍの膜厚で成膜した。次に、第３の酸化物として、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて、膜厚２ｎｍで成膜した。なお、第１乃至第３の酸化物は、減圧下で連続的に成膜した。 Explain the method of sample preparation. First, silicon oxynitride was formed into a film with a thickness of 300 nm on a silicon substrate by a CVD method. Next, by a sputtering method, a film of 5 nm was formed as a first oxide by using a target of In:Ga:Zn=1:3:4 [atomic ratio]. Next, as the second oxide, a film having a thickness of 15 nm was formed using a target of In:Ga:Zn=4:2:4.1 [atomic ratio]. Next, as a third oxide, a target of In:Ga:Zn=1:3:4 [atomic ratio] was used to form a film with a thickness of 2 nm. Note that the first to third oxides were continuously formed under reduced pressure.
　次に、窒素雰囲気にて、４００℃の温度で１時間の加熱処理と、酸素雰囲気にて、４００℃の温度で１時間の加熱処理を連続して行った。次に、スパッタリング法により、第１の窒化タンタルを２０ｎｍの膜厚で成膜した。次に、ＡＬＤ法により、第１の酸化アルミニウムを５ｎｍの膜厚で成膜した。　次に、スパッタリング法により、第２の窒化タンタルを１５ｎｍの膜厚で成膜した。 Next, heat treatment was performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, and heat treatment at a temperature of 400° C. for 1 hour was continuously performed in an oxygen atmosphere. Next, a first tantalum nitride film was formed to a thickness of 20 nm by a sputtering method. Next, a first aluminum oxide film was formed to a thickness of 5 nm by the ALD method. Next, a second tantalum nitride film was formed to a thickness of 15 nm by the sputtering method.
　次にリソグラフィー法により、レジストマスクを形成し、レジストマスクをエッチングマスクとして、第１の窒化タンタルの一部、第１の酸化アルミニウムの一部、および第２の窒化タンタルの一部をドライエッチング法によりエッチングした。ここで、レジストマスクは除去された。 Next, a resist mask is formed by a lithography method, and using the resist mask as an etching mask, a part of the first tantalum nitride, a part of the first aluminum oxide, and a part of the second tantalum nitride are dry-etched. Etched by. Here, the resist mask was removed.
　次に、第２の窒化タンタルをエッチングマスクとして、第１乃至第３の酸化物の一部をドライエッチング法によってエッチングした。 Next, using the second tantalum nitride as an etching mask, a part of the first to third oxides was etched by the dry etching method.
　次に、試料Ａは、スパッタリング法によって、第２の酸化アルミニウムを５ｎｍの膜厚で成膜した。試料Ｂは、スパッタリング法によって、第２の酸化アルミニウムを７ｎｍの膜厚で成膜した。ここで、試料Ａを試料Ａ−１、および試料Ａ−２に分断した。また、試料Ｂを試料Ｂ−１、および試料Ｂ−２に分断した。 Next, for sample A, a second aluminum oxide film having a thickness of 5 nm was formed by a sputtering method. For sample B, a second aluminum oxide film having a thickness of 7 nm was formed by a sputtering method. Here, the sample A was divided into the sample A-1 and the sample A-2. Further, the sample B was divided into the sample B-1 and the sample B-2.
　次に、試料Ａ−２、および試料Ｂ−２では、ドライエッチング法によって、第２の酸化アルミニウム、及び第２の窒化タンタルを異方性エッチングした。なお、試料Ａ−２と試料Ｂ−２の異方性エッチングの時間は、第２の酸化アルミニウムの膜厚に合わせてそれぞれ設定した。以上により、試料Ａ−１、試料Ａ−２、試料Ｂ−１、および試料Ｂ−２を作製した。 Next, in Samples A-2 and B-2, the second aluminum oxide and the second tantalum nitride were anisotropically etched by the dry etching method. The anisotropic etching times of Sample A-2 and Sample B-2 were set according to the film thickness of the second aluminum oxide. By the above, the sample A-1, the sample A-2, the sample B-1, and the sample B-2 were produced.
　次に、試料Ａ−１、試料Ａ−２、試料Ｂ−１、および試料Ｂ−２のチャネル幅方向の断面ＳＴＥＭ像の撮影およびＥＤＸマッピング分析によるアルミニウムの分布を観察した。 Next, the aluminum distribution was observed by photographing a cross-sectional STEM image of the sample A-1, sample A-2, sample B-1, and sample B-2 in the channel width direction and EDX mapping analysis.
　図２８Ａに試料Ａ−１の断面ＳＴＥＭ像、図２８ＢにＥＤＸマッピング分析によるアルミニウムの分布を示す。図２９Ａに試料Ａ−２の断面ＳＴＥＭ像、図２９ＢにＥＤＸマッピング分析によるアルミニウムの分布を示す。図３０Ａに試料Ｂ−１の断面ＳＴＥＭ像、図３０ＢにＥＤＸマッピング分析によるアルミニウムの分布を示す。図３１Ａに試料Ｂ−２の断面ＳＴＥＭ像、図３１ＢにＥＤＸマッピング分析によるアルミニウムの分布を示す。 28A shows a cross-sectional STEM image of Sample A-1, and FIG. 28B shows the distribution of aluminum by EDX mapping analysis. FIG. 29A shows a cross-sectional STEM image of Sample A-2, and FIG. 29B shows an aluminum distribution by EDX mapping analysis. FIG. 30A shows a cross-sectional STEM image of Sample B-1, and FIG. 30B shows the distribution of aluminum by EDX mapping analysis. FIG. 31A shows a cross-sectional STEM image of Sample B-2, and FIG. 31B shows the distribution of aluminum by EDX mapping analysis.
　図２８Ａ、図２８Ｂに示すように、試料Ａ−１の第２の酸化アルミニウムの膜厚は５ｎｍであるが、酸化窒化シリコン上の第１乃至第３の酸化物、第１の窒化タンタル、第１の酸化アルミニウム、および第２の窒化タンタルの積層体に良好な被覆性で成膜されていることが解った。また、図２９Ａ、図２９Ｂに示すように、第２の酸化アルミニウム、および第２の窒化タンタルを異方性エッチングした試料Ａ−２では、第２の酸化アルミニウムは、少なくとも第１乃至第３の酸化物の側面、および第１の窒化タンタルの側面に接するように形成されていることを確認した。 As shown in FIGS. 28A and 28B, the film thickness of the second aluminum oxide in Sample A-1 is 5 nm, but the first to third oxides on the silicon oxynitride, the first tantalum nitride, the It was found that the aluminum oxide of 1 and the tantalum nitride of the second layer were formed with good coverage. As shown in FIGS. 29A and 29B, in the sample A-2 obtained by anisotropically etching the second aluminum oxide and the second tantalum nitride, the second aluminum oxide is at least the first to the third. It was confirmed that it was formed so as to be in contact with the side surface of the oxide and the side surface of the first tantalum nitride.
　また、図３０Ａ、図３０Ｂに示すように、試料Ｂ−１の第２の酸化アルミニウムの膜厚は７ｎｍであるが、酸化窒化シリコン上の第１乃至第３の酸化物、第１の窒化タンタル、第１の酸化アルミニウム、および第２の窒化タンタルの積層体に良好な被覆性で成膜されていることが解った。また、図３１Ａ、図３１Ｂに示すように、第２の酸化アルミニウム、および第２の窒化タンタルを異方性エッチングした試料Ｂ−２では、第２の酸化アルミニウムは、少なくとも第１乃至第３の酸化物の側面、および第１の窒化タンタルの側面に接するように形成されていることを確認した。 Further, as shown in FIGS. 30A and 30B, although the thickness of the second aluminum oxide of Sample B-1 is 7 nm, the first to third oxides and the first tantalum nitride on the silicon oxynitride are used. It was found that a film was formed on the laminate of the first aluminum oxide and the second tantalum nitride with good coverage. Further, as shown in FIGS. 31A and 31B, in the sample B-2 obtained by anisotropically etching the second aluminum oxide and the second tantalum nitride, the second aluminum oxide is at least the first to the third. It was confirmed that it was formed so as to be in contact with the side surface of the oxide and the side surface of the first tantalum nitride.
　以上、本実施の形態に示す構成、方法などは、他の実施の形態および他の実施例に示す構成、構造、方法などと適宜組み合わせて用いることができる。 As described above, the structure, the method, and the like described in this embodiment can be used in appropriate combination with the structure, the structure, the method, and the like described in other embodiment modes and other examples.
１００：容量素子、１１０：導電体、１１２：導電体、１２０：導電体、１３０：絶縁体、１５０：絶縁体、２００：トランジスタ、２００＿ｎ：トランジスタ、２００＿１：トランジスタ、２０５：導電体、２０５ａ：導電体、２０５ｂ：導電体、２１０：絶縁体、２１２：絶縁体、２１４：絶縁体、２１６：絶縁体、２１７：絶縁体、２１８：導電体、２２２：絶縁体、２２４：絶縁体、２３０：酸化物、２３０ａ：酸化物、２３０Ａ：酸化膜、２３０ｂ：酸化物、２３０Ｂ：酸化膜、２３０ｃ：酸化物、２３０Ｃ：酸化膜、２３０ｎ：領域、２４０：導電体、２４０ａ：導電体、２４０ｂ：導電体、２４１：絶縁体、２４１ａ：絶縁体、２４１ｂ：絶縁体、２４２：導電体、２４２ａ：導電体、２４２Ａ：導電膜、２４２ｂ：導電体、２４２Ｂ：導電体層、２４３：酸化物、２４３ａ：酸化物、２４３Ａ：酸化膜、２４３ｂ：酸化物、２４３Ｂ：酸化物層、２４６：導電体、２４６ａ：導電体、２４６ｂ：導電体、２４７Ａ：導電膜、２４７Ｂ：導電体層、２５０：絶縁体、２５０Ａ：絶縁膜、２５５ａ：開口、２５５ｂ：開口、２６０：導電体、２６０ａ：導電体、２６０Ａａ：導電膜、２６０Ａｂ：導電膜、２６０ｂ：導電体、２６５：封止部、２６５ａ：封止部、２６５ｂ：封止部、２７２：絶縁体、２７２ａ：絶縁体、２７２Ａ：絶縁膜、２７２ｂ：絶縁体、２７２Ｂ：絶縁体層、２７３：絶縁体、２７３ａ：絶縁体、２７３Ａ：絶縁膜、２７３ｂ：絶縁体、２７３Ｂ：絶縁体層、２７４：絶縁体、２８０：絶縁体、２８２：絶縁体、２８３：絶縁体、３００：トランジスタ、３１１：基板、３１３：半導体領域、３１４ａ：低抵抗領域、３１４ｂ：低抵抗領域、３１５：絶縁体、３１６：導電体、３２０：絶縁体、３２２：絶縁体、３２４：絶縁体、３２６：絶縁体、３２８：導電体、３３０：導電体、３５０：絶縁体、３５２：絶縁体、３５４：絶縁体、３５６：導電体、４００：トランジスタ、４０５：導電体、４３０ｃ：酸化物、４３１ａ：酸化物、４３１ｂ：酸化物、４３２ａ：酸化物、４３２ｂ：酸化物、４４０：導電体、４４０ａ：導電体、４４０ｂ：導電体、４４２：導電体、４４２ａ：導電体、４４２ｂ：導電体、４４３：酸化物、４４３ａ：酸化物、４４３ｂ：酸化物、４５０：絶縁体、４６０：導電体、４６０ａ：導電体、４６０ｂ：導電体、４７２：絶縁体、４７２ａ：絶縁体、４７２ｂ：絶縁体、４７３：絶縁体、４７３ａ：絶縁体、４７３ｂ：絶縁体、１００１：配線、１００２：配線、１００３：配線、１００４：配線、１００５：配線、１００６：配線、１００７：配線、１００８：配線、１００９：配線、１０１０：配線 100: capacitive element, 110: conductor, 112: conductor, 120: conductor, 130: insulator, 150: insulator, 200: transistor, 200_n: transistor, 200_1: transistor, 205: conductor, 205a: conductor Body, 205b: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 217: insulator, 218: conductor, 222: insulator, 224: insulator, 230: oxidation Object, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 230n: region, 240: conductor, 240a: conductor, 240b: conductor , 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductor layer, 243: oxide, 243a: oxidation. Object, 243A: oxide film, 243b: oxide, 243B: oxide layer, 246: conductor, 246a: conductor, 246b: conductor, 247A: conductive film, 247B: conductor layer, 250: insulator, 250A : Insulating film, 255a: opening, 255b: opening, 260: conductor, 260a: conductor, 260Aa: conductive film, 260Ab: conductive film, 260b: conductor, 265: sealing portion, 265a: sealing portion, 265b : Sealing part, 272: Insulator, 272a: Insulator, 272A: Insulator, 272b: Insulator, 272B: Insulator layer, 273: Insulator, 273a: Insulator, 273A: Insulator, 273b: Insulator 273B: Insulator layer, 274: Insulator, 280: Insulator, 282: Insulator, 283: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance Region: 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulation Body, 354: insulator, 356: conductor, 400: transistor, 405: conductor, 430c: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 440: conductor 440a: conductor, 440b: conductor, 442: conductor, 442a: conductor, 442b: conductor, 443: oxide, 443a: oxide, 443b: oxide, 450: insulator, 460: conductor 460a: conductor, 460b: conductor, 472: insulator, 472a: insulator, 4 72b: insulator, 473: insulator, 473a: insulator, 473b: insulator, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring, 1007: wiring, 1008: Wiring, 1009: wiring, 1010: wiring

Claims (6)

  1. 　第１の酸化物と、
    　前記第１の酸化物上の第１の導電体および第２の導電体と、
    　前記第１の導電体上の第１の絶縁体と、
    　前記第２の導電体上の第２の絶縁体と、
    　前記第１の絶縁体および前記第２の絶縁体上の第３の絶縁体と、
    　少なくとも前記第１の酸化物の側面、および前記第１の導電体の側面と接する第４の絶縁体と、
    　少なくとも前記第１の酸化物の側面、および前記第２の導電体の側面と接する第５の絶縁体と、
    　前記第１の酸化物上で、前記第１の導電体と前記第２の導電体の間に配置される第２の酸化物と、
    　前記第２の酸化物上の第６の絶縁体と、
    　前記第６の絶縁体上の第３の導電体と、
    　前記第３の絶縁体の上面、前記第２の酸化物の上面、前記第６の絶縁体の上面、および前記第３の導電体の上面にそれぞれ接する、第７の絶縁体と、を有し、
    　前記第１の酸化物の前記第４の絶縁体と接する領域のキャリア濃度は、前記第１の酸化物の前記第２の酸化物と接する領域のキャリア濃度よりも高く、
    　前記第１の酸化物の前記第５の絶縁体と接する領域のキャリア濃度は、前記第１の酸化物の前記第２の酸化物と接する領域のキャリア濃度よりも高い、半導体装置。     A first oxide,
    A first conductor and a second conductor on the first oxide;
    A first insulator on the first conductor;
    A second insulator on the second conductor;
    A third insulator on the first insulator and the second insulator;
    At least a side surface of the first oxide, and a fourth insulator in contact with a side surface of the first conductor;
    A fifth insulator contacting at least the side surface of the first oxide and the side surface of the second conductor;
    A second oxide disposed on the first oxide and between the first conductor and the second conductor;
    A sixth insulator on the second oxide;
    A third conductor on the sixth insulator,
    A seventh insulator that is in contact with the upper surface of the third insulator, the upper surface of the second oxide, the upper surface of the sixth insulator, and the upper surface of the third conductor, respectively. ,
    The carrier concentration of the region of the first oxide in contact with the fourth insulator is higher than the carrier concentration of the region of the first oxide in contact with the second oxide,
    A semiconductor device, wherein a carrier concentration of a region of the first oxide in contact with the fifth insulator is higher than a carrier concentration of a region of the first oxide in contact with the second oxide.
  2. 　請求項１において、
    　前記第４の絶縁体は、前記第３の絶縁体よりも酸素を透過し難く、
    　前記第４の絶縁体は、前記第１の絶縁体よりも酸素を透過し易く、
    　前記第５の絶縁体は、前記第３の絶縁体よりも酸素を透過し難く、
    　前記第５の絶縁体は、前記第２の絶縁体よりも酸素を透過し易い、半導体装置。     In claim 1,
    The fourth insulator is less likely to transmit oxygen than the third insulator,
    The fourth insulator is more permeable to oxygen than the first insulator,
    The fifth insulator is less permeable to oxygen than the third insulator,
    The fifth insulator is a semiconductor device in which oxygen easily permeates more than the second insulator.
  3. 　請求項１または請求項２において、
    　前記第４の絶縁体の膜密度は、前記第１の絶縁体の膜密度より低く、
    　前記第５の絶縁体の膜密度は、前記第２の絶縁体の膜密度より低い、半導体装置。     In claim 1 or claim 2,
    The film density of the fourth insulator is lower than the film density of the first insulator,
    A semiconductor device, wherein the film density of the fifth insulator is lower than the film density of the second insulator.
  4. 　請求項１乃至請求項３のいずれか一項において、
    　前記第４の絶縁体、および前記第５の絶縁体は、アルミニウム、マグネシウム、タンタルのいずれか一を含む、半導体装置。     In any one of Claim 1 thru|or Claim 3,
    The semiconductor device in which the fourth insulator and the fifth insulator include any one of aluminum, magnesium, and tantalum.
  5. 　請求項１乃至請求項４のいずれか一項において、
    　前記第１の絶縁体、前記第２の絶縁体、前記第４の絶縁体、および前記第５の絶縁体は、酸化アルミニウムである、半導体装置。     In any one of Claim 1 thru|or Claim 4,
    The semiconductor device, wherein the first insulator, the second insulator, the fourth insulator, and the fifth insulator are aluminum oxide.
  6. 　基板上に、第１の酸化膜、第１の導電膜、第１の絶縁膜、および第２の導電膜を順に成膜し、
    　前記第１の酸化膜、前記第１の導電膜、前記第１の絶縁膜、および前記第２の導電膜を加工して、第１の酸化物、第１の導電体層、第１の絶縁体層、および第２の導電体層を形成し、
    　前記第１の酸化物、前記第１の導電体層、前記第１の絶縁体層、および前記第２の導電体層を覆って、第２の絶縁膜を成膜し、
    　前記第２の絶縁膜を異方性エッチングすることで、
    　少なくとも前記第１の酸化物の側面、および前記第１の導電体層の側面に接する第１の絶縁体を形成し、
    　前記第２の導電体層を除去し、
    　前記第１の酸化物、前記第１の導電体層、および前記第１の絶縁体層を覆って、第３の絶縁膜を成膜し、
    　前記第１の導電体層、前記第１の絶縁体層、前記第１の絶縁体および前記第３の絶縁膜に前記第１の酸化物が露出する開口を形成することで、
    　第１の導電体、第２の導電体、第２の絶縁体、第３の絶縁体、第４の絶縁体、第５の絶縁体および第６の絶縁体を形成し、
    　第２の酸化膜、第４の絶縁膜および第３の導電膜を順に成膜し、
    　平坦化処理を行うことによって、前記第２の酸化膜、前記第４の絶縁膜および前記第３の導電膜を前記第６の絶縁体の一部が露出するまで除去し、第２の酸化物、第７の絶縁体および第３の導電体を形成し、
    　前記第６の絶縁体、前記第２の酸化物、前記第７の絶縁体、および前記第３の導電体上に第５の絶縁膜を成膜する、半導体装置の作製方法。     A first oxide film, a first conductive film, a first insulating film, and a second conductive film are sequentially formed on a substrate,
    The first oxide film, the first conductive film, the first insulating film, and the second conductive film are processed to form a first oxide, a first conductor layer, and a first insulating film. A body layer and a second conductor layer are formed,
    A second insulating film is formed to cover the first oxide, the first conductor layer, the first insulator layer, and the second conductor layer,
    By anisotropically etching the second insulating film,
    Forming a first insulator in contact with at least a side surface of the first oxide and a side surface of the first conductor layer;
    Removing the second conductor layer,
    Forming a third insulating film to cover the first oxide, the first conductor layer, and the first insulator layer;
    By forming an opening in which the first oxide is exposed in the first conductor layer, the first insulator layer, the first insulator, and the third insulating film,
    Forming a first conductor, a second conductor, a second insulator, a third insulator, a fourth insulator, a fifth insulator and a sixth insulator,
    A second oxide film, a fourth insulating film, and a third conductive film are sequentially formed,
    By performing a planarization process, the second oxide film, the fourth insulating film, and the third conductive film are removed until a part of the sixth insulator is exposed, and the second oxide film is removed. Forming a seventh insulator and a third conductor,
    A method for manufacturing a semiconductor device, comprising forming a fifth insulating film over the sixth insulator, the second oxide, the seventh insulator, and the third conductor.
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