JP7044464B2 - Semiconductor devices, display devices and electronic devices - Google Patents

Description

One aspect of the present invention relates to a semiconductor device or a display device having the semiconductor device.

It should be noted that one aspect of the present invention is not limited to the above technical fields. The technical field of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, image pickup devices, storage devices, processors, electronic devices, and the like. Examples thereof include their driving methods, their manufacturing methods, their inspection methods, or their systems.

In recent years, the definition of display devices has been increasing. As the definition of the display device increases, the number of circuits and wirings for transmitting an image signal to the display device and supplying electric power to the display device tends to increase. In addition, since the number of circuits and wirings increases, the power consumption of the display device tends to increase.

As a method for reducing the power consumption of a display device, a technique for reducing the number of times when the same image (still image) is continuously displayed and the number of times the signal of the same image is written (hereinafter, may be refreshed) is known. (Patent Document 1). The frequency of refreshing is called the refresh rate.

Japanese Unexamined Patent Publication No. 2011-237760

An image can be displayed on the display device by driving a driver circuit (or a driver IC (Integrated Circuit) or the like) provided in the display device. The driver circuit includes a serial-parallel conversion circuit, a shift register circuit, a level shifter circuit, a pass transistor logic circuit, a buffer amplifier circuit, and the like, and the image signal transmitted to the driver circuit is processed by these circuits and then processed. The resulting image signal is supplied to the pixel array.

In particular, the buffer amplifier circuit has a function of amplifying the signal processed by each circuit to a predetermined size and transmitting the amplified signal to the pixels. While the display device is being driven, the buffer amplifier circuit is supplied with a plurality of bias voltages, but even when the same image (still image) is continuously displayed, the plurality of bias voltages are applied. Continue to be supplied. That is, the power consumption of the display device increases as the bias voltage continues to be supplied.

One aspect of the present invention is to provide a novel semiconductor device. Alternatively, one aspect of the present invention is to provide a display device or a display module having a novel semiconductor device. Alternatively, one aspect of the present invention is to provide a display device having a novel semiconductor device or an electronic device using a display module. Alternatively, one aspect of the present invention is to provide a display device having a novel semiconductor device or a system having a display module.

Alternatively, one aspect of the present invention is to provide a semiconductor device having reduced power consumption, a display device having the semiconductor device, or a display module having the semiconductor device. Alternatively, one aspect of the present invention is to provide a display device or a display module having excellent visibility. Alternatively, one aspect of the present invention is to provide a display device or a display module having good display quality.

The problems of one aspect of the present invention are not limited to the problems listed above. The issues listed above do not preclude the existence of other issues. Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from the description of the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention solves at least one of the above-listed descriptions and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed descriptions and other problems.

(1)
One aspect of the present invention is a semiconductor device having first to fifth circuits and first to k wiring (k is an integer of 2 or more), and the first circuit has an input terminal. , The second circuit has the first to (2k) output terminals, and the first circuit is electrically connected to the second circuit via the h wiring (h is an integer of 1 or more and k or less). The first circuit has a function of applying the first to kth potentials to the first to kth wirings, respectively, according to the potentials input to the input terminals when the semiconductor device is in the driving state. When the semiconductor device is in the driving state, the circuit is the first (k + 1) to the first (k + 1) to the first (k + 1) to the first (2k) output terminals, respectively, according to the first to kth potentials input from the first to kth wirings. (3k) It has a function of outputting a potential, the third circuit is electrically connected to the first to k wirings, and the fourth circuit is electrically connected to the first to kth output terminals. The fifth circuit is electrically connected to the first (k + 1) to (2k) output terminals, and the third circuit has a function of applying a low level potential to the first to k wirings when the semiconductor device is in the standby state. The fourth circuit has a function of outputting a high level potential to the first to kth output terminals when the semiconductor device is in the standby state, and the fifth circuit has a function when the semiconductor device is in the standby state. , A semiconductor device characterized by having a function of outputting a low level potential to the first (k + 1) to (2k) output terminals.

(2)
Alternatively, in one aspect of the present invention, in the above (1), the first circuit has the first to kth transistors, the first terminal of the first transistor is electrically connected to the input terminal, and the h The first terminal of the transistor is electrically connected to the gate of the h transistor, the first terminal of the h transistor is electrically connected to the h wiring, and the g transistor (g is 1 or more (k-1). ) The second terminal of the following integer) is a semiconductor device characterized by being electrically connected to the first terminal of the (g + 1) transistor.

(3)
Alternatively, one aspect of the present invention is the semiconductor device according to (2) above, wherein the first to kth transistors are n-channel transistors.

(4)
Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the third circuit has the first (k + 1) to the (2k) transistor and the first (k + h) transistor. The terminal is a semiconductor device that is electrically connected to the h-th wiring, and the gates of the first (k + 1) to (2k) transistors are electrically connected to each other.

(5)
Alternatively, one aspect of the present invention is the semiconductor device according to (4) above, wherein the first (k + 1) to (2k) transistors are n-channel transistors.

(6)
Alternatively, in one aspect of the present invention, in the above (5), at least one of the first (k + 1) to (2k) transistors has a back gate, and the back gate is provided by applying a potential to the back gate. It is a semiconductor device characterized by shifting the threshold voltage of a transistor.

(7)
Alternatively, in one aspect of the present invention, in any one of the above (1) to (6), the fourth circuit has the first (2k + 1) to the (3k) transistor and the first (2k + h) transistor. The terminal is electrically connected to the hth output terminal, and the gates of the first (2k + 1) to (3k) transistors are electrically connected to each other.

(8)
Alternatively, one aspect of the present invention is the semiconductor device according to (7) above, wherein the (2k + 1) to (3k) third transistors are p-channel transistors.

(9)
Alternatively, in one aspect of the present invention, in any one of the above (1) to (8), the fifth circuit has the first (3k + 1) to the (4k) transistor and the first (3k + h) transistor. The terminal is a semiconductor device characterized in that it is electrically connected to a third (k + h) output terminal, and the respective gates of the third (3k + 1) to (4k) transistors are electrically connected to each other.

(10)
Alternatively, one aspect of the present invention is the semiconductor device according to (9) above, wherein the (3k + 1) to (4k) transistors are n-channel transistors.

(11)
Alternatively, in one aspect of the present invention, in the above (10), at least one of the (3k + 1) to (4k) transistors has a back gate, and the back gate is provided by applying a potential to the back gate. It is a semiconductor device characterized by shifting the threshold voltage of a transistor.

(12)
Alternatively, in one aspect of the present invention, in any one of the above (1) to (11), the number of the second circuits is (2k) in the row direction and (2k) in the column direction, for a total of (4k ² ). (4k + 1) transistors are provided, and (2k) th (4k + 1) transistors are connected in series to the jth column (j is an integer of 1 or more (2k) or less) of the second circuit. The connection portion between the jth column and kth row (4k + 1) transistor of the second circuit and the jth column and (k + 1) th row (4k + 1) transistor of the second circuit is the first. As a j node, each gate of the second (k + h) th row of the second circuit and the first (4k + 1) transistor of the first to kth columns is electrically connected to the hth wiring, and the second h of the second circuit. The gates of the first (4k + 1) transistors in the rows and the first (k + 1) to (2k) columns are electrically connected to the h output terminal, and are in the hth column of the second circuit and the first to first gates. Each gate of the (4k + 1) transistor in the first (k + 1-h) row is electrically connected to the h node, and is in the hth row of the second circuit and in the (k + 1-h) to kth columns. Each gate of the first (4k + 1) transistor is electrically connected to the hth output terminal, and is in the (k + h) th column of the second circuit and in the first (2k + 1-h) to (2k) rows (4k + 1). ) Each gate of the transistor is electrically connected to the (k + h) node, and is the first (4k + 1) transistor in the second (k + h) row and the (k + 1) to (2k + 1-h) columns of the second circuit. Each gate of is a semiconductor device characterized by being electrically connected to a (k + h) th output terminal.

(13)
Alternatively, in one aspect of the present invention, in the above (12), the jth column of the second circuit and the (4k + 1) th transistor in the first to kth rows are p-channel type transistors, and the second circuit has one embodiment. The j-th column and the (4k + 1) th transistor in the (k + 1) to (2k) th rows is a semiconductor device characterized by being an n-channel transistor.

(14)
Alternatively, one aspect of the present invention is a display device including a drive circuit having the semiconductor device according to any one of (1) to (13) above and a display unit.

(15)
Alternatively, one aspect of the present invention is the display device having the touch sensor, the touch sensor drive circuit, and the touch sensor detection circuit in the above (14).

(16)
Alternatively, one aspect of the present invention is an electronic device having the display device according to the above (14) or the above (15) and a housing.

According to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, it is possible to provide a display device or a display module having a novel semiconductor device. Alternatively, according to one aspect of the present invention, it is possible to provide a display device having a novel semiconductor device or an electronic device using a display module. Alternatively, according to one aspect of the present invention, it is possible to provide a display device having a novel semiconductor device or a system having a display module.

Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device having reduced power consumption, a display device having the semiconductor device, or a display module having the semiconductor device. Alternatively, according to one aspect of the present invention, it is possible to provide a display device or a display module having excellent visibility. Alternatively, according to one aspect of the present invention, it is possible to provide a display device or a display module having good display quality.

The effect of one aspect of the present invention is not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from the description in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

The block diagram which shows an example of the semiconductor device. The block diagram which shows an example of the circuit which a semiconductor device has. The circuit diagram which shows the specific example of FIG. The circuit diagram which shows the specific example of FIG. The circuit diagram which shows the specific example of FIG. The block diagram which shows an example of the circuit which a semiconductor device has. The circuit diagram which shows the specific example of FIG. The circuit diagram which shows the specific example of FIG. The circuit diagram which shows the specific example of FIG. The circuit diagram which shows the specific example of FIG. The circuit diagram which shows the specific example of FIG. A circuit diagram showing an example of a buffer amplifier. A circuit diagram showing an example of a display device. A circuit diagram showing an example of display pixels. A circuit diagram showing an example of display pixels. A block diagram and a circuit diagram showing an example of a display device. The block diagram which shows an example of the semiconductor device. A circuit diagram and a timing chart showing an example of a touch sensor. The figure which shows an example of the display device. The figure which shows an example of the display device. The perspective view which shows an example of a display module. The perspective view which shows an example of the electronic device. The perspective view which shows an example of the electronic device. Top view and sectional view showing a configuration example of a transistor. Top view and sectional view showing a configuration example of a transistor. Top view and sectional view showing a configuration example of a transistor. The figure explaining the range of the atomic number ratio of an oxide. The figure explaining the crystal of InMZnO ₄ . Band diagram in a laminated structure of oxides. Top view and sectional view showing a configuration example of a transistor. Top view and sectional view showing a configuration example of a transistor. The figure explaining the structural analysis of CAAC-OS and a single crystal oxide semiconductor by XRD, and the figure which shows the selected area electron diffraction pattern of CAAC-OS. A cross-sectional TEM image of CAAC-OS, a planar TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. The figure which shows the change of the crystal part by electron irradiation of In—Ga—Zn oxide.

The description of "electronic device", "electronic component", "module", and "semiconductor device" will be described. Generally, "electronic equipment" means, for example, personal computers, mobile phones, tablet terminals, electronic book terminals, wearable terminals, AV equipment (AV; Audio Visual), electrical appliances, housing equipment, commercial equipment, and the like. It may refer to digital signage, automobiles, or electrical products having a system. Further, the "electronic component" or "module" is a processor, a storage device, a sensor, a battery, a display device, a light emitting device, an interface device, an RF tag (RF; Radio Frequency), a receiving device, and a transmitting device of the electronic device. And so on. Further, the "semiconductor device" is a device using a semiconductor element, or a drive circuit, a control circuit, a logic circuit, a signal generation circuit, a signal conversion circuit, and a potential level conversion to which a semiconductor element is applied, which is possessed by an electronic component or a module. It may refer to a circuit, a voltage source, a current source, a switching circuit, an amplification circuit, a storage circuit, a memory cell, a display circuit, a display pixel, or the like.

Further, in this specification, an oxide semiconductor may be referred to as an OS (Oxide Semiconductor). Therefore, a transistor having an oxide semiconductor in the channel forming region may be referred to as an OS transistor.

(Embodiment 1)
In this embodiment, the source driver circuit and the bias generator included in the source driver circuit will be described.

<Source driver circuit>
FIG. 1 shows an example of a source driver circuit according to one aspect of the present invention. The source driver circuit 100 includes an LVDS receiver 110 (Low Voltage Differential Signaling), a serial-parallel conversion circuit 120, a shift register circuit 130, a latch circuit 140, a level shifter circuit 150, a pass transistor logic circuit 160, and a resistance string circuit 170. It has an external correction circuit 180, a BGR circuit 190 (Band Gap Reference), a bias generator 200, and a buffer amplifier 300. In FIG. 1, the source driver circuit 100 has two bias generators 200.

The LVDS receiver 110 is electrically connected to an external host processor. The LVDS receiver 110 has a function of receiving a video signal from the host processor and a function of converting a differential signal into a single-ended signal and transmitting the signal to the serial-parallel conversion circuit 120. It is assumed that the above-mentioned operation is performed when the LVDS receiver 110 is in the driving state. In FIG. 1, as video signals, analog voltage signals DA, DB0, analog voltage signals DA, DB1, analog voltage signals DA, DB2, analog voltage signals DA, DB3, analog voltage signals DA, DB4, analog voltage signals DA, DB5, The analog voltage signals DA and DB6 and the analog voltage signals DA and DB7 are input to the LVDS receiver 110. The LVDS receiver 110 is sequentially operated by the input of the clock signal CLOCK and the clock signal CLOCKB, and the LVDS receiver 110 is changed from the drive state to the standby state (pause) by the standby signal STBY. can. The clock signal CLOCKB is an inverted signal of the clock signal CLOCK.

The serial-parallel conversion circuit 120 is electrically connected to the LVDS receiver 110. The serial-parallel conversion circuit 120 has a function of receiving a single-ended signal from the LVDS receiver 110. The serial-parallel conversion circuit 120 converts a single-ended signal into a parallel signal and transmits it to the internal bus as a BUS [127: 0] signal.

The shift register circuit 130 is electrically connected to the serial-parallel conversion circuit 120, and the latch circuit 140 is electrically connected to the shift register circuit 130. The shift register circuit 130 has a function of specifying a timing for storing data on the internal bus in the latch circuit 140 of each signal line (also referred to as a data line) in synchronization with the serial-parallel conversion circuit 120.

The level shifter circuit 150 is electrically connected to the latch circuit 140. The level shifter circuit 150 has a function of level-shifting the data of all the signal lines when the data of all the signal lines is stored in the latch circuit 140.

The pass transistor logic circuit 160 is electrically connected to the level shifter circuit 150 and the resistance string circuit 170. A DAC (Digital to Analog Converter) is configured by a pass transistor logic circuit 160 and a resistance string circuit 170. An 8-bit signal (described as VR0-VR255 in FIG. 1) is input to the resistance string circuit 170, and the potential corresponding to the signal is output to the pass transistor logic circuit 160. The path transistor logic circuit 160 has a function of digital-to-analog conversion of each level-shifted data by supplying the potential.

The buffer amplifier 300 is electrically connected to the pass transistor logic circuit 160. The buffer amplifier 300 has a function of amplifying the digital-to-analog converted data and transmitting the amplified data as a data signal (described as S [2159: 0] in FIG. 1) to the pixel array.

The BGR circuit 190 has a function of generating a reference voltage for driving the source driver circuit 100. The BGR circuit 190 is electrically connected to each of one and the other of the bias generators.

One of the bias generators 200 is electrically connected to the BGR circuit 190 and the buffer amplifier 300. One of the bias generators 200 has a function of generating a bias voltage for operating the buffer amplifier 300 from a reference voltage generated by the BGR circuit 190. Further, it is assumed that this operation is performed when the bias generator 200 is in the driving state. A standby signal STBY is input to one of the bias generators 200 at the same timing as the LVDS receiver 110, and one of the bias generators 200 can be changed from the drive state to the standby state (pause) by this signal.

The other side of the bias generator 200 is electrically connected to the external correction circuit 180. The other side of the bias generator 200 has a function of generating a bias voltage for operating the external correction circuit 180 from the reference voltage generated by the BGR circuit 190. When it is not necessary to operate the external correction circuit 180, a standby signal CMSTBY is transmitted to the other side of the bias generator 200, and this signal causes the other side of the bias generator 200 to change from the drive state to the standby state (pause). )be able to.

The external correction circuit 180 is electrically connected to a transistor included in the pixel. In the pixel array, if there is a variation in the voltage-current characteristics of each pixel transistor, it affects the image displayed on the display device, which causes a deterioration in the display quality of the display device. The external correction circuit 180 has a function of measuring the amount of current flowing through the pixel transistor and adjusting the amount of current flowing through the pixel transistor according to the amount of current. A set signal CMSET is input to the external correction circuit 180, and the external correction circuit 180 is initialized by this signal. Further, a clock signal CMCLK is input to the external correction circuit 180, and the external correction circuit 180 operates by this signal. Further, a signal from a transistor included in the pixel circuit (described as S [719: 0] in FIG. 1) is input to the external correction circuit 180, and the reference potential VREF1 and the reference potential VREF2 are compared by the external correction circuit 180. Judgment regarding image correction as a reference is made. CMOUT [11: 0] is transmitted to an image processor outside the source driver circuit 100 as an output signal of the determination result regarding the correction. The image processor corrects the video data based on the content of CMOUT [11: 0].

Note that one aspect of the present invention is not limited to the source driver circuit 100 shown in FIG. 1, and may not be configured to have an external correction circuit 180. For example, instead of the external correction circuit 180, a correction circuit may be provided for each pixel of the pixel array.

<Bias generator 200A>
Next, the circuit configuration of the bias generator 200 applicable to the source driver circuit 100 of FIG. 1 will be described.

FIG. 2 shows a bias generator according to one aspect of the present invention. The bias generator 200A has a circuit 201 and a circuit 202.

Circuit 201 is electrically connected to circuit 202 by one or more wiring VRLs. Further, the circuit 201 is electrically connected to the wiring L0. Further, the circuit 201 is electrically connected to the wiring GNDL that gives a low level potential.

The circuit 202 is electrically connected to a plurality of wiring VBLs. Further, the circuit 202 is electrically connected to the wiring VDDL that gives a high level potential. Further, the circuit 202 is electrically connected to the wiring GNDL that gives a low level potential.

The circuit 201 has a function of generating a potential corresponding to the current and outputting the potential by supplying a current from the wiring L0. The potential is generated for the number of wiring VRLs and applied to the wiring VRLs. When there are a plurality of wiring VRLs, the potential applied to the wiring VRL is assumed to be a different value for each wiring VRL.

The circuit 202 has a function of generating and outputting a plurality of bias voltages by the potential applied to the wiring VRL, the high level potential given by the wiring VDDL, and the low level potential given by the wiring GNDL. The bias voltage is generated for the number of wiring VBLs and applied to the wiring VBLs. The bias voltage applied to the wiring VBL is assumed to be a different value for each wiring VBL.

The wiring VBL is electrically connected to the buffer amplifier 300 or the external correction circuit 180, and the bias voltage generated by the circuit 202 is applied to the buffer amplifier 300 or the external correction circuit 180.

Each bias voltage is a potential equal to or higher than the low level potential given by the wiring GNDL and lower than or lower than the high level potential given by the wiring VDDL.

The current given from the wiring L0 is a constant current output from the BGR circuit 190.

<< Specific Example 1 >>
Here, an example of a specific circuit for realizing the bias generator 200A is shown in FIG. 3 as the bias generator 200A1.

The circuit 201 has a transistor RT1 and a transistor RT2, and the circuit 202 includes a transistor Tr [1,1], a transistor Tr [2,1], a transistor Tr [3,1], and a transistor Tr [4,1]. ], Transistor Tr [1,2], Transistor Tr [2,2], Transistor Tr [3,2], Transistor Tr [4,2], Transistor Tr [1,3], Transistor Tr. [2,3], Transistor Tr [3,3], Transistor Tr [4,3], Transistor Tr [1,4], Transistor Tr [2,4], Transistor Tr [3,4] And the transistor Tr [4,4]. The transistor Tr [1,1], the transistor Tr [1,2], the transistor Tr [1,3], the transistor Tr [1,4], the transistor Tr [2,1], and the transistor Tr [ 2,2], the transistor Tr [2,3], and the transistor Tr [2,4] are p-channel transistors, and the transistor Tr [3,1] and the transistor Tr [3,2] , Transistor Tr [3,3], Transistor Tr [3,4], Transistor Tr [4,1], Transistor Tr [4,2], Transistor Tr [4,3], Transistor Tr [4] , 4] are n-channel transistors. Further, it is assumed that the wiring VRL is composed of the wiring VRL1 and the wiring VRL2 as a plurality of wirings. Further, it is assumed that the wiring VBL is composed of wiring L1 to wiring L4 as a plurality of wirings.

The internal connection configuration of the circuit 201 will be described. The first terminal of the transistor RT1 is electrically connected to the wiring L0, the gate of the transistor RT1 is electrically connected to the wiring L0, and the first terminal of the transistor RT1 is electrically connected to the wiring VRL1. The first terminal of the transistor RT2 is electrically connected to the second terminal of the transistor RT1, the gate of the transistor RT2 is electrically connected to the first terminal of the transistor RT2, and the second terminal of the transistor RT2 is a wiring GNDL. The first terminal of the transistor RT2 is electrically connected to the wiring VRL2.

That is, the transistor RT1 and the transistor RT2 are respectively diode-connected. When the potential of the wiring L0 is higher than the low level potential, the current from the wiring L0 flows to the wiring GNDL via the transistor RT1 and the transistor RT2.

The internal connection configuration of the circuit 202 will be described. The first terminal of the transistor Tr [1, j] (j is an integer of 1 or more and 4 or less) is electrically connected to the wiring VDDL. The second terminal of the transistor Tr [1, j] is electrically connected to the first terminal of the transistor Tr [2, j], and the second terminal of the transistor Tr [2, j] is the transistor Tr [3, j]. ], The second terminal of the transistor Tr [3, j] is electrically connected to the first terminal of the transistor Tr [4, j]. Further, the connection portion between the second terminal of the transistor Tr [2,1] and the first terminal of the transistor Tr [3,1] is designated as a node N1, and the second terminal of the transistor Tr [2,2] and the transistor Tr are connected. The connection part with the first terminal of [3,2] is referred to as a node N2, and the connection part between the second terminal of the transistor Tr [2,3] and the first terminal of the transistor Tr [3,3] is referred to as a node N3. The connection portion between the second terminal of the transistor Tr [2,4] and the first terminal of the transistor Tr [3,4] is referred to as a node N4.

The second terminal of the transistor Tr [4, j] is electrically connected to the wiring GNDL. The gate of the transistor Tr [3,1] and the gate of the transistor Tr [3,2] are electrically connected to the wiring VRL1, and the gate of the transistor Tr [4,1] and the gate of the transistor Tr [4,2] are , Electrically connected to the wiring VRL2.

The node N1 is electrically connected to the gate of the transistor Tr [1,1], each gate of the transistor Tr [2,1] to the transistor Tr [2,4], and the wiring L3, and the node N2 is connected to the wiring L3. , Each gate of the transistor Tr [1, 2] to the transistor Tr [1, 4] is electrically connected to the wiring L4. The node N3 is electrically connected to the gate of the transistor Tr [4,3] and the wiring L1, and the node N4 is the gate of the transistor Tr [3,3] and the gate of the transistor Tr [3,4]. And the wiring L2 are electrically connected to each other.

<< Operation example >>
Next, the operation of the bias generator 200A1 will be described.

When the bias generator 200A1 operates, the potential Va is applied from the BGR circuit 190 via the wiring L0. As a result, in the circuit 201, the current I _REF is assumed to flow from the wiring L0 to the wiring GNDL via the transistor RT1 and the transistor RT2. At this time, it is assumed that the potential applied to the second terminal of the transistor RT2 is Vb. That is, the potential Vb is a potential larger than the low level potential and smaller than the potential Va.

The potential Va is applied to the gate of the transistor Tr [3,1] and the gate of the transistor Tr [3,2] via the wiring VRL1. Further, the potential Vb is applied to the gate of the transistor Tr [4,1] and the gate of the transistor Tr [4,2] via the wiring VRL2. As a result, the transistor Tr [3,1], the transistor Tr [3,2], the transistor Tr [4,1], and the transistor Tr [4,2] are in a conductive state. Therefore, since a current flows from the node N1 to the wiring GNDL via the transistor Tr [3,1] and the transistor Tr [4,1], a potential higher than the low level potential is generated in the node N1. Similarly, since a current flows from the node N2 to the wiring GNDL via the transistor Tr [3,2] and the transistor Tr [4,2], a potential higher than the low level potential is generated in the node N2.

Here, the potential of the node N1 is applied to the gate of the transistor Tr [1,1] and the gate of the transistor Tr [2,1] to the transistor Tr [2,4]. Therefore, the transistor Tr [1,1] and the transistor Tr [2,1] are in a conductive state, and a current is applied from the wiring VDDL to the node N1 via the transistor Tr [1,1] and the transistor Tr [2,1]. Flows. Since the transistor Tr [3,1] and the transistor Tr [4,1] are also in a conductive state, as a result, the potential of the node N1 converges to a constant potential _VBIAS3 over time, and from the wiring L3. V _{BIAS 3} is output.

Further, the potential of the node N2 becomes equal to the potential of each gate of the transistor Tr [1, 2] to the transistor Tr [1, 4], and in addition, the potential of the transistor Tr [1, 2] to the transistor Tr [1, 4] is equal to the potential of each gate. ], Since the potential of each first terminal is a high level potential, when the sizes of the transistors Tr [1, 2] to the transistors Tr [1, 4] are the same, the currents flowing through the respective transistors are the same. Further, the potentials of the second terminals of the transistors Tr [1, 2] to the transistors Tr [1, 4] are also equal to each other.

Further, the potential of the node N1 becomes equal to the potential of each gate of the transistor Tr [2,2] to the transistor Tr [2,4]. Since the potentials of the first terminals of the transistors Tr [2,2] to the transistors Tr [2,4] are equal to each other, if the sizes of the transistors Tr [2,2] to the transistors Tr [2,4] are the same, the transistors The currents flowing through each of the Tr [2,2] to the transistor Tr [2,4] are equal, and the potentials of the second terminals of the transistors Tr [2,2] to the transistor Tr [2,4] are temporary to each other. Is equal to. Since the transistor Tr [3,2] and the transistor Tr [4,2] are also in a conductive state, the potential of the node N2 converges to a constant potential _VBIAS4 over time, and the wiring L4 to _VBIAS4 It is output.

Further, as described above, since the transistor Tr [1,4] and the transistor Tr [2,4] are in a conductive state due to the potentials of the node N1 and the node N2, the transistor Tr [1,4] and the transistor are connected from the wiring VDDL. A current flows through the node N4 via the Tr [2,4]. Therefore, a potential lower than the high level potential is generated in the node N4. Since the potential of the node N4 is applied to the gate of the transistor Tr [3,4] and the gate of the transistor Tr [4,4], the transistor Tr [3,4] and the transistor Tr [4,4] are in a conductive state. Then, a current flows from the node N4 to the wiring GNDL via the transistor Tr [3,4] and the transistor Tr [4,4]. As a result, the potential of the node N4 converges to a constant potential V _BIAS2 over time, and V _BIAS2 is output from the wiring L2.

Further, as described above, since the transistor Tr [1,3] and the transistor Tr [2,3] are in a conductive state due to the potentials of the node N1 and the node N2, the transistor Tr [1,3] and the transistor are connected from the wiring VDDL. A current flows through the node N3 via the Tr [2,3]. Therefore, a potential lower than the high level potential is generated in the node N3. Since the potential of the gate of the transistor Tr [3,4] becomes equal to that of the node N3, the transistor Tr [3,4] is in a conductive state. In addition, since the potential of the gate of the transistor Tr [3,3] is equal to the potential of the node N4, the transistor Tr [3,3] is in a conductive state like the transistor Tr [3,4]. Therefore, a current flows from the node N3 to the wiring GNDL via the transistor Tr [3,3] and the transistor Tr [4,3]. As a result, the potential of the node N3 converges to a constant potential V _BIAS1 over time, and V _BIAS1 is output from the wiring L1.

The bias generator _200A1 generates V _BIAS1 , V _BIAS 2, V BIAS 3 and V _BIAS 4 as bias voltages based on the above principle, and outputs them to the wiring L1 to the wiring L4.

<< Specific Example 2 >>
Further, the configuration of the bias generator is not limited to the configuration of the bias generator 200A1 of FIG. 3, and may be another circuit configuration. For example, FIG. 4 shows a bias generator different from the bias generator 200A1. The bias generator 200A2 has a configuration in which one transistor is further added to the circuit 201 of the bias generator 200A1 and the number of transistors is further increased to the circuit 202 of the bias generator 200A1.

In the bias generator 200A2 of FIG. 4, the circuit 201 has a transistor RT1, a transistor RT2, and a transistor RT3. Further, the circuit 202 has a transistor Tr [1,1] to a transistor Tr [6,6]. In the transistor shown in FIG. 4, the reference numerals of the transistor RT1, the transistor RT2, the transistor RT3, the transistor Tr [1,1], and the transistor Tr [6,6] are described, and the reference numerals of the other transistors are omitted. is doing. Further, it is assumed that the wiring VRL is composed of wiring VRL1, wiring VRL2, and wiring VRL3 as a plurality of wirings. Further, it is assumed that the wiring VBL is composed of wiring L1, wiring L2, wiring L3, wiring L4, wiring L5, and wiring L6 as a plurality of wirings.

With such a circuit configuration, the bias generator 200A2 can generate a bias voltage and output it to the wiring L1 to the wiring L6 in the same manner as the bias generator 200A1.

Further, when it is desired to increase or decrease the number of output terminals of the bias voltage, the number of transistors included in the circuit 201 and the circuit 202 may be changed and configured as described above, similarly to the bias generator 200A1 and the bias generator 200A2. For example, the bias generator 200A when the number of transistors of the circuit 201 is k (k is an integer of 1 or more) is shown in FIG. 5 as the bias generator 200A3. In this case, the number of transistors constituting the circuit 202 is 4k ² , and the number of output terminals of the bias voltage (the number of wiring VBLs) can be (2 × k). In FIG. 5, the transistors constituting the circuit 201 are the transistors RT [1] to the transistors RT [k], and the transistors constituting the circuit 202 are the transistors Tr [1,1] to the transistors Tr [2k, 2k]. The plurality of wiring VBLs are the wiring L [1] to the wiring L [2k].

In the bias generator 200A3 of FIG. 5, the circuit 201, the circuit 202, the plurality of wiring VRLs (wiring VRL [1], wiring VRL [i] (i is an integer of 1 or more and k or less), wiring VRL [k]). Multiple wiring VBLs (wiring L [1], wiring L [i ₁ ] (i ₁ is an integer of 1 or more and k or less), wiring L [k], wiring L [k + 1], wiring L [i ₂ ] (i ₂ ) Is an integer of k + 1 or more and 2k or less), wiring L [2k]), wiring L0, wiring GNDL, wiring VDDL, transistor RT [1], transistor RT [i], transistor RT [k], transistor Tr [1,1]. , Transistor Tr [2k, 2k] is described only, and other wiring, symbols, and codes are omitted.

<Bias generator 200B>
When displaying a still image on the display device, the operation of the buffer amplifier 300 included in the source driver circuit 100 may be temporarily stopped. For example, when an OS transistor is applied to the transistor of each pixel of the display device, the OS transistor exhibits good switching characteristics and has a very low off-current property, so that the written data signal is lengthened. It can be held for a long time (details will be described later in the second embodiment). In particular, when the same image is displayed continuously for two or more frames such as a still image, by using this principle, the data signal of the same content is not always transmitted to the pixel circuit and is held by the pixel circuit. Images can be displayed by the data signal. That is, since it is not necessary to transmit the data signal to the pixel circuit, the power consumption of the display device can be reduced.

When the bias generator 200 is in the driving state, the bias generator 200 supplies a bias voltage to the buffer amplifier 300. When the display device is in the driving state, that is, when an image such as a moving image is displayed on the display device, the buffer amplifier 300 and the bias generator are used to transmit the data signal to the pixel circuit at a high driving frequency (for example, a frequency of 60 Hz or higher). The 200 is always in the driving state. Therefore, the power consumption of the buffer amplifier 300 and the bias generator 200 tends to be high. On the other hand, when displaying a still image on the display device, it is not necessary to rewrite the image, so that the display device can operate at a low drive frequency (for example, a frequency less than 60 Hz). When the display device is operated at a low drive frequency, the number of rewrites is smaller than when the display device is operated at a high drive frequency, so that there is a period during which the data of the display image is not rewritten. The power consumption of the display device can be reduced by putting the buffer amplifier 300 and the bias generator 200 in the standby state (pausing) during the period when the image data is not rewritten. Such an operation of putting (pausing) a drive circuit such as a buffer amplifier 300 or a bias generator 200 into a standby state (pause) when it is not necessary may be referred to as an idling stop (IDS) drive.

Here, a configuration that can put the bias generator 200 in the standby state will be described. FIG. 6 shows a configuration in which the bias generator 200 can be put into the standby state. The bias generator 200B has a configuration in which circuits 203 to 205 are provided on the bias generator 200A.

The bias generator 200B has a configuration in which a circuit 203 is provided between the circuit 201 and the circuit 202 of the bias generator 200A. That is, the circuit 201 is electrically connected to the circuit 202 via the circuit 203. Further, in the bias generator 200B, a circuit 204 is provided between the circuit 202 of the bias generator 200A and a part of the plurality of wiring VBLs, and the circuit 202 of the bias generator 200A and the remaining wiring of the plurality of wirings VBL are connected to each other. A circuit 205 is provided between them. That is, the circuit 202 is electrically connected to a part of the plurality of wiring VBLs via the circuit 204, and the circuit 202 is electrically connected to the remaining wirings of the plurality of wiring VBLs via the circuit 205. Has been done.

A specific connection configuration will be described. The circuit 201 is electrically connected to the circuit 203 by one or more wiring VRLas. Further, the circuit 201 is electrically connected to the wiring L0. Further, the circuit 201 is electrically connected to the wiring GNDL that gives a low level potential.

The circuit 202 is electrically connected to the circuit 203 by one or more wiring VRLbs. Further, the circuit 203 is electrically connected to the wiring GNDL that gives a low level potential, and the circuit 203 is electrically connected to the wiring STBYL.

The number of wirings of the wiring VRLa is the same as the number of wirings of the wiring VRLb.

Circuit 202 is electrically connected to one or more wiring VBLs. Further, the circuit 202 is electrically connected to the wiring VDDL that gives a high level potential. Further, the circuit 202 is electrically connected to the wiring GNDL that gives a low level potential. Further, the circuit 204 is electrically connected to the circuit 202, and the circuit 205 is electrically connected to the circuit 202.

The circuit 204 is electrically connected to the wiring STBYL-B, and the circuit 204 is electrically connected to the wiring VDDL that gives a high level potential. The wiring STBYL-B may be configured such that an inverted signal of an input signal to the wiring STBYL is input.

The circuit 205 is electrically connected to the wiring STBYL, and the circuit 205 is electrically connected to the wiring GNDL that gives a low level potential.

For the detailed functions of the circuit 201 and the circuit 202, the description of the circuit 201 and the circuit 202 described in the bias generator 200A will be referred to.

The circuit 203 has a function of outputting either the potential of the wiring VRLa or the low level potential to the wiring VRLb, and determines the potential applied to the wiring VRLb by the potential given from the wiring STBYL.

The circuit 204 has a function of applying a high level potential to a part of the wiring of the wiring VBL, and it is possible to determine whether or not the function is operated by the potential given from the wiring STBYL-B. Specifically, when the bias generator 200 is in the drive state, a predetermined bias voltage is output from the wiring VBL electrically connected to the circuit 204, and when the bias generator 200 is in the standby state, the circuit 204 A high level potential is output from the wiring VBL electrically connected to.

The circuit 205 has a function of applying a low level potential to all the remaining wirings of the wiring VBL, and it is possible to determine whether or not the function is operated by the potential given from the wiring STBYL. Specifically, when the bias generator 200 is in the driving state, a predetermined bias voltage is output from the wiring VBL electrically connected to the circuit 205, and when the bias generator 200 is in the standby state, the circuit 205 A low level potential is output from the wiring VBL electrically connected to.

With such a circuit configuration, it is possible to realize a bias generator that can put the operation into a standby state (pause) when the data signal does not need to be rewritten.

<< Specific Example 1 >>
Here, an example of a specific circuit for realizing the bias generator 200B is shown in FIG. 7 as the bias generator 200B1.

The bias generator 200B1 has a configuration in which the circuit 203, the circuit 204, and the circuit 205 are incorporated in the bias generator 200A1. Therefore, the description regarding the content different from the bias generator 200A1 will be described, and the description regarding the same content as the bias generator 200A1 will be omitted.

Note that the bias generator 200B1 of FIG. 7 has a configuration in which the circuit 202 and the circuit 205 are provided in the circuit 202, unlike the bias generator 200B shown in FIG. Since the circuit 204 and the circuit 205 may be electrically connected to a plurality of wiring VBLs, the circuit 204 and the circuit 205 may be provided inside the circuit 202. That is, one aspect of the present invention is not limited to the configuration of the bias generator 200B shown in FIG. 6, and if the same effect as that of the bias generator 200 can be obtained, the configuration of the bias generator 200B shown in FIG. 6 is used. It may be changed as appropriate.

The circuit 203 has the transistor ST11 and the transistor ST12, the circuit 204 has the transistor ST21 and the transistor ST22, and the circuit 205 has the transistor ST31 and the transistor ST32.

It is assumed that the wiring VRLa is composed of the wiring VRLa1 and the wiring VRLa2 as a plurality of wirings. It is assumed that the wiring VRLb is composed of a wiring VRLb1 and a wiring VRLb2 as a plurality of wirings.

The first terminal of the transistor RT1 of the circuit 201 of the bias generator 200B1 is electrically connected to the wiring VRLa1, and the first terminal of the transistor RT2 of the circuit 201 of the bias generator 200B1 is electrically connected to the wiring VRLa2. There is.

The internal connection configuration of the circuit 203 will be described. The first terminal of the transistor ST11 is electrically connected to the wiring VRLa1 and the wiring VRLb1, the gate of the transistor ST11 is electrically connected to the wiring STBYL, and the second terminal of the transistor ST11 is electrically connected to the wiring GNDL. Is connected. The first terminal of the transistor ST12 is electrically connected to the wiring VRLa2 and the wiring VRLb2, the gate of the transistor ST12 is electrically connected to the wiring STBYL, and the second terminal of the transistor ST12 is electrically connected to the wiring GNDL. Is connected.

The gate of the transistor Tr [3,1] of the circuit 202 of the bias generator 200B1 is electrically connected to the wiring VRLb1, and the gate of the transistor Tr [3,2] of the circuit 202 of the bias generator 200B1 is electrically connected to the wiring VRLb1. It is connected to the. The gate of the transistor Tr [4,1] of the circuit 202 of the bias generator 200B1 is electrically connected to the wiring VRLb2, and the gate of the transistor Tr [4,2] of the circuit 202 of the bias generator 200B1 is electrically connected to the wiring VRLb2. It is connected to the.

The internal connection configuration of the circuit 204 will be described. The first terminal of the transistor ST21 is electrically connected to the wiring VDDL, the gate of the transistor ST21 is electrically connected to the wiring STBYL-B, and the second terminal of the transistor ST21 is electrically connected to the wiring L4. ing. The first terminal of the transistor ST22 is electrically connected to the wiring VDDL, the gate of the transistor ST22 is electrically connected to the wiring STBYL-B, and the second terminal of the transistor ST22 is electrically connected to the wiring L3. ing.

The internal connection configuration of the circuit 205 will be described. The first terminal of the transistor ST31 is electrically connected to the wiring GNDL, the gate of the transistor ST31 is electrically connected to the wiring STBYL, and the second terminal of the transistor ST31 is electrically connected to the wiring L2. .. The first terminal of the transistor ST32 is electrically connected to the wiring GNDL, the gate of the transistor ST32 is electrically connected to the wiring STBYL, and the second terminal of the transistor ST32 is electrically connected to the wiring L1. ..

<< Operation example >>
Next, an operation example of the bias generator 200B1 will be described. Since the bias generator 200B1 performs almost the same operation as the bias generator 200A1, the same operation as the bias generator 200A1 of the bias generator 200B1 refers to the description of the operation example of the bias generator 200A1, and here, the circuits 203 to The function and operation due to the incorporation of the circuit 205 will be described.

As described above, when the display device is displaying a still image, the operation of the buffer amplifier 300 and the operation of the bias generator 200 are put into a standby state (pause) to reduce the power consumption of the display device. be able to. The bias generator 200B1 has a circuit configuration in which the operation of the bias generator 200B1 can be put into a standby state (pause) by the operation of the circuits 203 to 205.

The bias generator 200B1 can be in either the drive state or the standby state (pause) by applying an appropriate potential to the wiring STBYL and the wiring STBYL-B.

A high level potential is input to one of the wiring STBYL and the wiring STBYL-B, and a low level potential is input to the other of the wiring STBYL and the wiring STBYL-B. The high level potential here is a potential sufficiently high to make each of the transistor ST11, the transistor ST12, the transistor ST31, and the transistor ST32 in a conductive state, and the low level potential here is a transistor. It is assumed that the potentials are sufficiently low to make each of ST21 and the transistor ST22 conductive.

When operating the bias generator 200B1, a low level potential is applied to the wiring STBYL and a high level potential is applied to the wiring STBYL-B. As a result, the transistor ST11, the transistor ST12, the transistor ST21, the transistor ST22, the transistor ST31, and the transistor ST32 can be brought into a non-conducting state. That is, the bias generator 200B1 can perform the same operation as the bias generator 200A1 by applying a low level potential to the wiring STBYL and applying a high level potential to the wiring STBYL-B.

When the bias generator 200B1 is put into the standby state (pause), a high level potential is applied to the wiring STBYL and a low level potential is applied to the wiring STBYL-B. As a result, the transistor ST11, the transistor ST12, the transistor ST21, the transistor ST22, the transistor ST31, and the transistor ST32 can be brought into a conductive state. That is, the potentials of the wiring L0, the wiring VRLa1, the wiring VRLa2, the wiring VRLb1, the wiring VRLb2, the wiring L1, and the wiring L2 can be set to low level potentials, and the potentials of the wiring L3 and the wiring L4 can be set to high level potentials.

Therefore, in the circuit 201, the transistor RT1 and the transistor RT2 are in a non-conducting state, so that the potential Va and the potential Vb are not generated by the current I _REF supplied from the BGR circuit 190. Further, in the circuit 202, all of the transistors Tr [1,1] to the transistors Tr [4,4] are in a non-conducting state, so that the bias voltages V _BIAS1 , V _BIAS 2, V BIAS ₃ , and V _{BIAS 4} are not generated. Then, depending on the circuit configuration of the circuit 204 and the circuit 205, the low level potential is output to the wiring L1 and the wiring L2, and the high level potential is output to the wiring L3 and the wiring L4.

By applying the high level potential to the wiring STBYL and applying the low level potential to the wiring STBYL-B in this way, the bias generator 200B1 can be put into a standby state (pause). Further, by applying the low level potential output from the wiring L1 and the wiring L2 and the high level potential output from the wiring L3 and the wiring L4 to the buffer amplifier 300, the buffer amplifier 300 is also put into the standby state. The buffer amplifier 300 may be configured so that it can be (paused).

<< Specific Example 2 >>
Further, the configuration of the bias generator is not limited to the configuration of the bias generator 200B1 of FIG. 7, and may be another circuit configuration. For example, FIG. 8 shows a bias generator different from the bias generator 200B1. The bias generator 200B2 is a circuit in which the position of the circuit 203 of the bias generator 200B1 is changed, and the circuit 203 is electrically connected to the circuit 202 via the circuit 201. That is, since the electrical connection configuration of the bias generator 200B2 is the same as that of the bias generator 200B1, the bias generator 200B2 can operate in the same manner as the bias generator 200B1 and can be put into a standby state (pause).

Further, for example, the circuit 203 of the bias generator 200B1 may be provided inside the circuit 202. The configuration is shown in FIG. The bias generator 200B3 has a configuration in which circuits 203 to 205 that put the bias generator 200B3 into an operating state and a standby state (pause state) are provided inside the circuit 202. Since the electrical connection configuration of the bias generator 200B3 is the same as that of the bias generator 200B1, the bias generator 200B3 can be put into an operating state and a standby state (pause state) in the same manner as the bias generator 200B1.

Further, for example, the bias generator 200A3 may be provided with the circuits 203 to 205. The configuration is shown in FIG. The bias generator 200B4 inserts the circuit 203 into the electrical connection path between the circuit 201 and the circuit 202 of the bias generator 200A3, and electrically connects the circuit 202 of the bias generator 200A3 to the wiring L [k + 1] to the wiring L [2k]. The circuit 204 is inserted in the path, and the circuit 205 is inserted in the electrical connection path between the circuit 202 of the bias generator 200A3 and the wiring L [1] to the wiring L [k]. With such a configuration, it is possible to realize the bias generator 200 in which the number of output terminals of the bias voltage (the number of wiring VBLs) is (2 × k). In FIG. 10, the transistors constituting the circuit 201 are the transistors RT [1] to the transistors RT [k], and the transistors constituting the circuit 202 are the transistors Tr [1,1] to the transistors Tr [2k, 2k]. The transistor constituting the circuit 203 is the transistor ST1 [1] to the transistor ST1 [k], and the transistor constituting the circuit 204 is the transistor ST2 [1] to the transistor ST2 [k]. Is the transistor ST3 [1] to the transistor ST3 [k], and the plurality of wiring VBLs are the wiring L [1] to the wiring L [2k].

In the bias generator 200B4 of FIG. 10, the circuit 201, the circuit 202, the circuit 203, the circuit 204, the circuit 205, the plurality of wiring VRL1, the plurality of wiring VRL2, the plurality of wiring VBL, the wiring L [1], and the wiring L [i]. ₁ ], wiring L [k], wiring L [k + 1], wiring L [i ₂ ], wiring L [2k], wiring L0, wiring GNDL, wiring VDDL, wiring STBYL, wiring STBYL-B, transistor RT [1] , Transistor RT [i], Transistor RT [k], Transistor Tr [1,1], Transistor Tr [2k, 2k], Transistor ST1 [1], Transistor ST1 [i], Transistor ST1 [k], Transistor ST2 [ 1], Transistor ST2 [i], Transistor ST2 [k], Transistor ST3 [1], Transistor ST3 [i], Transistor ST3 [k] are described, and other wiring, symbols, and symbols are omitted. There is. Further, the reference numerals of the wiring GNDL electrically connected to the second terminals of the transistors ST1 [1] to the transistors ST1 [k] of the circuit 203 are omitted, and the transistors ST3 [1] to the transistors of the circuit 205 are omitted. The code of the wiring GNDL electrically connected to each first terminal of ST3 [k] is omitted.

Further, for example, in the bias generator 200B1 to the bias generator 200B4, at least one of the transistors constituting the circuit 203 and the circuit 205 may be an OS transistor. The OS transistor has very excellent switching characteristics and has a characteristic that the off-current is extremely small. When the bias generator 200B is operating, the transistors of the circuit 203 and the circuit 205 are in a non-conducting state, but by applying an OS transistor to the transistor, the leakage current of the non-conducting transistor can be reduced. It can be extremely small. Therefore, by using an OS transistor, a bias generator with stable operation can be realized.

Further, for example, in the bias generator 200B1 to the bias generator 200B4, when at least one of the transistors constituting the circuit 203 and the circuit 205 is an OS transistor, the OS transistor has a back gate in addition to the front gate. There may be. An example of the configuration of the bias generator 200B in that case is shown in FIG. The bias generator 200B5 replaces the transistor ST1 [1] to the transistor ST1 [k] included in the circuit 203 of the bias generator 200B4 with the transistor STB1 [1] to the transistor STB1 [k], and replaces the transistor ST3 [k] included in the circuit 205 of the bias generator 200B4. 1] to the transistor ST1 [k] are replaced with the transistor STB3 [1] to the transistor STB3 [k]. In FIG. 11, as the transistor included in the circuit 203, only the transistor STB1 [1], the transistor STB1 [i], and the transistor STB1 [k] are shown, and the other transistors are omitted. Further, in FIG. 11, as the transistor included in the circuit 205, only the transistor STB3 [1], the transistor STB3 [i], and the transistor STB3 [k] are shown, and the other transistors are omitted.

Each back gate of the transistor STB1 [1] to the transistor STB1 [k] is electrically connected to a plurality of wirings BGLS1. Each back gate of the transistor STB3 [1] to the transistor STB3 [k] is electrically connected to a plurality of wirings BGLS2. For other connection configurations, refer to the description of the bias generator 200B4.

The OS transistor having a back gate has a function of controlling the threshold voltage of the OS transistor by applying an arbitrary potential to the back gate. Therefore, by applying a positive potential to the back gate to bring the OS transistor into a normally-on state, a larger current can flow and the operation of the bias generator can be accelerated. Further, by applying a negative potential to the back gate, the OS transistor can be put into a non-conducting state (hereinafter, may be referred to as a normally off state). By utilizing this, it is possible to control the conduction state and the non-conduction state of the OS transistor by applying an arbitrary potential not only to the front gate but also to the back gate. As the OS transistor having a back gate, it is preferable to apply the transistor described in the seventh embodiment.

<Buffer amplifier>
Here, the configuration of the buffer amplifier 300 driven by using the output voltage of the bias generator 200 described above will be described.

<< Configuration example >>
FIG. 12 shows an example of a buffer amplifier 300 that operates using the output voltage of either the bias generator 200B1 or the bias generator 200B3. In the following description of the buffer amplifier 300, it is assumed that it is electrically connected to the bias generator 200B1.

The buffer amplifier 300 is a circuit having an input terminal IN and an output terminal OUT, and outputs a potential obtained by adding a potential ΔV to the potential input to the input terminal IN to the output terminal OUT. The input terminal IN is electrically connected to the pass transistor logic circuit 160, and a data signal (potential) digitally and analog-converted by the pass transistor logic circuit 160 and the resistance string circuit 170 is applied to the input terminal IN. The potential ΔV, which will be described later, is determined by the bias voltage input to the buffer amplifier 300.

The wirings L1 to L4 connected to the buffer amplifier 300 are wirings electrically connected to the bias generator 200B1. That is, the bias voltages V _BIAS1 , V _BIAS 2, V BIAS 3, and V _BIAS 4 generated by the bias generator _200B1 are input to the buffer amplifier 300 via the wiring L1 to the wiring L4, respectively.

The wiring LA1 and the wiring LA2 connected to the buffer amplifier 300 are wirings electrically connected to a bias generator different from the bias generator 200B1. That is, different bias voltages are input to the wiring LA1 and the wiring LA2 as in the wiring L1 to the wiring L4.

The input of the bias voltage is not limited to the method of using two bias generators, and a method of using one bias generator may be used. For example, the bias voltage may be input to the wiring L1 to the wiring L4, the wiring LA1, and the wiring LA2 by using only the bias generator 200B4 in which the value of k is 3.

The buffer amplifier 300 has a transistor AT1 to a transistor AT20, a transistor AST1, and a transistor AST2.

The input terminal IN is electrically connected to the gate of the transistor AT1 and the gate of the transistor AT3. The first terminal of the transistor AT1 is electrically connected to the first terminal of the transistor AT2 and the first terminal of the transistor AT5, and the second terminal of the transistor AT1 is the first terminal of the transistor AT13 and the transistor AT14. It is electrically connected to the first terminal. The first terminal of the transistor AT3 is electrically connected to the first terminal of the transistor AT4 and the first terminal of the transistor AT6, and the second terminal of the transistor AT3 is the first terminal of the transistor AT9 and the first terminal of the transistor AT10. It is electrically connected to the first terminal. The second terminal of the transistor AT5 is electrically connected to the wiring GNDL, and the gate of the transistor AT5 is electrically connected to the wiring L1. The second terminal of the transistor AT6 is electrically connected to the wiring VDDL, and the gate of the transistor AT6 is electrically connected to the wiring L4. The second terminal of the transistor AT2 is electrically connected to the first terminal of the transistor AT11 and the first terminal of the transistor AT12. The second terminal of the transistor AT4 is electrically connected to the first terminal of the transistor AT7 and the first terminal of the transistor AT8. The gate of the transistor AT2 and the gate of the transistor AT4 are electrically connected to the output terminal OUT.

The second terminal of the transistor AT7 is electrically connected to the wiring GNDL, the second terminal of the transistor AT9 is electrically connected to the wiring GNDL, and the second terminal of the transistor AT11 is electrically connected to the wiring VDDL. The second terminal of the transistor AT13 is electrically connected to the wiring VDDL. The gate of the transistor AT8 and the gate of the transistor AT10 are electrically connected to the wiring L2, and the gate of the transistor AT12 and the gate of the transistor AT14 are electrically connected to the wiring L3. The first terminal of the transistor AT15 is electrically connected to the first terminal of the transistor AT17, the second terminal of the transistor AT8, the gate of the transistor AT7, and the gate of the transistor AT9. The second terminal of the transistor AT15 is electrically connected to the second terminal of the transistor AT17, the second terminal of the transistor AT12, the gate of the transistor AT11, and the gate of the transistor AT13. The gate of the transistor AT15 and the gate of the transistor AT16 are electrically connected to the wiring LA1, and the gate of the transistor AT17 and the gate of the transistor AT18 are electrically connected to the wiring LA2.

The second terminal of the transistor AT10 is electrically connected to the first terminal of the transistor AT16, the first terminal of the transistor AT18, the gate of the transistor AT19, and the first terminal of the transistor AST1. The second terminal of the transistor AT14 is electrically connected to the second terminal of the transistor AT16, the second terminal of the transistor AT18, the gate of the transistor AT20, and the first terminal of the transistor AST2. The gate of the transistor AST1 is electrically connected to the wiring STBYL, and the gate of the transistor AST2 is electrically connected to the wiring STBYL-B.

The buffer amplifier 300 shown in FIG. 12 can be put into a standby state (pause) while displaying a still image on the display device. To put the buffer amplifier 300 in the standby state (pause), the bias generator 200B1 supplies a low level potential to the wiring L1, a low level potential to the wiring L2, a high level potential to the wiring L3, and a high level potential to the wiring L4. Then, a low level potential may be supplied to the wiring LA1 and a high level potential may be supplied to the wiring LA2. In particular, in order to give a predetermined potential to each of the wiring L1 to the wiring L4, the potential of the wiring STBYL may be set to a high level potential and the potential of the wiring STBYL-B may be set to a low level potential in the bias generator 200B1. At this time, at the same time, a high level potential is applied to the gate of the transistor AST1 and a low level potential is applied to the gate of the transistor AST2. Therefore, a high level potential is applied to the gate of the transistor AT19 and a low level potential is applied to the gate of the transistor AT20. Is applied. Therefore, since the transistor AT19 and the transistor AT20 are in a non-conducting state, the potential is not output to the output terminal OUT. Further, since the transistor AST1 and the transistor AST2 are in a conductive state, the electric charge charged in the gate of the transistor AT19 and the gate of the transistor AT20 can be discharged.

By configuring such a bias generator and a buffer amplifier, it is possible to realize a display device with reduced power consumption.

It should be noted that one aspect of the present invention can be appropriately combined with other embodiments shown in the present specification.

(Embodiment 2)
In the present embodiment, the display device having the semiconductor device of one aspect of the present invention will be described with reference to FIGS. 13 to 16.

FIG. 13A is a block diagram illustrating an example of a display device according to an aspect of the present invention, and FIG. 13B is a circuit illustrating an example of a pixel circuit included in the display device according to an aspect of the present invention. It is a figure. The display device of FIG. 13 is a display device using a light emitting element such as an organic EL.

<Explanation of display device>
The display device shown in FIG. 13A has a region having pixels of a display element (hereinafter referred to as a pixel unit 3302) and a circuit unit (hereinafter referred to as a circuit unit) arranged outside the pixel unit 3302 and having a circuit for driving the pixels. , Drive circuit unit 3304), a circuit having an element protection function (hereinafter referred to as protection circuit 3306), and a terminal unit 3307. The protection circuit 3306 may not be provided.

It is desirable that a part or all of the drive circuit unit 3304 is formed on the same substrate as the pixel unit 3302. This makes it possible to reduce the number of parts and the number of terminals. When a part or all of the drive circuit unit 3304 is not formed on the same substrate as the pixel unit 3302, a part or all of the drive circuit unit 3304 is subjected to COG or TAB (Tape Implemented Bonding). Can be implemented.

The pixel unit 3302 has a circuit (hereinafter referred to as a pixel circuit 3301) for driving a plurality of display elements arranged in the X row (X is a natural number of 2 or more) and the Y column (Y is a natural number of 2 or more). The drive circuit unit 3304 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver circuit 3304a), and a circuit for supplying a signal (data signal) for driving a display element of the pixel. It has a drive circuit such as (hereinafter, source driver circuit 3304b). As the source driver circuit 3304b, the source driver circuit 100 described in the first embodiment can be applied. As a result, in the display device shown in FIG. 13A, the buffer amplifier and the bias generator included in the source driver circuit 3304b can be put into a standby state (pause) while the still image is being displayed. The power consumption of the display device can be reduced.

The gate driver circuit 3304a has a shift register and the like. The gate driver circuit 3304a receives a signal for driving the shift register via the terminal portion 3307 and outputs the signal. For example, the gate driver circuit 3304a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver circuit 3304a shows wiring to which a scanning signal is given (hereinafter referred to as scanning lines GL_1 to GL_X. In FIG. 13A, scanning lines GL_1, scanning lines GL_2, and scanning lines GL_X are shown, and scanning lines other than these are shown. It is omitted. Further, it has a function of controlling the potential of the scanning lines GL_1 to GL_X, which may be collectively referred to as the scanning line GL). A plurality of gate driver circuits 3304a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate driver circuits 3304a. Alternatively, the gate driver circuit 3304a has a function of being able to supply an initialization signal. However, the present invention is not limited to this, and the gate driver circuit 3304a can also supply another signal.

The source driver circuit 3304b has a shift register and the like. In the source driver circuit 3304b, a signal (image signal) that is the source of the data signal is input in addition to the signal for driving the shift register via the terminal portion 3307. The source driver circuit 3304b has a function of generating a data signal to be written in the pixel circuit 3301 based on the image signal. Further, the source driver circuit 3304b has a function of controlling the output of a data signal according to a pulse signal obtained by inputting a start pulse signal, a clock signal, or the like. Further, the source driver circuit 3304b shows wiring to which a data signal is given (hereinafter referred to as data lines DL_1 to DL_Y; in FIG. 13A, data lines DL_1, data lines DL_2, and data lines DL_Y are shown, and data other than these are shown. The line is omitted. Further, the data lines DL_1 to DL_Y may be collectively referred to as a data line DL). Alternatively, the source driver circuit 3304b has a function of being able to supply an initialization signal. However, the present invention is not limited to this, and the source driver circuit 3304b can also supply another signal.

The source driver circuit 3304b is configured by using, for example, a plurality of analog switches. The source driver circuit 3304b can output a time-division signal of an image signal as a data signal by sequentially turning on a plurality of analog switches. Further, the source driver circuit 3304b may be configured by using a shift register or the like.

In each of the plurality of pixel circuits 3301, the pulse signal is input via one of the plurality of scanning lines GL to which the scanning signal is given, and the data signal is transmitted through one of the plurality of data line DLs to which the data signal is given. Entered. Further, in each of the plurality of pixel circuits 3301, the writing and holding of the data of the data signal is controlled by the gate driver circuit 3304a. For example, in the pixel circuit 3301 in the mth row and nth column, a pulse signal is input from the gate driver circuit 3304a via the scanning line GL_m (m is a natural number of X or less), and the data line DL_n (m is a natural number of X or less) is input according to the potential of the scanning line GL_m. A data signal is input from the source driver circuit 3304b via n) (a natural number equal to or less than Y).

The protection circuit 3306 shown in FIG. 13A is connected to, for example, a scanning line GL which is a wiring between the gate driver circuit 3304a and the pixel circuit 3301. Alternatively, the protection circuit 3306 is connected to the data line DL which is the wiring between the source driver circuit 3304b and the pixel circuit 3301. Alternatively, the protection circuit 3306 can be connected to the wiring between the gate driver circuit 3304a and the terminal portion 3307. Alternatively, the protection circuit 3306 can be connected to the wiring between the source driver circuit 3304b and the terminal portion 3307. The terminal portion 3307 is a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 3306 is a circuit that makes the wiring and another wiring in a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 3306 is connected.

As shown in FIG. 13A, by providing the protection circuit 3306 in the pixel unit 3302 and the drive circuit unit 3304, respectively, the resistance of the display device to the overcurrent generated by ESD (Electrostatic Discharge) or the like is enhanced. be able to. However, the configuration of the protection circuit 3306 is not limited to this, and for example, the configuration may be such that the protection circuit 3306 is connected to the gate driver circuit 3304a or the protection circuit 3306 is connected to the source driver circuit 3304b. Alternatively, the protection circuit 3306 may be connected to the terminal portion 3307.

Further, FIG. 13A shows an example in which the drive circuit unit 3304 is formed by the gate driver circuit 3304a and the source driver circuit 3304b, but the configuration is not limited to this. For example, a configuration may be configured in which only the gate driver circuit 3304a is formed and a substrate on which a separately prepared source driver circuit is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted. ..

<Pixel circuit configuration example>
The plurality of pixel circuits 3301 shown in FIG. 13 (A) can be configured as shown in FIG. 13 (B), for example.

The pixel circuit 3301 shown in FIG. 13B includes a transistor 3352, a transistor 3354, a capacitive element 3362, and a light emitting element 3372.

One of the source electrode and the drain electrode of the transistor 3352 is electrically connected to a wiring (hereinafter referred to as a data line DL_n) to which a data signal is given. Further, the gate electrode of the transistor 3352 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is given.

The transistor 3352 has a function of controlling the writing of data of the data signal.

One of the pair of electrodes of the capacitive element 3362 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 3352. Will be done.

The capacitive element 3362 has a function as a holding capacitance for holding the written data.

One of the source electrode and the drain electrode of the transistor 3354 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 3354 is electrically connected to the other of the source electrode and the drain electrode of the transistor 3352.

One of the anode and cathode of the light emitting device 3372 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 3354.

One of the potential supply line VL_a and the potential supply line VL_b is given a high power supply potential VDD, and the other is given a low power supply potential VSS.

In the display device having the pixel circuit 3301 of FIG. 13 (B), for example, the pixel circuit 3301 of each row is sequentially selected by the gate driver circuit 3304a shown in FIG. 13 (A), the transistor 3352 is turned on, and the data of the data signal is displayed. To write.

The pixel circuit 3301 to which the data is written is put into a holding state when the transistor 3352 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 3354 is controlled according to the potential of the written data signal, and the light emitting element 3372 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

It is preferable to apply the OS transistor described in the seventh embodiment to the transistor 3352 and the transistor 3354 shown in FIG. 13B. Since the OS transistor exhibits good switching characteristics and has a very low off-current property, the leakage current between the source and drain of the transistor can be reduced. For example, by applying an OS transistor to the transistor 3352, the leakage current of the transistor 3352 can be reduced, and the potential of the gate of the transistor 3354 and the potential of the other of the pair of electrodes of the capacitive element 3362 can be held for a long time. can. That is, when displaying a moving image in which the data signal does not change continuously for two or more frames, that is, a still image, it is not necessary to rewrite the potential of the gate of the transistor 3354 and the potential of the other of the pair of electrodes of the capacitive element 3362. Therefore, since the supply of the data signal to the pixel circuit 3301 can be stopped for a long time, the power consumption of the display device can be reduced.

Further, the pixel circuit may be provided with a function of correcting the influence of fluctuations such as the threshold voltage of the transistor. 14 (A) (B) and 15 (A) (B) show an example of a pixel circuit.

The pixel circuit shown in FIG. 14A has six transistors (transistor 3431, transistor 3432, transistor 3433, transistor 3434, transistor 3435, transistor 3436), a capacitive element 3440, and a light emitting element 3450. Further, in the pixel circuit shown in FIG. 14A, wiring 3411, wiring 3412, wiring 3413, wiring 3414, wiring 3415, and wiring 3421 and wiring 3422 are electrically connected. As the transistor 3431 to 3436, for example, a p-type transistor can be used.

The pixel circuit shown in FIG. 14B has a configuration in which a transistor 3437 is added to the pixel circuit shown in FIG. 14A. Further, the wiring 3416 and the wiring 3417 are electrically connected to the pixel circuit shown in FIG. 14B. Here, the wiring 3415 and the wiring 3416 may be electrically connected to each other. As the transistor 3437, for example, a p-type transistor can be used.

The pixel circuit shown in FIG. 15A has six transistors (transistor 3481, transistor 3482, transistor 3484, transistor 3484, transistor 3485, transistor 3486), a capacitive element 3440, and a light emitting element 3450. Further, wiring 3461, wiring 3462, wiring 3464, wiring 3471, wiring 3472, and wiring 3473 are electrically connected to the pixel circuit shown in FIG. 15A. Here, the wiring 3461 and the wiring 3436 may be electrically connected to each other. As for the transistor 3481 to the transistor 3486, for example, a p-type transistor can be used.

The pixel circuit shown in FIG. 15B has two transistors (transistor 3491 and transistor 3492), two capacitive elements (capacitive element 3441 and capacitive element 3442), and a light emitting element 3450. Further, the wiring 3511, the wiring 3512, the wiring 3513, the wiring 3521, and the wiring 3522 are electrically connected to the pixel circuit shown in FIG. 15B. Further, by adopting the configuration of the pixel circuit shown in FIG. 15B, for example, a voltage input-current drive system (also referred to as a CVCC system) can be adopted. For the transistor 3491 and the transistor 3492, for example, a p-type transistor can be used.

Further, the light emitting element according to one aspect of the present invention can be applied to each of an active matrix method in which the pixels of the display device have an active element and a passive matrix method in which the pixels of the display device do not have an active element. can.

In the active matrix method, not only a transistor but also various active elements (active element, non-linear element) can be used as the active element (active element, non-linear element). For example, MIM (Metal Insulator Metal), TFD (Thin Film Diode), or the like can also be used. Since these elements have few manufacturing processes, it is possible to reduce the manufacturing cost or improve the yield. Alternatively, since these elements have a small size, the aperture ratio can be improved, and low power consumption and high brightness can be achieved.

As a method other than the active matrix method, it is also possible to use a passive matrix type that does not use an active element (active element, non-linear element). Since no active element (active element, non-linear element) is used, the number of manufacturing processes is small, so that the manufacturing cost can be reduced or the yield can be improved. Alternatively, since an active element (active element, non-linear element) is not used, the aperture ratio can be improved, and low power consumption or high brightness can be achieved.

Further, one aspect of the present invention is not limited to the display device having a light emitting element shown in FIGS. 13 to 15. For example, a display device using a display element such as a liquid crystal display instead of the light emitting element may be used. FIG. 16 shows an example of a display device using a liquid crystal display as a display element.

In the liquid crystal display device 3600 shown in FIG. 16A, the pixel unit 3610, the scanning line driving circuit 3620, and the signal line driving circuit 3630 are arranged in parallel or substantially parallel to each other, and are provided by the scanning line driving circuit 3620. It has m scanning lines 3621 whose potential is controlled, and n signal lines 3631 which are arranged in parallel or substantially parallel to each other and whose potential is controlled by a signal line driving circuit 3630. Both m and n are integers of 1 or more. Further, the pixel unit 3610 has a plurality of pixels 3611 arranged in a matrix. Also, along the scanning lines 3621, each has a capacitive wiring 3622 arranged in parallel or substantially parallel. Further, the scanning line drive circuit 3620 and the signal line drive circuit 3630 may be collectively referred to as a drive circuit unit. As the signal line drive circuit 3630, the source driver circuit 100 described in the first embodiment can be applied. As a result, in the display device shown in FIG. 13A, the buffer amplifier and the bias generator included in the signal line drive circuit 3630 can be put into a standby state (pause) while the still image is being displayed. , The power consumption of the display device can be reduced.

Each scanning line 3621 is electrically connected to n pixels 3611 arranged in any of the pixels 3611 arranged in m rows and n columns in the pixel unit 3610. Further, each signal line 3631 is electrically connected to m pixels 3611 arranged in any of the pixels 3611 arranged in m rows and n columns. Further, each capacitive wiring 3622 is electrically connected to n pixels 3611 arranged in any of the pixels 3611 arranged in m rows and n columns.

16 (B) shows an example of a circuit configuration that can be used for the pixel 3611 of the liquid crystal display device 3600 shown in FIG. 16 (A).

The pixel 3611 shown in FIG. 16B includes a liquid crystal element 3643, a transistor 3641, and a capacitive element 3642.

One of the pair of electrodes of the liquid crystal element 3643 is connected to the transistor 3641, and the potential is appropriately set according to the specifications of the pixel 3611. The other of the pair of electrodes of the liquid crystal element 3634 is connected to a common line, and a common potential (common potential) is given to each pixel. The alignment state of the liquid crystal of the liquid crystal element 3643 is controlled by the data written in the transistor 3461.

The liquid crystal element 3643 is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used for the liquid crystal element 3643, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal and the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like depending on the conditions.

Further, when the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response rate and is optically isotropic. Further, the liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent does not require an orientation treatment and has a small viewing angle dependence. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. ..

As a driving method of the liquid crystal display device 3600 having a liquid crystal element 3643, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, and an ASM (Axially Cymetrically named) mode are used. , OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric Liquid Crystal) mode and the like can be used.

Further, as a driving method of the liquid crystal display device 3600 having the liquid crystal element 3643, a vertical orientation mode such as an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, and an ASV mode can be used.

In the configuration of the pixel 3611 shown in FIG. 16B, one of the source electrode and the drain electrode of the transistor 3641 is electrically connected to the signal line 3631 and the other is electrically connected to one of the pair of electrodes of the liquid crystal element 3643. Be connected. Further, the gate electrode of the transistor 3461 is electrically connected to the scanning line 3621. The transistor 3641 has a function of controlling the writing of data of the data signal.

In the configuration of the pixel 3611 shown in FIG. 16B, one of the pair of electrodes of the capacitive element 3642 is connected to the other of the source electrode and the drain electrode of the transistor 3461. The other of the pair of electrodes of the capacitive element 3642 is electrically connected to the capacitive wiring 3622. The potential value of the capacitive wiring 3622 is appropriately set according to the specifications of the pixel 3611. The capacitive element 3642 has a function as a holding capacitance for holding the written data.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 3)
In the present embodiment, the source driver circuit 100 described in the first embodiment, the drive circuit for the touch sensor, and the display device with the touch sensor formed by one IC will be described.

FIG. 17 is a circuit block diagram showing a configuration example of the display device 3800 according to one aspect of the present invention. The display device 3800 includes a display unit 3811, a touch sensor 3814, a scanning line drive circuit 3813, ICs 3820_1 to 3820_m (m is an integer of 2 or more), and a host 3816.

<Display unit>
The display unit 3811 has a plurality of pixels 3812 arranged in a matrix, a plurality of scanning lines GL, and a plurality of signal lines SL, and has a function of displaying an image.

The display unit 3811 can display an image by controlling the light emission / non-light emission of the pixel 3812. For the pixel 3812, for example, a liquid crystal element can be used. In addition to this, the pixel 3812 includes an EL (electroluminescence) element (EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element) and an LED chip (white LED chip, red LED chip, green LED chip, blue color). LED chips, etc.), transistors (transists that emit light according to current), electron emitting elements, display elements using carbon nanotubes, electronic ink, electrowetting elements, electrophoresis elements, MEMS (micro electro mechanical system) Display elements using (for example, light emitting light bulb (GLV), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interferrometric modulation) element, shutter method. (MEMS display element, optical interference type MEMS display element, piezoelectric ceramic display unit, etc.), or at least one such as a quantum dot can be used.

The display unit 3811 has an extremely high number of pixels such as HD (number of pixels 1280 × 720), FHD (number of pixels 1920 × 1080), WQHD (number of pixels 2560 × 1440), WQXGA (number of pixels 2560 × 1600), 4K, 8K. It is preferable to have it. In particular, the number of pixels is preferably 4K, 8K, or more. The pixel density (definition) of the pixels provided on the display unit 3811 is 300 ppi or more, preferably 500 ppi or more, more preferably 800 ppi or more, more preferably 1000 ppi or more, and more preferably 1200 ppi or more. The display unit 3811 having such a high number of pixels and high definition makes it possible to further enhance the sense of presence and depth in personal use such as portable type and home use.

<Scanning line drive circuit>
The scan line drive circuit 3813 is electrically connected to the pixel 3812 via the scan line GL. The scanning line drive circuit 3813 has a function of outputting a scanning signal to the scanning line GL. The scanning line drive circuit 3813 may be referred to as a gate driver.

<IC>
The IC3820 is a plurality of (m) IC chips (hereinafter referred to as ICs), and is preferably composed of IC3820_1 to 3820_m. Further, it is preferable that each IC is mounted on a substrate by a COG (Chip on Glass) method.

For example, consider the case where the IC 3820 is composed of one IC. As the resolution of the display unit 3811 increases as in 4K or 8K, the occupied area of the IC also increases. ICs that occupy a large area are difficult to manufacture and expensive. Further, when the IC is crimped to the substrate by the COG method, there is an optimum pressure per terminal of the IC. When the display unit 3811 has a high number of pixels such as 4K or 8K, the number of terminals of the IC is also very large, and the load applied to the entire IC during crimping is also large. As a result, cracks or the like occur in the IC, making it difficult to mount the IC. By configuring the IC 3820 with a plurality of ICs, the load applied to one IC is reduced, and the mounting of the IC becomes easy.

The IC 3820_1 includes a circuit 3821_1, a signal line drive circuit 3822_1, a touch sensor drive circuit 3823, and a touch sensor detection circuit 3824. The IC3820_m has a circuit 3821_m and a signal line drive circuit 3822_m. In the following, the IC 3820_1 to 3820_m may be collectively referred to as an IC 3820, and the signal line drive circuits 3822_1 to 3822_m may be collectively referred to as a signal line drive circuit 3822. As for the IC3820 shown in FIG. 17, only the IC3820_1, the IC3820_2, and the IC3820_m are described, and the other IC3820 is omitted. Further, in the signal line drive circuit 3822 shown in FIG. 17, only the signal line drive circuit 3822_1, the signal line drive circuit 3822_2, and the signal line drive circuit 3822_m are described, and the other signal line drive circuits 3822 are omitted.

The IC3820 may be provided by a mounting method such as a COF (Chip On Film) method or a TAB (Tape Automated Bonding) method.

<< Signal line drive circuit >>
The signal line drive circuit 3822 has a function of outputting a video signal (also referred to as a video signal) to the display unit 3811. The signal line drive circuit 3822 is electrically connected to the pixel 3812 via the signal line SL. The signal line drive circuit 3822 has a function of outputting a video signal, which is an analog signal, to the pixels 3812 of the display unit 3811 via the signal line SL. For example, the signal line drive circuit 3822 may have a configuration in which a shift register circuit and a buffer circuit are combined. Further, the display device 3800 may have a demultiplexer circuit connected to the signal line SL. The signal line drive circuit 3822 may be called a source driver. As the signal line drive circuit 3822, the source driver circuit 100 described in the first embodiment can be applied. As a result, while the still image is being displayed on the display device 3800, the buffer amplifier and bias generator of the signal line drive circuit 3822 can be put into a standby state (pause), and the display device is consumed. Power can be reduced.

<< Touch sensor drive circuit >>
The touch sensor drive circuit 3823 is electrically connected to the touch sensor 3814 via the wiring CLx. The touch sensor drive circuit 3823 has a function of outputting a signal for driving the sensor element of the touch sensor 3814. As the touch sensor drive circuit 3823, for example, a configuration in which a shift register circuit and a buffer circuit are combined can be used.

<< Touch sensor detection circuit >>
The touch sensor detection circuit 3824 is electrically connected to the touch sensor 3814 via the wiring CLI. The touch sensor detection circuit 3824 has a function of outputting an output signal from the sensor element of the touch sensor 3814 to the circuit 3821_1. For example, as the touch sensor detection circuit 3824, a configuration having an amplifier circuit and an analog-to-digital converter (ADC: Analog to Digital Converter) can be used. The touch sensor detection circuit 3824 converts the analog signal output from the touch sensor 3814 into a digital signal and outputs it to the circuit 3821_1.

In FIG. 17, the IC 3820_1 is connected to the pixel 3812 existing at the end of the display unit 3811, but the IC 3820_1 is not limited to this, and the IC 3820_1 is connected to the pixel 3812 existing in the center of the display unit 3811 or at another place. It may be connected.

<< Image processing circuit, RAM >>
The circuit 3821_1 has an image processing circuit 3825_1 and a RAM 3826_1. Similarly, the circuit 3821_m has an image processing circuit 3825_m and a RAM 3826_m. In the following, the circuits 3821_1 to 3821_m may be collectively referred to as a circuit 3821, the image processing circuits 3825_1 to 3825_m may be collectively referred to as an image processing circuit 3825, and the RAMs 3826_1 to 3826_m may be collectively referred to as a RAM 3826. .. In the circuit 3821 shown in FIG. 17, only the circuit 3821_1, the circuit 3821_2, and the circuit 3821_m are described, and the other circuits 3821 are omitted. Further, in the image processing circuit 3825 shown in FIG. 17, only the image processing circuit 3825_1, the image processing circuit 3825_2, and the image processing circuit 3825_m are described, and the other image processing circuits 3825 are omitted. Further, in the RAM 3826 shown in FIG. 17, only the RAM 3826_1, the RAM 3826_2, and the RAM 3826_m are described, and the other RAM 3826 is omitted.

The image processing circuit 3825 has a function of generating a video signal according to a command from the host 3816. Further, the image processing circuit 3825 has a function of performing signal processing on the video signal according to the specifications of the display unit 3811, converting it into an analog video signal, and supplying it to the signal line drive circuit 3822. Further, the image processing circuit 3825_1 has a function of generating a drive signal to be output to the touch sensor drive circuit 3823 in accordance with a command from the host 3816. Further, the image processing circuit 3825_1 has a function of analyzing the signal input from the touch sensor detection circuit 3824 and outputting it to the host 3816 as position information.

The RAM 3826 has a function of holding data necessary for the image processing circuit 3825 to perform processing.

The image processing circuit 3825 may be configured to include, for example, a processor. For example, other microprocessors such as DSP (Digital Signal Processor) and GPU (Graphics Processing Unit) can be used. Further, these microprocessors may be configured by PLD (Programmable Logic Device) such as FPGA (Field Programmable Gate Array) or FPGA (Field Programmable Analog Array). Various data processing and program control are performed by interpreting and executing instructions from various programs by a processor.

<Host>
The host 3816 has a CPU 3827 and a timing controller 3828. In the present specification, the host 3816 may be referred to as an external circuit.

<< Timing controller >>
The timing controller 3828 is input with various synchronization signals that determine the timing of rewriting of the display unit 3811. Examples of the synchronization signal include a horizontal synchronization signal, a vertical synchronization signal, a reference clock signal, and the like, and the timing controller 3828 uses the scanning line drive circuit 3813, the signal line drive circuit 3822, and the touch sensor drive circuit 3823 based on these signals. Generates a control signal for. Further, the timing controller 3828 may have a function of generating a signal that defines the timing at which the touch sensor detection circuit 3824 outputs a signal. Here, it is preferable that the timing controller 3828 outputs a signal synchronized with the signal output to the scanning line drive circuit 3813 and the signal output to the touch sensor drive circuit 3823, respectively. In particular, it is preferable to separate the period for rewriting the data of the display unit 3811 and the period for sensing with the touch sensor 3814. For example, the display device 3800 can be driven by dividing the one-frame period into a period for rewriting the data of the display unit 3811 and a period for sensing. Further, for example, by providing two or more sensing periods in one frame period, it is possible to improve the detection sensitivity and the detection accuracy.

<< CPU >>
The CPU 3827 has a function for executing instructions and controlling the display device 3800 in an integrated manner. The instructions executed by the CPU 3827 are instructions input from the outside and instructions stored in the internal memory. The CPU 3827 generates a signal for controlling the timing controller 3828 and the image processing circuit 3825.

By including the timing controller 3828 in the host 3816, it is not necessary to include the timing controller in the IC 3820. Therefore, it is possible to reduce the occupied area of the IC. In addition, the price of the IC can be kept low. Further, it becomes possible to control the timing of a plurality of ICs with one timing controller. The above configuration is preferable for the display device 3800 having a plurality of ICs.

<Touch sensor>
The touch sensor 3814 has a plurality of sensor elements for detecting the contact or proximity of the detected object to the display device 3800. As a touch sensor method that can be used for the touch sensor 3814, for example, a capacitance method can be applied. As the capacitance method, there are a surface type capacitance method, a projection type capacitance method and the like. Further, as the projection type capacitance method, there are a self-capacitance method, a mutual capacitance method and the like. It is preferable to use the mutual capacitance method because simultaneous multipoint detection is possible.

Not limited to this, various types of sensors capable of detecting the proximity or contact of the object to be detected such as a finger or a stylus can be applied to the touch sensor 3814. For example, as the sensor method, various methods such as a resistance film method, a surface acoustic wave method, an infrared method, and an optical method can be used in addition to the capacitance method.

<< An example of a touch sensor >>
FIG. 18A is a block diagram showing a configuration example when a mutual capacitance type touch sensor is used as an example of the touch sensor 3814. In FIG. 18A, as an example, the wiring CLx to which the pulse voltage is applied is shown as 6 wirings of X1 to X6, and the wiring CLy for detecting the change in current is shown as 6 wirings of Y1 to Y6. The number of wirings is not limited to this. Further, FIG. 18A illustrates a capacitive element 3829 formed by superimposing wiring CLx and wiring CLy or arranging wiring CLx and wiring CLy in close proximity to each other.

As an example, the touch sensor drive circuit 3823 is a circuit for applying a pulse voltage to the wirings of X1 to X6 in order. By applying a pulse voltage to the wirings of X1 to X6, an electric field is generated between the wiring CLx and the wiring CLy forming the capacitive element 3829. Then, a current flows through the capacitive element 3829 due to the pulse voltage. The electric field generated between the electrodes changes due to shielding by touching with a finger or a pen. That is, the capacitance value of the capacitive element 3829 changes due to the touch of a finger, a pen, or the like. In this way, it is possible to detect the proximity or contact of the object to be detected by utilizing the fact that the capacitance value is changed by the touch of a finger or a pen.

The touch sensor detection circuit 3824 is a circuit for detecting a change in the current in the wirings of Y1 to Y6 due to a change in the capacitance value in the capacitance element 3829. In the wiring of Y1 to Y6, the current value detected when there is no proximity or contact with the detected object does not change, but the current value decreases when the capacitance value decreases due to the proximity or contact of the detected object to be detected. Detect changes to be made. The current may be detected by detecting the total amount of current. In that case, the detection may be performed using an integrator circuit or the like. Alternatively, the peak value of the current may be detected. In that case, the current may be converted into a voltage to detect the peak value of the voltage value.

Next, FIG. 18B shows a timing chart of the input / output waveform in the touch sensor 3814 shown in FIG. 18A. In FIG. 18B, it is assumed that the detected object is detected in each matrix in one frame period. Further, FIG. 18B shows two cases, a case where the detected object is not detected (non-touch) and a case where the detected object is detected (touch). The wiring of Y1 to Y6 shows a waveform having a voltage value corresponding to the detected current value. It is desirable that the timing of the display operation on the display unit 3811 and the timing of the touch sensor 3814 operate in synchronization with each other, but in FIG. 18B, in order to simplify the explanation, the timing of the display operation is synchronized with the display operation. Here is an example of the case where it is not.

A pulse voltage is sequentially applied to the wirings of X1 to X6, and the waveform in the wirings of Y1 to Y6 changes according to the pulse voltage. When there is no proximity or contact with the object to be detected, the waveforms of Y1 to Y6 change uniformly according to the change in the voltage of the wiring of X1 to X6. On the other hand, since the current value decreases at the location where the object to be detected is close to or in contact with the object to be detected, the corresponding voltage value waveform also changes.

By detecting the change in the capacitance value in this way, it is possible to detect the proximity or contact of the object to be detected. It should be noted that the detected object such as a finger or a pen may not come into contact with the touch sensor or the display device, and the signal may be detected even when the object is close to the touch sensor or the display device.

Further, although FIG. 18A shows the configuration of a passive matrix type touch sensor in which only the capacitance element 3829 is provided at the intersection of the wirings as the touch sensor, it can also be used as an active matrix type touch sensor having a transistor and a capacitance. good.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, as application examples using the semiconductor device described in the above-described embodiment, an example of applying the display panel to a display module, an example of applying the display panel to a display module, an application example of the display module, and an electron. An example of application to the device will be described with reference to FIGS. 19 to 21.

<Implementation example on display panel>
An example of applying a semiconductor device functioning as a source driver IC to a display panel will be described with reference to FIGS. 19A and 19B.

In the case of FIG. 19A, the source driver 3712 and the gate drivers 3712A and 3712B are provided around the display unit 3711 of the display panel, and the source driver IC 3714 having the semiconductor device on the substrate 3713 is provided as the source driver 3712. An example of implementation is shown.

The source driver IC 3714 is mounted on the substrate 3713 using an anisotropic conductive adhesive and an anisotropic conductive film.

The source driver IC3714 is connected to the external circuit board 3716 via the FPC3715.

In the case of FIG. 19B, a source driver 3712 and gate drivers 3712A and 3712B are provided around the display unit 3711, and an example in which the source driver IC 3714 is mounted on the FPC 3715 as the source driver 3712 is shown.

By mounting the source driver IC 3714 on the FPC 3715, the display unit 3711 can be provided large on the substrate 3713, and a narrow frame can be achieved.

Further, one aspect of the present invention is not limited to FIGS. 19A and 19B, and a touch sensor may be mounted on the display panel of FIGS. 19A and 19B. That is, the display device 3800 described in the third embodiment may be configured.

FIG. 20 shows a display panel in which a touch sensor is mounted on the display panels of FIGS. 19A and 19B. The display device of FIG. 20A is a display panel in which a touch sensor is mounted on the display panel of FIG. 19A, and the input unit 3717 of the touch sensor is attached to the display surface side of the display unit 3711. It has become. Further, the display device of FIG. 20B is a display panel in which a touch sensor is mounted on the display panel of FIG. 19B, and the input unit 3717 of the touch sensor is attached to the display surface side of the display unit 3711. It has a structure like that. In FIGS. 20A and 20B, a part of the input unit 3717 is omitted. Therefore, it is assumed that the input unit 3717 exists even in an area where the input unit 3717 is not shown on the display surface side of the display unit 3711.

The source driver IC3714 included in the display panels of FIGS. 20A and 20B may be IC3820-1 to IC3830_m described in the third embodiment. With such a configuration, the drive circuit of the touch sensor and the source driver can be collectively formed as one IC, and FIGS. 20A and 20B have the touch sensor as an interface. It can be a display panel.

<Application example of display module>
Next, an application example of the display module using the display panels of FIGS. 19A and 19B will be described with reference to FIG. 21.

The display module 4000 shown in FIG. 21 has a touch panel 4004 connected to the FPC 4003, a display panel 4006 connected to the FPC 4005, a frame 4009, a printed circuit board 4010, and a battery 4011 between the upper cover 4001 and the lower cover 4002. The battery 4011, the touch panel 4004, and the like may not be provided.

The display panels described in FIGS. 19 (A), 19 (B), 20 (A), and (B) can be used for the display panel 4006 in FIG. 21.

The shape and / or dimensions of the upper cover 4001 and the lower cover 4002 can be appropriately changed according to the sizes of the touch panel 4004 and the display panel 4006.

The touch panel 4004 can be used by superimposing a resistance film type or capacitance type touch panel on the display panel 4006. It is also possible to equip the facing substrate (sealing substrate) of the display panel 4006 with a touch panel function. Alternatively, an optical sensor may be provided in each pixel of the display panel 4006 to form an optical touch panel. Alternatively, it is also possible to provide a touch sensor electrode in each pixel of the display panel 4006 to form a capacitive touch panel. In this case, the touch panel 4004 can be omitted.

The frame 4009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 4010, in addition to the protective function of the display panel 4006. The frame 4009 may have a function as a heat sink.

The printed circuit board 4010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying electric power to the power supply circuit may be an external commercial power source or a power source provided by a separately provided battery 4011. The battery 4011 can be omitted when a commercial power source is used.

Members such as a polarizing plate, a retardation plate, and a prism sheet may be additionally provided in the display module 4000.

It should be noted that this embodiment can be appropriately combined with other embodiments shown in the present specification.

(Embodiment 5)
Here, a display device (also referred to as an electronic device) having a semiconductor device according to one aspect of the present invention will be described.

The semiconductor device according to one aspect of the present invention is a display capable of reproducing a recording medium such as a display device, a personal computer, and an image reproduction device including a recording medium (typically, DVD: Digital Versaille Disc) and displaying the image. It can be used for a device having a device). In addition, as electronic devices that can use the semiconductor device according to one aspect of the present invention, mobile phones, game machines including portable types, mobile information terminals, electronic book terminals, video cameras, cameras such as digital still cameras, and goggles. Examples include type displays (head mount displays), navigation systems, copiers, facsimiles, multifunction printers, automatic cash deposit / payment machines (ATMs), vending machines, medical equipment, and the like. Specific examples of these electronic devices are shown in FIG.

FIG. 22A is a portable game machine, which has a housing 5201, a housing 5202, a display unit 5203, a display unit 5204, a microphone 5205, a speaker 5206, an operation key 5207, a stylus 5208, and the like. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of portable game machines. The portable game machine shown in FIG. 22A has two display units 5203 and a display unit 5204, but the number of display units of the portable game machine is not limited to this.

FIG. 22B is a mobile information terminal, which has a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection unit 5605, an operation key 5606, and the like. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of a portable information terminal. The first display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connecting portion 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connecting portion 5605. be. The image on the first display unit 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 on the connection unit 5605. Further, a display device having a function as a position input device may be used for at least one of the first display unit 5603 and the second display unit 5604. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, which is also called a photo sensor, in the pixel portion of the display device.

FIG. 22C is a notebook personal computer, which includes a housing 5401, a display unit 5402, a keyboard 5403, a pointing device 5404, and the like. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of a notebook personal computer.

FIG. 22D is a smart watch which is a kind of wearable terminal, and has a housing 5901, a display unit 5902, an operation button 5903, an operator 5904, a band 5905, and the like. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of smart watches. Further, a display device having a function as a position input device may be used for the display unit 5902. Further, the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel portion of the display device. Further, the operation button 5903 may be provided with any one of a power switch for activating the smartwatch, a button for operating the smartwatch application, a volume adjustment button, and a switch for turning on or off the display unit 5902. Further, in the smart watch shown in FIG. 22 (D), the number of operation buttons 5903 is shown as two, but the number of operation buttons possessed by the smart watch is not limited to this. Further, the operator 5904 functions as a crown for adjusting the time of the smart watch. Further, the operator 5904 may be used as an input interface for operating the smart watch application in addition to the time adjustment. The smart watch shown in FIG. 22D is configured to have an operator 5904, but the present invention is not limited to this, and a configuration may not have an operator 5904.

FIG. 22E is a video camera, which has a first housing 5801, a second housing 5802, a display unit 5803, an operation key 5804, a lens 5805, a connection unit 5806, and the like. The semiconductor device according to one aspect of the present invention can be used in various integrated circuits of a video camera. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display unit 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connecting portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connecting portion 5806. be. The image on the display unit 5803 may be switched according to the angle between the first housing 5801 and the second housing 5802 on the connection unit 5806.

FIG. 22F is a passenger car, which has a vehicle body 5701, wheels 5702, a dashboard 5703, a light 5704, and the like. The display device according to one aspect of the present invention can be used in a navigation system for a passenger car.

FIG. 22 (G) shows an example of a television device. In the television device, the display unit 5002 is incorporated in the housing 5001. Here, a configuration in which the housing 5001 is supported by the stand 5003 is shown. The operation of the television device can be performed by an operation switch included in the housing 5001 or a separate remote control operation device 5004. Alternatively, the display unit 5002 may be provided with a touch sensor, and may be operated by touching the display unit 5002 with a finger or the like. The remote control operating device 5004 may have a display unit that displays information output from the remote control operating device 5004. The channel and volume can be operated by the operation keys or the touch panel provided in the remote controller 5004, and the image displayed on the display unit 5002 can be operated. The television device may be configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via a modem, information communication is performed in one direction (sender to receiver) or two-way (sender and receiver, or between receivers, etc.). It is also possible.

FIG. 22H is a mobile phone having a function of an information terminal, and has a housing 5501, a display unit 5502, a microphone 5503, a speaker 5504, and an operation button 5505. Further, a display device having a function as a position input device may be used for the display unit 5502. Further, the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel portion of the display device. Further, the operation button 5505 may be provided with any one of a power switch for activating the mobile phone, a button for operating the application of the mobile phone, a volume adjustment button, and a switch for turning on or off the display unit 5502. Further, in the mobile phone shown in FIG. 22 (H), the number of operation buttons 5505 is shown as two, but the number of operation buttons possessed by the mobile phone is not limited to this. Further, although not shown, the mobile phone shown in FIG. 22 (H) may have a camera. Although not shown, the mobile phone shown in FIG. 22 (H) may have a flashlight or a light emitting device for lighting purposes. Although not shown, the mobile phone shown in FIG. 22 (H) has a sensor (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetic) inside the housing 5501. , Temperature, chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, infrared rays, etc.). .. In particular, by providing a detection device having a sensor for detecting tilt such as a gyro or an acceleration sensor, the orientation of the mobile phone shown in FIG. 22 (H) (which direction the mobile phone faces with respect to the vertical direction) can be determined. After determining, the screen display of the display unit 5502 can be automatically switched according to the orientation of the mobile phone. Further, in particular, by providing a detection device having a sensor for acquiring biometric information such as a fingerprint, a vein, an iris, or a voice print, a mobile phone having a biometric authentication function can be realized.

Next, a display device that can include a semiconductor device or a storage device according to one aspect of the present invention will be described. As an example, the display device has pixels. Pixels include, for example, transistors and display elements. Alternatively, the display device has a drive circuit for driving the pixels. The drive circuit has, for example, a transistor. For example, as these transistors, the transistors described in other embodiments can be adopted.

For example, in the present specification and the like, the display element, the display device which is a device having a display element, the light emitting element, and the light emitting device which is a device having a light emitting element use various forms or have various elements. Can be done. Display elements, display devices, light emitting elements or light emitting devices include, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chips, etc.). Green LED chip, blue LED chip, etc.), transistor (transistor that emits light according to current), plasma display panel (PDP), electron emitting element, display element using carbon nanotube, liquid crystal element, electronic ink, electrowetting element , Electroelectric element, Display element using MEMS (Micro Electro Mechanical System) (for example, Grating Light Valve (GLV), Digital Micro Mirror Device (DMD), DMS (Digital Micro Shutter), MIRASOL (Registration) Trademark), IMOD (Interferrometric Modulation) element, shutter type MEMS display element, optical interference type MEMS display element, piezoelectric ceramic display, etc.), or at least one such as a quantum dot. In addition to these, the display element, the display device, the light emitting element, or the light emitting device may have a display medium whose contrast, brightness, reflectance, transmittance, and the like are changed by an electric or magnetic action. An EL display or the like is an example of a display device using an EL element. As an example of a display device using an electron emitting element, there is a field emission display (FED) or an SED type planar display (SED: Surface-conduction Electron-emitter Display). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display). An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper. An example of a display device using quantum dots for each pixel is a quantum dot display. The quantum dots may be provided not as a display element but as a part of the backlight. By using quantum dots, it is possible to display with high color purity. In the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced. When an LED chip is used, graphene or graphite may be arranged under the electrode of the LED chip or the nitride semiconductor. Graphene and graphite may be formed by stacking a plurality of layers to form a multilayer film. By providing graphene or graphite in this way, a nitride semiconductor, for example, an n-type GaN semiconductor layer having crystals can be easily formed on the graphene. Further, a p-type GaN semiconductor layer having crystals or the like can be provided on the p-type GaN semiconductor layer to form an LED chip. An AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having crystals. The GaN semiconductor layer of the LED chip may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED chip can be formed by a sputtering method. Further, in a display element using a MEMS (Micro Electro Mechanical System), a space in which the display element is sealed (for example, an element substrate on which the display element is arranged and an element substrate facing the element substrate) are arranged. A desiccant may be placed between the facing substrate and the facing substrate. By arranging the desiccant, it is possible to prevent MEMS and the like from becoming difficult to move due to moisture and easily deteriorating.

It should be noted that this embodiment can be appropriately combined with other embodiments shown in the present specification.

(Embodiment 6)
Here, a display device having a semiconductor device of one aspect of the present invention, which is different from the display device described in the fifth embodiment, will be described.

FIG. 23A is a digital signage (electronic signage), which can have a housing 6000, a display unit 6001, a speaker 6003, and the like.

FIG. 23B is a digital signage attached to a columnar pillar, and can have a housing 6000, a display unit 6001, and the like. In particular, by applying a flexible base material to the display unit 6001, it may be possible to attach the display portion 6001 regardless of the shape of the pillar to be attached.

The electronic device shown in FIG. 23 can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a display device function, a function to display a calendar, date or time, etc., and a function to control processing by various software (programs). , Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, read out program or data recorded on recording medium It can have a function of displaying on a display unit, and the like. Further, in the case of an electronic device having a plurality of display units, a function of displaying image information mainly on one display unit and displaying character information mainly on another display unit, or parallax on a plurality of display units. By displaying the considered image, it is possible to have a function of displaying a three-dimensional image, and the like. Further, in an electronic device having an image receiving unit, a function of shooting a still image, a function of shooting a moving image, a function of automatically or manually correcting the shot image, and a function of recording the shot image as a recording medium (external or built in the camera). It can have a function of saving, a function of displaying a captured image on a display unit, and the like. The functions that the electronic device shown in FIG. 23 can have are not limited to these, and can have various functions.

(Embodiment 7)
In this embodiment, the transistor according to one aspect of the disclosed invention will be described.

The transistor according to one aspect of the present invention preferably has the nc-OS or CAAC-OS described in the eighth embodiment.

<Transistor configuration example 1>
Hereinafter, an example of the transistor according to one aspect of the present invention will be described. 24 (A), 24 (B), and 24 (C) are a top view and a cross-sectional view of a transistor according to an aspect of the present invention. 24 (A) is a top view, FIG. 24 (B) is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 24 (A), and FIG. 24 (C) is a cross-sectional view corresponding to the alternate long and short dash line Y1-Y2. .. In the top view of FIG. 24A, some elements are omitted for the sake of clarity of the figure.

The transistor 1200a includes a conductor 1205 and a conductor 1260 that function as a gate electrode, an insulator 1220, an insulator 1222, an insulator 1224, and an insulator 1250 that function as a gate insulating layer, and a region where a channel is formed. 1230, conductors 1240a and 1241a that function as one of the source or drain, conductors 1240b and 1241b that function as the other of the source or drain, insulator 1214, and insulator 1216. And an insulator 1270 and an insulator 1280 having excess oxygen.

Further, the metal oxide 1230 has a metal oxide 1230a, a metal oxide 1230b on the metal oxide 1230a, and a metal oxide 1230c on the metal oxide 1230b. When the transistor 1200a is turned on, a current mainly flows through the metal oxide 1230b (a channel is formed). On the other hand, in the metal oxide 1230a and the metal oxide 1230c, a current may flow in the vicinity of the interface with the metal oxide 1230b (which may be a mixed region), but the other regions function as insulators. In some cases.

<< Interlayer insulating film, protective insulating film >>
As the insulator 1214, it is preferable to use a material having a barrier property against oxygen and hydrogen. For example, as an example of a film having a barrier property against hydrogen, silicon nitride formed by the CVD method can be used for the insulator 1214. Further, for example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 1214. In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 1200a during and after the manufacturing process of the transistor. Further, it is possible to suppress the release of oxygen from the metal oxide constituting the transistor 1200a. Therefore, it is suitable for use as a protective film for the transistor 1200a.

The insulator 1216 is provided on the insulator 1214. Materials such as silicon oxide, silicon nitride nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, and aluminum nitride can be used for the insulator 1216.

The insulator 1220 and the insulator 1224 are preferably insulators containing oxygen, such as a silicon oxide film and a silicon nitride film. In particular, it is preferable to use an insulator containing excess oxygen (containing more oxygen than the stoichiometric composition) as the insulator 1224. By providing such an insulator containing excess oxygen in contact with the metal oxide constituting the transistor 1200a, oxygen deficiency in the metal oxide can be compensated. The insulator 1222 and the insulator 1224 do not necessarily have to be formed by using the same material.

The insulator 1222 may be, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, It is preferable to use an insulator containing a so-called high-k material such as Sr) TiO ₃ (BST) in a single layer or in a laminated manner. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.

The insulator 1222 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

By having the insulator 1222 containing the high-k material between the insulator 1220 and the insulator 1224, the insulator 1222 can capture electrons and increase the threshold voltage under specific conditions. That is, the insulator 1222 may be negatively charged.

For example, when silicon oxide is used for the insulator 1220 and the insulator 1224, and a material having a large electron capture level such as hafnium oxide, aluminum oxide, and tantalum oxide is used for the insulator 1222, the operating temperature of the semiconductor device is used. Or, at a temperature higher than the storage temperature (for example, 125 ° C. or higher and 450 ° C. or lower, typically 150 ° C. or higher and 300 ° C. or lower), the potential of the conductor 1205 is higher than the potential of the source electrode or the drain electrode. By maintaining for 10 milliseconds or more, typically 1 minute or more, electrons move from the metal oxide constituting the transistor 1200a toward the conductor 1205. At this time, some of the moving electrons are captured by the electron capture level of the insulator 1222.

The threshold voltage of the transistor in which the required amount of electrons is captured in the electron capture level of the insulator 1222 shifts to the positive side. The amount of electrons captured can be controlled by controlling the voltage of the conductor 1205, and the threshold voltage can be controlled accordingly. By having this configuration, the transistor 1200a becomes a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

Further, the process of capturing electrons may be performed in the process of manufacturing the transistor. For example, after the formation of the conductor connected to the source conductor or the drain conductor of the transistor, after the completion of the previous step (wafer processing), after the wafer dicing step, after packaging, etc., before shipment from the factory. It is good to do it in stages. In any case, it is preferable not to be subsequently exposed to a temperature of 125 ° C. or higher for 1 hour or longer.

When the insulator 1220 and the insulator 1224 are composed of silicon oxide and the insulator 1222 is composed of hafnium oxide, the insulator 1220 and the insulator 1224 are used by a chemical vapor phase growth method (CVD method, atomic layer deposition (ALD)). The insulator 1222 may be formed by a sputtering method. By using the sputtering method for forming the insulator 1222, the insulator 1222 is likely to crystallize at a low temperature, and the amount of fixed charge generated may be large.

Further, the threshold voltage can be controlled by appropriately adjusting the film thicknesses of the insulator 1220, the insulator 1222, and the insulator 1224. The materials and film thickness of the insulator 1220, the insulator 1222, and the insulator 1224 are preferably silicon oxide nitride 10 nm, aluminum oxide 20 nm, and silicon oxide 30 nm, respectively. More preferably, it is 5 nm of silicon oxide, 5 nm of aluminum oxide, and 5 nm of silicon oxide.

Further, it is preferable to use a material having a barrier property against oxygen and hydrogen for the insulator 1222. When formed using such a material, it is possible to prevent the release of oxygen from the metal oxide constituting the transistor 1200a and the mixing of impurities such as hydrogen from the outside.

The insulator 1250 may be, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Insulators containing so-called high-k materials such as Sr) TiO ₃ (BST) can be used in single layers or laminates. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.

Further, as the insulator 1250, it is preferable to use an oxide insulator containing more oxygen than oxygen satisfying the stoichiometric composition, similarly to the insulator 1224. By providing such an insulator containing excess oxygen in contact with the metal oxide 1230, oxygen deficiency in the metal oxide 1230 can be reduced.

Further, the insulator 1250 has a barrier property against oxygen and hydrogen such as aluminum oxide, aluminum nitride, gallium oxide, gallium nitride oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, and silicon nitride. An insulating film can be used. When formed using such a material, it functions as a layer for preventing the release of oxygen from the metal oxide 1230 and the mixing of impurities such as hydrogen from the outside.

The insulator 1250 may have the same laminated structure as the insulator 1220, the insulator 1222, and the insulator 1224. Since the insulator 1250 has an insulator in which the required amount of electrons is captured in the electron capture level, the transistor 1200a can shift the threshold voltage to the positive side. By having this configuration, the transistor 1200a becomes a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

Further, in the transistor shown in FIG. 24, a barrier membrane may be provided between the metal oxide 1230 and the conductor 1260 in addition to the insulator 1250. Alternatively, a metal oxide 1230c having a barrier property may be used.

For example, by providing an insulating film containing excess oxygen in contact with the metal oxide 1230 and further wrapping it with a barrier film, the metal oxide can be placed in a state that almost matches the stoichiometric ratio composition, or from a stoichiometric composition. It can be in a hypersaturated state with a lot of oxygen. In addition, it is possible to prevent impurities such as hydrogen from entering the metal oxide 1230.

The insulator 1270 may be provided so as to cover the conductor 1260. When an oxide material from which oxygen is desorbed is used for the insulator 1280, a material having a barrier property against oxygen is used for the insulator 1270 in order to prevent the conductor 1260 from being oxidized by the desorbed oxygen. ..

For example, a metal oxide such as aluminum oxide can be used for the insulator 1270. Further, the insulator 1270 may be provided to such an extent as to prevent oxidation of the conductor 1260. For example, the film thickness of the insulator 1270 is set to 1 nm or more and 10 nm or less, preferably 3 nm or more and 7 nm or less.

Therefore, it is possible to suppress the oxidation of the conductor 1260 and efficiently supply the oxygen desorbed from the insulator 1280 to the metal oxide 1230.

<< Metal Oxide >>
The metal oxide 1230a, the metal oxide 1230b, and the metal oxide 1230c are formed of a metal oxide such as an In—M—Zn oxide (M is Al, Ga, Y, or Sn). Further, In—Ga oxide or In—Zn oxide may be used as the metal oxide 1230.

Hereinafter, the metal oxide 1230 according to the present invention will be described.

The metal oxide used for the metal oxide 1230 preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. Further, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.

Here, consider the case where the metal oxide has indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

First, with reference to FIGS. 27 (A), 27 (B), and 27 (C), a preferable range of atomic number ratios of indium, element M, and zinc contained in the metal oxide according to the present invention will be described. Note that FIG. 27 does not show the atomic number ratio of oxygen. Further, the respective terms of the atomic number ratios of indium, element M, and zinc contained in the metal oxide are [In], [M], and [Zn].

In FIGS. 27 (A), 27 (B), and 27 (C), the broken line indicates the atomic number ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. (Α is a real number of -1 or more and 1 or less), [In]: [M]: [Zn] = (1 + α): (1-α): Line having an atomic number ratio of 2, [In]: [M]: [Zn] = (1 + α): (1-α): Line having an atomic number ratio of 3, [In]: [M]: [Zn] = (1 + α): (1-α): 4 Represents a line having an atomic number ratio of [In]: [M]: [Zn] = (1 + α): (1-α): 5.

Further, the one-point chain line is a line having an atomic number ratio of [In]: [M]: [Zn] = 1: 1: β (β is a real number of 0 or more), [In]: [M]: [Zn]. = 1: 2: Line with atomic number ratio of β, [In]: [M]: [Zn] = 1: 3: Line with atomic number ratio of β, [In]: [M]: [Zn] = 1: 4: β atomic number ratio line, [In]: [M]: [Zn] = 2: 1: β atomic number ratio line, and [In]: [M]: [Zn] ] = 5: 1: Represents a line having an atomic number ratio of β.

Further, the metal oxide having an atomic number ratio of [In]: [M]: [Zn] = 0: 2: 1 or a value close to the atomic number ratio shown in FIG. 27 tends to have a spinel-type crystal structure.

27 (A) and 27 (B) show an example of a preferable range of atomic number ratios of indium, element M, and zinc contained in the metal oxide of one aspect of the present invention.

As an example, FIG. 28 shows the crystal structure of InMZnO ₄ in which [In]: [M]: [Zn] = 1: 1: 1. Further, FIG. 28 is a crystal structure of InMZnO ₄ when observed from a direction parallel to the b-axis. The metal element in the layer having M, Zn, and oxygen (hereinafter, (M, Zn) layer) shown in FIG. 28 represents the element M or zinc. In this case, it is assumed that the ratios of the element M and zinc are equal. The elements M and zinc can be substituted and the arrangement is irregular.

InMZnO ₄ has a layered crystal structure (also referred to as a layered structure), and as shown in FIG. 28, indium and a layer having oxygen (hereinafter referred to as In layer) have 1 element M, zinc, and oxygen. The number of (M, Zn) layers is 2.

Indium and the element M are substitutable for each other. Therefore, the element M of the (M, Zn) layer can be replaced with indium and expressed as the (In, M, Zn) layer. In that case, it has a layered structure in which the In layer is 1 and the (In, M, Zn) layer is 2.

The metal oxide having an atomic number ratio of [In]: [M]: [Zn] = 1: 1: 2 has a layered structure in which the In layer is 1 and the (M, Zn) layer is 3. That is, when [Zn] becomes larger than [In] and [M], the ratio of the (M, Zn) layer to the In layer increases when the metal oxide crystallizes.

However, in the metal oxide, when the number of (M, Zn) layers is non-integer with respect to one In layer, the number of (M, Zn) layers is one with respect to one In layer. It may have multiple types of layered structures that are integers. For example, when [In]: [M]: [Zn] = 1: 1: 1.5, a layered structure in which the In layer is 1 and the (M, Zn) layer is 2, and (M, Zn). ) It may be a layered structure in which a layered structure having 3 layers is mixed.

For example, when a metal oxide is formed into a film by a sputtering apparatus, a film having an atomic number ratio deviating from the target atomic number ratio is formed. In particular, depending on the substrate temperature at the time of film formation, the film [Zn] may be smaller than the target [Zn].

In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, at an atomic number ratio that is close to the atomic number ratio of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel-type crystal structure and a layered crystal structure coexist. Cheap. Further, in the atomic number ratio, which is a value close to the atomic number ratio indicating [In]: [M]: [Zn] = 1: 0: 0, the two phases of the big bite type crystal structure and the layered crystal structure are present. Easy to coexist. When a plurality of phases coexist in a metal oxide, grain boundaries (also referred to as grain boundaries) may be formed between different crystal structures.

Further, by increasing the content of indium, the carrier mobility (electron mobility) of the metal oxide can be increased. This is because in metal oxides containing indium, element M and zinc, the s orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the content of indium, the region where the s orbitals overlap becomes larger. This is because the metal oxide having a high indium content has a higher carrier mobility than the metal oxide having a low indium content.

On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility is low. Therefore, in the atomic number ratio showing [In]: [M]: [Zn] = 0: 1: 0 and the atomic number ratio which is a value close to the atomic number ratio (for example, the region C shown in FIG. 27C), the insulating property Will be higher.

Therefore, it is preferable that the metal oxide according to one aspect of the present invention has the atomic number ratio shown in the region A of FIG. 27 (A), which tends to have a layered structure having high carrier mobility and few grain boundaries. ..

Further, the region B shown in FIG. 27 (B) shows [In]: [M]: [Zn] = 4: 2: 3 to 4.1, and values in the vicinity thereof. The neighborhood value includes, for example, an atomic number ratio of [In]: [M]: [Zn] = 5: 3: 4. The metal oxide having the atomic number ratio shown in the region B is an excellent metal oxide having high crystallinity and high carrier mobility.

The conditions under which the metal oxide forms a layered structure are not uniquely determined by the atomic number ratio. Depending on the atomic number ratio, there is a difference in the difficulty of forming a layered structure. On the other hand, even if the atomic number ratio is the same, the layered structure may or may not be formed depending on the formation conditions. Therefore, the region shown in the figure is a region showing the atomic number ratio of the metal oxide having a layered structure, and the boundary between the regions A and C is not strict.

Subsequently, a case where the above metal oxide is used for a transistor will be described.

By using the metal oxide in the transistor, carrier scattering and the like at the grain boundaries can be reduced, so that a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

Further, it is preferable to use a metal oxide having a low carrier density for the transistor. For example, metal oxides have a carrier density of less than 8 × 10 ¹¹ cm ^-3 , preferably less than 1 × 10 ¹¹ cm ^-3 , more preferably less than 1 × 10 ¹⁰ cm ^-3 , and 1 × 10 ^-9 cm. It should be ^-3 or more.

It should be noted that the metal oxide having high purity intrinsicity or substantially high purity intrinsicity has few carriers, so that the carrier density can be lowered. Further, since the metal oxide having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

In addition, the charge captured at the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in a metal oxide having a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the metal oxide. Further, in order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

Here, the influence of each impurity in the metal oxide will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the metal oxide, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon near the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, in the metal oxide, when nitrogen is contained, electrons which are carriers are generated, the carrier density is increased, and it is easy to form an n-type. As a result, a transistor using a metal oxide containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the metal oxide, nitrogen is preferably reduced as much as possible, for example, the nitrogen concentration in the metal oxide is less than 5 × 10 ¹⁹ atoms / cm ³ in SIMS, preferably 5 × 10 ¹⁸ . Atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using a metal oxide having sufficiently reduced impurities in the channel region of the transistor, stable electrical characteristics can be imparted.

Subsequently, a case where the metal oxide has a two-layer structure or a three-layer structure will be described. A band diagram of an insulator in contact with a laminated structure of a metal oxide S1, a metal oxide S2, and a metal oxide S3, a band diagram of an insulator in contact with a laminated structure of a metal oxide S1 and a metal oxide S2, and a metal oxidation. A band diagram of an insulator in contact with the laminated structure of the object S2 and the metal oxide S3 will be described with reference to FIG. 29.

FIG. 29A is an example of a band diagram in the film thickness direction of the laminated structure having the insulator I1, the metal oxide S1, the metal oxide S2, the metal oxide S3, and the insulator I2. Further, FIG. 29B is an example of a band diagram in the film thickness direction of the laminated structure having the insulator I1, the metal oxide S2, the metal oxide S3, and the insulator I2. Further, FIG. 29C is an example of a band diagram in the film thickness direction of the laminated structure having the insulator I1, the metal oxide S1, the metal oxide S2, and the insulator I2. The band diagram shows the energy level (Ec) at the lower end of the conduction band of the insulator I1, the metal oxide S1, the metal oxide S2, the metal oxide S3, and the insulator I2 for easy understanding.

The metal oxide S1 and the metal oxide S3 have an energy level at the lower end of the conduction band closer to the vacuum level than the metal oxide S2, and typically have an energy level at the lower end of the conduction band of the metal oxide S2. It is preferable that the difference between the energy level of the lower end of the conduction band of the metal oxide S1 and the metal oxide S3 is 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the metal oxide S1 and the metal oxide S3 and the electron affinity of the metal oxide S2 is 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less. preferable.

As shown in FIGS. 29 (A), 29 (B), and 29 (C), the energy level at the lower end of the conduction band changes gently in the metal oxide S1, the metal oxide S2, and the metal oxide S3. do. In other words, it can also be said to be continuously changing or continuously joining. In order to have such a band diagram, the defect level density of the mixed layer formed at the interface between the metal oxide S1 and the metal oxide S2 or the interface between the metal oxide S2 and the metal oxide S3 is lowered. It is good to do.

Specifically, the metal oxide S1 and the metal oxide S2, and the metal oxide S2 and the metal oxide S3 have a common element (main component) other than oxygen, so that the defect level density is low. Layers can be formed. For example, when the metal oxide S2 is an In—Ga—Zn oxide, In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide or the like may be used as the metal oxide S1 and the metal oxide S3.

At this time, the main path of the carrier is the metal oxide S2. Since the defect level density at the interface between the metal oxide S1 and the metal oxide S2 and the interface between the metal oxide S2 and the metal oxide S3 can be lowered, the influence of interfacial scattering on carrier conduction is small. High on-current is obtained.

When electrons are trapped at the trap level, the trapped electrons behave like a fixed charge, and the threshold voltage of the transistor shifts in the positive direction. By providing the metal oxide S1 and the metal oxide S3, the trap level can be kept away from the metal oxide S2. With this configuration, it is possible to prevent the threshold voltage of the transistor from shifting in the positive direction.

As the metal oxide S1 and the metal oxide S3, a material having a sufficiently low conductivity as compared with the metal oxide S2 is used. At this time, the metal oxide S2, the interface between the metal oxide S2 and the metal oxide S1, and the interface between the metal oxide S2 and the metal oxide S3 mainly function as a channel region. For example, for the metal oxide S1 and the metal oxide S3, the metal oxide having the atomic number ratio shown in the region C where the insulating property is high may be used in FIG. 27 (C). The region C shown in FIG. 27 (C) shows the atomic number ratio which is [In]: [M]: [Zn] = 0: 1: 0 or a value in the vicinity thereof.

In particular, when a metal oxide having an atomic number ratio shown in region A is used for the metal oxide S2, [M] / [In] is 1 or more, preferably 2 or more for the metal oxide S1 and the metal oxide S3. It is preferable to use a metal oxide which is. Further, as the metal oxide S3, it is preferable to use a metal oxide having [M] / ([Zn] + [In]) of 1 or more, which can obtain sufficiently high insulating properties.

<< Source electrode, drain electrode >>
One of the conductors 1240a and 1241a, the conductor 1240b, and the conductor 1241b functions as a source electrode, and the other functions as a drain electrode.

The conductor 1240a, the conductor 1241a, the conductor 1240b, and the conductor 1241b are made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or a main component thereof. Can be used. Further, although the two-layer structure is shown in the figure, it may be a single-layer structure or a laminated structure having three or more layers.

For example, an aluminum film may be used for the conductor 1241a and 1241b, and a titanium film may be laminated on the conductor 1240a and the conductor 1240b. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may have a two-layer structure in which copper films are laminated.

Further, a three-layer structure, a molybdenum film or a molybdenum film or a titanium film having a titanium film or a titanium nitride film and an aluminum film or a copper film laminated on the titanium film or the titanium nitride film and further forming a titanium film or a titanium nitride film on the aluminum film or the copper film. There is a three-layer structure in which a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed on the aluminum film or a copper film. A transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

<< Gate electrode >>
The conductor 1205a and the conductor 1205b that function as gate electrodes will be described. In FIG. 24, the two-layer structure of the conductor 1205a and the conductor 1205b is shown, but the structure is not limited to this, and a single layer or a laminated structure of three or more layers may be used. For example, as the conductor 1205a, tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen, and as the conductor 1205b, tungsten having high conductivity may be laminated. By using this combination, it is possible to suppress the diffusion of hydrogen into the metal oxide 1230 while maintaining the conductivity as wiring.

Further, the conductor 1260a and the conductor 1260b that function as gate electrodes are, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the above-mentioned metal as a component, or described above. It can be formed by using an alloy or the like in which a metal is combined. Further, a metal selected from any one or more of manganese and zirconium may be used. Further, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

For example, it is preferable to use aluminum for the conductor 1260a and to have a two-layer structure in which a titanium film is laminated on the conductor 1260b. Further, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, or a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film may be used. ..

Further, there is a titanium film and a three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed on the titanium film. Further, an alloy film or a nitride film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum may be used.

Further, the conductor 1260 includes indium tin oxide, indium metal oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxidation. It is also possible to apply a translucent conductive material such as an indium tin oxide to which a substance or silicon oxide is added. Further, it is also possible to form a laminated structure of the conductive material having the translucency and the metal.

<< s-channel structure >>
Further, as shown in FIG. 24C, the transistor 1200a has a structure in which the side surface of the metal oxide 1230b is surrounded by the conductor 1260. In the present specification, the structure of the transistor that electrically surrounds the region where the channel is formed by the electric field of the gate electrode is referred to as a curved channel (s-channel) structure. By adopting this structure, the electric field of the conductor 1260 can electrically surround the metal oxide 1230, and a channel can be formed in the whole (bulk) of the metal oxide 1230b. Therefore, in the s-channel structure, a large current can be passed between the source and drain of the transistor, and the on-current can be increased. Further, since the voltage is applied from the entire circumference to the region where the channel is formed, it is possible to provide a transistor in which the leakage current is suppressed.

Since the s-channel structure can obtain a high on-current, it can be said that the structure is suitable for semiconductor devices that require miniaturized transistors such as LSI (Large Scale Integration). Since the transistor can be miniaturized, the semiconductor device having the transistor can be a high-density semiconductor device with a high degree of integration.

<Transistor configuration example 2>
FIG. 25 shows an example of the structure of a transistor different from the transistor 1200a. FIG. 25A shows the upper surface of the transistor 1200b. 25 (B) is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 25 (A), and FIG. 25 (C) is a cross-sectional view corresponding to Y1-Y2.

In the transistor 1200b shown in FIG. 25, the same reference numerals are added to the structures having the same functions as the structures constituting the transistor 1200a shown in FIG. 24.

In the structure shown in FIG. 25, a metal oxide 1230c, an insulator 1250, and a conductor 1260 are formed in an opening formed in the insulator 1280. Further, the ends of the conductor 1240a, the conductor 1240b, the conductor 1241a, and the conductor 1241b coincide with the ends of the openings formed in the insulator 1280. Further, the ends of the conductor 1240a, the conductor 1240b, the conductor 1241a, and the conductor 1241b coincide with a part of the end of the metal oxide 1230. Therefore, the conductor 1240a, the conductor 1240b, the conductor 1241a, and the conductor 1241b can be shaped at the same time as the opening of the metal oxide 1230 or the insulator 1280. Therefore, the number of masks and processes can be reduced. In addition, yield and productivity can be improved.

Further, since the transistor 1200b shown in FIG. 25 has a structure in which the conductor 1240a, the conductor 1240b, the conductor 1241a, and the conductor 1241b and the conductor 1260 hardly overlap each other, the parasitic capacitance applied to the conductor 1260 is increased. It can be made smaller. That is, it is possible to provide a transistor 1200b having a high operating frequency.

<Transistor configuration example 3>
FIG. 26 shows an example of the structure of a transistor different from the transistor 1200a and the transistor 1200b. FIG. 26A shows the upper surface of the transistor 1200c. For the sake of clarity in the figure, some films are omitted in FIG. 26 (A). 26 (B) is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 26 (A), and FIG. 26 (C) is a cross-sectional view corresponding to Y1-Y2.

In the transistor 1200c shown in FIG. 26, the same reference numerals are added to the structures having the same functions as the structures constituting the transistor 1200a shown in FIG. 24.

In the structure shown in FIG. 26, the metal oxide 1230 is provided with a region 1245a that functions as one of the source region or the drain region and a region 1245b that functions as the other of the source region or the drain region. The region can be formed by adding impurities such as boron, phosphorus, and argon to the metal oxide 1230 using the conductor 1260 as a mask. Further, by using the insulator 1280 as an insulator containing hydrogen such as a silicon nitride film, it can be formed by diffusing hydrogen into a part of the metal oxide 1230. Therefore, the number of masks or processes can be reduced. In addition, yield and productivity can be improved.

<Transistor configuration example 4>
30 (A) to 30 (D) are a top view and a cross-sectional view of the transistor 1400. 30 (A) is a top view of the transistor 1400, FIG. 30 (B) is a cross-sectional view corresponding to the alternate long and short dash line A1-A2 shown in FIG. 30 (A), and FIG. 30 (C) is the alternate long and short dash line A3. -It is a cross-sectional view corresponding to A4. The alternate long and short dash line A1-A2 may be referred to as the channel length direction, and the alternate long and short dash line A3-A4 may be referred to as the channel width direction. The transistor 1400 is also a transistor having an s-channel structure, like the transistor 1200a and the like.

The transistor 1400 includes a substrate 1450, an insulator 1401 on the substrate 1450, a conductor 1414 on the insulator 1401, an insulator 1402 formed so as to cover the conductor 1414, and an insulator 1403 on the insulator 1402. And the insulator 1404 on the insulator 1403, and the laminate formed on the insulator 1404 in the order of the metal oxide 1431, the metal oxide 1432, and the metal oxide 1433 (when collectively referred to as the metal oxide 1430). Insulator 1406 on the metal oxide 1433, the conductor 1412 on the insulator 1406, the insulator 1409 on the side surface of the conductor 1412, the insulator 1404, the metal oxide 1433 and the insulator. It has an insulator 1407 formed so as to cover the 1409 and the conductor 1412, and an insulator 1408 on the insulator 1407.

The insulator 1406 and the conductor 1412 overlap at least a part of the conductor 1414 and the metal oxide 1432. It is preferable that the side end portion of the conductor 1412 in the channel length direction and the side end portion of the insulator 1406 in the channel length direction substantially coincide with each other. Here, the insulator 1406 functions as a gate insulator of the transistor 1400, the conductor 1412 functions as a gate electrode of the transistor 1400, and the insulator 1409 functions as a sidewall insulator of the transistor 1400.

The metal oxide 1432 has a region overlapping with the conductor 1412 via the metal oxide 1433 and the insulator 1406. It is preferable that the outer periphery of the metal oxide 1431 substantially coincides with the outer periphery of the metal oxide 1432, and the outer periphery of the metal oxide 1433 is located outside the outer periphery of the metal oxide 1431 and the metal oxide 1432. Here, the outer circumference of the metal oxide 1433 is located outside the outer circumference of the metal oxide 1431, but the transistor shown in the present embodiment is not limited to this. For example, the outer circumference of the metal oxide 1431 may be located outside the outer circumference of the metal oxide 1433, or the shape is such that the side surface end portion of the metal oxide 1431 and the side surface end portion of the metal oxide 1433 substantially coincide with each other. May be good.

<< Board >>
As the substrate 1450, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, and the like. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

Further, a flexible substrate may be used as the substrate 1450. As a method of providing the transistor on the flexible substrate, there is also a method of forming the transistor on the non-flexible substrate, peeling off the transistor, and transposing it to the substrate 1450 which is a flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. As the substrate 1450, a sheet, film, foil or the like woven with fibers may be used. Further, the substrate 1450 may have elasticity. Further, the substrate 1450 may have a property of returning to the original shape when bending or pulling is stopped. Alternatively, it may have a property of not returning to the original shape. The thickness of the substrate 1450 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By thinning the substrate 1450, the weight of the semiconductor device can be reduced. Further, by thinning the substrate 1450, it may have elasticity even when glass or the like is used, or it may have a property of returning to the original shape when bending or pulling is stopped. Therefore, it is possible to alleviate the impact applied to the semiconductor device on the substrate 1450 due to dropping or the like. That is, it is possible to provide a durable semiconductor device.

As the substrate 1450 which is a flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. As for the substrate 1450, which is a flexible substrate, the lower the coefficient of linear expansion, the more the deformation due to the environment is suppressed, which is preferable. As the substrate 1450 which is a flexible substrate, for example, if a material having a linear expansion coefficient of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less is used. good. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE), and the like. In particular, aramid has a low coefficient of linear expansion and is therefore suitable as a substrate 1450 which is a flexible substrate.

<< Underlying insulator >>
The insulator 1401 has a function of electrically separating the substrate 1450 and the conductor 1414.

The insulator 1401 or the insulator 1402 is formed of an insulator having a single-layer structure or a laminated structure. Materials constituting the insulator include, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and oxidation. Hafnium, tantalum oxide, etc.

Further, as the insulator 1402, silicon oxide having good step covering property formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen or nitrous oxide may be used.

Further, after forming the insulator 1402, a flattening treatment using a CMP method or the like may be performed in order to improve the flatness of the upper surface thereof.

The insulator 1404 preferably contains an oxide. In particular, it is preferable to contain an oxide material in which a part of oxygen is desorbed by heating. Preferably, it is preferable to use an oxide containing more oxygen than oxygen satisfying the stoichiometric composition. An oxide film containing more oxygen than oxygen satisfying a stoichiometric composition is desorbed by heating. The oxygen desorbed from the insulator 1404 is supplied to the metal oxide 1430, and it becomes possible to reduce the oxygen deficiency of the metal oxide 1430. As a result, fluctuations in the electrical characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than oxygen satisfying a chemical quantitative composition has an oxygen desorption amount of 1.0 × 10 in terms of oxygen atoms in, for example, TDS (Thermal Desorption Spectroscopy) analysis. An oxide film having ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower.

The insulator 1404 preferably contains an oxide capable of supplying oxygen to the metal oxide 1430. For example, it is preferable to use a material containing silicon oxide or silicon nitride nitride.

Alternatively, as the insulator 1404, metal oxides such as aluminum oxide, aluminum nitride, gallium oxide, gallium nitride oxide, yttrium oxide, yttrium oxide, hafnium oxide, and hafnium oxide may be used.

In order to allow the insulator 1404 to contain an excessive amount of oxygen, for example, the insulator 1404 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulator 1404 after the film formation to form a region containing an excessive amount of oxygen, or both means may be combined.

For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator 1404 after film formation to form a region containing an excess of oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma implantation ion implantation method, a plasma treatment, or the like can be used.

As the oxygen introduction method, a gas containing oxygen can be used. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction process, the gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be contained. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

Further, after forming the insulator 1404, a flattening treatment using a CMP method or the like may be performed in order to improve the flatness of the upper surface thereof.

The insulator 1403 has a passion function for preventing oxygen contained in the insulator 1404 from being combined with a metal contained in the conductor 1414 and reducing the oxygen contained in the insulator 1404.

The insulator 1403 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal and the like. By providing the insulator 1403, it is possible to prevent the diffusion of oxygen from the metal oxide 1430 to the outside and the entry of hydrogen, water, etc. into the metal oxide 1430 from the outside.

As the insulator 1403, for example, a nitride insulator can be used. Examples of the nitride insulator include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride. In addition, instead of the nitride insulator, an oxide insulator having a blocking effect such as oxygen, hydrogen, and water may be provided. Examples of the oxide insulator include aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, and hafnium oxide.

The transistor 1400 can control the threshold voltage by injecting electrons into the charge capture layer. The charge capture layer is preferably provided on the insulator 1402 or the insulator 1403. For example, by forming the insulator 1403 with hafnium oxide, aluminum oxide, tantalum oxide, aluminum silicate, or the like, it can function as a charge trapping layer.

<< Gate electrode >>
The conductor 1412 functions as a first gate electrode. Further, the conductor 1412 may have a laminated structure in which a plurality of conductors are overlapped. Further, the conductor 1414 of the gate electrode functions as a second gate electrode.

As the conductor 1412 and the conductor 1414, copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel. Low in (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) It is preferable to use a simple substance made of a resistance material, an alloy, or a single layer or a laminate of a conductor containing a compound containing these as a main component. In particular, it is preferable to use a melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Further, it is preferably formed of a low resistance conductive material such as aluminum or copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu.

Further, as the conductor 1412 or the conductor 1414, any one of the metal oxide 1431 to the metal oxide 1433 may be used. In this case, in order to make the metal oxide 1431 to the metal oxide 1433 function as a conductor, it is necessary to perform a separate step. Specifically, any one of the metal oxide 1431 to the metal oxide 1433 is formed as the conductor 1412 or the conductor 1414, silicon nitride is formed as the insulator 1407, and plasma containing hydrogen such as a CVD method is used. By forming the film, the resistance of the metal oxide 1431 to the metal oxide 1433 can be reduced. Thereby, any one of the metal oxide 1431 to the metal oxide 1433 can be used as the conductor for the conductor 1412 or the conductor 1414.

<< Metal Oxide >>
For details of the metal oxide 1431, refer to the description of the metal oxide 1230a shown in FIG. 24. Further, for details of the metal oxide 1432, the description of the metal oxide 1230b shown in FIG. 24 may be referred to. Further, for details of the metal oxide 1433, the description of the metal oxide 1230c shown in FIG. 24 may be referred to.

<< Low resistance region >>
FIG. 30 (D) shows a partially enlarged view of FIG. 30 (B). As shown in FIG. 30D, regions 1461a, 1461b, 1461c, 1461d and 1461e are formed in the metal oxide 1430. The regions 1461b to 1461e have a higher concentration of dopant and lower resistance than the region 1461a. Further, the region 1461b and the region 1461c have a higher hydrogen concentration than the region 1461d and the region 1461e, and the resistance is further lowered. For example, the region 1461a may be a region having a concentration of 5% or less, a region having a concentration of 2% or less, or a region having a concentration of 1% or less with respect to the maximum concentration of the dopant in the region 1461b or the region 1461c. The dopant may be paraphrased as a donor, an acceptor, an impurity or an element.

As shown in FIG. 30 (D), in the metal oxide 1430, the region 1461a is a region substantially overlapping with the conductor 1412, and the region 1461b, the region 1461c, the region 1461d and the region 1461e are regions excluding the region 1461a. .. In the region 1461b and the region 1461c, the upper surface of the metal oxide 1433 is in contact with the insulator 1407. In the regions 1461d and 1461e, the upper surface of the metal oxide 1433 is in contact with the insulator 1409 or the insulator 1406. That is, as shown in FIG. 30 (D), the boundary between the region 1461b and the region 1461d overlaps with the boundary between the side end portion of the insulator 1407 and the insulator 1409. The same applies to the boundary between the region 1461c and the region 1461e. Here, it is preferable that a part of the region 1461d and the region 1461e overlaps a part of the region (channel forming region) that overlaps with the conductor 1412 of the metal oxide 1432. For example, it is preferable that the side surface ends of the region 1461d and the region 1461e in the channel length direction are located inside the conductor 1412 by a distance d from the side surface ends of the conductor 1412. At this time, it is preferable that the film thickness t ₄₀₆ and the distance d of the insulator 1406 satisfy 0.25 t ₄₀₆ <d <t ₄₀₆ .

In this way, the region 1461d and the region 1461e are formed in a part of the region overlapping the conductor 1412 of the metal oxide 1430. As a result, the channel formation region of the transistor 1400 is in contact with the low resistance regions 1461d and 1461e, and a high resistance offset region is not formed between the regions 1461d and the region 1461e and the region 1461a. The on-current can be increased. Further, since the side end portions of the region 1461d and the region 1461e in the channel length direction are formed so as to satisfy the above range, the region 1461d and the region 1461e are formed too deeply with respect to the channel forming region and are always in a conductive state. It is also possible to prevent it from happening.

The region 1461b, region 1461c, region 1461d and region 1461e are formed by an ion doping treatment such as an ion implantation method. Therefore, as shown in FIG. 30 (D), the positions of the side end portions of the region 1461d and the region 1461e in the channel length direction become deeper from the upper surface of the metal oxide 1433 in the channel length direction of the metal oxide 1430. It may shift to the side edge side. At this time, the distance d is the distance between the side end portion of the region 1461d and the region 1461e in the channel length direction and the side surface end portion of the conductor 1412 in the channel length direction, which are located closest to the inside of the conductor 1412.

In this case, for example, the region 1461d and the region 1461e formed in the metal oxide 1431 may not be formed in the region overlapping with the conductor 1412. In this case, it is preferable that at least a part of the region 1461d and the region 1461e formed on the metal oxide 1431 or the metal oxide 1432 is formed in a region overlapping with the conductor 1412.

Further, it is preferable that the low resistance region 1451 and the low resistance region 1452 are formed in the vicinity of the interface between the metal oxide 1431 and the metal oxide 1432 and the insulator 1433 of the metal oxide 1433. The low resistance region 1451 and the low resistance region 1452 contain at least one of the elements contained in the insulator 1407. It is preferable that a part of the low resistance region 1451 and the low resistance region 1452 substantially touches the region (channel forming region) overlapping with the conductor 1412 of the metal oxide 1432, or overlaps with a part of the region.

Further, since the metal oxide 1433 has a large region in contact with the insulator 1407, the low resistance region 1451 and the low resistance region 1452 are likely to be formed in the metal oxide 1433. The low resistance region 1451 and the low resistance region 1452 of the metal oxide 1433 are more than the low resistance region 1451 and the region other than the low resistance region 1452 of the metal oxide 1433 (for example, the region overlapping the conductor 1412 of the metal oxide 1433). The concentration of the element contained in the insulator 1407 is high.

A low resistance region 1451 is formed in the region 1461b, and a low resistance region 1452 is formed in the region 1461c. The ideal structure of the metal oxide 1430 is, for example, the regions having the highest concentration of additive elements in the low resistance regions 1451 and 1452, and the regions having the next highest concentration in the regions 1461b and the regions 1461c-1461e having low resistance regions. The region does not include 1451 and 1452, and the region having the lowest concentration is the region 1461a. The additive element corresponds to a dopant for forming the regions 1461b and 1461c, and an element added from the insulator 1407 to the low resistance regions 1451 and 1452.

The transistor 1400 is configured to form low resistance regions 1451 and 1452, but the semiconductor device shown in the present embodiment is not necessarily limited to this. For example, if the resistance of the regions 1461b and 1461c is sufficiently low, it is not necessary to form the low resistance region 1451 and the low resistance region 1452.

<< Gate insulating film >>
The insulator 1406 preferably has an insulator having a high relative permittivity. For example, the insulator 1406 has gallium oxide, hafnium oxide, an oxide having aluminum and hafnium, a nitride having aluminum and hafnium, an oxide having silicon and hafnium, or a nitride having silicon and hafnium. Is preferable.

Further, the insulator 1406 preferably has a laminated structure of silicon oxide or silicon oxide nitride and an insulator having a high relative permittivity. Since silicon oxide and silicon oxynitride are thermally stable, they can be combined with an insulator having a high relative permittivity to form a laminated structure that is thermally stable and has a high relative permittivity. For example, by having aluminum oxide, gallium oxide or hafnium oxide on the metal oxide 1433 side, it is possible to prevent silicon contained in silicon oxide or silicon oxide nitride from being mixed in the metal oxide 1432.

Further, for example, by having silicon oxide or silicon oxide on the metal oxide 1433 side, a trap center may be formed at the interface between aluminum oxide, gallium oxide or hafnium oxide and silicon oxide or silicon nitride. be. The trap center may be able to fluctuate the threshold voltage of the transistor in the positive direction by capturing electrons.

<< Interlayer insulating film, protective insulating film >>
The insulator 1407 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal and the like. By providing the insulator 1407, it is possible to prevent the diffusion of oxygen from the metal oxide 1430 to the outside and the entry of hydrogen, water, etc. into the metal oxide 1430 from the outside.

As the insulator 1407, for example, a nitride insulator can be used. Examples of the nitride insulator include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride. In addition, instead of the nitride insulator, an oxide insulator having a blocking effect such as oxygen, hydrogen, and water may be provided. Examples of the oxide insulator include aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, and hafnium oxide.

The aluminum oxide film is preferable for application to the insulator 1407 because it has a high blocking effect of not allowing the film to permeate against both hydrogen, impurities such as water, and oxygen.

The insulator 1408 includes aluminum oxide, aluminum oxide oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and hafnium oxide. , An insulator containing one or more selected from tantalum oxide and the like can be used. Further, as the insulator 1408, a resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can also be used. Further, the insulator 1408 may be a laminate of the above materials.

<Transistor configuration example 5>
31 (A) and 31 (B) are a top view and a cross-sectional view of the transistor 1600. FIG. 31 (A) is a top view, and the cross section in the alternate long and short dash line AB direction shown in FIG. 31 (A) corresponds to FIG. 31 (B). In addition, in FIG. 31 (A) and FIG. 31 (B), some elements are enlarged, reduced, or omitted for the purpose of clarifying the figure. Further, the alternate long and short dash line AB direction may be referred to as the channel length direction.

The transistor 1600 shown in FIG. 31B has a conductor 1609 functioning as a first gate, a conductor 1608 functioning as a second gate, a semiconductor 1602, a conductor 1603 functioning as a source and a drain, and a conductor. It has a body 1604, an insulator 1601, an insulator 1605, an insulator 1606, and an insulator 1607.

The conductor 1609 is provided on the insulating surface. The conductor 1609 and the semiconductor 1602 overlap each other with the insulator 1601 interposed therebetween. Further, the conductor 1608 and the semiconductor 1602 overlap each other with the insulator 1605, the insulator 1606, and the insulator 1607 sandwiched between them. Further, the conductor 1603 and the conductor 1604 are connected to the semiconductor 1602.

For details of the conductor 1609 and the conductor 1608, refer to the description of the conductor 1412 or the conductor 1414 shown in FIG. 30.

The conductor 1609 and the conductor 1608 may be given different potentials, or may be given the same potential at the same time. The transistor 1600 can stabilize the threshold voltage by providing the conductor 1608 that functions as the second gate electrode. The conductor 1608 may be omitted in some cases.

For details of the semiconductor 1602, refer to the description of the metal oxide 1230b shown in FIG. 24. Further, the semiconductor 1602 may be a single layer or may be a stack of a plurality of semiconductor layers.

As the conductor 1603 and the conductor 1604, copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel. Low in (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) It is preferable to use a simple substance made of a resistance material, an alloy, or a single layer or a laminate of a conductor containing a compound containing these as a main component. In particular, it is preferable to use a melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Further, it is preferably formed of a low resistance conductive material such as aluminum or copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with the insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu.

Further, it is preferable to use a conductive oxide containing a noble metal such as iridium oxide, ruthenium oxide, and strontium ruthenium for the conductor 1603 and the conductor 1604. These conductive oxides rarely deprive the oxide semiconductor of oxygen even when they come into contact with the oxide semiconductor, and it is difficult to create oxygen deficiency in the oxide semiconductor.

For details of the insulator 1601, the description of the insulator 1406 shown in FIG. 30 may be referred to.

In addition, in FIG. 31B, the case where the insulator 1605 to the insulator 1607 which are laminated in order is provided on the semiconductor 1602, the conductor 1603 and the conductor 1604 is illustrated, but the semiconductor 1602, the conductor The insulator provided on the body 1603 and the conductor 1604 may be a single layer or a laminated stack of a plurality of insulators.

When an oxide semiconductor is used for the semiconductor 1602, the insulator 1606 is an insulator that contains oxygen having a chemical quantitative composition or higher and has a function of supplying a part of the oxygen to the semiconductor 1602 by heating. Is desirable. However, if the insulator 1606 is provided directly on the semiconductor 1602 and the semiconductor 1602 is damaged during the formation of the insulator 1606, as shown in FIG. 31 (B), the insulator 1605 is used between the semiconductor 1602 and the insulator 1606. It is good to install it in between. It is desirable that the insulator 1605 is an insulator that causes less damage to the semiconductor 1602 at the time of its formation than that of the insulator 1606 and has a function of allowing oxygen to permeate. However, if the insulator 1606 can be directly formed on the semiconductor 1602 while keeping the damage given to the semiconductor 1602 small, the insulator 1605 does not necessarily have to be provided.

For example, as the insulator 1605 and the insulator 1606, it is preferable to use a material containing silicon oxide or silicon nitride nitride. Alternatively, metal oxides such as aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, and hafnium oxide can also be used.

It is desirable that the insulator 1607 has a blocking effect to prevent the diffusion of oxygen, hydrogen and water. Alternatively, it is desirable that the insulator 1607 has a blocking effect of preventing the diffusion of hydrogen and water.

The denser and denser the insulator, and the less unbonded hands it is chemically stable, the higher the blocking effect. As an insulator showing a blocking effect that prevents the diffusion of oxygen, hydrogen, and water, for example, aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, and the like are used. , Can be formed. As the insulator showing a blocking effect of preventing the diffusion of hydrogen and water, for example, silicon nitride, silicon nitride oxide and the like can be used.

When the insulator 1607 has a blocking effect of preventing the diffusion of water, hydrogen, etc., it is possible to prevent the resin inside the panel and impurities such as water, hydrogen, etc. existing outside the panel from invading the semiconductor 1602. When an oxide semiconductor is used for the semiconductor 1602, a part of water or hydrogen that has entered the oxide semiconductor becomes an electron donor (donor). Therefore, by using the insulator 1607 having the blocking effect, the threshold value of the transistor 1600 is reached. It is possible to prevent the voltage from shifting due to the generation of donors.

Further, when an oxide semiconductor is used for the semiconductor 1602, the insulator 1607 has a blocking effect of preventing the diffusion of oxygen, so that oxygen from the oxide semiconductor can be prevented from diffusing to the outside. Therefore, since the oxygen deficiency as a donor is reduced in the oxide semiconductor, it is possible to prevent the threshold voltage of the transistor 1600 from shifting due to the generation of the donor.

It should be noted that this embodiment can be appropriately combined with other embodiments shown in the present specification.

(Embodiment 8)
In this embodiment, the structure of the oxide semiconductor film applicable to the OS transistor described in the above embodiment will be described.

<Structure of oxide semiconductor>
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudoamorphic oxide semiconductor (a-likeOS). : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another viewpoint, the oxide semiconductor is divided into an amorphous oxide semiconductor and other crystalline oxide semiconductors. Examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic and have no anisotropic structure, the arrangement of atoms is not fixed in a metastable state, the bond angle is flexible, and short-range order is present but long-range order is present. It is said that it does not have.

That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic, but has an unstable structure having voids (also referred to as voids). In terms of instability, the a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, CAAC-OS will be described.

CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis oriented crystal portions (also referred to as pellets).

A case where CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by the out-of-plane method is performed on CAAC-OS having crystals of InGaZnO ₄ classified in the space group R-3m, the diffraction angle (2θ) is as shown in FIG. 32 (A). A peak appears near 31 °. Since this peak is attributed to the (009) plane of the crystal of InGaZnO ₄ , in CAAC-OS, the crystal has c-axis orientation and the c-axis forms the CAAC-OS film (formed). It can be confirmed that the surface is oriented substantially perpendicular to the surface) or the upper surface. In addition to the peak near 31 ° in 2θ, a peak may appear near 36 ° in 2θ. The peak in which 2θ is in the vicinity of 36 ° is due to the crystal structure classified into the space group Fd-3m. Therefore, it is preferable that CAAC-OS does not show the peak.

On the other hand, when structural analysis is performed by the in-plane method in which X-rays are incident on CAAC-OS from a direction parallel to the surface to be formed, a peak appears in the vicinity of 2θ at 56 °. This peak is attributed to the (110) plane of the crystal of InGaZnO ₄ . Then, even if 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), it is clear as shown in FIG. 32 (B). No peak appears. On the other hand, when 2θ is fixed in the vicinity of 56 ° and φ-scanned with respect to the single crystal InGaZnO ₄ , six peaks attributed to the crystal plane equivalent to the (110) plane are observed as shown in FIG. 32 (C). Will be done. Therefore, from the structural analysis using XRD, it can be confirmed that the orientation of the a-axis and the b-axis of CAAC-OS is irregular.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam having a probe diameter of 300 nm is incident on CAAC-OS having a crystal of InGaZnO ₄ in parallel with the surface to be formed of CAAC-OS, a diffraction pattern (selected area) as shown in FIG. 32 (D) is applied. An electronic diffraction pattern) may appear. This diffraction pattern includes spots due to the (009) plane of the crystal of InGaZnO ₄ . Therefore, it can be seen from the electron diffraction that the pellets contained in CAAC-OS have c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. On the other hand, FIG. 32 (E) shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. From FIG. 32 (E), a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation even by electron diffraction using an electron beam having a probe diameter of 300 nm. It is considered that the first ring in FIG. 32 (E) is caused by the (010) plane and the (100) plane of the crystal of InGaZnO ₄ . Further, it is considered that the second ring in FIG. 32 (E) is caused by the (110) plane or the like.

In addition, when observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image of CAAC-OS and a diffraction pattern with a transmission electron microscope (TEM), multiple pellets can be confirmed. Can be done. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, the grain boundary (also referred to as grain boundary) may not be clearly confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries.

FIG. 33 (A) shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction substantially parallel to the sample surface. The spherical aberration correction (Spherical Aberration Director) function was used for observing the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed, for example, with an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 33 (A), pellets, which are regions where metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellets can also be referred to as nanocrystals (nc: nanocrystals). Further, CAAC-OS can also be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellet reflects the unevenness of the formed surface or upper surface of CAAC-OS and is parallel to the formed surface or upper surface of CAAC-OS.

Further, FIGS. 33 (B) and 33 (C) show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. 33 (D) and 33 (E) are images obtained by image-processing FIGS. 33 (B) and 33 (C), respectively. The method of image processing will be described below. First, an FFT image is acquired by performing a fast Fourier transform (FFT: Fast Fourier Transform) process on FIG. 33 (B). Next, in the acquired FFT image, mask processing is performed to leave a range between 2.8 nm ^-1 and 5.0 nm ^-1 with respect to the origin. Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image thus obtained is called an FFT filtering image. The FFT filtering image is an image obtained by extracting a periodic component from a Cs-corrected high-resolution TEM image, and shows a grid array.

In FIG. 33 (D), the disordered portion of the lattice arrangement is shown by a broken line. The area surrounded by the broken line is one pellet. The part indicated by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to the regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 33 (E), the area between the region where the grid arrangement is aligned and the region where another grid arrangement is aligned is shown by a dotted line, and the direction of the grid arrangement is shown by a broken line. A clear grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding grid points around the grid points near the dotted line, a distorted hexagon, pentagon and / or heptagon can be formed. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. Conceivable.

As shown above, CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, CAAC-OS can also be referred to as an oxide semiconductor having a CAA crystal (c-axis-aligned a-b-plane-anchored crystal).

CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of an oxide semiconductor may decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.).

Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than a metal element constituting an oxide semiconductor, deprives the oxide semiconductor of oxygen, disturbs the atomic arrangement of the oxide semiconductor, and lowers the crystallinity. It becomes a factor. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may fluctuate due to light, heat, or the like. For example, impurities contained in an oxide semiconductor may be a carrier trap or a carrier generation source. For example, oxygen deficiency in an oxide semiconductor may become a carrier trap or a carrier generation source by capturing hydrogen.

CAAC-OS, which has few impurities and oxygen deficiency, is an oxide semiconductor having a low carrier density. Specifically, carriers of less than 8 × 10 ¹¹ cm ^-3 , preferably less than 1 × 10 ¹¹ cm ^-3 , more preferably less than 1 × 10 ¹⁰ cm ^-3 , and 1 × 10 ^-9 cm ^-3 or more. It can be a density oxide semiconductor. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

The case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on nc-OS by the out-of-plane method, a peak indicating orientation does not appear. That is, the crystals of nc-OS have no orientation.

Further, for example, when nc-OS having a crystal of InGaZnO ₄ is sliced and an electron beam having a probe diameter of 50 nm is incident on a region having a thickness of 34 nm in parallel with the surface to be formed, FIG. 34 (A) shows. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. Further, FIG. 34 (B) shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 34 (B), a plurality of spots are observed in the ring-shaped region. Therefore, the order of the nc-OS is not confirmed by incident an electron beam having a probe diameter of 50 nm, but the order is confirmed by incident an electron beam having a probe diameter of 1 nm.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. 34 (C). May occur. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in the range of the thickness of less than 10 nm. Since the crystals are oriented in various directions, there are some regions where regular electron diffraction patterns are not observed.

FIG. 34 (D) shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the surface to be formed. The nc-OS has a region in which a crystal portion can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal portion contained in nc-OS has a size of 1 nm or more and 10 nm or less, and in particular, it often has a size of 1 nm or more and 3 nm or less. An oxide semiconductor having a crystal portion larger than 10 nm and 100 nm or less may be referred to as a microcrystalline oxide semiconductor. In the nc-OS, for example, the crystal grain boundaries may not be clearly confirmed in a high-resolution TEM image. It should be noted that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystal portion of nc-OS may be referred to as a pellet.

As described above, the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

Since the crystal orientation is not regular among the pellets (nanocrystals), the nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor having higher regularity than the amorphous oxide semiconductor. Therefore, the defect level density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in crystal orientation between different pellets. Therefore, the defect level density of nc-OS is higher than that of CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

FIG. 35 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 35 (A) is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 35 (B) is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . From FIGS. 35 (A) and 35 (B), it can be seen that in the a-like OS, a striped bright region extending in the vertical direction is observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is presumed to be a void or a low density region.

Due to the presence of voids, the a-like OS has an unstable structure. In the following, in order to show that the a-like OS has an unstable structure as compared with CAAC-OS and nc-OS, the structural change due to electron irradiation is shown.

Prepare a-like OS, nc-OS and CAAC-OS as samples. Both samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Due to the high resolution cross-sectional TEM image, each sample has a crystal part.

The unit cell of the crystal of InGaZnO ₄ has a structure in which a total of 9 layers are stacked in a layered manner in the c-axis direction, having 3 In—O layers and 6 Ga—Zn—O layers. Are known. The spacing between these adjacent layers is about the same as the grid plane spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, in the following, the portion where the interval between the plaids is 0.28 nm or more and 0.30 nm or less is regarded as the crystal portion of InGaZnO ₄ . The plaids correspond to the ab planes of the InGaZnO ₄ crystal.

FIG. 36 is an example of investigating the average size of the crystal portions (22 to 30 locations) of each sample. The length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 36, it can be seen that in the a-like OS, the crystal portion becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of a TEM image or the like. From FIG. 36, the crystal portion (also referred to as the initial nucleus) having a size of about 1.2 nm at the initial stage of observation by TEM has a cumulative irradiation amount of electrons (e ⁻ ) of 4.2 × ¹⁰⁸ e ⁻ / nm. In ² , it can be seen that it has grown to a size of about 1.9 nm. On the other hand, in nc-OS and CAAC-OS, there is no change in the size of the crystal part in the range where the cumulative irradiation amount of electrons is 4.2 × 10 ⁸ e ⁻ / nm ² from the start of electron irradiation. I understand. From FIG. 36, it can be seen that the sizes of the crystal portions of nc-OS and CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative irradiation amount of electrons. A Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × ¹⁰⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, growth of the crystal portion may be observed by electron irradiation. On the other hand, in nc-OS and CAAC-OS, almost no growth of the crystal portion due to electron irradiation is observed. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

Further, since it has a void, the a-like OS has a structure having a lower density than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. Further, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal having the same composition. Oxide semiconductors having a density of less than 78% of a single crystal are difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of the single crystal InGaZnO ₄ having a rhombohedral crystal structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ³ . .. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm ³ or more and 6.3 g /. It is less than cm ³ .

When a single crystal having the same composition does not exist, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, and each has various characteristics. The oxide semiconductor may be, for example, a laminated film having two or more of amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

It should be noted that this embodiment can be appropriately combined with other embodiments shown in the present specification.

(Additional notes regarding the description of this specification, etc.)
The description of each configuration in the above embodiments will be described below.

<Supplementary note concerning one aspect of the present invention described in the embodiment>
The configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

It should be noted that the content described in one embodiment (may be a part of the content) is different from the content described in the embodiment (may be a part of the content) and one or more different implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).

In addition, the content described in the embodiment is the content described by using various figures or the content described by using the text described in the specification in each embodiment.

It should be noted that the figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more different figures. By combining at least one figure with the figure (which may be a part) described in the embodiment, more figures can be formed.

<Additional notes on ordinal numbers>
In the present specification and the like, the ordinal numbers "first", "second", and "third" are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. Further, for example, the component referred to in "first" in one of the embodiments of the present specification and the like is regarded as another embodiment or the component referred to in "second" in the scope of claims. It is possible. Further, for example, the component referred to in "first" in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the scope of claims.

<Additional notes regarding the description explaining the drawings>
The embodiment is described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments, and the embodiments and details can be variously changed without departing from the spirit and scope thereof. To. Therefore, the present invention is not construed as being limited to the description of the embodiments. In the configuration of the invention of the embodiment, the same reference numerals are commonly used between different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted.

Further, in the present specification and the like, words and phrases indicating arrangements such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. The positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, the phrase indicating the arrangement is not limited to the description described in the specification, and can be appropriately paraphrased according to the situation.

Further, the terms "upper" and "lower" do not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other. For example, in the case of the expression "electrode B on the insulating layer A", the electrode B does not have to be formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.

Further, in the present specification and the like, in the block diagram, the components are classified by function and shown as blocks independent of each other. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved in a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately paraphrased according to the situation.

Further, in the drawings, the size, the thickness of the layer, or the area are shown in any size for convenience of explanation. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in the signal, voltage, or current due to noise, or variations in the signal, voltage, or current due to timing deviation.

Further, in the drawings, in order to ensure the clarity of the drawings in the top view (also referred to as a plan view or a layout view) or a perspective view, the description of some components may be omitted.

Further, in the drawings, the same elements or elements having the same function, elements of the same material, elements formed at the same time, etc. may be designated by the same reference numerals, and the repeated description thereof may be omitted. ..

<Additional notes regarding paraphrasable descriptions>
In the present specification and the like, when explaining the connection relationship of transistors, one of the source and the drain is referred to as "one of the source or the drain" (or the first electrode or the first terminal), and the source and the drain are referred to. The other is referred to as "the other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of the transistor change depending on the structure of the transistor, operating conditions, and the like. The names of the source and drain of the transistor can be appropriately paraphrased according to the situation, such as the source (drain) terminal and the source (drain) electrode. Further, in the present specification and the like, the two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal. Further, when the transistor described in the present specification or the like has two or more gates (this configuration may be referred to as a dual gate structure), those gates may be referred to as a first gate and a second gate, or a front gate. , May be called a back gate. In particular, the phrase "front gate" can be simply paraphrased into the phrase "gate". The bottom gate refers to a terminal formed before the channel formation region when the transistor is manufactured, and the "top gate" is formed after the channel formation region when the transistor is manufactured. Transistor terminal.

Transistors have three terminals called gates, sources, and drains. The gate is a terminal that functions as a control terminal that controls the conduction state of the transistor. The two input / output terminals that function as sources or drains are one source and the other drain depending on the type of transistor and the high and low potentials given to each terminal. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably. Further, in the present specification and the like, the two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal.

Further, in the present specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring" and vice versa. Further, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally formed.

Further, in the present specification and the like, the voltage and the potential can be paraphrased as appropriate. The voltage is a potential difference from a reference potential. For example, if the reference potential is a ground potential (ground potential), the voltage can be paraphrased as a potential. The ground potential does not always mean 0V. The potential is relative, and the potential given to the wiring or the like may be changed depending on the reference potential.

In the present specification and the like, terms such as "membrane" and "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer". Or, in some cases, or depending on the situation, it is possible to replace the term with another term without using the terms such as "membrane" and "layer". For example, it may be possible to change the term "conductive layer" or "conductive" to the term "conductor". Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

In the present specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "wiring" to the term "signal line". Further, for example, it may be possible to change the term "wiring" to a term such as "power line". The reverse is also true, and it may be possible to change terms such as "signal line" and "power line" to the term "wiring". A term such as "power line" may be changed to a term such as "signal line". The reverse is also true, and a term such as "signal line" may be changed to a term such as "power line". Further, the term "potential" applied to the wiring may be changed to a term such as "signal" in some cases or depending on the situation. The reverse is also true, and terms such as "signal" may be changed to the term "potential".

<Additional notes regarding the definition of words and phrases>
Hereinafter, the definitions of the terms and phrases referred to in the above embodiments will be described.

<< About semiconductors >>
In the present specification, even when the term "semiconductor" is used, for example, when the conductivity is sufficiently low, it may have characteristics as an "insulator". In addition, the boundary between "semiconductor" and "insulator" is ambiguous, and it may not be possible to make a strict distinction. Therefore, the "semiconductor" described in the present specification may be paraphrased as an "insulator". Similarly, the "insulator" described herein may be paraphrased as a "semiconductor."

Further, even when the term "semiconductor" is used, for example, if the conductivity is sufficiently high, it may have characteristics as a "conductor". In addition, the boundary between "semiconductor" and "conductor" is ambiguous, and it may not be possible to strictly distinguish them. Therefore, the "semiconductor" described in the present specification may be paraphrased as a "conductor". Similarly, the "conductor" described herein may be paraphrased as a "semiconductor."

The semiconductor impurities are, for example, other than the main components constituting the semiconductor layer. For example, an element having a concentration of less than 0.1 atomic% is an impurity. The inclusion of impurities may cause, for example, the formation of DOS (Density of States) in the semiconductor, the decrease in carrier mobility, the decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, group 1 element, group 2 element, group 13 element, group 14 element, group 15 element, and other than the main component. There are transitional metals and the like, and in particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of oxide semiconductors, oxygen deficiency may be formed by mixing impurities such as hydrogen. When the semiconductor is a silicon layer, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements excluding oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

<< About Transistor >>
As used herein, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel forming region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current is passed through the drain, the channel forming region and the source. It can be shed. In the present specification and the like, the channel forming region means a region in which a current mainly flows.

Further, the functions of the source and the drain may be switched when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably.

<< About the switch >>
In the present specification and the like, the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows. Alternatively, the switch means a switch having a function of selecting and switching a path through which a current flows.

As an example, an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.

Examples of electrical switches include transistors (eg, bipolar transistors, MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, shotkey diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes). , Diode-connected transistors, etc.), or logic circuits that combine these.

When a transistor is used as a switch, the "conduction state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Further, the "non-conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically cut off. When the transistor is operated as a simple switch, the polarity (conductive type) of the transistor is not particularly limited.

An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology, such as a Digital Micromirror Device (DMD). The switch has an electrode that can be moved mechanically, and by moving the electrode, conduction and non-conduction are controlled and operated.

<< About channel length >>
In the present specification and the like, the channel length is defined as, for example, in the top view of the transistor, a region or a channel where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap is formed. The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region.

In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

<< About channel width >>
In the present specification and the like, the channel width is, for example, a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap in a top view, or a region where a channel is formed. The length of the part where the source and drain face each other.

In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as an apparent channel width). ) And may be different. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap, is referred to as “enclosure channel width (SCW)”. : Surrounded Channel With) ". Further, in the present specification, when simply described as a channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by acquiring a cross-sectional TEM image or the like and analyzing the image. can.

When calculating the electric field effect mobility of the transistor, the current value per channel width, or the like, the enclosed channel width may be used for calculation. In that case, the value may be different from the case calculated using the effective channel width.

<< About high level potential and low level potential >>
In the present specification, when it is described that a high level potential is applied to a certain wiring, is the high level potential a potential of a magnitude large enough to make an n-type transistor having a gate connected to the wiring in a conductive state? Or, it may indicate at least one of the potentials having a potential that causes the p-type transistor having a gate connected to the wiring to be in a non-conducting state. Therefore, when high level potentials are applied to two or more different wirings, the magnitudes of the high level potentials applied to the respective wirings may differ from each other.

In the present specification, when it is described that a low level potential is applied to a certain wiring, the low level potential is a potential of a magnitude large enough to make an n-type transistor having a gate connected to the wiring non-conducting state. Or, it may indicate at least one of the potentials having a potential that makes the p-type transistor having a gate connected to the wiring conductive. Therefore, when low level potentials are applied to two or more different wirings, the magnitudes of the low level potentials applied to the respective wirings may differ from each other.

<< About connection >>
In the present specification and the like, when it is described that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y are functionally connected. And the case where X and Y are directly connected. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and includes the connection relationship other than the connection relationship shown in the figure or text.

It is assumed that X, Y and the like used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is displayed. One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion, etc.) Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the potential level of the signal, etc.), voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, storage circuits, control circuits, etc.) are X and Y. It is possible to connect one or more in between. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. do.

When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element between X and Y). Or when it is connected by sandwiching another circuit) and when X and Y are functionally connected (that is, when they are functionally connected by sandwiching another circuit between X and Y). (When) and the case where X and Y are directly connected (that is, the case where another element or another circuit is not sandwiched between X and Y) is included. In other words, the case where it is explicitly stated that it is electrically connected is the same as the case where it is simply stated that it is simply connected.

Note that, for example, the source of the transistor (or the first terminal, etc.) is electrically connected to X via (or not) Z1, and the drain of the transistor (or the second terminal, etc.) connects Z2. Through (or not), if electrically connected to Y, or if the source of the transistor (or the first terminal, etc.) is directly connected to one part of Z1 and another part of Z1. Is directly connected to X, the drain of the transistor (or the second terminal, etc.) is directly connected to one part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, "X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) (Terminals, etc.), transistor drains (or second terminals, etc.), and Y are electrically connected in this order. " Or, "the source of the transistor (or the first terminal, etc.) is electrically connected to X, the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (such as the second terminal). Or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. " Or, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor. The terminals, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. " By defining the order of connections in the circuit configuration using the same representation as these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. It should be noted that these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1 and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Even if the circuit diagram shows that the independent components are electrically connected to each other, the case where one component has the functions of a plurality of components together. There is also. For example, when a part of the wiring also functions as an electrode, one conductive film has both the function of the wiring and the function of the component of the function of the electrode. Therefore, the electrical connection in the present specification also includes the case where one conductive film has the functions of a plurality of components in combination.

<< Parallel and vertical >>
As used herein, the term "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

<< About trigonal crystals and rhombohedral crystals >>
In the present specification, when a crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

DA, DB0 analog voltage signal DA, DB1 analog voltage signal DA, DB2 analog voltage signal DA, DB3 analog voltage signal DA, DB4 analog voltage signal DA, DB5 analog voltage signal DA, DB6 analog voltage signal DA, DB7 analog voltage signal CLOCK clock Signal CLOCKB Clock signal CMCLK Clock signal STBY Standby signal CMSTBY Standby signal CMSET Set signal GL_1 Scanning line GL_1 Scanning line GL_m Scanning line GL_X Scanning line DL_1 Data line DL_1 Data line DL_n Data line DL_Y Data line VL_a Potential supply line VL_b GNDL Wiring VRL Wiring VRL1 Wiring VRL2 Wiring VRL3 Wiring VRL [1] Wiring VRL [i] Wiring VRL [k] Wiring VRLa Wiring VRLa1 Wiring VRLa2 Wiring VRLb Wiring VRLb1 Wiring VRL Wire L6 Wire L [1] Wire L [i 1] Wire L [k] Wire L [k + ₁ ] Wire L [i ₂ ] Wire L [2k] Wire STBYL Wire STBYL-B Wire BGLS1 Wire BGLS2 Wire RT1 Transistor RT2 Transistor RT3 Transistor RT [1] Transistor RT [i] Transistor RT [k] Transistor ST11 Transistor ST12 Transistor ST1 [1] Transistor ST1 [i] Transistor ST1 [k] Transistor ST21 Transistor ST22 Transistor ST2 [1] Transistor ST2 [i] Transistor ST2 [K] Transistor ST31 Transit ST32 Transistor ST3 [1] Transistor ST3 [i] Transistor ST3 [k] Transistor STB1 [1] Transistor STB1 [i] Transistor STB1 [k] Transistor STB3 [1] Transistor STB3 [i] Transistor STB3 [i] k] Transistor Tr [1,1] Transistor Tr [2,1] Transistor Tr [3,1] Transistor Tr [4,1] Transistor Tr [1,2] Transistor Tr [2,3] Transistor Tr [3,3] ] Transistor Tr [4,3] Transistor Tr [1,4] Transistor Tr [2,4] Transistor Tr [3, 4] Transistor Tr [4,4] Transistor Tr [6,6] Transistor Tr [2k, 2k] Transistor N1 node N2 node N3 node N4 node LA1 wiring LA2 wiring IN input terminal OUT output terminal AT1 transistor AT2 transistor AT3 transistor AT4 transistor AT5 Transistor AT6 Transistor AT7 Transistor AT8 Transistor AT9 Transistor AT10 Transistor AT11 Transistor AT12 Transistor AT13 Transistor AT14 Transistor AT15 Transistor AT16 Transistor AT17 Transistor AT18 Transistor AT19 Transistor AT20 Transistor AST1 Transistor AST2 Transistor S1 Metal oxide S2 Metal oxide S3 Metal oxide I1 Insulation Body I2 Insulator CLx wiring CLy wiring 100 Source driver circuit 110 LVDS receiver 120 Serial parallel conversion circuit 130 Shift register circuit 140 Latch circuit 150 Level shifter circuit 160 Pass transistor Logic circuit 170 Resistance string circuit 180 External correction circuit 190 BGR circuit 200 Bias generator 200A Bias generator 200A1 Bias generator 200A2 Bias generator 200A3 Bias generator 200B Bias generator 200B1 Bias generator 200B2 Bias generator 200B3 Bias generator 200B4 Bias generator 200B5 Bias generator 201 Circuit 202 Circuit 203 Circuit 204 Circuit 205 Circuit 300 Buffer amplifier 1200a Transistor 1200b Transistor 1200c Transistor 1205 Body 1205a Transistor 1205b Transistor 1214 Insulator 1216 Insulator 1220 Insulator 1222 Insulator 1224 Insulator 1230 Metal oxide 1230a Metal oxide 1230b Metal oxide 1230c Metal oxide 1240a Conductor 1240b Conductor 1241a Conductor 1241b Conductor 1245a Region 1245b Region 1250 Insulator 1260 Conductor 1260a Conductor 1260b Conductor 1270 Insulator 1280 Insulator 1400 Transistor 1401 Insulator 1402 Insulator 1403 Insulator 1404 Insulator 1406 Insulator 1407 Insulator 1408 Insulator 1409 Insulator 1412 Conductor 1414 Conductor 1430 Metal oxide 1431 Metal oxide 1432 Metal oxide 1433 Metal oxide 1450 Substrate 1451 Low resistance region 1452 Low resistance region 1461a Region 1461b Region 1461c Region 1461d Region 1461e Region 1600 Transistor 1601 Insulator 1602 Semiconductor 1603 Conductor 1604 Conductor 1605 Insulator 1606 Insulator 1607 Insulator 1608 Conductor 1609 Conductor 3301 Pixel circuit 3302 Pixel part 3304 Drive circuit unit 3304a Gate driver Circuit 3304b Source driver Circuit 3306 Protection circuit 3307 Terminal 3352 Transistor 3354 Transistor 3362 Capacitive element 3372 Light emitting element 3411 Wiring 3412 Wiring 3413 Wiring 3414 Wiring 3415 Wiring 3416 Wiring 3417 Wiring 3421 Wiring 3422 Wiring 3431 Transistor 3432 Transistor 3433 Transistor 3434 Transistor 3435 Transistor 3437 Transistor 3440 Capacitive element 3441 Capacitive element 3445 Light emitting element 3461 Wiring 3462 Wiring 3464 Wiring 3471 Wiring 3472 Wiring 3473 Wiring 348 1 Transistor 3482 Transistor 3484 Transistor 3484 Transistor 3485 Transistor 3486 Transistor 3491 Transistor 3492 Transistor 3511 Wiring 35 Wiring 3522 Wiring 3600 Liquid crystal display device 3610 Pixel part 3611 Pixel 3620 Scanning line drive circuit 3621 Scanning line 3622 Capacitive wiring 3630 Signal line drive circuit 3631 Signal line 3461 Transistor 3642 Capacitive element 3634 Liquid crystal element 3711 Display unit 3712 Source driver 3712A Gate driver 3712B Gate Driver 3713 Board 3714 Source driver IC
3715 FPC
3716 External circuit board 3800 Display device 3811 Display unit 3812 Pixel 3813 Scanning line drive circuit 3814 Touch sensor 3816 Host 3820_1 IC
3820_2 IC
3820_m IC
3821_1 circuit 3821_1 circuit 3821_m circuit 3822_1 signal line drive circuit 3822_2 signal line drive circuit 3822_m signal line drive circuit 3824 touch sensor detection circuit 3823 touch sensor drive circuit 3825_1 image processing circuit 3825_1 image processing circuit 3825_m image processing circuit 3826_1 RAM
3826_2 RAM
3826_m RAM
3827 CPU
3828 Timing controller 3829 Capacitive element 4000 Display module 4001 Top cover 4002 Bottom cover 4003 FPC
4004 Touch panel 4005 FPC
4006 Display panel 4009 Frame 4010 Printed circuit board 4011 Battery 5001 Housing 5002 Display unit 5003 Stand 5004 Remote control operation machine 5201 Housing 5202 Housing 5203 Display unit 5204 Display unit 5205 Microphone 5206 Speaker 5207 Operation key 5208 Stylus 5401 Housing 5402 Display unit 5403 Keyboard 5404 Pointing device 5501 Housing 5502 Display 5503 Microphone 5504 Speaker 5505 Operation button 5601 1st housing 5602 2nd housing 5603 1st display 5604 2nd display 5605 Connection 5606 Operation key 5701 Body 5702 Wheel 5703 Dashboard 5704 Light 5801 1st chassis 5802 2nd chassis 5803 Display unit 5804 Operation key 5805 Lens 5806 Connection unit 5901 Housing 5902 Display unit 5903 Operation button 5904 Operation button 5905 Band 6000 Housing 6001 Display unit 6003 Speaker

Claims (18)

A semiconductor device having first to fifth circuits and a plurality of wirings.
The first circuit has a first input terminal and a plurality of first output terminals .
The second circuit has a plurality of second input terminals and a plurality of second output terminals.
The plurality of second output terminals include a first terminal group and a second terminal group.
The plurality of first output terminals of the first circuit are electrically connected to the plurality of wirings on a one-to-one basis.
The plurality of wires are electrically connected to the plurality of second input terminals on a one-to-one basis.
The first circuit has a function of applying different potentials to each of the plurality of second input terminals according to the current input to the first input terminal when the semiconductor device is in the driving state. ,
The second circuit is different from the plurality of second output terminals having twice the number of the plurality of wirings by using all the potentials from the plurality of wirings when the semiconductor device is in the driving state. It has a function to output a bias voltage and has a function to output a bias voltage.
The plurality of third output terminals of the third circuit are electrically connected to the plurality of wires on a one-to-one basis.
The plurality of fourth output terminals of the fourth circuit are electrically connected to the first terminal group on a one-to-one basis.
The plurality of fifth output terminals of the fifth circuit are electrically connected to the second terminal group on a one-to-one basis.
The third circuit has a function of applying a low level potential to each of the plurality of wirings when the semiconductor device is in the standby state.
The fourth circuit has a function of outputting a high level potential to the first terminal group of the plurality of output terminals when the semiconductor device is in the standby state.
The fifth circuit is a semiconductor device having a function of outputting a low level potential to a second terminal group of the plurality of output terminals when the semiconductor device is in a standby state. A semiconductor device having first to fifth circuits and first to k-th wiring (k is an integer of 2 or more).
The first circuit has an input terminal and first to kth output terminals .
The second circuit has a first to kth input terminal and a first to (2k) output terminal.
The first to kth output terminals of the first circuit are electrically connected to the first to kth wiring on a one-to-one basis.
The first to kth wirings are electrically connected to the first to kth input terminals of the second circuit on a one-to-one basis.
The first circuit has a function of applying a first to kth potential to the first to kth wirings, respectively, according to a current input to the input terminal when the semiconductor device is in a driving state. ,
The second circuit uses all the first to kth potentials input from the first to kth wirings when the semiconductor device is in the driving state, and the first to second circuits of the second circuit are used. 2k) It has a function to output the first (k + 1) to the (3k) potentials from the output terminals, respectively.
The first to kth output terminals of the third circuit are electrically connected to the first to kth wirings on a one-to-one basis.
The first to kth output terminals of the fourth circuit are electrically connected to the first to kth output terminals of the second circuit on a one-to-one basis.
The first to kth output terminals of the fifth circuit are electrically connected to the first (k + 1) to (2k) output terminals of the second circuit on a one-to-one basis.
The third circuit has a function of applying a low level potential to the first to kth wirings when the semiconductor device is in the standby state.
The fourth circuit has a function of outputting a high level potential to the first to kth output terminals of the second circuit when the semiconductor device is in the standby state.
The fifth circuit is characterized by having a function of outputting a low level potential to the first (k + 1) to (2k) output terminals of the second circuit when the semiconductor device is in the standby state. .. In claim 2,
The first circuit has first to kth transistors and has.
The first terminal of the first transistor is electrically connected to the input terminal and is connected to the input terminal.
Each of the first terminals of the first to kth transistors is electrically connected to each of the first to kth output terminals of the first circuit on a one-to-one basis.
Each of the first terminals of the first to kth transistors is electrically connected to each of the gates of the first to kth transistors on a one-to-one basis.
A semiconductor device characterized in that each of the second terminals of the first to (k-1) transistors is electrically connected to each of the first terminals of the second to k-transistors on a one-to-one basis. .. In claim 3,
The first to kth transistors are semiconductor devices having an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin) and zinc in a channel forming region. .. In any one of claims 2 to 4,
The third circuit has first (k + 1) to third (2k) transistors.
Each of the first terminals of the first (k + 1) to (2k) transistor is electrically connected to each of the first to k output terminals of the third circuit on a one-to-one basis.
A semiconductor device characterized in that the gates of the first (k + 1) to (2k) transistors are electrically connected to each other. In claim 5,
The first (k + 1) to (2k) transistors are characterized by having an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin) and zinc in the channel forming region. Semiconductor device. In claim 6,
At least one of the first (k + 1) to (2k) transistors has a back gate and has a back gate.
A semiconductor device characterized by shifting the threshold voltage of a transistor having the back gate by applying a potential to the back gate. In any one of claims 2 to 7,
The fourth circuit has first (2k + 1) to third (3k) transistors.
Each of the first terminals of the first (2k + 1) to (3k) transistors is electrically connected one-to-one with each of the first to k output terminals of the fourth circuit .
A semiconductor device characterized in that the gates of the first (2k + 1) to (3k) transistors are electrically connected to each other. In claim 8,
The third (2k + 1) to (3k) transistor is a semiconductor device characterized by being a p-channel type transistor. In any one of claims 2 to 9,
The fifth circuit has third (3k + 1) to (4k) transistors.
Each of the first terminals of the first (3k + 1) to (4k) transistors is electrically connected one-to-one with each of the first to k output terminals of the fifth circuit .
A semiconductor device characterized in that the gates of the first (3k + 1) to (4k) transistors are electrically connected to each other. In claim 10,
The first (3k + 1) to (4k) transistors are characterized by having an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin) and zinc in the channel forming region. Semiconductor device. In claim 11,
At least one of the first (3k + 1) to (4k) transistors has a back gate.
A semiconductor device characterized by shifting the threshold voltage of a transistor having the back gate by applying a potential to the back gate. In any one of claims 2 to 12,
The second circuit has (2k) transistors in the row direction and (2k) transistors in the column direction, for a total of (4k ² ) transistors.
In the transistor of the second circuit, (2k) transistors are connected in series in the column direction, respectively.
Of the transistors in the first to kth columns, the gates of the transistors in the first to kth rows are electrically connected in the column direction, respectively.
Of the transistors in the first to kth columns, the gates of the transistors in the (k + 1) to (2k) rows are electrically connected in the row direction, respectively.
Of the transistors in the first (k + 1) to (2k) columns, the gates of the transistors in the first to kth rows are electrically connected in the row direction, respectively.
Of the transistors in the first (k + 1) to (2k) columns, the gates of the transistors in the (k + 1) to (2k) rows are electrically connected in the column direction, respectively.
Of the transistors in the first column, the gates of the transistors in the (k + 1) to (2k) rows are electrically connected one-to-one with each of the first to k wirings.
Among the transistors in the first (2k) column, the gates of the transistors in the first to kth rows are electrically connected to each of the first to kth output terminals of the second circuit on a one-to-one basis.
The connection portion between the transistor in the kth row and the transistor in the (k + 1) th row in the jth column (j is 1 to (2k)) is set as the jth node.
Each of the j-nodes (j is 1 to k) is electrically connected to each of the k-first output terminals of the second circuit on a one-to-one basis.
The j-node (j is (k + 1) to (2k)) is electrically connected to each of the (2k) to (k + 1) th output terminals of the second circuit on a one-to-one basis. Semiconductor device. In claim 13,
Of the (4k ² ) transistors, the transistors in the first to kth rows are p-channel transistors.
A semiconductor device characterized in that, of the (4k ² ) transistors, the transistors in the (k + 1) to (2k) rows are n-channel transistors. In claim 14,
Of the (4k ² ) transistors, the transistors in the (k + 1) to (2k) rows have at least indium, element M (element M is aluminum, gallium, yttrium, or tin) and zinc in the channel forming region. A semiconductor device characterized by having an oxide containing any one of them. The drive circuit having the semiconductor device according to any one of claims 1 to 15.
A display device having a display unit. In claim 16, a display device including a touch sensor, a touch sensor drive circuit, and a touch sensor detection circuit. An electronic device having the display device according to claim 16 or claim 17, and a housing.

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