JP7028679B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

One aspect of the present invention relates to a semiconductor device and a method for driving the semiconductor device. Alternatively, one aspect of the invention relates to semiconductor wafers, modules and electronic devices.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of a semiconductor device. It may be said that a display device (liquid crystal display device, light emission display device, etc.), projection device, lighting device, electro-optic device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, and the like have a semiconductor device.

It should be noted that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).

Attention is being paid to a technique for constructing a transistor using a semiconductor thin film. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also referred to simply as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique for manufacturing a display device using a transistor having zinc oxide or an In—Ga—Zn-based oxide as an active layer as an oxide semiconductor is disclosed (see Patent Document 1 and Patent Document 2). ..

Further, in recent years, a technique for manufacturing an integrated circuit of a storage device using a transistor having an oxide semiconductor has been published (see Patent Document 3). Further, not only the storage device but also the arithmetic unit and the like have been manufactured by a transistor having an oxide semiconductor.

Japanese Unexamined Patent Publication No. 2007-123861 Japanese Unexamined Patent Publication No. 2007-96055 Japanese Unexamined Patent Publication No. 2011-119674

With the increase in performance, miniaturization, and weight reduction of electronic devices, integrated circuits have become highly integrated, and the process rules for manufacturing integrated circuits have become smaller year by year to 45 nm, 32 nm, and 22 nm. Along with this, semiconductor devices such as capacitive elements, resistance elements, and transistors having oxide semiconductors are also required to have good electrical characteristics as designed in a fine structure.

One aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device having a small off-current. Alternatively, one aspect of the present invention is to provide a transistor having a large on-current. Alternatively, one of the issues is to provide a capacitive element capable of high integration. Alternatively, one aspect of the present invention is to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention is to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention is to provide a highly productive semiconductor device.

Alternatively, one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. Alternatively, one aspect of the present invention is to provide a semiconductor device having a high information writing speed. Alternatively, one aspect of the present invention is to provide a semiconductor device having a high degree of freedom in design. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. Alternatively, one aspect of the present invention is to provide a novel semiconductor device.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. Is.

One aspect of the present invention includes a first insulator, second to sixth insulators arranged in an island shape on the first insulator, and oxides on the first to sixth insulators. , A first conductor located between the seventh insulator, the second insulator, and the third insulator on the oxide and in contact with the seventh insulator, and the third insulator. And a second conductor located between the fourth insulator and in contact with the seventh insulator, and between the fourth insulator and the fifth insulator, and the seventh insulator. A third conductor in contact with the insulator, a fourth conductor located between the fifth insulator and the sixth insulator, and in contact with the seventh insulator, and on the seventh insulator, And an eighth insulator on the first to fourth conductors, a ninth insulator on the eighth insulator, and the seventh insulator and the eighth insulator include: A first opening to reach the oxide is provided, and the seventh insulator, the eighth insulator, and the ninth insulator are provided with a second opening and a third opening to reach the oxide. The first opening is superimposed on the fourth insulator, the second opening is superimposed on the third insulator, the third opening is superimposed on the fifth insulator, and the first opening is superimposed. Is provided with a fifth conductor, a sixth opening is provided with a sixth conductor, a third opening is provided with a seventh conductor, and the third opening is provided with a seventh conductor on the fifth conductor. Is provided with an eighth insulator, a ninth insulator, a sixth insulator, and a tenth insulator in contact with the seventh insulator, which overlaps with the second opening and overlaps with the second opening. It is a semiconductor device in which a ninth conductor is provided in contact with a tenth insulator, overlapped with a third opening, and a tenth conductor is provided in contact with a tenth insulator.

Further, in one aspect of the present invention, the oxide, the seventh insulator and the second conductor constitute the first transistor, and the oxide, the seventh insulator and the third conductor are the first. The second transistor, the oxide, the seventh insulator and the first conductor constitute the third transistor, and the oxide, the seventh insulator and the fourth conductor are the fourth. The sixth conductor, the tenth insulator and the ninth conductor constitute the transistor, and the sixth conductor, the tenth insulator and the ninth conductor constitute the first capacitive element, and the seventh conductor, the tenth insulator and the tenth conductor. Consists of a second capacitive element, the first transistor and the second transistor are arranged between the first capacitive element and the second capacitive element, and the first capacitive element and the second capacitive element are arranged. Is located between the third transistor and the fourth transistor, one of the source or drain regions of the first transistor is connected to one electrode of the first capacitive element and the source of the second transistor. One of the region or drain region is connected to one electrode of the second capacitive element, and the other of the source or drain region of the first transistor is shared with the other of the source or drain region of the second transistor. , The other of the source or drain region of the first transistor, and the other of the source or drain region of the second transistor are connected to the eighth conductor, and the channel length of the first transistor is the second. A semiconductor device that is longer than the length in the direction parallel to the short side of the conductor and the channel length of the second transistor is longer than the length in the direction parallel to the short side of the third conductor.

Further, the eighth conductor is provided with the long side direction of the eighth conductor, the long side direction of the second conductor, and the long side direction of the third conductor substantially orthogonal to each other, and is oxidized. It is preferable that the object is provided so that the angle formed by the long side direction of the oxide and the long side direction of the eighth conductor is 20 ° or more and 70 ° or less.

Further, the oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.

According to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention can provide a semiconductor device having good electrical characteristics. Alternatively, according to one aspect of the present invention, a semiconductor device having a small off-current can be provided. Alternatively, one aspect of the present invention can provide a transistor having a large on-current. Alternatively, according to one aspect of the present invention, it is possible to provide a capacitive element capable of high integration. Alternatively, according to one aspect of the present invention, a highly reliable semiconductor device can be obtained. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

Alternatively, it is possible to provide a semiconductor device capable of retaining data for a long period of time. Alternatively, it is possible to provide a semiconductor device having a high information writing speed. Alternatively, it is possible to provide a semiconductor device having a high degree of freedom in design. Alternatively, it is possible to provide a semiconductor device capable of suppressing power consumption. Alternatively, a new semiconductor device can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. The circuit diagram of the semiconductor device which concerns on one aspect of this invention. Top view of the semiconductor device according to one aspect of the present invention. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. A circuit diagram and a sectional view showing a configuration of a storage device according to one aspect of the present invention. The block diagram which shows the structural example of the storage device which concerns on one aspect of this invention. A block diagram and a circuit diagram showing a configuration example of a storage device according to one aspect of the present invention. The figure explaining the power consumption of the storage device which concerns on one aspect of this invention. The schematic diagram of the semiconductor device which concerns on one aspect of this invention. The schematic diagram of the storage device which concerns on one aspect of this invention. The figure which shows the electronic device which concerns on one aspect of this invention.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that embodiments can be implemented in many different embodiments and that the embodiments and details can be varied in various ways without departing from the spirit and scope thereof. To. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may be omitted for ease of understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular reference numeral may be added.

Further, in order to facilitate understanding of the invention, in particular, in a top view (also referred to as a “plan view”) or a perspective view, the description of some components may be omitted. In addition, some hidden lines may be omitted.

Further, in the present specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Further, in the present specification and the like, words and phrases indicating arrangements such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

For example, in the present specification and the like, when it is explicitly stated that X and Y are directly connected and that X and Y are connected, X and Y are electric. It is assumed that the case where X and Y are functionally connected and the case where X and Y are functionally connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is also described in the figure or text.

Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Further, the functions of the source and the drain may be switched when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.

In the present specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor. (Hereinafter, also referred to as "apparent channel width") and may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the ratio of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

Further, depending on the structure of the transistor, the channel length in the region where the channel is actually formed (hereinafter, also referred to as “effective channel length”) and the channel length shown in the top view of the transistor (hereinafter, “apparently”). Also referred to as "channel length") and may differ. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel length may be larger than the apparent channel length, and the influence thereof may not be negligible. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the ratio of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel length is larger than the apparent channel length.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Further, in the present specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

The semiconductor impurities are, for example, other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may result in, for example, an increase in DOS (Density of States) of the semiconductor, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors. There are transition metals other than the main components of the above, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, water may also function as an impurity. Further, in the case of an oxide semiconductor, oxygen deficiency may be formed, for example, by mixing impurities. When the semiconductor is silicon, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements excluding oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

In the present specification and the like, silicon oxide is composed of silicon oxide having a higher oxygen content than nitrogen. Further, silicon nitride oxide has a higher nitrogen content than oxygen in its composition.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

In the present specification, the barrier membrane is a membrane having a function of suppressing the permeation of impurities such as hydrogen and oxygen, and when the barrier membrane has conductivity, it is referred to as a conductive barrier membrane. There is.

In the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS FET or an OS transistor, it can be rephrased as a transistor having an oxide or an oxide semiconductor.

Further, in the present specification and the like, normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the current per 1 μm of the channel width flowing through the transistor is 1 × 10 ^-20 at room temperature. A or less, 1 × 10 ^-18 A or less at 85 ° C, or 1 × 10 ^-16 A or less at 125 ° C.

(Embodiment 1)
The semiconductor device of one aspect of the present invention is a semiconductor device having an oxide in a channel forming region. In this embodiment, one embodiment of the semiconductor device will be described with reference to FIGS. 1 to 14.

<Semiconductor device configuration example>
Hereinafter, an example of a semiconductor device including a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a, and a capacitive element 100b according to one aspect of the present invention will be described. Hereinafter, one form of the semiconductor device will be described with reference to FIGS. 1 to 14.

1A and 2A are top views of a semiconductor device including a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a, and a capacitive element 100b. Further, FIGS. 1 (B) and 2 (B) are cross-sectional views of the portions shown by the alternate long and short dash lines in FIGS. 1 (A) and 2 (A). 2 (C) is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIGS. 1 (A) and 2 (A). In the top views of FIGS. 1 (A) and 2 (A), some elements are omitted for the sake of clarity of the figure. Further, FIG. 2 is a drawing in which each component of FIG. 1 is coded.

As shown in FIGS. 1 and 2, the semiconductor device of one aspect of the present invention includes a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a and a capacitive element 100b, and an insulator 210 that functions as an interlayer film. , Insulator 212, Insulator 280, and Insulator 283. Further, a conductor 240 that functions as a plug, a conductor 245 that is electrically connected to the conductor 240 and functions as a wiring, a conductor 110_1 that functions as a lower electrode of the capacitive element 100a, and a lower electrode of the capacitive element 100b. The conductor 110_2, which functions as a conductor 110_1, and the insulator 130, which is arranged on the conductor 110_1 and 110_2, and functions as a dielectric of the capacitive element 100a and the capacitive element 100b, and is arranged on the insulator 130. It has a conductor 120_1 that functions as an upper electrode of the capacitive element 100a, and a conductor 120_1 that is arranged on the insulator 130 and functions as an upper electrode of the capacitive element 100b.

Further, the transistor 200a and the transistor 200b are arranged between the capacitive element 100a and the capacitive element 100b, and the capacitive element 100a and the capacitive element 100b are arranged between the transistor 140a and the transistor 140b.

Further, as shown in FIGS. 1A and 2A, the angle of the oxide 230 in the long side direction with respect to the long side direction of the conductor 245 is 20 ° or more and 70 ° or less, preferably 30 °. It is preferable to arrange the conductor 245 and the oxide 230 so that the temperature is 60 ° or less. By arranging in this way, for example, the capacitive element 100a and the capacitive element 100b and the conductor 245 can be arranged without crossing each other.

Here, the transistor 200a and the transistor 200b have a point-symmetrical configuration centered on the point where the alternate long and short dash line between A1-A2 and the alternate long and short dash line between A5-A6 intersect at the site shown in FIG. 1 (A). is doing.

Similarly, the transistor 140a and the transistor 140b have a point-symmetrical configuration centered on the point where the alternate long and short dash line between A1-A2 and the alternate long and short dash line between A5-A6 intersect at the site shown in FIG. 1 (A). is doing.

Similarly, the capacitive element 100a and the capacitive element 100b have a point-symmetrical configuration centered on the point where the alternate long and short dash line between A1-A2 and the alternate long and short dash line between A5-A6 intersect at the site shown in FIG. 1 (A). have.

Further, it is preferable that the semiconductor device is provided with an insulator 280 so as to cover the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b. The insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the membrane.

The conductor 240 is formed so as to be in contact with the inner wall of the opening provided in the insulator 280. The oxide 230 is located at least in part of the bottom of the opening, and the conductor 240 is in contact with the oxide 230 (see FIG. 2B).

The conductor 240 may be formed after forming aluminum oxide on the side wall portion of the opening. By forming aluminum oxide on the side wall portion of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the conductor 240 from being oxidized. Further, it is possible to prevent impurities such as water and hydrogen from diffusing from the conductor 240 to the outside. The aluminum oxide can be formed by forming aluminum oxide on the openings by using the ALD method or the like and performing anisotropic etching.

The conductor 240 has a function as a plug for connecting one of the source or drain of the transistor 200a, one of the source or drain of the transistor 200b, and the conductor 245 functioning as wiring. With this configuration, the distance between the adjacent transistors 200a and the transistors 200b can be reduced. Therefore, the transistors can be arranged at a high density, and the semiconductor device can be highly integrated.

Further, the other of the source or drain of the transistor 200a and the capacitive element 100a are superposed and provided. Similarly, the other of the source or drain of the transistor 200b and the capacitive element 100b are superposed and provided.

Further, the conductor 110_1 that functions as a lower electrode of the capacitive element 100a is connected to the other of the source region or the drain region of the transistor 200a. Similarly, the conductor 110_2, which functions as the lower electrode of the capacitive element 100b, is connected to the other of the source region or the drain region of the transistor 200b.

In one aspect of the present invention, by connecting a plurality of capacitive elements and a plurality of transistors as described above, it is possible to provide a semiconductor device capable of miniaturization or high integration.

[Transistor 200a and Transistor 200b]
As shown in FIGS. 1 and 2, the transistor 200a includes an insulator 212 arranged on a substrate (not shown), a conductor 203_1 arranged so as to be embedded in the insulator 212, and a conductor. It covers the insulator 214 arranged on the 203_1 and the insulator 212, the insulator 220_2 and the insulator 220_3 arranged on the insulator 214, and the insulator 214, the insulator 220_2, and the insulator 220_3. It has an oxide 230 formed in, an insulator 250 on the oxide 230, and a conductor 260_2 located between the insulator 220_2 and the insulator 220_3 and in contact with the insulator 250.

Further, as shown in FIGS. 1 and 2, the transistor 200b includes an insulator 212 arranged on a substrate (not shown) and a conductor 203_2 arranged so as to be embedded in the insulator 212. Insulator 214 placed on the conductor 203_2 and on the insulator 212, insulator 220_3 and insulator 220_4 placed on the insulator 214, and insulator 214, insulator 220_3 and insulator 220_4. It has an oxide 230 formed to cover the oxide 230, an insulator 250 on the oxide 230, and a conductor 260_3 located between the insulator 220_3 and the insulator 220_4 and in contact with the insulator 250.

The transistor 200a and the transistor 200b show a configuration in which the oxide 230 is a single layer, but the present invention is not limited thereto. For example, a laminated structure having two layers, three layers, or four or more layers may be used.

Further, in the transistor 200a and the transistor 200b, the conductor 260_2 and the conductor 260_3 are shown in a two-layer structure, but the present invention is not limited thereto. For example, the conductor 260_2 and the conductor 260_3 may have a laminated structure of three or more layers.

Here, as described above, the transistor 200a and the transistor 200b are centered on the point where the alternate long and short dash line between A1-A2 and the alternate long and short dash line between A5-A6 intersect at the site shown in FIG. 1 (A). It has a symmetrical structure.

That is, the transistor 200b has a structure corresponding to that of the transistor 200a. Therefore, in the figure, in the transistor 200a and the transistor 200b, basically the same three-digit number is assigned as a code to the corresponding configuration. Further, in the following, unless otherwise specified, the description of the transistor 200a can be referred to for the transistor 200b.

As an example, the conductor 203_1 and the conductor 260_2 of the transistor 200a correspond to the conductor 203_2 and the conductor 260_3 of the transistor 200b, respectively.

The oxide 230 has a structure common to the transistor 200a and the transistor 200b. Therefore, the oxide 230 has a region that functions as a channel forming region of the transistor 200a, a region that functions as one of a source region or a drain region of the transistor 200a, a region that functions as a channel forming region of the transistor 200b, and a region of the transistor 200b. It has a region that functions as one of the source region or the drain region and a region that functions as the other of the source region or the drain region of the transistor 200a and the transistor 200b.

With the above configuration, a plug that is electrically connected to one of the source and the drain can be shared. In particular, the transistor 200a and the transistor 200b share the oxide 230 between the conductor 260_2 which functions as the first gate of the transistor 200a and the conductor 260_3 which functions as the first gate of the transistor 200b. May be the minimum processing dimension. By setting the distance between the conductor 260_2 and the conductor 260_3 to the minimum processing dimension, the area occupied by the two transistors can be reduced.

Examples of the oxide 230 include In—M—Zn oxide (element M is aluminum, gallium, ittrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium). , Neodim, Hafnium, Tantal, Tungsten, Magnesium, etc. (one or more) It is preferable to use an oxide semiconductor typified by a metal oxide. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. Alternatively, In—Ga oxide or In—Zn oxide may be used as the oxide 230.

Since the transistor 200a and the transistor 200b using the oxide semiconductor in the channel forming region have an extremely small leakage current in the non-conducting state, it is possible to provide a semiconductor device having low power consumption. Further, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for the transistor 200a and the transistor 200b constituting the highly integrated semiconductor device.

Here, an enlarged view of a region near the channel of the transistor 200a in FIG. 2B is shown in FIG. 6A.

As shown in FIG. 6A, the oxide 230 has a region 234 that functions as a channel forming region of the transistor 200a and a region 231 (region 231a and region 231b) that functions as a source region or a drain region of the transistor 200a. , Have. In FIG. 6A, the vicinity of the region 234 is shown by a broken line. In FIG. 6A, the position of the region 234 is shown near the center of the oxide 230 for the sake of clarity of the figure, but the present invention is not limited to this, and the position is not limited to this, but is near the interface between the oxide 230 and the insulator 250, or. It may be near the interface between the oxide 230 and the insulator 220_2, the insulator 220_3 and the insulator 214, or the entire oxide 230 in the range shown by the broken line.

The region 231 functioning as a source region or a drain region is a region having a low oxygen concentration, a high carrier density, and a low resistance. Further, the region 234 functioning as a channel forming region is a high resistance region having a higher oxygen concentration and a lower carrier density than the region 231 functioning as a source region or a drain region.

In the region 231 of the oxide 230, the resistance may be reduced at least in the vicinity of the surface of the oxide 230.

In the transistor 200a, each region of the oxide 230 forms a self-aligned and low resistance region by using the conductor 260_2 as a mask and adding an impurity or a metal element to the oxide 230. May be good. Further, in the transistor 200b, a region having a low resistance may be formed in a self-aligned manner by using the conductor 260_3 as a mask and adding an impurity or a metal element to the oxide 230. Therefore, when a plurality of semiconductor devices having the transistors 200a and the transistors 200b are formed at the same time, the variation in electrical characteristics between the semiconductor devices can be reduced.

Further, as shown in FIG. 6A, the channel length of the transistor 200a is substantially equal to the length of the region 234. The length of the region 234 is the length of the region where both sides of the conductor 260_1 and the oxide 230 are overlapped via the insulator 250, the bottom surface of the short side of the conductor 260_2, and the oxide 230. , Is approximately equal to the length of the overlapping regions via the insulator 250 plus the length. That is, the channel length of the transistor 200a can be longer than the length 260W in the direction parallel to the short side of the conductor 260_2. FIG. 6A shows the approximate length of the region 234 with a dotted line.

Since the channel length of the transistor 200a can be made longer than the length 260W, even if the transistor 200a is made finer and the length 260W is made finer, the channel length of the transistor 200a can be made longer than the length 260W, so that the transistor is short-circuited. The channel effect can be suppressed. The channel length of the transistor 200a is 1.5 times or more and 10 times or less the length of 260W.

Regarding the configuration and effect of the transistor 200b, the configuration and effect of the transistor 200a described above can be taken into consideration.

Hereinafter, the transistor 200a and the transistor 200b according to one aspect of the present invention will be described in detail. In the following, the transistor 200a can be taken into consideration for the configuration of the transistor 200b.

The conductor 203_1 functioning as the second gate electrode of the transistor 200a is arranged so as to overlap the oxide 230 and the conductor 260_1.

Here, the conductor 260_2 may function as a first gate electrode of the transistor 200a. Further, the conductor 203_1 may function as a second gate electrode of the transistor 200a.

The potential applied to the conductor 203_1 may be an arbitrary potential different from the ground potential or the potential applied to the conductor 260_1. For example, the threshold voltage of the transistor 200a can be controlled by changing the potential applied to the conductor 203_1 independently of the potential applied to the conductor 260_1 without interlocking with the potential applied to the conductor 260_1. In particular, by applying a negative potential to the conductor 203_1, the threshold voltage of the transistor 200a can be made larger than 0V, and the off-current can be reduced. Therefore, the drain current when the voltage applied to the conductor 260_2 is 0 V can be reduced.

On the other hand, the potential applied to the conductor 203_1 may be the same as the potential applied to the conductor 260_1. When the potential applied to the conductor 203_1 is the same as the potential applied to the conductor 260_1, the conductor 203_1 is provided so as to have a larger length in the channel width direction than the region 234 in the oxide 230. You may. In particular, the conductor 203_1 is preferably stretched even in a region outside the end where the region 234 of the oxide 230 intersects the channel width direction. That is, it is preferable that the conductor 203_1 and the conductor 260_1 are superimposed on each other via the insulator on the side surface of the oxide 230 in the channel width direction.

By having the above configuration, when a potential is applied to the conductor 260_1 and the conductor 203_1, the electric field generated from the conductor 260_1 and the electric field generated from the conductor 203_1 are connected to form a closed circuit and oxidize. The channel formation region formed on the object 230 can be covered.

That is, the channel forming region of the region 234 can be electrically surrounded by the electric field of the conductor 260_1 having the function as the first gate electrode and the electric field of the conductor 203_1 having the function as the second gate electrode. .. In the present specification, the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is referred to as a curved channel (S-channel) structure.

The insulator 210 can function as a barrier insulating film that prevents impurities such as water and hydrogen from being mixed into the transistor from the lower layer. As the insulator 210, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen. For example, it is preferable to use silicon nitride, aluminum oxide, hafnium oxide, an oxide containing silicon and hafnium (hafnium silicate), an oxide containing aluminum and hafnium (hafnium aluminate), and the like as the insulator 210. This makes it possible to prevent impurities such as hydrogen and water from diffusing into the upper layer of the insulator 210. The insulator 210 suppresses the permeation of at least one of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ₍ N2O, NO, _NO2 , etc.) and copper atom. It is preferable to have a function. Further, the same applies to the case where the insulating material having a function of suppressing the permeation of impurities is described below.

Further, it is preferable to use an insulating material having a function of suppressing the permeation of oxygen (for example, oxygen atom or oxygen molecule) as the insulator 210. As a result, it is possible to suppress the downward diffusion of oxygen contained in the insulator 214 or the like.

The insulator 250 can function as the first gate insulating film of the transistor 200a, and the insulator 214 can function as the second gate insulating film of the transistor 200a. In the transistor 200a, the insulator 214 is shown in a single-layer configuration, but the present invention is not limited to this. For example, the insulator 214 may have a structure in which two or more layers are laminated.

As the oxide 230, it is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor. As the metal oxide, it is preferable to use an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a wide energy gap, the off-current of the transistor can be reduced.

A transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state, so that a semiconductor device having low power consumption can be provided. Further, since the oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.

Here, consider the case where the oxide semiconductor is an In—M—Zn oxide having indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

In addition, in this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as a metal oxynitride.

Here, the oxide semiconductor becomes a metal compound by adding metal elements such as aluminum, ruthenium, titanium, tantalum, chromium, and tungsten in addition to the elements constituting the oxide semiconductor, and the resistance is lowered. There is. It is preferable to use aluminum, titanium, tantalum, tungsten or the like. In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film having the metal element, or an oxide film having the metal element may be provided on the oxide semiconductor. Further, by providing the film, a part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film or the like, forming an oxygen deficiency and oxidizing. The resistance of the vicinity of the interface of the physical semiconductor may be lowered.

The periphery of the oxygen deficiency formed near the interface has strain. Further, when the film is formed by a sputtering method, if the sputtering gas contains a rare gas, the rare gas may be mixed into the oxide semiconductor during the film formation of the film. When the noble gas is mixed into the oxide semiconductor, distortion or structural disorder occurs in the vicinity of the interface and in the vicinity of the noble gas. Examples of the noble gas include He and Ar. It should be noted that Ar is preferable to He because it has a larger atomic radius. When the Ar is mixed in the oxide semiconductor, distortion or structural disorder is preferably generated. In these strained or disturbed regions, it is thought that the number of metal atoms with a small number of bound oxygen increases. As the number of metal atoms with a small number of bound oxygen increases, the resistance near the interface and around the noble gas may decrease.

Further, when a crystalline oxide semiconductor is used as the oxide semiconductor, the crystallinity may be broken and it may be observed as amorphous in the above-mentioned strained or structurally disturbed region.

Further, it is preferable to provide a metal film, a nitride film having a metal element, or an oxide film having a metal element on the oxide semiconductor, and then perform heat treatment in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal element diffuses from the metal film to the oxide semiconductor, and the metal element can be added to the oxide semiconductor.

Further, hydrogen existing in the oxide semiconductor diffuses into the region where the resistance of the oxide semiconductor is lowered, and when it enters the oxygen deficiency existing in the region where the resistance is lowered, it becomes a relatively stable state. Further, the hydrogen in the oxygen deficiency existing in the oxide semiconductor escapes from the oxygen deficiency by the heat treatment at 250 ° C. or higher, diffuses into the region where the resistance of the oxide semiconductor is lowered, and the oxygen deficiency existing in the region where the resistance is lowered. It is known that it will be in a relatively stable state. Therefore, the region where the resistance of the oxide semiconductor is lowered by the heat treatment is lowered, and the oxide semiconductor which is not lowered is highly purified (reduction of impurities such as water and hydrogen) to be higher resistance. Tend to do.

Further, in the oxide semiconductor, the carrier density increases in the presence of an impurity element such as hydrogen or nitrogen. Hydrogen in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, the carrier density increases. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. That is, the oxide semiconductor having nitrogen or hydrogen has a low resistance.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to the oxide semiconductor, a high resistance region and a low resistance region can be provided in the oxide semiconductor. That is, by selectively reducing the resistance of the oxide 230, it is possible to provide the oxide 230 with a region that functions as a semiconductor having a low carrier density and a region that functions as a source region or a drain region. can.

[Transistor 140a and Transistor 140b]
As shown in FIGS. 1 and 2, the transistor 140a and the transistor 140b have the same configuration as the transistor 200a and the transistor 200b described above, that is, the conductor 203_1 and the second transistor 200b that function as the second gate electrode of the transistor 200a. The difference is that it does not have the conductor 203_2 that functions as a gate electrode. Other configurations are the same as those of the transistor 200a and the transistor 200b.

As shown in FIGS. 1 and 2, the transistor 140a and the transistor 140b are arranged adjacent to each other so as to sandwich both ends of the transistor 200a and the transistor 200b in the A1-A2 direction. That is, the transistor 140a is arranged so as to be adjacent to the A1 direction of the transistor 200a, and the transistor 140b is arranged so as to be adjacent to the A2 direction of the transistor 200b.

For example, in a semiconductor device having a plurality of memory cells composed of a transistor 200a, a transistor 200b, a capacitive element 100a, and a capacitive element 100b, the memory cells are continuous in the A1-A2 direction and the A5-A6 direction in FIGS. 1 and 2. In the A1-A2 direction, the adjacent memory cells have a common oxide 230, so that the transistors are electrically connected between the adjacent memory cells.

By having the transistor 140a and the transistor 140b, the adjacent memory cells can be electrically separated from each other. That is, the transistor 140a has a function of being electrically separated from the memory cell adjacent in the A1 direction, and the transistor 140b has a function of being electrically separated from the memory cell adjacent in the A2 direction. For such a function, the transistor 140a and the transistor 140b may be always turned off. In order to keep the transistor 140a and the transistor 140b always off, the transistor 140a and the conductor 260_1 having the function of the first gate electrode of the transistor 140a and the conductor 260_1 having the function of the first gate electrode of the transistor 140b It suffices to give a potential that turns off each of the transistors 140b.

Further, as shown in FIG. 4, the conductor 205_1 having the function of the second gate electrode of the transistor 140a and the conductor 205_1 having the function of the second gate electrode of the transistor 140b may be provided. With such a configuration, for example, by giving a negative potential to the conductor 205_1 and the conductor 205_1, the potential given to the conductor 260_1 in which the transistor 140a and the transistor 140b are turned off and the potential given to the conductor 260_1 Can be kept low. It is also possible to reduce the off current.

Alternatively, the conductor 205_1 and the conductor 260_1 may be connected to give the same potential, and the conductor 205_1 and the conductor 260_1 may be connected to give the same potential.

[Capacitive element 100a and capacitive element 100b]
As shown in FIGS. 1 and 2, the capacitive element 100a is provided so as to be superimposed on the transistor 200a. Similarly, the capacitive element 100b is provided so as to be superimposed on the transistor 200b. Specifically, it is connected to one of the source region or drain region of the transistor 200a and one electrode of the capacitive element 100a, and is connected to one of the source region or drain region of the transistor 200b and one electrode of the capacitive element 100b. ..

As in the description of the transistor 200a, the capacitive element 100b has a structure corresponding to the structure of the capacitive element 100a. Therefore, in the figure, in the capacitive element 100a and the capacitive element 100b, basically the same three-digit number is assigned as a code to the corresponding configuration. Therefore, in the following, the description of the capacitive element 100a can be referred to with respect to the capacitive element 100b unless otherwise specified.

In the capacitive element 100a, the conductor 110_1 that functions as a lower electrode and the conductor 120_1 that functions as an upper electrode on the bottom surface and the side surface of the opening provided in the insulator 283 and the insulator 283 are used as dielectrics. It is configured to face each other with a functioning insulator 130 interposed therebetween. Therefore, the capacitance per unit area can be increased. The capacitive element 100a is not limited to the configuration shown in FIGS. 1 and 2. For example, as shown in FIG. 6B, the conductor 110_1 may be configured not only to be in contact with the openings provided in the insulator 283 and the insulator 280 but also to be in contact with the upper surface of the insulator 283. With such a configuration, the capacitance of the capacitive element 100a can be increased.

In particular, by increasing the depth of the openings provided in the insulator 283 and the insulator 283, the projected area does not change and the capacitance of the capacitive element 100a can be increased. Therefore, it is preferable that the capacitive element 100a is a cylinder type (the side area is larger than the bottom area).

Further, it is preferable to use an insulator having a large dielectric constant as the insulator 130. For example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.

Further, the insulator 130 may have a laminated structure, for example, an oxide containing silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, aluminum, zirconium oxide and hafnium (hafnium aluminum). Two or more layers may be selected from Nate) and the like to form a laminated structure. For example, it is preferable to form a film of hafnium oxide, aluminum oxide and hafnium oxide in order by the ALD method to form a laminated structure. The film thicknesses of hafnium oxide and aluminum oxide shall be 0.5 nm or more and 5 nm or less, respectively. With such a laminated structure, it is possible to obtain a capacitance element 100a having a large capacitance value and a small leakage current. Alternatively, zirconium oxide, aluminum oxide, and zirconium oxide may be formed in this order by the ALD method to form a laminated structure. The film thicknesses of zirconium oxide and aluminum oxide shall be 0.5 nm or more and 5 nm or less, respectively.

<Board>
As the substrate on which the transistor is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, and the like. Examples of the semiconductor substrate include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

Further, a flexible substrate may be used as the substrate. As a method of providing the transistor on the flexible substrate, there is also a method of forming the transistor on the non-flexible substrate, peeling off the transistor, and transposing it to the substrate which is the flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. As the substrate, a sheet, a film, a foil, or the like in which fibers are woven may be used. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Alternatively, it may have a property that does not return to the original shape. The substrate has, for example, a region having a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of the semiconductor device having a transistor can be reduced. Further, by making the substrate thinner, it may have elasticity even when glass or the like is used, or it may have a property of returning to the original shape when bending or pulling is stopped. Therefore, it is possible to alleviate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, it is possible to provide a durable semiconductor device.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. As for the substrate which is a flexible substrate, the lower the linear expansion rate, the more the deformation due to the environment is suppressed, which is preferable. As the substrate which is a flexible substrate, for example, a material having a linear expansion ratio of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less may be used. .. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like. In particular, aramid has a low linear expansion rate, and is therefore suitable as a substrate that is a flexible substrate.

<Insulator>
Examples of the insulator include oxides having insulating properties, nitrides, nitride oxides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like.

By surrounding the transistor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. For example, as the insulator 210, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulations containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers.

Further, for example, the insulator 210 includes aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, oxides including silicon and hafnium, aluminum and hafnium. Metal oxides such as oxides or tantalum oxide, silicon nitride or silicon nitride may be used. For example, the insulator 210 preferably has aluminum oxide, hafnium oxide, or the like.

The insulator 214 and the insulator 250 preferably have an insulator having a high dielectric constant. For example, insulators 214 and 250 have gallium oxide, hafnium oxide, zirconium oxide, oxides with aluminum and hafnium, nitrides with aluminum and hafnium, oxides with silicon and hafnium, silicon and hafnium. It is preferable to have a nitride oxide or a nitride having silicon and hafnium.

Alternatively, the insulator 214 and the insulator 250 preferably have a laminated structure of silicon oxide or silicon nitride nitride and an insulator having a high dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, they can be combined with an insulator having a high dielectric constant to form a laminated structure that is thermally stable and has a high dielectric constant.

The insulator 212, the insulator 220 (insulator 220_1, insulator 220_2, insulator 220_3, insulator 220_4 and insulator 220_5), insulator 280, and insulator 283 preferably have an insulator having a low dielectric constant. .. For example, the insulator 212, the insulator 220, the insulator 280, and the insulator 283 include silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, carbon and carbon. It is preferable to have silicon oxide to which nitrogen is added, silicon oxide having pores, a resin, or the like. Alternatively, the insulator 212, insulator 220, insulator 280, and insulator 283 may be silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon added, carbon, and the like. It is preferable to have a laminated structure of silicon oxide to which nitrogen is added, silicon oxide having pores, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

<Conductor>
Conductor 203 (Conductor 203_1 and Conductor 203_1), Conductor 205 (Conductor 205_1 and Conductor 205_1), Conductor 260 (Conductor 260_1, Conductor 260_1, Conductor 260_3 and Conductor 260_1), Conductor 240 , Conductor 245, Conductor 110 (Conductor 110_1 and Conductor 110_2), and Conductor 120 (Conductor 120_1 and Conductor 120_2) include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, A material containing one or more metal elements selected from titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium and the like can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

Further, in particular, as the conductor 260, a conductive material containing a metal element and oxygen contained in a metal oxide applicable to the oxide 230 may be used. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide 230 may be captured. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

When an oxide is used in the channel forming region of the transistor, it is preferable to use a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined as a gate electrode. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.

<Metal oxide>
As the oxide 230, it is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the semiconductor layer and the oxide 230 according to the present invention will be described.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.

Here, consider the case where the oxide semiconductor is an In—M—Zn oxide having indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

[Structure of metal oxide]
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned crystal linear semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide semiconductor (a-lik). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have strain. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have non-regular hexagonal shapes. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. It is considered that this is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. Be done.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as a (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can also be expressed as a (In, M) layer.

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since a clear crystal grain boundary cannot be confirmed, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the oxide semiconductor may be deteriorated due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

<Method of manufacturing semiconductor devices>
Next, a method of manufacturing a semiconductor device having the transistor 200a, the transistor 200b, the capacitive element 100a, and the capacitive element 100b according to the present invention will be described with reference to FIGS. 7 to 14. Further, in FIGS. 7 to 14, (A) in each figure is a top view. (B) of each figure is a cross-sectional view of the part shown by the alternate long and short dash line of A1-A2 in (A) of each figure.

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The film formation of the insulator 210 is performed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or a pulsed laser deposition (PLD) method. It can be done by using.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (Metal CVD) method and an organometallic CVD (MOCVD: Metalorganic CVD) method depending on the raw material gas used.

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage during film formation does not occur, so that a film having few defects can be obtained.

The ALD method is also a film forming method capable of reducing damage to the object to be processed. Further, the ALD method also does not cause plasma damage during film formation, so that a film having few defects can be obtained.

The CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage. In particular, the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film forming speed, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming speed.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas. Further, for example, in the CVD method and the ALD method, a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for forming a film can be shortened by the amount of time required for transportation and pressure adjustment, as compared with the case of forming a film using a plurality of film forming chambers. Therefore, it may be possible to increase the productivity of the semiconductor device.

In the ALD method, the composition can also be controlled by a method in which different raw material gases (also referred to as precursors) are alternately flowed. For example, in the case of forming an oxide having an element A and an element B, a first step of flowing a precursor containing the element A, a second step of flowing an oxidizing gas such as oxygen, ozone or water, and an element The third step of flowing the precursor containing B and the fourth step of flowing an oxidizing gas such as oxygen, ozone or water may be repeated. The composition of the oxide having the element A and the element B can be controlled by adjusting the flow rate of the precursor, the oxidizing gas and the like in each step and the time. Alternatively, element A and element B can be obtained by repeating the first step and the second step n times (n is a natural number) and then repeating the third step and the fourth step m times (m is a natural number). The composition of the oxide having the above can be controlled. Alternatively, the composition of the oxide having the element A and the element B can be controlled by adjusting the film formation temperature. If it is desired to form a nitride film instead of an oxide, the oxidizing gas may be changed to a nitride gas. Further, when the oxynitride is formed, a step of flowing an oxidizing gas and a step of flowing a nitrided gas may be provided. Further, when it is desired to form a metal or a metalloid instead of an oxide, the oxidizing gas may be changed to a reducing gas such as hydrogen. Here, a film forming method has been described when two types of precursors, a precursor containing the element A and a precursor containing the element B, have been used, but the same method can be adopted even when three or more types of precursors are used. Further, in addition to the first step to the fourth step, a step for flowing a carrier gas or the like may be provided as appropriate. Alternatively, the carrier gas may continue to flow over a plurality of steps.

For example, as the insulator 210, aluminum oxide may be formed into a film by a sputtering method. Further, the insulator 210 may have a multi-layer structure. For example, a structure may be used in which aluminum oxide is formed by a sputtering method and aluminum oxide is formed on the aluminum oxide by an ALD method. Alternatively, the structure may be such that aluminum oxide is formed by the ALD method and aluminum oxide is formed on the aluminum oxide by the sputtering method.

Next, a conductive film to be the conductor 203_1 and the conductor 203_2 is formed on the insulator 210. The film formation of the conductive film to be the conductor 203_1 and the conductor 203_1 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductive film to be the conductor 203_1 and the conductor 203_2 can be a multilayer film. For example, tungsten may be formed as a conductive film to be the conductor 203_1 and the conductor 203_1.

Next, the conductive film to be the conductor 203_1 and the conductor 203_2 is processed by a lithographic method to form the conductor 203_1 and the conductor 203_1.

In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left with a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used. When using an electron beam or an ion beam, a mask is not required. To remove the resist mask, a dry etching process such as ashing, a wet etching process, a wet etching process after the dry etching process, or a dry etching process after the wet etching process can be performed.

Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film to be a hard mask material is formed on the conductive films to be the conductor 203_1 and the conductor 203_1, a resist mask is formed on the insulating film or the conductive film, and the hard mask material is etched. A hard mask having a desired shape can be formed. The etching of the conductive films to be the conductor 203_1 and the conductor 203_1 may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive films to be the conductors 203_1 and 203_1. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate type electrodes can be used. The capacitive coupling type plasma etching apparatus having a parallel plate type electrode may be configured to apply a high frequency power source to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate type electrodes. Alternatively, a high frequency power supply having the same frequency may be applied to each of the parallel plate type electrodes. Alternatively, a high frequency power supply having a different frequency may be applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

Next, an insulating film to be the insulator 212 is formed on the insulator 210, the conductor 203_1, and the conductor 203_2. The film formation of the insulating film to be the insulator 212 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as an insulating film to be the insulator 212, silicon oxide may be formed by a CVD method.

Here, the film thickness of the insulating film to be the insulator 212 is preferably equal to or larger than the film thickness of the conductor 203_1 and the film thickness of the conductor 203_1. For example, assuming that the film thickness of the conductor 203_1 and the film thickness of the conductor 203_1 are 1, the film thickness of the insulating film to be the insulator 212 is 1 or more and 3 or less.

Next, by performing a CMP (chemical mechanical polishing) treatment on the insulating film to be the insulator 212, a part of the insulating film to be the insulator 212 is removed, and the surface of the conductor 203_1 and the surface of the conductor 203_2 are exposed. Let me. As a result, the conductor 203_1 and the conductor 203_2 having a flat upper surface and the insulator 212 can be formed (see FIG. 7).

Hereinafter, a method for forming the conductor 203_1 and the conductor 203_2 different from the above will be described.

An insulator 212 is formed on the insulator 210. The film formation of the insulator 212 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an opening reaching the insulator 210 is formed in the insulator 212. The opening also includes, for example, a groove or a slit. Further, the area where the opening is formed may be referred to as an opening. Although wet etching may be used to form the openings, it is preferable to use dry etching for microfabrication. Further, as the insulator 210, it is preferable to select an insulator that functions as an etching stopper film when the insulator 212 is etched to form a groove. For example, when a silicon oxide film is used for the insulator 212 forming the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film may be used for the insulator 210.

After the opening is formed, a conductive film to be a conductor 203_1 and a conductor 203_2 is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The film formation of the conductive film to be the conductor 203_1 and the conductor 203_1 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the conductive films to be the conductor 203_1 and the conductor 203_1 have a multilayer structure, for example, tantalum nitride or a film in which titanium nitride is laminated on tantalum nitride may be formed by a sputtering method. By using the metal nitride in the lower layer of the conductive film to be the conductor 203_1 and the conductor 203_2, a metal such as copper which is easily diffused can be used as the conductive film in the upper layer of the conductive film to be the conductor 203_1 and the conductor 203_1 described later. Can also be used to prevent the metal from diffusing out from the conductor 203_1 and the conductor 203_2.

Next, a conductive film on the upper layer of the conductive film to be the conductor 203_1 and the conductor 203_1 is formed. The film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a low resistance conductive material such as copper is formed as a conductive film on the upper layer of the conductive film to be the conductor 203_1 and the conductor 203_1.

Next, by performing the CMP treatment, a part of the upper layer of the conductive film to be the conductor 203_1 and the conductor 203_1 and the lower layer of the conductive film to be the conductor 203_1 and the conductor 203_2 are removed, and the insulator 212 is exposed. do. As a result, the conductive films to be the conductor 203_1 and the conductor 203_2 remain only in the opening. This makes it possible to form the conductor 203_1 and the conductor 203_2 having a flat upper surface. In addition, a part of the insulator 212 may be removed by the CMP treatment. The above is a different forming method of the conductor 203_1 and the conductor 203_1.

Next, the insulator 214 is formed on the conductor 203_1 and the conductor 203_1. The film formation of the insulator 214 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 7).

Next, it is preferable to perform heat treatment. The heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower. The heat treatment is carried out in an atmosphere of nitrogen or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas and 1% or more or 10% or more of an oxidizing gas. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in a nitrogen or inert gas atmosphere. .. By heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed. Alternatively, in the heat treatment, plasma treatment containing oxygen may be performed in a reduced pressure state. For plasma treatment containing oxygen, for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. Higher density oxygen radicals can be generated by using high density plasma, and oxygen radicals generated by high density plasma can be efficiently guided into the insulator 224 by applying RF to the substrate side. Alternatively, the plasma treatment containing oxygen may be performed to supplement the desorbed oxygen after the plasma treatment containing the inert gas is performed using this device. In some cases, the heat treatment may not be performed.

Next, an insulating film to be an insulator 220 (insulator 220_1, insulator 220_2, insulator 220_3, insulator 220_4 and insulator 220_5) is formed. The film formation of the insulating film to be the insulator 220 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the insulating film to be the insulator 220 is processed by the lithography method to form the insulator 220 (insulator 220_1, insulator 220_2, insulator 220_3, insulator 220_4 and insulator 220_5). Here, the insulator 220 is arranged so that the space between the insulator 220_2 and the insulator 220_3 overlaps with the conductor 203_1, and the space between the insulator 220_3 and the insulator 220_4 overlaps with the conductor 203_1 (FIG. FIG. See 7.).

Next, the oxide film 230C is formed so as to cover the insulator 214 and the insulator 220 (see FIG. 8). The film formation of the oxide film 230C can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230C is formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film formed can be increased. Further, when the oxide film to be the oxide 230 is formed by a sputtering method, the above-mentioned In—M—Zn oxide target can be used.

In particular, when the oxide film 230C is formed, a part of oxygen contained in the sputtering gas may be supplied to the insulator 214.

The proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

When the oxide film 230C is formed by the sputtering method, for example, a target of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio], In: Ga: Zn = 1: 1: 1 [ Atomic number ratio] target or In: Ga: Zn = 1: 1: 0.5 [atomic number ratio] target is used to form a film.

Since the oxide film 230C is a channel forming region of the transistor, it is preferable that the film is formed with good coverage in the stepped portion composed of the insulator 214 and the insulator 220. As a method for forming the oxide film 230C with good coverage, it is preferable to use the ALD method and the CVD method. When the sputtering method is used, the coverage on the stepped portion can be improved by using ionization sputtering that ionizes the sputtered particles to form a film. Alternatively, there is also a method in which the distance between the target and the substrate is widened to 200 mm or more, or sputtered particles having high straightness are used by using a member such as a collimator. Alternatively, reverse sputtering or bias sputtering that applies a bias to the substrate side may be used.

Although the present embodiment shows a configuration in which the oxide film 230C is a single layer, the present invention is not limited to this. For example, a laminated structure having two layers, three layers, or four or more layers may be used. In the case of a laminated structure, in the case of forming a film by a sputtering method, a plurality of targets having different atomic number ratios of In, Ga and Zn may be used to form a laminated structure. Alternatively, the laminated structure may be formed by changing the ratio of oxygen contained in the sputtering gas. Alternatively, the laminated structure may be formed by changing the atomic number ratio of In, Ga and Zn and the ratio of oxygen contained in the sputtering gas.

Next, heat treatment may be performed. For the heat treatment, the same conditions as those for the above-mentioned heat treatment can be used. Impurities such as hydrogen and water in the oxide film which becomes the oxide 230 can be removed by the heat treatment. For example, after performing the treatment at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, the treatment is continuously performed at a temperature of 400 ° C. for 1 hour in an oxygen atmosphere.

Next, the oxide film to be the oxide 230 is processed to form the oxide 230 (see FIG. 9).

Here, as shown in FIG. 9A, the angle formed by the oxide 230 between the long side direction of the oxide 230 and the long side of the insulator 220 is 20 ° or more and 70 ° or less, preferably 30. It is formed so that it becomes ° or more and 60 ° or less. Further, at least a part thereof is formed so as to overlap with the conductor 203.

The oxide film may be processed by using a lithography method. Further, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication.

Further, as the etching mask, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film to be a hard mask material is formed on the oxide film 230C, a resist mask is formed on the insulating film or a conductive film, and the hard mask material is etched to form a hard mask having a desired shape. can. The etching of the oxide film to be the oxide 230 may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the oxide film 230C.

By performing the conventional dry etching or the like, impurities caused by the etching gas or the like may adhere to or diffuse on the surface or the inside of the oxide 230 or the like. Impurities include, for example, fluorine or chlorine.

Cleaning is performed to remove the above impurities and the like. The cleaning method includes wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.

As the wet cleaning, a cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning may be performed using pure water or carbonated water.

Next, heat treatment may be performed. As the heat treatment conditions, the above-mentioned heat treatment conditions can be used.

Next, the insulator 250 is formed on the insulator 214, the insulator 220, and the oxide 230 (see FIG. 10). The film formation of the insulator 250 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the insulator 250 may have a laminated structure. For example, when the insulator 250 has a two-layer structure, oxygen is formed in the first layer of the insulator 250 by forming a second layer of the insulator 250 in an atmosphere containing oxygen by using a sputtering method. Can be added.

Here, heat treatment may be performed. The above-mentioned heat treatment conditions can be used for the heat treatment. By the heat treatment, the water concentration and the hydrogen concentration in the insulator 250 can be reduced.

Next, a conductive film 260A is formed on the insulator 250 (see FIG. 11). The film formation of the conductive film 260A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film 260A may have a laminated structure of two or more layers. In the present embodiment, titanium nitride is formed into a film by a CVD method or an ALD method, and then tungsten is formed by a CVD method.

Next, a part of the conductive film 260A is removed by performing a CMP treatment to expose the insulator 250. Here, the conductor to be the conductor 260 (conductor 260_1, conductor 260_2, conductor 260_3 and conductor 260_4) is etched until it becomes approximately the same height as the upper surface of the oxide 230 on the insulator 220. Then, the conductor 260 is formed (see FIG. 12).

Next, the insulator 280 is formed into a film. The film formation of the insulator 280 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the spin coating method, dip method, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife method, roll coater method, curtain coater method, or the like can be used. In this embodiment, silicon oxide nitride is used as the insulator 280.

The insulator 280 is preferably formed so that the upper surface has a flat surface. For example, the upper surface of the insulator 280 may have a flat surface immediately after the film is formed. Alternatively, for example, the insulator 280 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to the reference surface such as the back surface of the substrate after the film formation. Such a process is called a flattening process. The flattening treatment includes a CMP treatment, a dry etching treatment, and the like. In this embodiment, a CMP process is used as the flattening process (see FIG. 13).

Although the insulator 280 has a single-layer structure in the figure, it may have a laminated structure of two or more layers. For example, in order to suppress the warp of the substrate, the internal stress may be offset by laminating a layer having a compressive stress and a layer having a tensile stress.

Next, the insulator 280 is formed with an opening reaching the region 231b of the oxide 230. Since the aspect ratio of the opening is large in this step, it is preferable to perform anisotropic etching using, for example, a hard mask. Further, it is preferable to use dry etching for anisotropic etching having a large aspect ratio.

Here, ion implantation may be performed in the region 231b by using an ion implantation method, an ion implantation method in which an ionized raw material gas is added without mass separation, a plasma immersion ion implantation method, or the like. Other than the opening, ions cannot reach due to the insulator 280. That is, ions can be implanted into the opening in a self-aligned manner. By this ion implantation, the carrier density of the opening region 231 can be made higher, so that the contact resistance between the conductor 240 and the oxide 230 may be reduced.

Next, a conductive film to be the conductor 240 is formed. It is desirable that the conductive film to be the conductor 240 has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water or hydrogen. For example, tantalum nitride, titanium nitride and the like can be laminated with tungsten, molybdenum, copper and the like. The film formation of the conductive film to be the conductor 240 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the CMP treatment is performed to remove the conductive film that becomes the conductor 240 on the insulator 280. As a result, the conductor 240 having a flat upper surface can be formed by leaving the conductive film only in the opening (see FIG. 13).

Further, the conductor 240 may be formed after forming aluminum oxide on the side wall portion of the opening. By forming aluminum oxide on the side wall portion of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the conductor 240 from being oxidized. Further, it is possible to prevent impurities such as water and hydrogen from diffusing from the conductor 240 to the outside. The aluminum oxide can be formed by forming aluminum oxide on the openings by using the ALD method or the like and performing anisotropic etching.

Next, a conductive film to be a conductor 245 is formed. The film formation of the conductive film to be the conductor 245 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, the conductive film to be the conductor 245 is processed by the lithography method to form the conductor 245. The conductor 245 is formed by extending in a direction orthogonal to the A5-A6 direction shown in FIG. 1 (A) (see FIG. 13).

Next, the insulator 283 is formed into a film. For the film formation of the insulator 283, the same film forming method as that of the insulator 280 can be used. In this embodiment, silicon oxide nitride is used as the insulator 283.

The insulator 283 is preferably formed so that the upper surface has a flat surface. For example, the upper surface of the insulator 283 may have a flat surface immediately after the film is formed. Alternatively, for example, the insulator 283 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to the reference surface such as the back surface of the substrate after the film formation. Such a process is called a flattening process. The flattening treatment includes a CMP treatment, a dry etching treatment, and the like. In this embodiment, a CMP process is used as the flattening process (see FIG. 13).

Next, the insulator 280 and the insulator 283 are formed with an opening reaching the region 231a of the oxide 230. Since the aspect ratio of the opening is large in this step, it is preferable to perform anisotropic etching using, for example, a hard mask. Further, it is preferable to use dry etching for anisotropic etching having a large aspect ratio.

Here, ion implantation may be performed in the region 231a by using an ion implantation method, an ion implantation method in which an ionized raw material gas is added without mass separation, a plasma immersion ion implantation method, or the like. Other than the opening, ions cannot be reached by the insulator 280 and the insulator 283. That is, ions can be implanted into the opening in a self-aligned manner. By this ion implantation, the carrier density of the opening region 231a can be made higher, so that the contact resistance between the conductors 110_1 and the conductors 110_2 formed later and the oxide 230 may be reduced.

Next, a conductor to be the conductor 110_1 and the conductor 110_2 is formed in the opening. The film formation of the conductor can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, titanium nitride is formed into a film by the ALD method.

Next, an insulator is formed on the conductors to be the conductor 110_1 and the conductor 110_2 (not shown). The film formation of the insulator can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the CMP treatment is performed to remove the conductor 110_1 and the conductor 110_2 on the insulator 283 and the above-mentioned insulator. Next, the conductor 110_1 and the conductor 110_2 can be formed by etching the above-mentioned insulator remaining in the opening (see FIG. 14).

It is preferable that the insulator 283 has, for example, a laminated structure of silicon oxide and silicon nitride, because the silicon nitride functions as a stopper film for the CMP treatment, and productivity can be improved and production variation can be suppressed. ..

Next, the insulator 130 is formed on the insulator 283, the conductor 110_1, and the conductor 110_2. The film formation of the insulator 130 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 14).

Next, the conductors to be the conductor 120_1 and the conductor 120_2 are formed into a film. The film formation of the conductor can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductors to be the conductors 120_1 and 120_2 are subjected to CMP treatment to flatten the surfaces of the conductors to be the conductors 120_1 and 120_2. At this time, after forming an insulator on the conductors to be the conductors 120_1 and 120_2, a CMP treatment is performed to remove the insulators, and further, the conductors to be the conductors 120_1 and 120_2 are formed. The surface may be flattened.

Next, the conductors to be the conductors 120_1 and 120_2 are processed by a lithographic method to form the conductors 120_1 and 120_2.

Here, as shown in FIG. 3, the conductor 120 may be formed so that the conductor 120_1 and the conductor 120_2 are integrated without being separated.

As described above, the semiconductor device having the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitive element 100b shown in FIGS. 1 and 2 can be manufactured.

<Modification example of semiconductor device>
FIG. 5 shows an example of a semiconductor device including a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a, and a capacitive element 100b. FIG. 5A shows the upper surface of the semiconductor device. In addition, in order to clarify the figure, some films are omitted in FIG. 5 (A). Further, FIG. 5B is a cross-sectional view corresponding to the alternate long and short dash line A1-A2 shown in FIG. 5A. Further, FIG. 5C is a cross-sectional view corresponding to the alternate long and short dash line A3-A4 shown in FIG. 8A.

In the semiconductor device shown in FIG. 5, the insulator 217 (insulator 217_1, insulator 217_2, insulator 217_3, Insulator 217_4 and insulator 217_5) are arranged. In other words, it differs from the semiconductor device shown in FIGS. 1 and 2 in that the insulator 217 is arranged between the source region or drain region of the oxide 230 and the insulator 220.

The insulator 217 is preferably an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. By arranging the insulator 217 between the source region or drain region of the oxide 230 and the insulator 220, oxygen contained in the insulator 220 is injected into the source region or drain region of the oxide 230. Since this can be suppressed, it is possible to prevent high resistance in the source region or the drain region. Further, by absorbing the oxygen to the conductor 240, it is possible to prevent the conductor 240 from being oxidized and having a high resistance.

As the insulator 217, the same insulator as the insulator 210 can be used. For other configurations and effects, the semiconductor devices shown in FIGS. 1 and 2 can be taken into consideration.

<Application example of semiconductor device>
In the above, the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitive element 100b are mentioned as configuration examples of the semiconductor device, but the semiconductor device shown in the present embodiment is not limited to this. .. For example, as shown in FIG. 15, the cell 600 and the cell 601 having the same configuration as the cell 600 may be connected via the transistor 140b. In this specification, a semiconductor device having a transistor 200a, a transistor 200b, a capacitive element 100a, and a capacitive element 100b is referred to as a cell. Regarding the configuration of the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitive element 100b, the description relating to the above-mentioned transistor 200a, transistor 200b, transistor 140a, transistor 140b, capacitive element 100a, and capacitive element 100b. Can be taken into consideration.

FIG. 15 is a cross-sectional view in which a cell 600 having a transistor 200a, a transistor 200b, a capacitive element 100a, and a capacitive element 100b and a cell 601 having the same configuration as the cell 600 are connected via a transistor 140b.

As shown in FIG. 15, a transistor 140b is arranged between the cell 600 and the cell 601. By keeping the transistor 140b in the off state at all times, the cell 600 and the cell 601 are electrically separated from each other. can. Regarding the functions and effects of the transistor 140b, the above-mentioned description of the transistor 140a and the transistor 140b can be referred to.

As described above, by forming the transistor 200a, the transistor 200b, the capacitive element 100a, and the capacitive element 100b in the configuration shown in the present embodiment, the cell area can be reduced, and the semiconductor device can be miniaturized or highly integrated. Can be planned.

[Structure of cell array]
Here, an example of the cell array of the present embodiment is shown in FIG. For example, the semiconductor device shown in FIG. 1 can be configured as one cell, and the cells can be arranged in a matrix or on a matrix to form a cell array.

FIG. 16 is a circuit diagram showing a form in which the cell configurations shown in FIG. 1 are arranged in a matrix. In the cell array shown in FIG. 16, the wiring WL is extended in the column direction.

As shown in FIG. 16, one of the source and drain of the transistor 200a and the transistor 200b constituting the cell is electrically connected to the common wiring BL (BL01, BL02, BL03 and BL04). The first gate of the transistor 200a and the first gate of the transistor 200b constituting the cell 600 are electrically connected to different wiring WLs (WL01 to WL06). Further, these wiring WLs are electrically connected to the first gate of the transistor 200a and the first gate of the transistor 200b of the cells 600 arranged in the column direction, respectively. Further, the transistor 140a and the transistor 140b are arranged between adjacent cells 600 arranged in the row direction. The first gate of the transistor 140a and the first gate of the transistor 140b are electrically connected to different wiring ILs (IL01 to IL04). Further, these wiring ILs are electrically connected to the first gate of the transistor 140a and the first gate of the transistor 140b arranged in the column direction, respectively. By applying a potential to the wiring IL so that the transistor 140a and the transistor 140b are always in the off state, the adjacent cells can be electrically separated from each other.

For example, in the cell 600 connected to BL02, WL03, WL04 shown in FIG. 15, the conductor 240 is electrically connected to BL02 and the conductor 260_2 is electrically connected to WL03 as shown in FIG. , Conductor 260_3 is electrically connected to WL04.

Further, the transistor 200a and the transistor 200b of each cell 600 may be provided with a second gate BG. The threshold value of the transistor can be controlled by the potential applied to the BG. The BG is connected to the transistor 400, and the potential applied to the BG can be controlled by the transistor 400. Further, the conductor 235_2 of the capacitance element 100a and the conductor 235_4 of the capacitance element 100b of the cell 600 are electrically connected to different wiring PLs, respectively.

Further, FIG. 17 shows a schematic diagram showing the layout of each wiring and each part of the circuit diagram shown in FIG. As shown in FIG. 17, by arranging the oxide 230 and the wiring WL in a matrix, the semiconductor device of the circuit diagram shown in FIG. 16 can be formed. Here, it is preferable that the wiring BL is provided in a layer different from the wiring WL and the oxide 230. Further, as shown in FIG. 17, the long side direction of the wiring BL and the long side direction of the oxide 230 are not arranged in parallel, and are in the long side direction of the oxide 230 with respect to the long side direction of the wiring BL. It is preferable to arrange the wiring BL and the oxide 230 so that the angle is 20 ° or more and 70 ° or less, preferably 30 ° or more and 60 ° or less. By arranging in this way, for example, the capacitive element 100a and the capacitive element 100b and the wiring BL can be arranged without crossing each other.

Further, the cellar array may be laminated not only on a flat surface but also on a flat surface. By stacking a plurality of cell array, cells can be integrated and arranged without increasing the occupied area of the cell array. That is, a 3D cell array can be configured.

As described above, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention can provide a semiconductor device having good electrical characteristics. Alternatively, according to one aspect of the present invention, a semiconductor device having a small off-current can be provided. Alternatively, one aspect of the present invention can provide a transistor having a large on-current. Alternatively, one aspect of the present invention can provide a highly reliable semiconductor device. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments.

(Embodiment 2)
In this embodiment, one embodiment of the semiconductor device will be described with reference to FIG.

[Storage device 1]
The storage device shown in FIG. 18 includes a transistor 200a, a capacitive element 100a, a transistor 200b, a capacitive element 100b, a transistor 140a, a transistor 140b, and a transistor 300. FIG. 18 is a cross-sectional view of the transistor 300 in the channel length direction. FIG. 19 is a cross-sectional view of a portion shown by a dotted chain line of W1-W2 in FIG. That is, it is a cross-sectional view in the channel width direction of the transistor 300 in the vicinity of the transistor 300.

The transistor 200a and the transistor 200b are transistors in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200a and the transistor 200b have a small off current, it is possible to retain the stored contents for a long period of time by using the transistor 200a and the transistor 200b as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

In the storage device shown in FIG. 18, the wiring 3001 is electrically connected to one of the source and drain of the transistor 300, the wiring 3002 is electrically connected to the other of the source and drain of the transistor 300, and the wiring 3007 is connected to the transistor 300. It is electrically connected to the gate. Further, the wiring 3003 is electrically connected to one of the source and drain of the transistor 200a and one of the source and drain of the transistor 200b, the wiring 3004a is electrically connected to the first gate of the transistor 200a, and the wiring 3004b is It is electrically connected to the first gate of the transistor 200b, the wiring 3006a is electrically connected to the second gate of the transistor 200a, and the wiring 3006b is electrically connected to the second gate of the transistor 200b. Further, the wiring 3005a is electrically connected to one of the electrodes of the capacitance element 100a, and the wiring 3005b is electrically connected to one of the electrodes of the capacitance element 100b.

The semiconductor device shown in FIG. 18 can be applied to a storage device provided with an oxide transistor such as DOSRAM, which will be described later. The off-current of the transistor 200a and the transistor 200b is small, and the potential of the other of the source and the drain (which can also be the other of the capacitive element 100a and the electrode of the capacitive element 100b) can be maintained. It can be written, held, and read.

<Structure of storage device 1>
As shown in FIG. 18, the semiconductor device of one aspect of the present invention includes a transistor 300, a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a, and a capacitive element 100b. The transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a and the capacitive element 100b are provided above the transistor 300, and the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b are provided on the same layer. Further, the capacitive element 100a and the capacitive element 100b are provided above the transistor 200a, the transistor 200b, the transistor 140a, and the transistor 140b. Regarding the configurations of the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitive element 100b, the above-described embodiment can be referred to.

The transistor 300 is provided on the substrate 311 and has a semiconductor region 313 composed of a conductor 316, an insulator 315, and a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b that function as a source region or a drain region. Have.

As shown in FIG. 19, in the transistor 300, the upper surface of the semiconductor region 313 and the side surface in the channel width direction are covered with the conductor 316 via the insulator 315. As described above, by making the transistor 300 a Fin type, the on characteristic of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.

The transistor 300 may be either a p-channel type or an n-channel type.

It is preferable to include a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like. It preferably contains crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

In the low resistance region 314a and the low resistance region 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or p-type conductivity such as boron are imparted. Contains elements that

The conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

The transistor 300 shown in FIG. 18 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.

The insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 300 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, for the insulator 324, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 200a and the transistor 200b are provided from the substrate 311 or the transistor 300.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as the transistor 200a and the transistor 200b, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200a and the transistor 200b and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane in which the amount of hydrogen desorbed is small.

The amount of hydrogen desorbed can be analyzed by using, for example, a heated desorption gas analysis method (TDS). For example, in the TDS analysis, the amount of hydrogen desorbed from the insulator 324 is the amount desorbed in terms of hydrogen atoms in the range of 50 ° C. to 500 ° C. in the surface temperature of the film, which is converted into the area of the insulator 324. It may be 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the dielectric constant of the insulator 324. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings.

Further, a conductor 328 electrically connected to the transistor 300, a conductor 330, and the like are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as a plug or wiring. In addition, a conductor that functions as a plug or wiring may collectively assign a plurality of structures to the same reference numeral. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is single-layered or laminated. Can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 18, the insulator 350 and the insulator 352 are sequentially laminated and provided. Further, a conductor 356 is formed on the insulator 350 and the insulator 352. The conductor 356 functions as a plug or wiring. The conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.

For example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening provided in the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b can be performed. Can be suppressed.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.

Although the wiring layer including the conductor 356 has been described above, the storage device according to the present embodiment is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be 3 or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be 5 or more.

Further, a wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 18, a wiring layer including an insulator 360, an insulator 362, and a conductor 366, a wiring layer including an insulator 372, an insulator 374, and a conductor 376 are laminated in this order. Further, a plurality of wiring layers are provided between the wiring layer including the insulator 360, the insulator 362, and the conductor 366 and the wiring layer including the insulator 372, the insulator 374, and the conductor 376. May be good. The conductor 366 and the conductor 376 function as a plug or wiring. Further, the insulator 360 to the insulator 374 can be provided by using the same material as the above-mentioned insulator.

An insulator 210 and an insulator 212 are laminated on the insulator 374 in order. As either the insulator 210 or the insulator 212, it is preferable to use a substance having a barrier property against oxygen or hydrogen.

The insulator 210 is provided with a film having a barrier property so that hydrogen and impurities do not diffuse from, for example, the region where the substrate 311 or the transistor 300 is provided to the region where the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b are provided. It is preferable to use it. Therefore, the same material as the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by the CVD method can be used. Here, the characteristics of the semiconductor element may deteriorate due to the diffusion of hydrogen into the semiconductor element having the oxide semiconductor such as the transistor 200a, the transistor 200b, the transistor 140a, and the transistor 140b. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b, and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane in which the amount of hydrogen desorbed is small.

Further, as a film having a barrier property against hydrogen, for example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 210.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 200a, the transistor 200b, the transistor 140a, and the transistor 140b during and after the manufacturing process of the transistor. Further, it is possible to suppress the release of oxygen from the oxides constituting the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b. Therefore, it is suitable for use as a protective film for the transistor 200a, the transistor 200b, the transistor 140a, and the transistor 140b.

Further, for example, the same material as the insulator 320 can be used for the insulator 212. Further, by using a material having a relatively low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 212, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with the conductor 218 and the conductors constituting the transistor 200a and the transistor 200b. The conductor 218 has a function as a plug or wiring for electrically connecting the transistor 200a and the transistor 200b, or the transistor 300. The conductor 218 can be provided by using the same material as the conductor 328 and the conductor 330.

In particular, the conductor 210 and the conductor 218 in the region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b can be separated by a layer having a barrier property against oxygen, hydrogen and water, and the transistor 300 can be separated from the transistor 200a and the transistor 200b. The diffusion of hydrogen into the transistor 140a and the transistor 140b can be suppressed.

A transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a, and a capacitive element 100b are provided above the insulator 212. The structures of the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitive element 100b are the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitance described in the previous embodiment. The element 100b may be used. Further, the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitive element 100b shown in FIG. 18 are examples, and the transistor is not limited to the structure thereof, and an appropriate transistor can be used according to the circuit configuration and the driving method. Just do it.

Further, by providing the conductor 248 so as to be in contact with the conductor 218, the conductor 253 connected to the transistor 300 can be taken out above the transistor 200a and the transistor 200b. In FIG. 18, the wiring 3002 is taken out above the transistor 200a and the transistor 200b, but the present invention is not limited to this, and the wiring 3001 or the wiring 3007 may be taken out above the transistor 200a and the transistor 200b. ..

The above is the description of the configuration example. By using this configuration, it is possible to suppress fluctuations in electrical characteristics and improve reliability in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Alternatively, a transistor having an oxide semiconductor having a small off-current can be provided. Alternatively, it is possible to provide a semiconductor device with reduced power consumption.

<Storage device 2>
The semiconductor device shown in FIG. 20 is a storage device including a transistor 400, a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a, and a capacitive element 100b. Hereinafter, one form as a storage device will be described with reference to FIG. 20.

FIG. 20A shows a circuit diagram showing an example of the connection relationship between the transistor 400, the transistor 200a, the transistor 200b, the capacitive element 100a, and the capacitive element 100b in the semiconductor device shown in the present embodiment. Further, FIG. 20 (B) shows a cross-sectional view of the semiconductor device corresponding to the wiring 1003 to the wiring 1010 shown in FIG. 20 (A). Further, FIG. 20 (C) shows a cross-sectional view of the portion shown by the alternate long and short dash line of W3-W4 in FIG. 20 (B). FIG. 20C is a cross-sectional view of the transistor 400 in the channel forming region in the channel width direction.

As shown in FIG. 20, in the transistor 200a, the gate is electrically connected to the wiring 1004a, and one of the source and the drain is electrically connected to the wiring 1003. Further, the other of the source and drain of the transistor 200a is electrically connected to the lower electrode of the capacitive element 100a. The upper electrode of the capacitive element 100a is electrically connected to the wiring 1005a. In the transistor 200b, the gate is electrically connected to the wiring 1004b, and one of the source and the drain is electrically connected to the wiring 1003. Further, the other of the source and drain of the transistor 200b is electrically connected to the lower electrode of the capacitive element 100b. The upper electrode of the capacitive element 100b is electrically connected to the wiring 1005b. Further, the drain of the transistor 400 is electrically connected to the wiring 1010. Further, as shown in FIG. 20B, the second gate of the transistor 200a, the source of the transistor 400, the first gate, and the second gate have wiring 1006a, wiring 1006b, wiring 1007, wiring 1008, and so on. And are electrically connected via wiring 1009.

Here, by applying a potential to the wiring 1004a, the on state and the off state of the transistor 200a can be controlled. By applying a potential to the wiring 1003 with the transistor 200a turned on, electric charges can be supplied to the capacitive element 100a via the transistor 200a. At this time, by turning off the transistor 200a, the electric charge supplied to the capacitive element 100a can be retained. Further, the wiring 1005a can control the potential of the connection portion between the transistor 200a and the capacitive element 100a by capacitive coupling by giving an arbitrary potential. For example, when a ground potential is applied to the wiring 1005a, it becomes easy to retain the above charge.

Similarly, by applying a potential to the wiring 1004b, the on state and the off state of the transistor 200b can be controlled. By applying a potential to the wiring 1003 with the transistor 200b turned on, electric charges can be supplied to the capacitive element 100b via the transistor 200b. At this time, by turning off the transistor 200b, the electric charge supplied to the capacitive element 100b can be retained. Further, the wiring 1005b can control the potential of the connection portion between the transistor 200b and the capacitive element 100b by capacitive coupling by giving an arbitrary potential. For example, when a ground potential is applied to the wiring 1005b, it becomes easy to retain the above charge. Further, by applying a negative current to the wiring 1010, a negative potential is given to the second gates of the transistor 200a and the transistor 200b via the transistor 400, and the threshold voltage of the transistor 200a and the transistor 200b is set. It can be made larger than 0V, the off-current can be reduced, and the drain current when the first gate voltage is 0V can be made very small.

The first gate and the second gate of the transistor 400 are connected to the source by a diode, and the source of the transistor 400 is connected to the second gate of each of the transistor 200a and the transistor 200b. The second gate voltage of each of the transistor 200a and the transistor 200b can be controlled. When holding the negative potential of the second gate of each of the transistor 200a and the transistor 200b, the voltage between the first gate source and the voltage between the second gate sources of the transistor 400 becomes 0V. Since the drain current when the first gate voltage of the transistor 400 is 0V is very small and the threshold voltage is larger than the transistor 200a and the transistor 200b, this configuration eliminates the need to supply power to the transistor 400. Can also maintain the negative potential of the second gate of each of the transistor 200a and the transistor 200b for a long time.

Further, by holding the negative potential of the second gate of the transistor 200a and the transistor 200b, the first gate voltage of the transistor 200a and the transistor 200b can be increased without supplying power to the transistor 200a and the transistor 200b. The drain current at 0V can be made very small. That is, the electric charge can be held in the capacitive element 100a and the capacitive element 100b for a long time without supplying power to the transistor 200a, the transistor 200b, and the transistor 400. For example, by using such a semiconductor device as a storage element, it is possible to perform storage retention for a long time without supplying power. Therefore, it is possible to provide a storage device that has a low frequency of refresh operations or does not require refresh operations.

The connection relationship between the transistor 200a, the transistor 200b, the transistor 400, the capacitive element 100a, and the capacitive element 100b is not limited to those shown in FIGS. 20A and 20B. The connection relationship can be changed as appropriate according to the required circuit configuration.

<Structure of storage device 2>
FIG. 20B is a cross-sectional view of a storage device including a capacitive element 100a, a capacitive element 100b, a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, and a transistor 400. In the storage device shown in FIG. 20, the same reference numerals are given to the above-described embodiment, the semiconductor device shown in <Structure of storage device 1>, and the structure having the same function as the structure constituting the storage device. do.

As shown in FIG. 20, the storage device of one aspect of the present invention includes a transistor 400, a transistor 200a, a transistor 200b, a transistor 140a, a transistor 140b, a capacitive element 100a, and a capacitive element 100b. The transistor 400, the transistor 200a, the transistor 200b, the transistor 140a and the transistor 140b are arranged in the same layer. The capacitive element 100a and the capacitive element 100b are arranged above the transistor 400, the transistor 200a, the transistor 200b, the transistor 140a, and the transistor 140b.

As the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, the capacitive element 100a, and the capacitive element 100b, the capacitive element and the transistor possessed by the above-described embodiment and the semiconductor device described with reference to FIG. 1 may be used. The capacitive element 100a, the capacitive element 100b, the transistor 200a, the transistor 200b, the transistor 140a, the transistor 140b, and the transistor 400 shown in FIG. 20 are examples, and are not limited to their structures and are appropriate depending on the circuit configuration and driving method. Transistors may be used.

The transistor 400 is formed in the same layer as the transistor 200a, the transistor 200b, the transistor 140a, and the transistor 140b, and is a transistor that can be manufactured in parallel. The transistor 400 includes a conductor 460 that functions as a first gate electrode, a conductor 403 that functions as a second gate electrode, an insulator 450 that is in contact with the side surface of the conductor 460, and an oxide that functions as a source or drain. It has 230 and.

In the transistor 400, the conductor 403 is the same layer as the conductor 203. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260_1, the conductor 260_1, the conductor 260_1, and the conductor 260_1.

The oxide 230 that functions as the active layer of the transistor 400 has reduced oxygen deficiency and reduced impurities such as hydrogen and water. As a result, the threshold voltage of the transistor 400 can be made larger than 0V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small.

By using this structure, it is possible to suppress fluctuations in electrical characteristics and improve reliability in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments.

(Embodiment 3)
In the present embodiment, using FIGS. 21 and 22, a transistor using an oxide as a semiconductor (hereinafter referred to as an OS transistor) and a storage device to which a capacitive element according to one aspect of the present invention are applied. DOSRAM will be described as an example of the device. DOSRAM (registered trademark) is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having a 1T (transistor) 1C (capacity) type memory cell. In the following, a memory device using an OS transistor such as DOSRAM may be referred to as an OS memory.

In DOSRAM, a memory device (hereinafter, referred to as “OS memory”) in which an OS transistor is used as a memory cell is applied. The OS memory is a memory having at least a capacitive element and an OS transistor that controls charging / discharging of the capacitive element. Since the OS transistor is a transistor with a minimum off current, the OS memory has excellent holding characteristics and can function as a non-volatile memory.

<< DOSRAM1400 >>
FIG. 21 shows a configuration example of the DOSRAM. As shown in FIG. 21, the DOSRAM 1400 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).

The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 has a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, a global bit line GBLL, and a GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a laminated structure in which a memory cell array 1422 is laminated on a sense amplifier array 1423. The global bit lines GBLL and GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a layered bit line structure in which a local bit line and a global bit line are layered is adopted as the bit line structure.

The memory cell array 1422 has N local memory cell array 1425 <0> -1425 <N-1> (N is an integer of 2 or more). FIG. 22A shows a configuration example of the local memory cell array 1425. The local memory cell array 1425 has a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, and a BLR. In the example of FIG. 22A, the structure of the local memory cell array 1425 is an open bit linear type, but it may be a folded bit linear type.

FIG. 22B shows a circuit configuration example of a pair of memory cells 1445a and memory cells 1445b connected to a common bit line BLL (BLR). The memory cell 1445a has a transistor MW1a, a capacitive element CS1a, terminals B1a, and B2a, and is connected to a word line WLa and a bit line BLL (BLR). Further, the memory cell 1445b has a transistor MW1b, a capacitive element CS1b, terminals B1b, and B2b, and is connected to a word line WLb and a bit line BLL (BLR). In the following, when any one of the memory cell 1445a and the memory cell 1445b is not particularly limited, the memory cell 1445 and the configuration attached thereto may not be designated by a or b.

The transistor MW1a has a function of controlling the charge / discharge of the capacitive element CS1a, and the transistor MW1b has a function of controlling the charge / discharge of the capacitive element CS1b. The gate of the transistor MW1a is electrically connected to the word line WLa, the first terminal is electrically connected to the bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of the capacitive element CS1a. There is. Further, the gate of the transistor MW1b is electrically connected to the word line WLb, the first terminal is electrically connected to the bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of the capacitive element CS1b. Has been done. As described above, the bit line BLL (BLR) is commonly used for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.

The transistor MW1 has a function of controlling charge / discharge of the capacitive element CS1. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant voltage (for example, a low power supply voltage) is input to the terminal B2.

When the semiconductor device shown in the above embodiment is used for the memory cells 1445a and 1445b, the transistor 200a is used as the transistor MW1a, the transistor 200b is used as the transistor MW1b, the capacitive element 100a is used as the capacitive element CS1a, and the capacitive element 100b is used as the capacitive element CS1b. Can be used. As a result, the occupied area of each set of the transistor and the capacitive element in the top view can be reduced, so that the storage device according to the present embodiment can be highly integrated. Therefore, the storage capacity per unit area of the storage device according to the present embodiment can be increased.

The transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1. For example, the voltage of the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage of the terminal B1 may be changed according to the operation of the DOSRAM 1400.

The back gate of transistor MW1 may be electrically connected to the gate, source, or drain of transistor MW1. Alternatively, the transistor MW1 may not be provided with a back gate.

The sense amplifier array 1423 has N local sense amplifier arrays 1426 <0> -1426 <N-1>. The local sense amplifier array 1426 has one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging a bit line pair, a function of amplifying a voltage difference between the bit line pairs, and a function of maintaining this voltage difference. The switch array 1444 has a function of selecting a bit line pair and making a conduction state between the selected bit line pair and the global bit line pair.

Here, the bit line pair means two bit lines that are simultaneously compared by the sense amplifier. The global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form a pair of bit lines. The global bit line GBLL and the global bit line GBLR form a pair of global bit lines. Hereinafter, it is also referred to as a bit line pair (BLL, BLR) and a global bit line pair (GBLL, GBLR).

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 has a function of logically performing a command signal input from the outside to determine an operation mode, and a function of generating control signals of the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. It has a function to hold an address signal input from the outside and a function to generate an internal address signal.

(Line circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target line.

The column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by the selection signal of the column selector 1413. A plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.

(Column circuit 1415)
The column circuit 1415 has a function of controlling the input of the data signal WDA [31: 0] and a function of controlling the output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between global bit line pairs (GBLL, GBLR) and a function of maintaining this voltage difference. Writing and reading of data to and from the global bit line pair (GBLL, GBLR) is performed by the input / output circuit 1417.

The outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. The data of the global bit line pair is held by the global sense amplifier array 1416. The switch array 1444 of the local sense amplifier array 1426 specified by the address writes the data of the global bit line pair to the bit line pair of the target column. The local sense amplifier array 1426 amplifies and retains the written data. In the designated local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the holding data of the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.

The outline of the read operation of the DOSRAM 1400 will be described. The address signal specifies one row of the local memory cell array 1425. In the designated local memory cell array 1425, the word line WL of the target line is selected, and the data of the memory cell 1445 is written to the bit line. The voltage difference between the bit line pairs in each column is detected and held as data by the local sense amplifier array 1426. The switch array 1444 writes the data in the column specified by the address among the retained data of the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and retains the data of the global bit line pair. The holding data of the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.

Since the data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no limitation on the number of rewritings in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, it is easy to increase the capacity.

The transistor MW1 is an OS transistor. Since the off-current of the OS transistor is extremely small, it is possible to suppress the leakage of electric charge from the capacitive element CS1. Therefore, the holding time of the DOSRAM 1400 is much longer than that of the DRAM. Therefore, since the frequency of refreshing can be reduced, the power required for the refreshing operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that frequently rewrites a large amount of data, for example, a frame memory used for image processing.

Since the MC-SA array 1420 has a laminated structure, the bit wire can be shortened to a length as long as the length of the local sense amplifier array 1426. By shortening the bit line, the bit line capacity becomes small, and the holding capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when the DOSRAM 1400 is accessed can be reduced, and the power consumption can be reduced.

Therefore, it is easy to increase the capacity of the DOSRAM using the OS transistor. Further, since the DOSRAM using the OS transistor can be held for a long time, the penalty of the refresh operation can be substantially ignored. Further, the DOSRAM using the OS transistor can perform power gating of peripheral circuits by utilizing the potential of the back gate.

Here, FIG. 23 shows a graph comparing the power consumption of a DOS RAM using an OS transistor and a general DRAM. The vertical axis is a ratio (AU: arbitrary unit) in which the power consumption of a general DRAM is set to 1 when a use case is taken into consideration. The use case also assumes that 10% of the day is active, 90% is in standby, or self-refresh mode. As shown in the figure, it is estimated that the power consumption of the DOS RAM using the OS transistor can be reduced by about 20% of the power consumption of a general DRAM when the frequency of the refresh operation is reduced. Further, it is estimated that the power consumption of the DOS RAM using the OS transistor can be reduced by about 60% when power gating is performed.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, FIG. 24 is used to show an example of a chip 1200 on which the semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. Such a technique for integrating a plurality of circuits (systems) on one chip may be called a system on chip (SoC).

As shown in FIG. 24A, the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more. Interface 1215, one or more network circuits 1216 and the like.

The chip 1200 is provided with a bump (not shown) and is connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 24 (B). Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.

The motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Further, for example, the NO SRAM shown in the previous embodiment can be used for the flash memory 1222.

The CPU 1211 preferably has a plurality of CPU cores. Further, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. As the memory, the above-mentioned NOSRAM or DOSRAM can be used. Further, the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, it becomes possible to execute image processing and product-sum calculation with low power consumption.

Further, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, and data transfer between the memories of the CPU 1211 and the GPU 1212. And after the calculation on the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.

The analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.

The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.

The interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface) and the like can be used.

The network circuit 1216 has a network circuit such as a LAN (Local Area Network). Further, it may have a circuit for network security.

The circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

A PCB 1201 provided with a chip 1200 having a GPU 1212, a DRAM 1221, and a motherboard 1203 provided with a flash memory 1222 can be referred to as a GPU module 1204.

Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines. In addition, a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DEM) are provided by a product-sum calculation circuit using GPU1212. Since the operation such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 5)
In this embodiment, an application example of a storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording / playback device, a navigation system, etc.). Can be applied to. Here, the computer includes a tablet-type computer, a notebook-type computer, a desktop-type computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 25 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.

FIG. 25A is a schematic diagram of the USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like of the substrate 1104.

25 (B) is a schematic diagram of the appearance of the SD card, and FIG. 25 (C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 on the back surface side of the board 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. As a result, the data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like of the substrate 1113.

25 (D) is a schematic diagram of the appearance of the SSD, and FIG. 25 (E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like of the substrate 1153.

This embodiment can be appropriately combined with the configurations described in other embodiments and the like.

(Embodiment 6)
The semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip. FIG. 26 shows a specific example of a processor such as a CPU or GPU, or an electronic device provided with a chip according to one aspect of the present invention.

<Electronic devices / systems>
The GPU or chip according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include television devices, desktop or notebook personal chips, monitors for chips, digital signage (electronic signage), and relatively large game machines such as pachinko machines. In addition to electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, mobile information terminals, sound reproduction devices, and the like can be mentioned. Further, by providing an integrated circuit or chip according to one aspect of the present invention in an electronic device, artificial intelligence can be mounted on the electronic device.

The electronic device of one aspect of the present invention may have an antenna. By receiving the signal with the antenna, the display unit can display images, information, and the like. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

The electronic device of one aspect of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).

The electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like. FIG. 26 shows an example of an electronic device.

[cell phone]

FIG. 26A illustrates a mobile phone (smartphone) which is a kind of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and a button is provided in the housing 5510.

The information terminal 5500 can execute an application utilizing artificial intelligence by applying the chip of one aspect of the present invention. Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5511. Examples include an application displayed on the display unit 5511 and an application for performing biometric authentication such as fingerprints and voice prints.

[Information terminal 1]
FIG. 26B shows a desktop information terminal 5300. The desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

Similar to the information terminal 5500 described above, the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like. Further, by using the desktop type information terminal 5300, it is possible to develop a new artificial intelligence.

In the above description, smartphones and desktop information terminals are taken as examples as electronic devices, and although they are shown in FIGS. 26A and 26B, respectively, information terminals other than smartphones and desktop information terminals can be applied. can. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[electric appliances]
FIG. 26C shows an electric freezer / refrigerator 5800, which is an example of an electric appliance. The electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

By applying the chip of one aspect of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 has a function of automatically generating a menu based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, etc., and is stored in the electric refrigerator-freezer 5800. It can have a function to automatically adjust the temperature according to the food.

In this example, an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an microwave oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Examples include appliances, washing machines, dryers, audiovisual equipment, etc.

[game machine]

FIG. 26D shows a portable game machine 5200, which is an example of a game machine. The portable game machine has a housing 5201, a display unit 5202, a button 5203, and the like.

By applying the GPU or chip of one aspect of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.

Further, by applying the GPU or chip of one aspect of the present invention to the portable game machine 5200, the portable game machine 5200 having artificial intelligence can be realized.

Originally, expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5200, , Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.

Further, when a plurality of players are required to play a game on the portable game machine 5200, the game player can be constructed by artificial intelligence in an anthropomorphic manner. Therefore, by setting the opponent as a game player by artificial intelligence, even one player can play the game. You can play the game.

FIG. 26 (D) illustrates a portable game machine as an example of a game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this. Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a sports facility. A throwing machine for practicing batting can be mentioned.

[Mobile]
The GPU or chip of one aspect of the present invention can be applied to a moving vehicle and the vicinity of the driver's seat of the vehicle.

FIG. 26 (E1) shows an automobile 5700 which is an example of a moving body, and FIG. 26 (E2) is a diagram showing a periphery of a windshield in the interior of an automobile. FIG. 26 (E1) illustrates the display panel 5701, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar, which are attached to the dashboard.

The display panel 5701 to the display panel 5703 can provide various other information such as a speedometer, a tachometer, a mileage, a refueling amount, a gear state, and an air conditioner setting. In addition, the display items and layouts displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panel 5701 to 5703 can also be used as a lighting device.

By projecting an image from an image pickup device (not shown) provided in the automobile 5700 on the display panel 5704, the view (blind spot) blocked by the pillar can be complemented. That is, by displaying the image from the image pickup device provided on the outside of the automobile 5700, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, it is possible to confirm safety more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

Since the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system of an automobile 5700. In addition, the chip can be used in a system for road guidance, danger prediction, and the like. The display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.

In the above description, the automobile is described as an example of the moving body, but the moving body is not limited to the automobile. For example, moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, it is possible to provide a system using artificial intelligence.

[Broadcasting system]
The GPU or chip of one aspect of the present invention can be applied to a broadcasting system.

FIG. 26F schematically shows data transmission in a broadcasting system. Specifically, FIG. 26F shows a route for a radio wave (broadcast signal) transmitted from a broadcasting station 5680 to reach a television receiving device (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.

In FIG. 26 (F), the antenna 5650 illustrates a UHF (Ultra High Frequency) antenna, but as the antenna 5650, a BS / 110 ° CS antenna, a CS antenna, or the like can also be applied.

The radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio waves 5675A and transmits the radio waves 5675B. In each home, by receiving the radio wave 5675B with the antenna 5650, it is possible to watch the terrestrial TV broadcast on the TV 5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 26 (F), and may be satellite broadcasting using an artificial satellite, data broadcasting by an optical line, or the like.

The above-mentioned broadcasting system may be a broadcasting system using artificial intelligence by applying the chip of one aspect of the present invention. When broadcasting data is transmitted from the broadcasting station 5680 to the TV 5600 of each household, the broadcasting data is compressed by the encoder, and when the antenna 5650 receives the broadcasting data, the decoder of the receiving device included in the TV 5600 compresses the broadcasting data. Restoration is done. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of an encoder, it is possible to recognize a display pattern included in a display image. In-frame prediction using artificial intelligence can also be performed. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on the TV 5600 having a high resolution, it is possible to perform image interpolation processing such as up-conversion in the restoration of the broadcast data by the decoder.

The above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcasting data increases.

Further, as an application of artificial intelligence on the TV5600 side, for example, a recording device having artificial intelligence may be provided on the TV5600. With such a configuration, it is possible to automatically record a program that suits the user's preference by having the recording device learn the user's preference by artificial intelligence.

The electronic device described in this embodiment, the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be appropriately combined with the description of other electronic devices.

This embodiment can be appropriately combined with the configurations described in other embodiments and the like.

100a Capacitive Element, 100b Capacitive Element, 110 Conductor, 110_1 Conductor, 110_2 Conductor, 120 Conductor, 120_1 Conductor, 120_1 Conductor, 130 Insulator, 140a Transistor, 140b Transistor, 200a Transistor, 200b Transistor, 203 Conductor Body, 203_1 Conductor, 203_1 Conductor, 205 Conductor, 205_1 Conductor, 205_1 Conductor, 210 Insulation, 212 Insulation, 214 Insulation, 216 Insulation, 217 Insulation, 217_1 Insulation, 217_2 Insulation, 217_3 Insulation, 217_4 Insulation, 217_5 Insulation, 218 Conductor, 220 Insulation, 220_1 Insulation, 220_2 Insulation, 220_3 Insulation, 220_4 Insulation, 220_5 Insulation, 224 Insulation, 230 Oxide, 230C Oxidation Membrane, 231 region, 231a region, 231b region, 234 region, 235_2 conductor, 235_4 conductor, 240 conductor, 245 conductor, 248 conductor, 250 insulator, 253 conductor, 260 conductor, 260_1 conductor, 260_1 Conductor, 260_3 Conductor, 260_4 Conductor, 260A Conductor, 280 Insulator, 283 Insulator, 300 Transistor, 311 Substrate, 313 Semiconductor Region, 314a Low Resistance Region, 314b Low Resistance Region, 315 Insulator, 316 Conductor Body, 320 Insulator, 322 Insulator, 324 Insulator, 326 Insulator, 328 Conductor, 330 Conductor, 350 Insulator, 352 Insulator, 354 Insulator, 356 Conductor, 360 Insulator, 362 Insulator, 366 Conductor, 372 Insulator, 374 Insulator, 376 Conductor, 400 Conductor, 403 Conductor, 450 Insulator, 460 Conductor, 600 Cell 601 Cell, 1003 Wire, 1004a Wire, 1004b Wire, 1005a Wire, 1005b Wire , 1006a wiring, 1006b wiring, 1007 wiring, 1008 wiring, 1009 wiring, 1010 wiring, 3001 wiring, 3002 wiring, 3003 wiring, 3004a wiring, 3004b wiring, 3005a wiring, 3005b wiring, 3006a wiring, 3006b wiring, 3007 wiring.

Claims (4)

With the first insulator,
The second to sixth insulators arranged in an island shape on the first insulator,
With the oxides on the first to sixth insulators,
With the seventh insulator on the oxide,
A first conductor located between the second insulator and the third insulator and in contact with the seventh insulator.
A second conductor located between the third insulator and the fourth insulator and in contact with the seventh insulator.
A third conductor located between the fourth insulator and the fifth insulator and in contact with the seventh insulator,
A fourth conductor located between the fifth insulator and the sixth insulator and in contact with the seventh insulator.
With the eighth insulator on the seventh insulator and on the first to fourth conductors,
With a ninth insulator on the eighth insulator,
The seventh insulator and the eighth insulator are provided with a first opening to reach the oxide.
The seventh insulator, the eighth insulator, and the ninth insulator are provided with a second opening and a third opening to reach the oxide.
The first opening overlaps with the fourth insulator.
The second opening overlaps with the third insulator.
The third opening overlaps with the fifth insulator.
A fifth conductor is provided in the first opening, and a fifth conductor is provided.
A sixth conductor is provided in the second opening, and a sixth conductor is provided.
A seventh conductor is provided in the third opening, and a seventh conductor is provided.
An eighth conductor is provided on the fifth conductor, and an eighth conductor is provided.
A tenth insulator is provided in contact with the ninth insulator, the sixth conductor, and the seventh conductor.
A ninth conductor is provided so as to be superimposed on the second opening and in contact with the tenth insulator.
A semiconductor device that overlaps with the third opening and is provided with a tenth conductor in contact with the tenth insulator. In claim 1,
The oxide, the seventh insulator and the second conductor constitute the first transistor.
The oxide, the seventh insulator and the third conductor constitute a second transistor.
The oxide, the seventh insulator and the first conductor constitute a third transistor.
The oxide, the seventh insulator and the fourth conductor constitute a fourth transistor.
The sixth conductor, the tenth insulator, and the ninth conductor constitute a first capacitive element.
The seventh conductor, the tenth insulator, and the tenth conductor constitute a second capacitive element.
The first transistor and the second transistor are arranged between the first capacitive element and the second capacitive element.
The first capacitive element and the second capacitive element are arranged between the third transistor and the fourth transistor.
One of the source region and the drain region of the first transistor is connected to one electrode of the first capacitive element.
One of the source region and the drain region of the second transistor is connected to one electrode of the second capacitive element.
The other of the source or drain regions of the first transistor is shared with the other of the source or drain regions of the second transistor.
The other of the source or drain regions of the first transistor and the other of the source or drain regions of the second transistor are connected to the eighth conductor.
The channel length of the first transistor is longer than the length in the direction parallel to the short side of the second conductor.
A semiconductor device in which the channel length of the second transistor is longer than the length in the direction parallel to the short side of the third conductor. In claim 1 or 2,
The eighth conductor is provided so that the long side direction of the eighth conductor, the long side direction of the second conductor, and the long side direction of the third conductor are substantially orthogonal to each other. ,
The oxide is a semiconductor device provided with an angle formed by the long side direction of the oxide and the long side direction of the eighth conductor of 20 ° or more and 70 ° or less. In any one of claims 1 to 3,
A semiconductor device in which the oxide contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.

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