JP2019047101A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

To provide a semiconductor device having favorable electrical characteristics.SOLUTION: In a transistor 200 where conductors 242a, 242b are provided in contact with an oxide 230 and function as a source electrode and a drain electrode, when the conductors 242a, 242b have a function of absorbing oxygen in the oxide 230 or a function of supplying an impurity such as hydrogen or nitrogen or a metallic element to the oxide 230, a low-resistance region may be partially formed in the oxide 230. By making a film thickness of an insulator 250 between the conductors 242a, 242b and a conductor 260 thicker than a film thickness between the oxide 230b and the conductor 260, parasitic capacitance between the conductor 260 and the conductors 242a, 242b is further reduced to achieve higher frequency characteristics. Further, because the film thickness between the oxide 230b and the conductor 260 is thin, an electric field from a gate electrode does not weaken thereby to achieve favorable electrical characteristics.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device. Display devices (liquid crystal display devices, light emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, and the like may have semiconductor devices in some cases. .

  Note that one embodiment of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  In recent years, semiconductor devices have been developed, and in particular, processors such as LSIs, CPUs and GPUs, and memories have been developed. The processor is a group of semiconductor elements including a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and in which electrodes serving as connection terminals are formed.

  A processor such as an LSI, a CPU or a GPU, and a semiconductor circuit (IC chip) such as a memory are mounted on a circuit board, for example, a printed wiring board, and used as one of components of a variety of electronic devices including a computer.

  In addition, a technique of forming a transistor by using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have attracted attention as other materials.

  In addition, a transistor including an oxide semiconductor is known to have extremely small leakage current in a non-conduction state. For example, a low power consumption CPU or the like to which a characteristic that a leak current of a transistor including an oxide semiconductor is low is applied is disclosed (see Patent Document 1).

  In addition, a method of manufacturing a transistor including an oxide semiconductor by embedding a gate electrode in an opening and the like is disclosed (see Patent Document 2).

  Further, in recent years, with the miniaturization and weight reduction of electronic devices, the demand for integrated circuits in which transistors and the like are integrated at high density is increasing. There is also a need to improve the productivity of semiconductor devices including integrated circuits. Also, the semiconductor device as described above can be applied to artificial intelligence (AI) and AI systems, and is preferable.

  Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials. As the oxide semiconductor, for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known. Among oxides of multi-element metals, in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

  According to research on IGZO, a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure which are neither single crystal nor amorphous are found in an oxide semiconductor (see Non-Patent Documents 1 to 3) ). Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, non-patent documents 4 and 5 show that even oxide semiconductors that are less crystalline than the CAAC structure and the nc structure have minute crystals.

  Furthermore, a transistor using IGZO as an active layer has extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing its characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8) ).

JP 2012-257187 A JP, 2017-050530, A

S. Yamazaki et al. “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED 18-1-04 ED 18-10 S. Ito et al. , "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p. 151-154 S. Yamazaki et al. “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, "ECS Transactions", 2014, volume 64, issue 10, p. 155-164 K. Kato et al. , "Japanese Journal of Applied Physics", 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , "2015 Symposium on VLSI Technology Digest of Technical Papers", 2015, p. T216-T217 S. Amano et al. “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p. 626-629

  An object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device having favorable frequency characteristics. An object of one embodiment of the present invention is to provide a semiconductor device with high reliability. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

  An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time. An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

  Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, it is not necessary to solve all of these problems. In addition, problems other than these are naturally apparent from the description of the specification, drawings, claims and the like, and it is possible to extract the problems other than these from the description of the specification, drawings, claims and the like. It is.

  One embodiment of the present invention provides a first insulator, an oxide on the first insulator, a first conductor on the oxide, and a second conductor, and a third on the oxide. A second insulator disposed between the conductor, the oxide, and the third conductor and disposed to cover the side surface of the third conductor, and in contact with the side surface of the second insulator And a third insulator covering the top and side surfaces of the first conductor, the top and side surfaces of the second conductor, and the side surface of the oxide, and a fourth insulator on the third insulator And a fifth insulator in contact with the top surface of the second insulator and covering the third conductor, wherein the third insulator is an opening that exposes the first insulator And the fourth insulator is a semiconductor device in contact with the first insulator through the opening.

  One embodiment of the present invention is a first insulator, a first oxide having a first opening on the first insulator, a second oxide on the first oxide, Disposed between the first conductor on the second oxide and the second conductor, the third conductor on the oxide, the oxide and the third conductor, and A second insulator arranged to cover the side surface of the conductor, an upper surface and a side surface of the first conductor in contact with the side surface of the second insulator, and an upper surface of the second conductor, A third insulator covering the side surface, the first oxide side surface, and the second oxide side surface, a fourth insulator on the third insulator, and a second insulator And a fifth insulator in contact with the upper surface and covering the third conductor, wherein the second oxide is in contact with the first insulator via the first opening, and the third insulator The body exposes a first insulator and a second opening A fourth insulator, a semiconductor device in contact with the first insulator through the second opening.

  In the above, the oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.

  In the above, the first oxide includes In, the element M (M is Al, Ga, Y, or Sn), and Zn, and the second oxide includes In and the element M (M It is preferable to have Al, Ga, Y or Sn) and Zn.

  In the above, the second insulator is preferably an oxide containing one or both of aluminum and hafnium.

  In the above, the third insulator is preferably an oxide containing one or both of aluminum and hafnium.

  In the above, the fifth insulator is preferably an oxide containing one or both of aluminum and hafnium.

  In the above, the semiconductor device preferably further includes a sixth insulator, and the sixth insulator is preferably provided between the third conductor and the second insulator.

  In the above, the first conductor and the second conductor are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium It is preferable to have at least one of beryllium, indium, ruthenium, iridium, strontium and lanthanum.

  In the above, the first conductor and the second conductor include tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to have at least one of an oxide and an oxide containing lanthanum and nickel.

  According to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having favorable frequency characteristics can be provided. According to the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  Alternatively, a semiconductor device capable of holding data for a long time can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with a high degree of freedom in design can be provided. Alternatively, a semiconductor device capable of suppressing power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not have to have all of these effects. Note that effects other than these are naturally apparent from the description of the specification, drawings, claims and the like, and other effects can be extracted from the descriptions of the specification, drawings, claims and the like. It is.

7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and a cross-sectional view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 16 is a circuit diagram of a memory device according to one embodiment of the present invention. FIG. 10 is a schematic view of a memory device according to one embodiment of the present invention. FIG. 10 is a schematic view of a memory device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. 5A and 5B are a block diagram and a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the structural example of AI system which concerns on 1 aspect of this invention. The block diagram explaining the application example of the AI system concerning one mode of the present invention. The perspective view showing the example of composition of IC which incorporated the AI system concerning one mode of the present invention. 5A and 5B illustrate a configuration example of an electronic device and a system according to one embodiment of the present invention. FIG. 7 is a diagram showing an example of the configuration of a parallel computer, a computer, and a PC card according to an aspect of the present invention. FIG. 1 is a diagram showing an example of the configuration of a system according to an aspect of the present invention.

  Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiment can be implemented in many different aspects and that the form and details can be variously changed without departing from the spirit and the scope thereof. Ru. Therefore, the present invention should not be construed as being limited to the following description of the embodiments.

  Also, in the drawings, the size, layer thicknesses, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer, a resist mask, and the like may be unintentionally reduced by a process such as etching, but may be omitted for ease of understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description may be omitted. In addition, when referring to the same function, the hatch pattern may be the same and no reference numeral may be given.

  In particular, in order to facilitate the understanding of the invention, the description of some of the components may be omitted particularly in a top view (also referred to as a "plan view") or a perspective view. In addition, the description of some hidden lines may be omitted.

  Further, in the present specification and the like, the ordinal numbers given as the first, second and the like are used for convenience and do not indicate the order of steps or the order of layers. Therefore, for example, "first" can be appropriately replaced with "second" or "third" and the like. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

  Further, in the present specification and the like, the terms indicating the arrangement such as “above” and “below” are used for the sake of convenience to explain the positional relationship between the configurations with reference to the drawings. In addition, the positional relationship between the components is appropriately changed in accordance with the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification, and can be appropriately rephrased depending on the situation.

  For example, in the present specification, when X and Y are directly connected and when it is explicitly described that X and Y are connected, X and Y are electrically It is assumed that the case where they are connected as well as the case where X and Y are functionally connected are disclosed in this specification and the like. Therefore, the present invention is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the sentence, and anything other than the connection relationship shown in the figure or the sentence is also described in the figure or the sentence.

  Here, X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).

  As an example in the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) capable of electrically connecting X and Y An element (e.g., a switch, a transistor, a capacitive element, an inductor) that enables an electrical connection between X and Y when the element, the light emitting element, the load, etc. is not connected between X and Y , X, and Y are connected without interposing a resistance element, a diode, a display element, a light emitting element, a load, and the like.

  As an example when X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) which enables electrical connection of X and Y One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on and off. That is, the switch has a function of turning on (on) or non-conducting (off) and controlling whether current flows or not. Alternatively, the switch has a function of selecting and switching a path through which current flows. In addition, when X and Y are electrically connected, the case where X and Y are directly connected shall be included.

  As an example when X and Y are functionally connected, a circuit (for example, a logic circuit (for example, an inverter, a NAND circuit, a NOR circuit, etc.) that enables functional connection of X and Y, signal conversion Circuits (DA converter circuit, AD converter circuit, gamma correction circuit, etc.), potential level converter circuits (power supply circuits (boost circuit, step-down circuit etc.), level shifter circuits for changing the potential level of signals, etc.) voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc. It is possible to connect one or more in between. As an example, even if another circuit is interposed between X and Y, X and Y are functionally connected if the signal output from X is transmitted to Y. Do. Note that when X and Y are functionally connected, the case where X and Y are directly connected and the case where X and Y are electrically connected are included.

  Further, in this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. Then, there is a region where a channel is formed between the drain (the drain terminal, the drain region, or the drain electrode) and the source (the source terminal, the source region, or the source electrode). Current can flow between the source and the drain. Note that in this specification and the like, a region where a channel is formed refers to a region through which current mainly flows.

  In addition, the functions of the source and the drain may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in the present specification and the like, the terms “source” and “drain” may be used interchangeably.

  Note that a channel length is, for example, a region where a semiconductor (or a portion through which current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region. Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be determined to one value. Therefore, in the present specification, the channel length is any one value, maximum value, minimum value, or average value in a region where a channel is formed.

  The channel width is, for example, a region where a semiconductor (or a portion through which current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other or a region where a channel is formed; The length of the part facing each other. Note that in one transistor, the channel width may not be the same in all regions. That is, the channel width of one transistor may not be determined to one value. Therefore, in the present specification, the channel width is taken as any one value, maximum value, minimum value, or average value in the region where the channel is formed.

  Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor (hereinafter, “apparently” Channel width) and may be different. For example, when the gate electrode covers the side of the semiconductor, the effective channel width may be larger than the apparent channel width, and the effect may not be negligible. For example, in a transistor in which the gate electrode covers the side surface of the semiconductor finely, the ratio of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

  In such a case, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width unless the shape of the semiconductor is accurately known.

  Thus, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. Also, in the present specification, the term “channel width only” may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term “channel width” may refer to an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width and the like can be determined by analyzing a cross-sectional TEM image or the like.

  Note that the impurity of a semiconductor means, for example, elements other than the main components of the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may cause, for example, an increase in the DOS (Density of States) of the semiconductor, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and an oxide semiconductor. And transition metals other than the main components thereof, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by the addition of impurities. Further, when the semiconductor is silicon, examples of the impurity that changes the characteristics of the semiconductor include oxygen, a group 1 element excluding hydrogen, a group 2 element, a group 13 element, and a group 15 element.

  In this specification and the like, the silicon oxynitride film is a film having a higher oxygen content than nitrogen as the composition. For example, preferably, oxygen is 55 atomic% or more and 65 atomic% or less, nitrogen is 1 atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, hydrogen is 0.1 atomic% or more and 10 atomic% or less It refers to what is included in the concentration range. Further, the silicon nitride oxide film is a film having a nitrogen content higher than that of oxygen as the composition thereof. For example, preferably, nitrogen is 55 atomic percent or more and 65 atomic percent or less, oxygen is 1 atomic percent or more and 20 atomic percent or less, silicon is 25 atomic percent or more and 35 atomic percent or less, and hydrogen is 0.1 atomic percent or more and 10 atomic percent or less It refers to what is included in the concentration range.

  In the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

  Further, in this specification and the like, the term "insulator" can be reworded as an insulating film or an insulating layer. Further, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be reworded as a semiconductor film or a semiconductor layer.

  In addition, transistors shown in the present specification and the like are field effect transistors except when explicitly stated. In addition, transistors shown in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V except when explicitly stated.

  Moreover, in this specification etc., "parallel" means the state in which two straight lines are arrange | positioned by the angle of -10 degree or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Further, “substantially parallel” refers to a state in which two straight lines are arranged at an angle of −30 degrees or more and 30 degrees or less. Moreover, "vertical" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Further, “substantially perpendicular” refers to a state in which two straight lines are disposed at an angle of 60 degrees or more and 120 degrees or less.

  In this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and in the case where the barrier film has conductivity, it is called a conductive barrier film. There is.

  In the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET or an OS transistor, it can be said to be a transistor having an oxide or an oxide semiconductor.

In this specification and the like, normally-off means that the current per 1 μm of the channel width flowing in the transistor is 1 × 10 ⁻²⁰ at room temperature when no potential is applied to the gate or the ground potential is applied to the gate. A or less, 1 × 10 ⁻¹⁸ A or less at 85 ° C., or 1 × 10 ⁻¹⁶ A or less at 125 ° C.

Embodiment 1
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

<Configuration Example of Semiconductor Device>
1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 200 and a periphery of the transistor 200 according to one embodiment of the present invention.

  FIG. 1A is a top view of a semiconductor device including the transistor 200. FIG. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 1A, and is also a cross-sectional view in the channel length direction of the transistor 200. 1C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 1A, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 1A, some elements are omitted for clarity of the drawing.

  The semiconductor device of one embodiment of the present invention includes the transistor 200, the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 280, and the insulator 281. Further, the transistor 200 includes the conductor 203 electrically connected to the transistor 200 and functioning as a wiring, and the conductor 240 functioning as a plug (conductors 240 a and 240 b).

  A conductor 203a is formed in contact with the inner wall of the opening of the insulator 212, and a conductor 203b is formed inside the conductor 203. Here, the height of the top surface of the conductor 203 and the height of the top surface of the insulator 212 can be approximately the same. Note that although the transistor 200 illustrates a structure in which the conductor 203a and the conductor 203b are stacked, the present invention is not limited to this. For example, the conductor 203 may be provided as a single layer or a stacked structure of three or more layers. In the case where the structure has a stacked structure, ordinal numbers may be assigned in order of formation to be distinguished.

  In addition, the conductor 240 is in contact with the insulator 244, the insulator 280, the insulator 274, and the inner wall of the opening of the insulator 281, and the first conductor of the conductor 240 is formed. A second conductor is formed. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 281 can be approximately the same. Note that although the transistor 200 illustrates a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. In the case where the structure has a stacked structure, ordinal numbers may be assigned in order of formation to be distinguished.

[Transistor 200]
As shown in FIG. 1, the transistor 200 includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, and the insulator 214 and the insulator 216. A conductor 205 disposed to be embedded, an insulator 220 disposed on the insulator 216 and the conductor 205, an insulator 222 disposed on the insulator 220, and an insulator 222 An insulator 230 disposed, an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and a conductor 242 disposed on the oxide 230b; An insulator 244 covering the insulator 224, the oxide 230a, the oxide 230b, and the conductor 242, an insulator 280 disposed on the insulator 244 and having an opening, and the oxide 230b in the opening An insulator 273 provided in contact with the surface, the side surface of the conductor 242, the side surface of the insulator 244, and the side surface of the insulator 280, and the insulator 250 provided inside the insulator 273; The insulator 272 provided inside the insulator 250, the conductor 260a provided inside the insulator 272, the conductor 260b provided so as to be embedded inside the conductor 260a, and the insulator 280 , The insulator 250, the insulator 272, the conductor 260a, the insulator 274 provided on the conductor 260b, and the insulator 281 on the insulator 274.

  Note that the insulator 244 preferably includes an opening 290 which exposes the insulator 224, and the insulator 224 and the insulator 280 are preferably in contact with each other through the opening 290. The insulator 244 and the insulator 273 are preferably in contact with each other. Further, it is preferable that the insulator 273 and the insulator 274 be in contact with each other.

  Note that in the transistor 200, a structure in which two layers of the oxide 230a and the oxide 230b are stacked in a region where a channel is formed (hereinafter, also referred to as a channel formation region) and in the vicinity thereof is described. The invention is not limited to this. For example, a single layer of the oxide 230 b or a stacked structure of three or more layers may be provided. In the transistor 200, the conductor 260 is illustrated as a two-layer structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

  Here, the conductor 260 functions as a gate electrode of the transistor, and the conductor 242a and the conductor 242b function as a source electrode or a drain electrode, respectively. As described above, the conductor 260 is embedded in the opening of the insulator 280 and the region between the conductor 242 a and the conductor 242 b via the insulator 273, the insulator 250, and the insulator 272. It is formed. Here, the arrangement of the conductor 260, the conductor 242a, and the conductor 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 200, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Thus, the conductor 260 can be formed without providing a positioning margin, so that the area occupied by the transistor 200 can be reduced. Thus, the semiconductor device can be miniaturized and highly integrated.

  Further, since the conductor 260 is formed in a self-aligned manner in the region between the conductor 242a and the conductor 242b, the conductor 260 does not have a region overlapping with the conductor 242a or the conductor 242b. Thus, parasitic capacitance formed between the conductor 260 and the conductor 242a and the conductor 242b can be reduced. Thus, the switching speed of the transistor 200 can be improved and high frequency characteristics can be provided.

  In the transistor 200, a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a and the oxide 230b) including a channel formation region. .

  The transistor 200 in which an oxide semiconductor is used for a channel formation region has extremely low leakage current in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. Further, an oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.

  For example, an In-M-Zn oxide is used as the oxide 230 (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium It is preferable to use a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium. In addition, as the oxide 230, an In-Ga oxide or an In-Zn oxide may be used.

  Here, when an impurity such as hydrogen, nitrogen, or a metal element is present in the oxide 230, the carrier density may be increased to reduce resistance. In addition, when the concentration of oxygen contained in the oxide 230 is lowered, the carrier density may be increased, and the resistance may be lowered.

  When the conductor 242 a and the conductor 242 b are provided so as to be in contact with the oxide 230 and function as a source electrode and a drain electrode, the oxide 230 has a function of absorbing oxygen, or the oxide 230 When the oxide 230 has a function of supplying an impurity such as hydrogen, nitrogen, or a metal element to the oxide 230, a low resistance region may be partially formed in the oxide 230.

  In addition, the insulator 250 may have a larger thickness between the conductor 242 and the conductor 260 than the thickness between the oxide 230 b and the conductor 260. In order to obtain such a structure, the oxide 230 b and the insulator 250 located between the conductors 260 are a single layer, and the conductor 242 and the insulator 250 located between the conductors 260 are stacked. It is preferable to do. When the insulator 250 located between the oxide 230 b and the conductor 260 has a stacked structure, the number of stacked insulators 250 located between the conductor 242 and the conductor 260 is the oxide 230 b and the number of stacked insulators 250. The number may be greater than the number of stacked insulators 250 located between the conductors 260.

  By thus making the film thickness of the insulator 250 between the conductor 242 and the conductor 260 thicker than the film thickness between the oxide 230 b and the conductor 260, the film thickness between the conductor 260 and the conductor 242 is The parasitic capacitance can be further reduced, and the transistor 200 having higher frequency characteristics can be provided. Further, since the film thickness between the oxide 230 b and the conductor 260 is thin, the electric field from the gate electrode is not weakened, so that the transistor 200 having favorable electrical characteristics can be provided.

  The insulator 244 is provided so that the side surface of the oxide 230 does not directly touch the insulator 280. In addition, it is provided to suppress the oxidation of the conductor 242. However, the insulator 244 does not have to have an effect of suppressing the oxidation of the conductor 242 when the conductor 242 does not significantly reduce the conductivity even when it absorbs an oxidation resistant material or oxygen.

  By providing the insulator 244, oxygen which the insulator 280 has can be suppressed from being injected from the side surface of the oxide 230.

  The insulator 244 has an opening 290. In FIG. 1A, the insulator 244 shows an example having a slit-shaped opening 290. The slits may extend in the A3-A4 direction and may be shared by a plurality of transistors arranged in the direction, or a slit-shaped opening 290 may be provided for each transistor. Further, the shape of the opening 290 is not limited to the slit shape. One or more openings 290 having a circular, rectangular, or polygonal shape may be provided for each transistor. In addition, the opening 290 may be provided to surround the outer periphery of the oxide 230. For example, the openings 290 may be provided in a grid. In this case, it is preferable that one or more of the transistors 200 have a structure surrounded by the grid-like openings 290.

  Further, the area of the opening 290 corresponds to the contact area of the insulator 224 and the insulator 280, and the contact area of the insulator 244 and the insulator 280 increases as the area of the opening 290 increases. That is, a path for oxygen contained in the insulator 280 to diffuse to the insulator 224 is expanded. In order to supply more oxygen to the oxide 230, the area of the opening 290 may be increased, and when it is desired to limit the amount of oxygen supplied to the oxide 230, the area of the opening 290 may be reduced.

  The insulator 272 is provided to suppress the oxidation of the conductor 260. Therefore, the insulator 272 is not necessarily provided if the conductor 260 does not significantly reduce the conductivity even when it absorbs an oxidation resistant material or oxygen.

  Here, FIG. 2 shows an enlarged view of a region 239 surrounded by a dashed dotted line in FIG. 1 (B).

  As shown in FIG. 2, a conductor 242 is provided on and in contact with the oxide 230, and a region 231 of the oxide 230 which functions as a source region or a drain region in the interface with the conductor 242 and the vicinity thereof. The regions 231a and 231b) are formed. In addition, the oxide 230 includes a region 234 which functions as a channel formation region of the transistor 200 between the region 231 a and the region 231 b. The region 231 functioning as a source region or a drain region has lower resistance than the region 234 functioning as a channel formation region, and can be called a low-resistance region.

  The region 231 functioning as a source region or a drain region is a region in which the carrier concentration is increased by containing hydrogen, nitrogen, an impurity such as a metal element, or the like, or the concentration of oxygen is low, and the resistance is lowered. That is, the region 231 is a low resistance region in which the carrier density is higher than that of the region 234. In addition, the region 234 which functions as a channel formation region is a high resistance region in which the carrier density is low because the impurity concentration is lower or the oxygen concentration is higher than the region 231.

  Note that in the case where the region 231 which is a low resistance region contains a metal element, in addition to the oxide 230, the region 231 contains aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, It is preferable to have any one or more metal elements selected from metal elements such as vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum.

  Further, in FIG. 2, the region 231 is formed from the interface of the oxide 230 b with the conductor 242 to the interface of the oxide 230 a with the insulator 224 in the film thickness direction of the oxide 230. It is not limited. For example, the region 231 may have a thickness substantially the same as the thickness of the oxide 230 b or may be formed only in the vicinity of the interface between the oxide 230 b and the conductor 242.

  Further, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes in each region, and are continuously changed (also referred to as gradation) in each region. May be That is, the concentration of the metal element and the impurity element such as hydrogen and nitrogen may be reduced as the region is closer to the channel formation region.

  In order to selectively reduce the resistance of the oxide 230, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, or the like can be used as the conductor 242. It is preferable to use a material containing at least one of a metal element that enhances conductivity such as manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, and an impurity. Alternatively, in the formation of the conductive film 242A to be the conductor 242, a material, a deposition method, or the like in which an impurity such as an element forming an oxygen vacancy or an element trapped in an oxygen vacancy is implanted is used for the oxide 230. Good. For example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, a rare gas and the like can be mentioned as the element. In addition, helium, neon, argon, krypton, xenon and the like are representative examples of the rare gas element.

  Here, in the transistor including an oxide semiconductor, when impurities and oxygen vacancies are present in a region of the oxide semiconductor in which a channel is formed, the electrical characteristics are easily changed and the reliability might be deteriorated. In addition, when oxygen vacancies are included in the region in the oxide semiconductor in which a channel is formed, the transistor is likely to be normally on. Therefore, it is preferable that oxygen deficiency in the region 234 where the channel is formed be reduced as much as possible.

  In order to suppress normally-on conversion of the transistor, an oxygen-containing insulator is provided in contact with the oxide 230, and oxygen in the insulator is diffused to the oxide 230 to reduce oxygen vacancies in the oxide 230. Thus, the transistor can be suppressed from being normally on. On the other hand, when oxygen is excessively supplied to the oxide 230, the reliability of the transistor may be deteriorated. Therefore, it is preferable to define a route for supplying oxygen to the oxide 230 so that the oxide 230 is not excessively supplied with oxygen.

  In this embodiment mode, oxygen is supplied to the oxide 230 from the insulator 224 in proximity to the oxide 230. Oxygen in the insulator 224 can be diffused to the oxide 230, so that oxygen vacancies in the oxide 230 can be reduced and normally on conversion of the transistor can be suppressed.

  In order to supply oxygen from the insulator 224 to the oxide 230, the insulator 224 may be formed to contain oxygen. For example, a gas containing oxygen may be used as a gas for forming the insulator 224, and the insulator 224 may be formed to contain oxygen at a higher proportion than the stoichiometric composition. Alternatively, after the insulator 224 is formed, oxygen may be supplied to the insulator 224 using one or more methods selected from an ion implantation method, an ion doping method, a plasma treatment, and a plasma immersion ion implantation method. Good. At this time, oxygen can be supplied to the insulator 224 with good control by using an ion implantation method in which ionized source gas is separated by mass and added, which is preferable. Alternatively, oxygen may be supplied to the insulator 224 by forming the insulator 274 over the insulator 280 in contact with the insulator 224 through the opening 290 provided in the insulator 244. At that time, the insulator 274 is preferably formed using a gas containing oxygen as a deposition gas. Alternatively, a sputtering target containing oxygen is preferably used for sputtering. For example, a mixed gas of oxygen and argon and a target containing oxygen and aluminum are used to form the insulator 274 having aluminum oxide. Oxygen contained in the insulator 280 is supplied to the insulator 224 through the opening 290.

  On the other hand, since the side surface of the oxide 230 is covered with the insulator 244, oxygen supplied to the insulator 280 can be suppressed from being supplied from the side surface of the oxide 230. In addition, since the insulator 244 and the insulator 273 are in contact with each other, oxygen in the insulator 280 can be suppressed from being supplied from the upper surface or the side surface of the oxide 230 through the insulator 250 or the like.

  With the above structure, the supply amount of oxygen to the oxide 230 can be controlled, and a transistor with high reliability and suppressed on-normalization can be obtained.

  In addition, the insulator 222, the insulator 244, the insulator 273, the insulator 272, the insulator 274, and the like are included in order to suppress diffusion of oxygen in the oxide 230 and the insulator 224 to the outside of the transistor 200. It is preferable to be provided. As these insulators, it is preferable to use a material that hardly transmits oxygen. For example, an oxide containing one of aluminum and hafnium, a nitride of silicon, or the like can be used. Furthermore, these insulating films are preferably materials which are hard to transmit impurities such as hydrogen, water, nitrogen, and metal elements. By using such a material, entry of impurities into the transistor 200 can be suppressed from the outside of the transistor 200.

  Further, an oxide semiconductor can be formed by a sputtering method or the like and thus can be used for a transistor included in a highly integrated semiconductor device. In addition, a transistor in which an oxide semiconductor is used for a channel formation region has extremely low leak current (off current) in a non-conduction state; thus, a semiconductor device with low power consumption can be provided.

  Thus, a semiconductor device having a transistor with a large on current can be provided. Alternatively, a semiconductor device having a transistor with low off current can be provided. Alternatively, a semiconductor device can be provided which has stable electrical characteristics and suppressed reliability while suppressing fluctuations in the electrical characteristics.

  Hereinafter, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

  The conductor 203 is extended in the channel width direction as shown in FIGS. 1A and 1C, and functions as a wiring for applying a potential to the conductor 205. Note that the conductor 203 is preferably provided so as to be embedded in the insulator 212.

  The conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. The conductor 205 may be provided on and in contact with the conductor 203. The conductor 205 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.

  Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking. In particular, by applying a negative potential to the conductor 205, Vth of the transistor 200 can be larger than 0 V and off current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.

  Further, by providing the conductor 205 over the conductor 203, the distance between the conductor 260 having the function of the first gate electrode and the wiring and the conductor 203 can be appropriately designed. That is, by providing the insulator 214, the insulator 216, and the like between the conductor 203 and the conductor 260, the parasitic capacitance between the conductor 203 and the conductor 260 is reduced, and the conductor 203 and the conductor 260 are formed. The withstand voltage between them can be increased.

  In addition, by reducing parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor 200 can be improved, and a transistor with high frequency characteristics can be provided. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200 can be improved. Therefore, the thicknesses of the insulator 214 and the insulator 216 are preferably large. Note that the extension direction of the conductor 203 is not limited to this. For example, the conductor 203 may extend in the channel length direction of the transistor 200.

  Note that the conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260 as illustrated in FIG. In addition, the conductor 205 may be larger than the region 234 in the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 is preferably extended also in a region outside the end portion of the region 234 of the oxide 230 which intersects the channel width direction. That is, on the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other through an insulator.

  With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230 The area can be covered.

  That is, the channel formation region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode and the electric field of the conductor 205 having a function as the second gate electrode. . In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

  In addition, the conductor 205 is in contact with the inner wall of the opening of the insulator 214 and the insulator 216, the conductor 205a is formed, and the conductor 205b is formed further inside. Here, the heights of the top surfaces of the conductors 205a and 205b and the top surface of the insulator 216 can be approximately the same. Note that although the transistor 200 illustrates a structure in which the conductor 205a and the conductor 205b are stacked, the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a stacked structure of three or more layers. In the case where the structure has a stacked structure, ordinal numbers may be assigned in order of formation to be distinguished.

Here, the conductor 205a or the conductor 203a can diffuse impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _{2 and the} like), copper atoms, and the like. It is preferable to use a conductive material having a suppressing function (the above-mentioned impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of at least one of oxygen (for example, an oxygen atom, an oxygen molecule, and the like) (the above oxygen is hardly transmitted). In the present specification, the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above-described impurities or oxygen.

  When the conductor 205a or the conductor 203a has a function of suppressing the diffusion of oxygen, the conductor 205b or the conductor 203b can be suppressed from being oxidized to be lowered in conductivity. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used. Therefore, as the conductor 205a or the conductor 203a, the above conductive material may be formed as a single layer or a stack. Accordingly, diffusion of impurities such as hydrogen and water can be suppressed from the insulator 210 to the transistor 200 side through the conductor 203 and the conductor 205 from the substrate side.

  The conductor 205 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the conductor 205 b is illustrated as a single layer, a layered structure may be used, and for example, titanium, titanium nitride, and the above conductive material may be stacked.

  In addition, since the conductor 203b functions as a wiring, it is preferable to use a conductor having higher conductivity than the conductor 205b. For example, a conductive material containing copper or aluminum as a main component can be used. The conductor 203 b may have a stacked structure, for example, a stack of titanium or titanium nitride and the above conductive material.

  In particular, copper is preferably used for the conductor 203 b. Copper is preferably used for wiring and the like because it has low resistance. On the other hand, copper is easily diffused; thus, diffusion to the oxide 230 may deteriorate the electrical characteristics of the transistor 200. Therefore, for example, by using a material such as aluminum oxide or hafnium oxide with low copper permeability for the insulator 214, copper diffusion can be suppressed.

  Note that the conductor 205, the insulator 214, and the insulator 216 may not necessarily be provided. In that case, part of the conductor 203 can function as a second gate electrode.

The insulator 210 and the insulator 214 preferably function as a barrier insulating film which suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulator 210 and the insulator 214 can diffuse impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _{2, and the} like), copper atoms, and the like. It is preferable to use an insulating material having a suppressing function (the above-mentioned impurities are difficult to transmit). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atom, oxygen molecule, and the like) (the above-described oxygen is hardly transmitted).

  For example, aluminum oxide or the like is preferably used as the insulator 210, and silicon nitride or the like is preferably used as the insulator 214. Accordingly, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 200 side with respect to the insulator 210 and the insulator 214 can be suppressed. Alternatively, diffusion of oxygen contained in the insulator 224 or the like to the substrate side than the insulator 210 and the insulator 214 can be suppressed.

  Further, by providing the conductor 205 over the conductor 203, the insulator 214 can be provided between the conductor 203 and the conductor 205. Here, even if a metal such as copper is easily diffused as the second conductor of the conductor 203, the metal is diffused to a layer higher than the insulator 214 by providing silicon nitride or the like as the insulator 214. Can be suppressed.

  The insulator 212, the insulator 216, the insulator 280, and the insulator 281 each functioning as an interlayer film preferably have a lower dielectric constant than the insulator 210 or the insulator 214. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

For example, as the insulator 212, the insulator 216, the insulator 280, and the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT Insulators such as strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used in a single layer or stacked layers. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  The insulator 220, the insulator 222, the insulator 224, the insulator 273, the insulator 250, and the insulator 272 function as a gate insulator.

  The insulator 224 is preferably an insulator that contains oxygen at a higher proportion than the stoichiometric composition. By thus providing the insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and normally-on conversion can be suppressed without reduction in the reliability of the transistor 200. it can.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator containing oxygen. The oxide from which oxygen is released by heating is a desorption amount of oxygen of at least 1.0 × 10 ¹⁸ atoms / cm ³ , preferably 1 in terms of oxygen atom in TDS (thermal desorption spectroscopy) analysis. It is an oxide film having a density of not less than 0 × 10 ¹⁹ atoms / cm ³ , more preferably not less than 2.0 × 10 ¹⁹ atoms / cm ³ , or not less than 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

  In the case where the insulator 224 contains oxygen, the insulator 222 has a function of suppressing the diffusion of at least one of oxygen (e.g., an oxygen atom, an oxygen molecule, and the like) (the above oxygen is difficult to transmit). preferable.

  Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, oxygen included in the oxide 230 is preferably not diffused to the insulator 220 side. In addition, the conductor 205 can be inhibited from reacting with the insulator 224 and oxygen in the oxide 230.

The insulator 222 is, for example, a so-called high material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator containing a -k material in a single layer or a stack. As the miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential at the time of transistor operation while maintaining the physical thickness.

  In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium which is an insulating material having a function of suppressing diffusion of impurities, oxygen, and the like (the above oxygen is difficult to transmit). As an insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 suppresses the release of oxygen from the oxide 230 and the entry of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Act as a layer.

  Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  In addition, the insulator 220 and the insulator 224 are preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, the combination of an insulator with a high-k material and the insulator 220 or the insulator 224 produces a thermally stable and high dielectric constant. It can be a laminated structure.

  Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.

  The oxide 230 includes an oxide 230a and an oxide 230b over the oxide 230a. By including the oxide 230a under the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, by including the insulator 273 over the oxide 230 b, diffusion of impurities from the structure formed above the insulator 273 to the oxide 230 b can be suppressed.

  Note that the oxide 230 preferably has a stacked-layer structure of oxides having different atomic ratios of metal atoms. For example, an In-M-Zn oxide is used as the oxide 230 (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium It is preferable to use a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium. In addition, as the oxide 230, an In-Ga oxide or an In-Zn oxide may be used. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is larger than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. Is preferred. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

  Further, it is preferable that the energy at the lower end of the conduction band of the oxide 230a be higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a is smaller than the electron affinity of the oxide 230b.

  Here, at the junction of the oxide 230 a and the oxide 230 b, the energy level at the lower end of the conduction band changes gradually. In other words, the energy level at the lower end of the conduction band at the junction of the oxide 230a and the oxide 230b can be said to be continuously changed or continuous junction. In order to do this, it is preferable to lower the density of defect states in the mixed layer formed at the interface between the oxide 230 a and the oxide 230 b.

  Specifically, a mixed layer with low defect state density can be formed by the oxide 230 a and the oxide 230 b having a common element other than oxygen (being a main component). For example, in the case where the oxide 230 b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like may be used as the oxide 230 a.

  At this time, the main route of the carrier is the oxide 230b. With the oxide 230 a having the above-described structure, the density of defect states at the interface between the oxide 230 a and the oxide 230 b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-state current.

  In addition, the oxide 230 includes a region 231 and a region 234. Note that at least part of the region 231 includes a region in contact with the conductor 242.

  Note that when the transistor 200 is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least a part of the region 234 functions as a region in which a channel is formed.

  As the oxide 230, a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide to be the region 234, one having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. Thus, by using a metal oxide with a large band gap, the off-state current of the transistor can be reduced.

  A transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. Further, an oxide semiconductor can be formed by a sputtering method or the like and thus can be used for a transistor included in a highly integrated semiconductor device.

  A conductor 242 (a conductor 242 a and a conductor 242 b) functioning as a source electrode and a drain electrode is provided over the oxide 230 b. As the conductor 242, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material which maintains conductivity even by absorbing oxygen.

  By providing the conductor 242 in contact with the oxide 230, the oxygen concentration in the region 231 may be reduced. In addition, a metal compound layer containing a metal contained in the conductor 242 and a component of the oxide 230 may be formed in the region 231. In such a case, the carrier density of the region 231 is increased, and the region 231 becomes a low resistance region.

  Here, the region between the conductor 242 a and the conductor 242 b is formed to overlap with the opening of the insulator 280. Thus, the conductor 260 can be disposed between the conductor 242a and the conductor 242b in a self-aligned manner.

  The insulator 244 is provided to cover the conductor 242 and the oxide 230, and prevents the side surface of the oxide 230 from coming into contact with the insulator 280. In addition, the insulator 244 suppresses the oxidation of the conductor 242. At this time, the insulator 244 is preferably provided in contact with the insulator 224. In addition, the insulator 244 is provided with an opening 290 which exposes part of the insulator 224.

  As the insulator 244, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium may be used. it can.

  In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing one or both oxides of aluminum and hafnium, is preferably used. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in a later step. The insulator 244 prevents oxygen contained in the insulator 280 from diffusing from the side surface of the oxide 230 into the oxide 230. Note that the insulator 244 does not have to have a function of suppressing the oxidation of the conductor 242 in the case where the conductivity is not significantly reduced even if the conductor 242 has oxidation resistance or absorbs oxygen.

  The insulator 273 is disposed in contact with the side surface of the oxide 230 a, the side surface and the top surface of the oxide 230 b, the side surface of the conductor 242, the side surface of the insulator 244, and the side surface of the insulator 280. In the processing of the insulator 280, the insulator 244, and the conductor 242, the insulator 224 may also be processed. At this time, the insulator 273 may be in contact with the side surface of the insulator 224 as illustrated in FIG. In addition, the insulator 273 may be in contact with the insulator 222. The insulator 273 has a function of suppressing permeation of impurities such as oxygen, hydrogen, water, and a metal element. As the insulator 273, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium may be used. it can. Alternatively, silicon nitride such as silicon nitride or silicon nitride oxide can be used.

  In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing one or both oxides of aluminum and hafnium, is preferably used. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in a later step.

  The insulator 250 is preferably disposed in contact with the inner side (upper surface and side surface) of the insulator 273.

  As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having voids is used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

  The insulator 250 preferably has a reduced concentration of impurities such as water or hydrogen in the insulator 250 in the same manner as the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

  In addition, the insulator 250 is provided not only between the oxide 230 b and the conductor 260 but also between the conductor 242 and the conductor 260. In the case where a parasitic capacitance is formed between the conductor 242 and the conductor 260 depending on the film thickness required for the insulator 250 and the characteristics of the transistor 200 or the semiconductor device are adversely affected, the conductor 242 is electrically conductive. Preferably, the thickness of the insulator 250 located between the bodies 260 is greater than the thickness of the insulator 250 located between the oxide 230 b and the conductor 260. For that purpose, the insulator 250 located between the conductor 242 and the conductor 260 may have a two-layer structure, and the insulator 250 located between the oxide 230 b and the conductor 260 may have a single-layer structure. For example, an insulating film to be a first insulator is formed inside the insulator 273, anisotropic etching is performed on the insulating film, and the first insulator is formed only on the inner wall of the insulator 273. . Subsequently, by forming the insulating film to be the second insulator, the insulator 250 located between the oxide 230 b and the conductor 260 has a single-layer structure, and the insulator 250 is located between the conductor 242 and the conductor 260. The insulator 250 has a two-layer structure. Thus, the thickness of the insulator 250 located between the conductor 242 and the conductor 260 can be larger than the thickness of the insulator 250 located between the oxide 230 b and the conductor 260.

  Further, an insulator 272 may be provided between the insulator 250 and the conductor 260 in order to suppress oxidation of the conductor 260 due to oxygen included in the insulator 250. The insulator 272 preferably suppresses oxygen diffusion from the insulator 250.

  The insulator 273, the insulator 250, and the insulator 272 each function as a gate insulator. Therefore, in the case of using silicon oxide, silicon oxynitride, or the like for the insulator 250, the insulator 273 and the insulator 272 preferably use a metal oxide which is a high-k material having a high dielectric constant. When the gate insulator has a stacked-layer structure of the insulator 273, the insulator 250, and the insulator 272, a stacked-layer structure which is stable against heat and has a high relative dielectric constant can be obtained. Therefore, while maintaining the physical thickness of the gate insulator, it is possible to reduce the gate potential applied at the time of transistor operation. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator.

  Specifically, metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium as the insulator 272 A thing can be used.

  In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing one or both oxides of aluminum and hafnium, is preferably used. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in a later step. Note that the insulator 272 is not an essential component. It may be appropriately designed according to the transistor characteristics to be obtained.

The conductor 260 functioning as the first gate electrode is illustrated as a two-layer structure in FIG. 1, but may be a single-layer structure or a stacked structure of three or more layers. For example, in the case where the conductor 260 has a two-layer structure, the conductor 260a is, like the conductor 205a, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen molecule (N ₂ O, NO It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as NO ₂ ) and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of at least one of oxygen (eg, oxygen atom, oxygen molecule, and the like).

  Since the conductor 260a has a function of suppressing the diffusion of oxygen, the oxygen contained in the insulator 250 can suppress the oxidation of the conductor 260b and the decrease in conductivity. As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

  The conductor 260 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In addition, since the conductor 260 also functions as a wiring, a conductor with high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 260b may have a stacked structure, for example, a stacked structure of titanium and titanium nitride and the above conductive material.

  Further, as shown in FIG. 1C, in the case where the conductor 205 extends in a region outside the end portion of the oxide 230 which intersects the channel width direction, the conductor 260 in the region, It is preferable to overlap through the insulator 250. That is, in the outside of the side surface of the oxide 230, the conductor 205, the insulator 250, and the conductor 260 preferably form a stacked structure.

  With the above structure, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a channel formed in the oxide 230 The area can be covered.

  That is, the channel formation region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode and the electric field of the conductor 205 having a function as the second gate electrode. .

  The insulator 280 is provided on the conductor 242 via the insulator 244. The insulator 280 preferably contains oxygen. For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having voids It is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Note that in the insulator 280, the concentration of impurities such as water or hydrogen is preferably reduced.

  The insulator 280 is in contact with the insulator 224 through an opening 290 provided in the insulator 244. The insulator 224 is in contact with the bottom surface of the oxide 230 and supplies oxygen contained in the insulator 224 or oxygen supplied to the insulator 224 to the oxide 230. On the other hand, since the side surfaces and the top surface of the oxide 230 are covered with the insulator 224 or 273, the supply of oxygen from the insulator 280 and the supply of oxygen from the insulator 250 are suppressed.

  Since the supply path of oxygen to the oxide 230 is limited, control of the amount of oxygen supplied to the oxide 230 is facilitated, and an optimal amount of oxygen can be supplied to the oxide 230. The amount of oxygen supplied to the oxide 230 is controlled by the amount of oxygen that the insulator 224 has, the amount of oxygen that is supplied to the insulator 224, the amount of oxygen that the insulator 280 has, the amount of oxygen that is supplied to the insulator 280, and , And the area of the opening 290 which the insulator 244 has. The amount of oxygen and the area of the opening 290 can be determined in accordance with the required performance of the transistor 200 or the semiconductor device. A transistor using the oxide 230 whose amount of oxygen is optimized and a semiconductor device using the transistor can suppress normally on and have high reliability.

  Further, an insulator 281 which functions as an interlayer film is preferably provided over the insulator 274. The insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen in the film, similarly to the insulator 224, the insulator 280, and the like.

  Further, the conductor 240 a and the conductor 240 b are provided in the openings formed in the insulator 281, the insulator 280, and the insulator 244. The conductor 240 a and the conductor 240 b are provided opposite to each other with the conductor 260 interposed therebetween. The conductor 240a and the conductor 240b are electrically connected to the conductor 242a and the conductor 242b, respectively. Note that the top surfaces of the conductor 240 a and the conductor 240 b may be flush with the top surface of the insulator 281.

  Note that a first conductor of the conductor 240 a is formed in contact with the inner wall of the opening of the insulator 281, the insulator 280, and the insulator 244. The conductor 242a is positioned at least at a part of the bottom of the opening, and the conductor 240a is in contact with the conductor 242a. Similarly, a first conductor of the conductor 240b is formed in contact with the inner wall of the opening of the insulator 281, the insulator 280, and the insulator 244. The conductor 242 b is positioned at least at a part of the bottom of the opening, and the conductor 240 b is in contact with the conductor 242 b. Note that an insulator may be provided in contact with the inner wall of the opening of the insulator 281, the insulator 280, and the insulator 244. For the insulator, a material similar to that of the insulator 244, the insulator 273, or the insulator 272 can be used. The insulator can be provided only on the inner wall of the opening by providing the insulating film inside the opening and over the insulator 281 and performing anisotropic etching on the insulating film. By providing the insulator, absorption of oxygen contained in the insulator 280 and the insulator 281 by the conductor 240 can be suppressed.

  Here, FIG. 3A illustrates a cross-sectional view of a portion indicated by an alternate long and short dash line A5-A6 in FIG. 1A, that is, a source region or a drain region of the transistor 200. As shown in FIG. 3, the conductor 240a (conductor 240b) is in contact with at least the top surface and the side surface of the conductor 242a (conductor 242b), and further in contact with the side surface of the oxide 230b and the side surface of the oxide 230a. Is preferred. In particular, the conductor 240a (conductor 240b) is preferably in contact with one or both of the side surface on the A5 side and the side surface on the A6 side on the side surface of the oxide 230 which intersects the channel width direction. Alternatively, the conductor 240a (conductor 240b) may be in contact with the side surface on the A1 side (A2 side) on the side surface of the oxide 230 that intersects the channel length direction. In this manner, by adding the conductor 240a and the conductor 240b to the top surface and the side surface of the conductor 242a (conductor 242b), and in contact with the side surface of the oxide 230b and the side surface of the oxide 230a The contact area of the contact portion is increased without increasing the area of the contact portion of the conductor 240a (conductor 240b) and the conductor 242a (conductor 242b), and the conductor 240a (conductor 240b) and the conductor 242a The contact resistance of (conductor 242b) can be reduced. Thus, the on current can be increased while the source electrode and the drain electrode of the transistor are miniaturized.

  Further, FIG. 3B shows an example in which the mask alignment in the lithography method is deviated in the A5 direction when forming an opening for exposing a part of the conductor 242a (conductor 242b). There is. Conductor 242a (conductor 242b) is formed even if misalignment occurs by making the width of the opening larger than the width of conductor 242a (conductor 242b), oxide 230b, and oxide 230a in the channel width direction. ) Can be in contact with the top and side surfaces of the conductor 242a (conductor 242b), the side surface of the oxide 230b, and the side surface of the oxide 230a, and a good contact can be obtained.

  It is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductors 240a and 240b. The conductor 240 a and the conductor 240 b may have a stacked structure.

  In the case where the conductor 240 has a stacked-layer structure, the conductor 205a can be a conductor in contact with the oxide 230a, the oxide 230b, the conductor 242, the insulator 244, the insulator 280, the insulator 274, and the insulator 281. Similarly to the above, it is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide or the like is preferably used. In addition, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stack. By using the conductive material, impurities such as hydrogen and water from above the insulator 281 can be prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

  Although not shown, a conductor that functions as a wiring may be disposed in contact with the top surface of the conductor 240a and the top surface of the conductor 240b. It is preferable to use a conductive material whose main component is tungsten, copper, or aluminum as the conductor functioning as the wiring. The conductor may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material. Note that as in the case of the conductor 203 or the like, the conductor may be formed so as to be embedded in an opening provided in an insulator.

<Material of semiconductor device>
Hereinafter, constituent materials which can be used for the semiconductor device will be described.

<< board >>
As a substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. The semiconductor substrate may be, for example, a semiconductor substrate of silicon, germanium or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. As the conductive substrate, there are a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, or the like. Further, there are a substrate provided with a conductor or a semiconductor on an insulator substrate, a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on the conductor substrate, and the like. Alternatively, those provided with elements on these substrates may be used. The elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a memory element, and the like.

  Alternatively, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor on a flexible substrate, there is a method in which the transistor is peeled off after being manufactured on a non-flexible substrate and transposed to a substrate which is a flexible substrate. In that case, a release layer may be provided between the non-flexible substrate and the transistor. In addition, the substrate may have stretchability. In addition, the substrate may have the property of returning to its original shape when bending or pulling is stopped. Alternatively, it may have the property that it does not return to its original shape. The substrate has, for example, a region having a thickness of 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate is thinned, the weight of the semiconductor device including the transistor can be reduced. In addition, when the substrate is made thin, it may have elasticity even when using glass or the like, or may return to its original shape when bending or pulling is stopped. Therefore, an impact or the like applied to the semiconductor device on the substrate due to a drop or the like can be alleviated. That is, a robust semiconductor device can be provided.

As a substrate which is a flexible substrate, for example, a metal, an alloy, a resin or glass, or a fiber thereof can be used. Further, as the substrate, a sheet, a film, a foil or the like in which fibers are woven may be used. As the substrate which is a flexible substrate has a low coefficient of linear expansion, deformation due to the environment is preferably suppressed. As a substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is suitable as a flexible substrate because it has a low coefficient of linear expansion.

<< insulator >>
The insulator includes, for example, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, and the like.

  For example, as the miniaturization and higher integration of transistors progress, the thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator that functions as a gate insulator, voltage reduction during transistor operation can be achieved while maintaining the physical thickness. On the other hand, for an insulator functioning as an interlayer film, by using a material having a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, depending on the function of the insulator, the material may be selected.

  In addition, as insulators with high dielectric constants, oxides of gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium, oxynitrides of aluminum and hafnium, oxides of silicon and hafnium, silicon and hafnium can be used. And the like, or nitrides having silicon and hafnium.

  Further, as an insulator having a low relative dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, empty There is silicon oxide having a hole, or a resin.

  Also, in particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, it is possible to obtain a laminated structure having a low thermal conductivity and a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate or acrylic. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator with high relative permittivity to form a stacked structure with high thermal stability and high relative permittivity.

  In addition, in the transistor including an oxide semiconductor, electrical characteristics of the transistor can be stabilized by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen.

  As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stack. Specifically, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. Alternatively, metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

  For example, as the insulator 244, the insulator 273, or the insulator 272, one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like Can be used. Alternatively, silicon nitride or silicon nitride containing oxygen, that is, silicon nitride, silicon nitride oxide, or the like can be used.

  In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even if it is a thin film of 0.5 nm or more and 3.0 nm or less. In addition, although hafnium oxide has lower barrier properties than aluminum oxide, the barrier properties can be enhanced by increasing the film thickness.

  The insulator 224 is preferably an insulator containing oxygen. For example, with a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

  For example, as the insulator 222 which functions as part of a gate insulator, an insulator containing one or more oxides of aluminum, hafnium, and gallium can be used. In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium.

  The insulator 222 preferably has a function of suppressing oxygen in the insulator 224 from diffusing to the insulator 220 side.

  For example, as the insulator 220, silicon oxide or silicon oxynitride which is stable against heat is preferably used. By using a stack that has a stable film against heat and a high dielectric constant as the gate insulator, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulator while maintaining the physical thickness. It becomes.

  With the above-described stacked structure, the on current can be improved without weakening the influence of the electric field from the gate electrode. Further, by keeping the distance between the gate electrode and the region where the channel is formed by the physical thickness of the gate insulator, the leakage current between the gate electrode and the channel formation region can be suppressed. .

  Each of the insulator 212, the insulator 216, the insulator 280, and the insulator 281 preferably includes an insulator with a low relative dielectric constant. For example, the insulator 212, the insulator 216, the insulator 280, and the insulator 281 are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, and It is preferable to have a silicon oxide to which nitrogen is added, a silicon oxide having holes, a resin, or the like. Alternatively, the insulator 212, the insulator 216, the insulator 280, and the insulator 281 are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, and It is preferable to have a layered structure of a silicon oxide to which nitrogen is added, or a silicon oxide having holes and a resin. Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with a resin, a stacked structure with a thermally stable and low dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

  As the insulator 210, the insulator 214, the insulator 244, the insulator 273, the insulator 272, and the insulator 274, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used. As the insulator 210, the insulator 214, the insulator 244, the insulator 273, the insulator 272, and the insulator 274, for example, aluminum oxide, hafnium oxide, magnesium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, or the like can be used. Or a metal oxide such as lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like.

<< Conductor >>
As the conductor, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum A material containing one or more metal elements selected from the above can be used. Alternatively, a semiconductor with high electrical conductivity, typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

  Alternatively, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked structure in which a material containing a metal element described above and a conductive material containing oxygen are combined may be used. Alternatively, a stacked structure in which the material containing the metal element described above and the conductive material containing nitrogen are combined may be used. Alternatively, a stacked structure in which the above-described material containing a metal element, the conductive material containing oxygen, and the conductive material containing nitrogen are combined may be used.

  Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode. Is preferred. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen in the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

  In particular, as a conductor functioning as a gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in a metal oxide in which a channel is formed. Alternatively, it may be possible to capture hydrogen mixed from an outer insulator or the like.

  As the conductor 260, the conductor 203, the conductor 205, the conductor 242, and the conductor 240, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, or the like can be used. Or a metal element selected from manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-described metal element as a component, or an alloy or the like in combination with the above-described metal element preferable. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material which maintains conductivity even by absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

<< metal oxides >>
As the oxide 230, a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.

  The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium or tin is preferably contained. In addition, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

  Here, it is assumed that the metal oxide is an In-M-Zn oxide having indium, an element M and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the aforementioned elements may be combined in some cases.

  In the present specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides. In addition, a metal oxide having nitrogen may be referred to as metal oxynitride.

[Metal oxide composition]
Hereinafter, a configuration of a Cloud-Aligned Composite (CAC) -OS that can be used for the transistor disclosed in one embodiment of the present invention will be described.

  In this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a structure of a material.

  The CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor throughout the material. Note that in the case where CAC-OS or CAC-metal oxide is used for a semiconductor layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as a carrier, and the insulating function is a carrier. It is a function that does not flow electrons. A function of switching (function of turning on / off) can be imparted to the CAC-OS or the CAC-metal oxide by causing the conductive function and the insulating function to be complementary to each other. By separating the functions of CAC-OS or CAC-metal oxide, both functions can be maximized.

  In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed as connected in a cloud shape with a blurred periphery.

  In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from the insulating region and a component having a narrow gap resulting from the conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above-described CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on current, and high field effect mobility can be obtained in the on state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be called a matrix composite (matrix composite) or a metal matrix composite (metal matrix composite).

[Structure of metal oxide]
Oxide semiconductors (metal oxides) can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. As the non-single crystal oxide semiconductor, for example, c-axis aligned crystalline oxide semiconductor (CAAC-OS), polycrystalline oxide semiconductor, nanocrystalline oxide semiconductor (nc-OS), pseudo amorphous oxide semiconductor (a-like) OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductor.

  The CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure. Note that distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

  The nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon. Note that in the CAAC-OS, it is difficult to confirm clear crystal grain boundaries (also referred to as grain boundaries) even in the vicinity of strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is for.

  In addition, a CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing element M, zinc and oxygen (hereinafter referred to as (M, Zn) layer) are stacked. It tends to have a structure (also referred to as a layered structure). Note that indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as a (In, M, Zn) layer. In addition, when indium in the In layer is substituted with the element M, it can also be represented as an (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, it is difficult to confirm clear crystal grain boundaries in CAAC-OS, so it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, since crystallinity of a metal oxide may be lowered due to mixing of impurities or generation of defects, CAAC-OS has a metal with few impurities or defects (also referred to as oxygen vacancy (V 2 _O )). It can be said that it is an oxide. Therefore, the metal oxide having a CAAC-OS has stable physical properties. Therefore, a metal oxide having a CAAC-OS is resistant to heat and has high reliability.

  The nc-OS has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS may not be distinguished from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

  Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium, gallium and zinc, may have a stable structure by using the above-mentioned nanocrystals. is there. In particular, IGZO tends to be difficult to grow crystals in the atmosphere, so smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, crystals of a few mm or crystals of a few cm) But may be structurally stable.

  The a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a wrinkle or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

  Oxide semiconductors (metal oxides) have various structures, and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor having metal oxide]
Subsequently, a case where the above metal oxide is used for a channel formation region of a transistor will be described.

  Note that by using the above metal oxide for the channel formation region of the transistor, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

  Here, an example of the hypothesis of the electrical conductivity of the metal oxide will be described.

  Electrical conduction in solids is inhibited by scattering sources called scattering centers. For example, in the case of single crystal silicon, it is known that lattice scattering and ionized impurity scattering are the main scattering centers. In other words, in the essential state with few lattice defects and impurities, there is no factor that inhibits the electric conduction in the solid, and the carrier mobility is high.

  The above is assumed to apply to metal oxides as well. For example, in metal oxides in which the amount of oxygen is smaller than the stoichiometric composition, it is considered that many oxygen vacancies exist. The atoms present around this oxygen vacancy are located at a distorted place than in the essential state. The distortion due to this oxygen deficiency may be a scattering center.

Also, for example, in metal oxides where the amount of oxygen is less than the stoichiometric composition, excess oxygen is present. Excess oxygen present in the free state in the metal oxide, by accepting electrons, O ^- or become O ^2-. O ^- or O ^2- and excess oxygen becomes may become scattering centers.

  From the above, it is considered that the mobility of the carrier is high when the metal oxide has an intrinsic state including oxygen satisfying the stoichiometric composition.

  Indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium, gallium and zinc, tends to be difficult to grow crystals particularly in the atmosphere, so a large crystal It may be structurally stable if the crystal (for example, the above-mentioned nanocrystal) is smaller than (here, a crystal of several mm or a crystal of several cm). This is considered to be because strain energy is relaxed when small crystals are connected to each other rather than forming a large crystal.

  In a region where small crystals are connected to each other, a defect may be formed in order to reduce strain energy in the region. Therefore, the mobility of carriers can be increased by reducing strain energy without forming a defect in the region.

In addition, for the transistor, a metal oxide with low carrier density is preferably used. In order to lower the carrier density of the metal oxide film, the impurity concentration in the metal oxide film may be lowered to lower the density of defect states. In the present specification and the like, a low impurity concentration and a low density of defect levels are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the metal oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. It should be cm ³ or more.

  In addition, since the high purity intrinsic or the substantially high purity intrinsic metal oxide film has a low defect state density, the trap state density may also be low.

  In addition, the charge trapped in the trap level of the metal oxide may take a long time to disappear and behave as if it were fixed charge. Therefore, a transistor including a metal oxide with a high trap state density in a channel formation region may have unstable electrical characteristics.

  Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. Further, in order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. The impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

  Further, a thin film with high crystallinity is preferably used as the metal oxide used for the semiconductor of the transistor. By using the thin film, the stability or the reliability of the transistor can be improved. Examples of the thin film include thin films of single crystal metal oxides or thin films of polycrystalline metal oxides. However, to form a thin film of monocrystalline metal oxide or a thin film of polycrystalline metal oxide on a substrate, a high temperature or laser heating step is required. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

  It is reported in Non-Patent Document 1 and Non-Patent Document 2 that In-Ga-Zn oxide (referred to as CAAC-IGZO) having a CAAC structure was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, can not be clearly identified in grain boundaries, and can be formed on a substrate at a low temperature. Furthermore, a transistor using CAAC-IGZO is reported to have excellent electrical characteristics and reliability.

  In 2013, an In-Ga-Zn oxide (referred to as nc-IGZO) having an nc structure was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in atomic arrangement in a minute area (for example, an area of 1 nm or more and 3 nm or less) and regularity in crystal orientation is not observed between different areas. There is.

  Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size by the irradiation of an electron beam to the thin films of the above-described CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity. In a low crystalline IGZO thin film, crystalline IGZO of about 1 nm has been observed even before electron beam irradiation. Therefore, it is reported here that in IGZO, the presence of a completely amorphous structure could not be confirmed. Furthermore, it is shown that the thin film of CAAC-IGZO and the thin film of nc-IGZO have high stability to electron beam irradiation as compared with the thin film of IGZO having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.

A transistor using a metal oxide has extremely low leakage current in the non-conductive state, specifically, the off-state current per μm channel width of the transistor is on the order of yA / μm (10 ^-24 A / μm). Is shown in Non-Patent Document 6. For example, a low power consumption CPU or the like to which a characteristic that a leak current of a transistor using a metal oxide is low is disclosed (see Non-Patent Document 7).

In addition, application of a transistor using a metal oxide to a display device utilizing a characteristic that a leak current of the transistor is low has been reported (see Non-Patent Document 8). In the display device, the displayed image is switched several tens of times per second. The number of times of switching images per second is called a refresh rate. Also, the refresh rate may be referred to as a drive frequency. Such fast screen switching, which is difficult for human eyes to perceive, is considered as the cause of eye fatigue. Therefore, it has been proposed to reduce the number of image rewrites by reducing the refresh rate of the display device. In addition, power consumption of the display device can be reduced by driving with a lower refresh rate. Such a driving method is called idling stop (IDS) driving.

The discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of a transistor using a metal oxide having a CAAC structure or an nc structure, as well as to the cost reduction and the throughput improvement of the manufacturing process. In addition, researches on application of the transistor to a display device and an LSI using the characteristic that the leakage current of the transistor is low have been advanced.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

When the metal oxide contains silicon or carbon, which is one of the group 14 elements, a defect level is formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon in the vicinity of the interface with the metal oxide (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × ¹⁰ 18 atoms / cm ³ or less, preferably 2 × ¹⁰ 17 atoms / cm ³ or less.

In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed to generate a carrier. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in the metal oxide, electrons which are carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor in which a metal oxide containing nitrogen is used for a channel formation region is likely to be normally on. Therefore, in the metal oxide, nitrogen in the channel formation region is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, in SIMS. Preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

  In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated. In addition, a part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor using a metal oxide that contains hydrogen is likely to be normally on.

  In addition, hydrogen contained in the metal oxide may form a shallow defect level (sDOS) in the metal oxide. Shallow defect states refer to interface states located near the lower end of the conduction band. Shallow defect states are presumed to exist near the boundary between the high density region and the low density region in the metal oxide. Here, the high density region and the low density region in the metal oxide are distinguished by the amount of hydrogen contained in the region. That is, the high density region is a region containing more hydrogen as compared to the low density region. In the vicinity of the boundary between the high density region and the low density region in the metal oxide, a micro crack is easily generated due to the stress strain between the both regions, and oxygen vacancy and indium dangling bond are generated in the vicinity of the crack. It is presumed that shallow defect levels are formed due to the localization of impurities such as hydrogen or water.

  In addition, the high density region in the metal oxide may be higher in crystallinity than the low density region. In addition, the high density region in the metal oxide may have a higher film density than the low density region. Further, in the case where the metal oxide contains indium, gallium and zinc, the high density region contains indium, gallium and zinc, and the low density region contains indium, zinc and , May have. In other words, the low density region may have a lower percentage of gallium than the high density region.

  The shallow defect level is presumed to be due to oxygen deficiency. It is presumed that as oxygen deficiency in the metal oxide increases, deep defect levels (dDOS: deep level Density of States) also increase with shallow defect levels. This is because deep defect levels are also considered to be oxygen deficiency. The deep defect level refers to a defect level located near the center of the band gap.

  Therefore, by suppressing oxygen vacancies in the metal oxide, it is possible to reduce both the shallow defect level and the deep defect level. The shallow defect levels may be controlled to some extent by adjusting the temperature at the time of film formation of the metal oxide. Specifically, the shallow defect level can be reduced by setting the temperature for film formation of the metal oxide to 170 ° C. or near, preferably 130 ° C. or near, more preferably room temperature.

  In addition, shallow defect states of the metal oxide affect the electrical characteristics of a transistor in which the metal oxide is used for the semiconductor layer. That is, due to the shallow defect states, in the drain current-gate voltage (Id-Vg) characteristics of the transistor, the change of the drain current Id relative to the gate voltage Vg becomes gentle, and the rise characteristic from the off state to the on state of the transistor is improved. The S value (Subthreshold Swing, also referred to as SS), which is one of the criteria, is deteriorated. This is considered to be because electrons were trapped in shallow defect levels.

For this reason, hydrogen in the metal oxide is preferably reduced as much as possible. Specifically, in a metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. ^{It is} less than ³ and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

  By using a metal oxide in which impurities are sufficiently reduced for the channel formation region of the transistor, stable electrical characteristics can be provided.

[Effect of vacuum baking]
Here, a weak Zn—O bond included in a metal oxide is described, and an example of a method of reducing an oxygen atom and a zinc atom constituting the bond is described.

  In a transistor using a metal oxide, oxygen vacancies are an example of defects leading to defects in the electrical characteristics of the transistor. For example, in a transistor using a metal oxide in which oxygen vacancies are contained in a film, the threshold voltage is likely to fluctuate in the negative direction, and thus, the transistor may be normally on. This is because a donor is generated due to oxygen deficiency contained in the metal oxide, and the carrier concentration is increased. When the transistor has normally-on characteristics, various problems occur such as an operation failure is likely to occur during operation, or power consumption during non-operation is increased.

  In addition, due to the thermal history (thermal budget) in the process of forming a connection wiring for manufacturing a module, deterioration in electrical characteristics of the transistor such as fluctuation in threshold voltage, increase in parasitic resistance, and the like can be caused. There is a problem such as an increase in the variation in electrical characteristics accompanying with it. Since these problems are directly linked to the decrease in manufacturing yield, it is important to consider measures. In addition, deterioration in electrical characteristics occurs even in a stress test that can evaluate in a short time the characteristic change (aging change) of a transistor that occurs due to long-term use. The deterioration of the electrical properties is presumed to be due to the loss of oxygen in the metal oxide due to the high temperature treatment performed in the process of thermal history, or the electrical stress applied at the time of a stress test.

  In the metal oxide, there is an oxygen atom which has a weak bond with the metal atom and tends to be oxygen deficient. In particular, in the case where the metal oxide is an In—Ga—Zn oxide, a zinc atom and an oxygen atom are likely to form a weak bond (also referred to as a weak Zn—O bond). Here, a weak Zn-O bond is a bond between zinc atoms and oxygen atoms bonded with such a strength that it is broken by high temperature treatment performed in the process of thermal history or electrical stress given in a stress test. Bond that occurs in When a weak Zn-O bond is present in the metal oxide, thermal history or current stress breaks the bond and forms an oxygen vacancy. The formation of oxygen vacancies reduces the stability of the transistor, such as resistance to thermal history, resistance to stress test, and the like.

  The bond generated between the zinc atom and the oxygen atom which is bonded to a large number of zinc atoms may be a weak Zn-O bond. Zinc atoms have a weaker bond to oxygen atoms than gallium atoms. Therefore, oxygen atoms, which are bound to a large number of zinc atoms, are easily lost. That is, the bond generated between the zinc atom and the oxygen atom is presumed to be weaker than the bonds with other metals.

  In addition, when impurities are present in the metal oxide, it is presumed that a weak Zn-O bond is likely to be formed. Examples of impurities in the metal oxide include water molecules and hydrogen. The presence of water molecules or hydrogen in the metal oxide may cause a hydrogen atom to be bonded to an oxygen atom constituting the metal oxide (also referred to as an OH bond). When the In—Ga—Zn oxide is a single crystal, oxygen atoms constituting the metal oxide are bonded to four metal atoms constituting the metal oxide. However, an oxygen atom bonded to a hydrogen atom may be bonded to two or three metal atoms. The reduction in the number of metal atoms bonded to the oxygen atom makes the oxygen atom more likely to be deficient. When a zinc atom is bonded to an oxygen atom forming an OH bond, the bond between the oxygen atom and the zinc atom is presumed to be weak.

  In addition, weak Zn-O bonds may be formed in a strain existing in a region where a plurality of nanocrystals are connected. The nanocrystals are based on hexagons, but at the strain they have lattice arrangements such as pentagons and heptagones. In this strain, it is presumed that weak Zn—O bonds are formed because the bonding distance between atoms is not uniform.

  In addition, it is presumed that weak Zn-O bonds are likely to be formed when the crystallinity of the metal oxide is low. When the crystallinity of the metal oxide is high, zinc atoms constituting the metal oxide are bonded to four or five oxygen atoms. However, as the crystallinity of the metal oxide decreases, the number of oxygen atoms bonded to zinc atoms tends to decrease. When the number of oxygen atoms bonded to a zinc atom decreases, the zinc atom is more likely to be deficient. That is, the bond generated between the zinc atom and the oxygen atom is presumed to be weaker than the bond generated in the single crystal.

  By reducing the oxygen atom and the zinc atom that constitute the weak Zn—O bond, formation of oxygen vacancies due to thermal history or current stress can be suppressed, and the stability of the transistor can be improved. When only the oxygen atom that constitutes the weak Zn-O bond is reduced and the zinc atom that constitutes the weak Zn-O bond does not decrease, when the oxygen atom is supplied near the zinc atom, the weak Zn-O bond re-grows May be formed. Therefore, it is preferable to reduce zinc atoms and oxygen atoms that constitute weak Zn-O bonds.

As a method of reducing oxygen atoms and zinc atoms that constitute weak Zn—O bonds, a method of forming a metal oxide and performing vacuum baking can be mentioned. Vacuum baking is heat treatment performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like. Note that the pressure in the treatment chamber may be 1 × 10 ⁻² Pa or less, preferably 1 × 10 ⁻³ Pa or less. The temperature of the substrate at the time of heat treatment may be 300 ° C. or higher, preferably 400 ° C. or higher.

  By performing vacuum baking, oxygen atoms and zinc atoms that constitute weak Zn—O bonds can be reduced. In addition, since heat is applied to the metal oxide by vacuum baking, the number of oxygen atoms and zinc atoms constituting the weak Zn-O bond is reduced, and then the atoms constituting the metal oxide are rearranged to obtain four metals. More oxygen atoms are attached to atoms. Therefore, while reducing the oxygen atom and zinc atom which comprise a weak Zn-O bond, it can suppress that a weak Zn-O bond is reformed.

  In addition, when impurities are present in the metal oxide, by performing vacuum baking, water molecules or hydrogen in the metal oxide can be released to reduce OH bonds. The reduction of the OH bond in the metal oxide increases the proportion of oxygen atoms bonded to the four metal atoms. In addition, when water molecules or hydrogen are released, the atoms constituting the metal oxide rearrange to increase oxygen atoms bonded to four metal atoms. Therefore, it is possible to suppress the re-formation of weak Zn-O bonds.

  As described above, by performing vacuum baking after depositing a metal oxide, oxygen atoms and zinc atoms that form weak Zn—O bonds can be reduced. Therefore, the stability of the transistor can be improved by the process. In addition, as the stability of the transistor is improved, the degree of freedom in selection of materials and formation methods is increased.

<Method for manufacturing semiconductor device>
Next, a method for manufacturing a semiconductor device including the transistor 200 according to the present invention will be described with reference to FIGS. Moreover, in FIG. 5 to FIG. 14, (A) of each figure shows a top view. Further, (B) in each drawing is a cross-sectional view corresponding to a portion indicated by an alternate long and short dash line A1-A2 illustrated in (A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) in each drawing is a cross-sectional view corresponding to a portion indicated by dashed dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. In addition, in the top view of (A) of each figure, in order to clarify a figure, one part element is abbreviate | omitted and shown in figure.

  First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The film formation of the insulator 210 may be performed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD. This can be performed using an atomic layer deposition (Atomic Layer Deposition) method or the like.

  The CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: thermal CVD) method using heat, a photo CVD method using light, etc. . Furthermore, it can be divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD) depending on the source gas used.

  The plasma CVD method provides high quality films at relatively low temperatures. Further, the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (such as a transistor or a capacitor), or the like included in a semiconductor device may be charged up by receiving charge from plasma. At this time, wirings, electrodes, elements, and the like included in the semiconductor device may be broken by the stored charge. On the other hand, in the case of a thermal CVD method which does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

  In addition, the ALD method is also a film formation method capable of reducing plasma damage to an object to be processed. Further, in the ALD method, since plasma damage does not occur during film formation, a film with few defects can be obtained. Some precursors used in the ALD method include impurities such as carbon. For this reason, the film provided by the ALD method may contain a large amount of impurities such as carbon, as compared with a film provided by another film formation method. In addition, quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

  The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed unlike a film forming method in which particles released from a target or the like are deposited. Therefore, the film forming method is less susceptible to the shape of the object to be processed, and has good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for coating the surface of an opening with a high aspect ratio. However, since the deposition rate is relatively slow, the ALD method may be preferably used in combination with another deposition method such as a CVD method having a high deposition rate.

  The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gas. For example, in the CVD method and the ALD method, a film having any composition can be formed depending on the flow rate ratio of the source gas. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time taken for film formation is shortened because time for conveyance and pressure adjustment is not required compared to the case where film formation is performed using a plurality of film formation chambers. can do. Therefore, the productivity of the semiconductor device may be enhanced.

  In this embodiment mode, aluminum oxide is deposited as the insulator 210 by a sputtering method. In addition, the insulator 210 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed by an ALD method over the aluminum oxide. Alternatively, an aluminum oxide film may be formed by an ALD method, and an aluminum oxide film may be formed by a sputtering method over the aluminum oxide.

  Next, the insulator 212 is formed over the insulator 210. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 212 by a CVD method.

  Next, an opening reaching the insulator 210 is formed in the insulator 212. The openings include, for example, grooves and slits. In addition, the region in which the opening is formed may be referred to as an opening. Although wet etching may be used to form the openings, it is preferable to use dry etching for fine processing. Further, as the insulator 210, it is preferable to select an insulator that functions as an etching stopper at the time of forming the opening by etching the insulator 212. For example, in the case where silicon oxide is used for the insulator 212 which forms an opening, silicon nitride, aluminum oxide, or hafnium oxide may be used as the insulator 210 which functions as an etching stopper.

  After the opening is formed, a conductive film to be the conductor 203a is formed. The conductive film preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. The conductive film to be the conductor 203a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, as a conductive film to be the conductor 203a, a film in which titanium nitride is stacked over tantalum nitride or tantalum nitride is formed by sputtering. By using such a metal nitride as the conductor 203a, even if a metal that easily diffuses such as copper is used in the conductor 203b described later, the metal can be prevented from diffusing out of the conductor 203a. .

  Next, a conductive film to be the conductor 203b is formed over the conductive film to be the conductor 203a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film to be the conductor 203 b.

  Next, CMP treatment is performed to remove part of the conductive film to be the conductor 203 a and the conductive film to be the conductor 203 b, thereby exposing the insulator 212. As a result, the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening. Accordingly, the conductor 203 including the conductor 203a and the conductor 203b whose top surface is flat can be formed (see FIG. 5). Note that part of the insulator 212 may be removed by the CMP treatment.

  Next, the insulator 214 is formed over the insulator 212 and the conductor 203. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon nitride is formed as the insulator 214 by a CVD method. In this manner, by using an insulator that is less likely to transmit copper such as silicon nitride as the insulator 214, even if a metal that easily diffuses copper such as copper is used for the conductor 203b, the metal is a layer higher than the insulator 214 Can be suppressed.

  Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 216 by a CVD method.

  Next, an opening which reaches the conductor 203 is formed in the insulator 214 and the insulator 216. Although wet etching may be used to form the openings, it is preferable to use dry etching for fine processing.

  After the opening is formed, a conductive film to be the conductor 205a is formed. The conductive film preferably contains a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. The conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment mode, tantalum nitride is formed by a sputtering method as a conductive film to be the conductor 205a.

  Next, a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment mode, titanium nitride is formed by a CVD method as a conductive film to be the conductor 205b, and tungsten is formed over the titanium nitride film by a CVD method.

  Next, CMP treatment is performed to remove part of the conductive film to be the conductor 205 a and the conductive film to be the conductor 205 b, thereby exposing the insulator 216. As a result, the conductive film to be the conductor 205a and the conductor 205b remains only in the opening. Thus, the conductor 205 including the conductor 205a and the conductor 205b with a flat top surface can be formed (see FIG. 5). Note that part of the insulator 216 may be removed by the CMP treatment.

  Next, the insulator 220 is formed over the insulator 216 and the conductor 205. The insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 220 by a CVD method.

  Next, the insulator 222 is formed over the insulator 220. As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium may be deposited. Note that aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium. An insulator containing one or both oxides of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. By the insulator 222 having a barrier property to oxygen, diffusion of the insulator 224 and oxygen contained thereabove to the insulator 220 side is suppressed, and oxygen can be efficiently supplied to the oxide 230. it can. In addition, hydrogen and water contained in a structure provided in the periphery of the transistor 200 can diffuse into the transistor 200 through the insulator 222 because the insulator 222 has a barrier property to hydrogen and water. Thus, the formation of oxygen vacancies in the oxide 230 can be suppressed.

  The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 224 by a CVD method.

  Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., more preferably 320 ° C. to 450 ° C. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment is performed in a nitrogen or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen. Good.

  In this embodiment mode, heat treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere after film formation of the insulator 224. By the heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed, and the like.

  The heat treatment can also be performed at each timing after the insulator 220 is formed and after the insulator 222 is formed. Although the heat treatment conditions described above can be used for the heat treatment, it is preferable that the heat treatment after the deposition of the insulator 220 be performed in an atmosphere containing nitrogen.

  Here, in order to add oxygen to the insulator 224, plasma treatment including oxygen may be performed under reduced pressure. For plasma treatment containing oxygen, for example, it is preferable to use a device having a power supply for generating high density plasma using microwaves. Alternatively, the substrate side may have a power supply for applying an RF (Radio Frequency). By using high density plasma, high density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high density plasma can be efficiently introduced into the insulator 224. it can. Alternatively, after performing plasma treatment including an inert gas using this apparatus, plasma treatment including oxygen may be performed to compensate for the released oxygen. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting the conditions of the plasma treatment. In that case, the heat treatment may not be performed.

  Next, on the insulator 224, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed (see FIG. 5). Note that the oxide film is preferably formed continuously without being exposed to the air environment. By forming the film without opening to the atmosphere, impurities or moisture from the air environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be It can be kept clean.

  The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  For example, in the case where the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, oxygen in the oxide film to be formed can be increased. In the case where the above oxide film is formed by sputtering, an In-M-Zn oxide target can be used, for example.

  In particular, when the oxide film 230A is formed, part of oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

  In addition, in the case where the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor can be formed by deposition with the proportion of oxygen contained in the sputtering gas being 1% to 30%, preferably 5% to 20%. It is formed. A transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region can achieve relatively high field-effect mobility.

  In this embodiment, a target of In: Ga: Zn = 1: 1: 0.5 [atomic number ratio] (2: 2: 1 [atomic number ratio]) is used as the oxide film 230A by sputtering. Form a film. In addition, as the oxide film 230B, In: Ga: Zn = 4: 2: 2 [atomic number ratio], 4: 2: 1 [atomic number ratio], or 4: 2: 0 [atomic number ratio] by a sputtering method. A film is formed using a target of (In: Ga = 4: 2 [atomic number ratio]). Note that each oxide film may be formed in accordance with the characteristics to be obtained for the oxide 230 by appropriately selecting deposition conditions and an atomic ratio.

  Next, heat treatment may be performed. For the heat treatment, the above-described heat treatment conditions can be used. By the heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed. In this embodiment, after performing treatment for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere, treatment for 1 hour at a temperature of 400 ° C. in an oxygen atmosphere is continuously performed.

  The oxide film 230B obtained by the above steps has a CAAC structure.

  Next, the conductive film 242A is formed over the oxide film 230B (see FIG. 5). The conductive film 242A is made of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum It is preferable to use a metal element selected from or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material which maintains conductivity even by absorbing oxygen. Note that the conductive film 240A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the conductive film 242A is processed to form a hard mask for processing the oxide film 230A and the oxide film 230B.

  Note that the conductive film 242A may be processed by a lithography method. Further, dry etching or wet etching can be used for the processing. Machining by dry etching is suitable for micromachining.

  In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled and exposed between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. In the case of using an electron beam or an ion beam, the mask for resist exposure described above is unnecessary because writing is performed directly on the resist. Note that the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, dry etching treatment after wet etching treatment, or the like. .

  Next, the conductive film 242A is etched using a resist mask to form a conductor 242B which functions as a hard mask (see FIG. 6). After the conductor 242B is formed, the resist mask may be removed and then the oxide film may be processed, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. Although the hard mask may be removed by etching after the etching of the oxide film, in the present embodiment, the conductor 242B is not processed because the conductor 242B is further processed to form a source electrode and a drain electrode. .

  As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having a parallel plate electrode can be used. The capacitive coupling type plasma etching apparatus having a parallel plate type electrode may be configured to apply a high frequency power to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate electrodes. Alternatively, a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency power supplies having different frequencies may be applied to the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high density plasma source.

  Next, the oxide film 230A and the oxide film 230B are processed into an island shape using the conductor 242B as a hard mask to form an oxide 230a and an oxide 230b (see FIG. 6). Note that part of the insulator 224 may be removed in the processing process.

  Here, the oxide 230 a and the oxide 230 b are formed so that at least part thereof overlaps with the conductor 205. The side surfaces of the oxide 230 a and the oxide 230 b preferably have a tapered shape with respect to the top surface of the insulator 222 or the top surface of the substrate. The side surfaces of the oxide 230 a and the oxide 230 b have a tapered shape with respect to the top surface of the insulator 222 or the top surface of the substrate, so that a film formed on the side surface of the oxide 230 a and the oxide 230 b in a later step Coverage of the On the other hand, in the case of using an ALD method, a CVD method, or the like which is excellent in coverage, a film formed on a side surface of the oxide 230a and the oxide 230b in a later step may have a vertical shape.

  In addition, a curved surface is provided between the side surfaces of the oxide 230a, the oxide 230b, and the conductor 242B, and the top surface of the conductor 242B. That is, the end of the side surface and the end of the upper surface are preferably curved (hereinafter, also referred to as a round shape). The radius of curvature of the curved surface is, for example, 3 nm to 10 nm, preferably 5 nm to 6 nm, at an end portion of the oxide 230 b. By not having a corner at the end, the coverage of the film in the subsequent film formation process is improved.

  Note that for the processing of the oxide film, a dry etching method or a wet etching method can be used using the conductor 242B as a hard mask. Machining by dry etching is suitable for micromachining.

  Further, by performing the process such as the above-described dry etching, impurities derived from an etching gas or the like may be attached or diffused to side surfaces or inside of the oxide 230a, the oxide 230b, and the like. The impurities include, for example, fluorine or chlorine.

  Washing is performed to remove the above-mentioned impurities and the like. The cleaning method may be wet cleaning using a cleaning solution or the like, plasma treatment using plasma, or cleaning by heat treatment, and the above cleaning may be performed in combination as appropriate.

  As wet cleaning, cleaning treatment may be performed using an aqueous solution prepared by diluting oxalic acid, phosphoric acid, hydrogen peroxide water, hydrofluoric acid or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning may be performed using pure water or carbonated water. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

  Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used. However, when oxidation of the conductor 242B is a concern due to the heat treatment, the heat treatment is preferably performed in an atmosphere containing no oxygen. On the other hand, in the case where the conductor 242B contains an oxidation resistant material, the heat treatment may be performed in an atmosphere containing oxygen.

  Next, an insulator 244A is formed over the insulator 224, the oxide 230a, the oxide 230b, and the conductor 242B (see FIG. 7). Note that the insulator 244A preferably functions as an insulating barrier, and an insulator including one or both of an oxide of aluminum and hafnium is preferably deposited. Note that aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium. By covering the side surface of the oxide 230 with the insulator 244A having a barrier property, entry of impurities such as oxygen and hydrogen and water from the side surface of the oxide 230 can be suppressed. Further, the insulator 244A can suppress the oxidation of the conductor 242B, and the choice of materials which can be used for the conductor 242 can be expanded. The insulator 244A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, an opening 290 which exposes the insulator 224 is formed in the insulator 244. The openings 290 can be formed by dry etching or wet etching using a lithography method (see FIG. 8).

  The shape of the opening 290 can be any of a slit shape, a circle, a rectangle, and a polygon. In addition, the opening 290 may be provided to surround the outer periphery of the oxide 230. For example, the openings 290 may be provided in a grid. In addition, the area of the opening 290 can be appropriately adjusted in accordance with the amount of oxygen supplied to the oxide 230.

  Next, an insulator 280 is formed on the insulator 244A (see FIG. 9). The insulator 280 preferably contains oxygen. Further, the insulator 280 preferably includes an insulator with a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, or resin It is preferable to have. In particular, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having a void is preferably used as the insulator 280 because oxygen can be easily added to the insulator 280 in a later step. In addition, silicon oxide and silicon oxynitride are preferable because they are thermally stable. The film formation of the insulator 280 can be performed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an inkjet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, a curtain coater method, or the like can be used. . In this embodiment mode, silicon oxynitride is deposited as the insulator 280 by a CVD method.

  Note that the insulator 280 is preferably formed so that the top surface has flatness. For example, the top surface of the insulator 280 may have flatness immediately after film formation. Alternatively, for example, the insulator 280 may have flatness by removing the insulator or the like from the top surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such processing is called planarization processing. The planarization process includes a CMP process, a dry etching process, and the like. In this embodiment, a CMP process is used as the planarization process. However, the upper surface of the insulator 280 may not necessarily have flatness.

  Next, the conductor 246A is formed over the insulator 280. Note that the conductor 246A may function as a hard mask in etching the insulator 280, the insulator 244A, and the conductor 242B in a later step, and does not necessarily have to be conductive. The hard mask may be formed of an insulator as long as it functions as a hard mask as described above.

  Next, the conductor 246A is processed using a lithography method to form the conductor 246 which functions as a hard mask (see FIG. 10).

  Next, using the conductor 246 as a hard mask, the insulator 280, the insulator 244A, and the conductor 242B are processed to have an opening 245 so as to have at least a region overlapping with the conductor 205. (See Figure 10). In addition, the conductor 242a and the conductor 242b are formed from the conductor 242B. Although wet etching may be used to form the opening, it is preferable to use dry etching from the viewpoint that microfabrication is possible and that the side surface of the insulator 280 can be processed substantially vertically.

Here, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., more preferably 320 ° C. to 450 ° C. The heat treatment is performed in a nitrogen or inert gas atmosphere. On the other hand, in the case where the conductor 242 is a conductor having oxidation resistance, the heat treatment may be performed in an atmosphere containing oxygen. Further, the heat treatment may be performed under reduced pressure. The heat treatment may be vacuum baking in which the heat treatment is performed in a vacuum state in which the pressure in the treatment chamber is reduced to 1 × 10 ⁻² Pa or less. By performing vacuum baking, zinc atoms and oxygen atoms that form weak Zn—O bonds can be reduced, and deterioration due to electrical characteristics of the transistor, in particular, thermal history can be reduced. The vacuum baking may be performed in a processing chamber for forming the insulator 273A. In this case, the insulator 273A can be formed in the treatment chamber after vacuum baking. For example, heat treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.

  By the heat treatment, impurities such as hydrogen and water contained in the oxide 230a and the oxide 230b can be removed. Further, damage caused to the oxide 230 a or the oxide 230 b in dry etching in the above processing can be recovered. In the case where heat treatment is performed in an atmosphere containing oxygen, oxygen can be added to the oxide 230a and the oxide 230b.

  Further, the metal element contained in the conductor 242 may be diffused to the oxide 230 by the heat treatment, and the metal element may be added to the oxide 230. In addition, oxygen in the oxide 230 may be absorbed by the conductor 242. As a result, the vicinity of the oxide 230 and the conductor 242 becomes a metal compound, which reduces the resistance. At that time, a part of the oxide 230 and the above-described metal element may be alloyed. By alloying part of the oxide 230 and the metal element, the metal element added to the oxide 230 is in a relatively stable state, so that a highly reliable semiconductor device can be provided. Note that in FIG. 10B, regions 231 a and 231 b are denoted by dotted lines as an example of the above-described low-resistance region of the oxide 230.

  Although the regions 231a and 231b are provided so as to diffuse in the depth direction and the horizontal direction from the conductor 242 in the oxide 230b and the oxide 230a, the present invention is not limited thereto. . The region 231a and the region 231b may be formed only in the vicinity of the conductor 242 of the oxide 230b in the depth direction, or may be formed over the entire oxide 230b. Although the regions 231 a and 231 b are formed to be diffused in the horizontal direction from the conductor 242 in the horizontal direction, the present invention is not limited thereto. The region 231 a and the region 231 b may be formed only in the region overlapping with the conductor 242 or may be formed in a region overlapping with part of the conductor 260 formed in a later step.

  In addition, hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancy existing in the region 231, which results in a relatively stable state. Further, hydrogen in the oxygen vacancy existing in the region 234 is released from the oxygen vacancy by heat treatment at 250 ° C. or higher, diffused into the region 231, and enters the oxygen vacancy existing in the region 231, and is relatively stable. Become. Therefore, the heat treatment makes the region 231 lower in resistance, and the region 234 is highly purified (reduction of impurities such as water and hydrogen) and is higher in resistance.

  In addition, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed at 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., more preferably 320 ° C. to 450 ° C.

  Note that in the heat treatment after the formation of the conductive film 242A or the formation of the conductor 242, oxygen in the region 231 of the oxide 230 is absorbed by the conductive film 242A or the conductor 242, whereby the region 231 is formed. Oxygen deficiency may occur. The hydrogen in the oxide 230 enters the oxygen vacancies, whereby the carrier density in the region 231 is increased. Therefore, the region 231 of the oxide 230 is n-type and has a low resistance.

  The oxygen concentration in the region 231 may be lower than the oxygen concentration in the region 234. Further, the hydrogen concentration in the region 231 may be higher than the oxygen concentration in the region 234.

  Next, an insulator 273A is formed in the opening 245 and over the conductor 246 (see FIG. 11). As the insulator 273A, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium may be used. it can. In addition, silicon nitride, silicon nitride containing oxygen, that is, silicon nitride, silicon nitride oxide, or the like is formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. be able to.

  Subsequently, an insulator 250A is formed on the insulator 273A (see FIG. 11).

  The insulator 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 250A, silicon oxynitride is preferably deposited by a CVD method. In addition, it is preferable that the film-forming temperature at the time of forming the insulator 250A into a film is 350 degreeC or more and less than 450 degreeC, especially about 400 degreeC. By forming the insulator 250A at 400 ° C., an insulator with few impurities can be formed.

  Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, the water concentration and the hydrogen concentration of the insulator 250A can be reduced.

  Here, the conductor 242 and the conductor 260 formed in a later step can form parasitic capacitance. That is, the insulating film provided on the side surface of the conductor 242 can function as a dielectric of the parasitic capacitance. On the other hand, since the insulating film functions as a gate insulator of the transistor 200, the insulating film is preferably formed using a thin film of 20 nm or less, preferably 10 nm or less, more preferably 5 nm or less. In order to thicken the insulating film provided on the side surface of the conductor 242 to such an extent that the parasitic capacitance can be ignored, it is preferable that the insulating film have a laminated structure of two or more layers only on the side surface.

  Therefore, it is preferable that anisotropic etching be performed on the insulator 250A to form an insulator on the side surface of the conductor 242, the side surface of the insulator 244, and the side surface of the insulator 280 via the insulator 273A.

  Next, an insulator is newly formed to cover the insulator 273A and the insulator. The insulator can be formed of a similar material using a device similar to the insulator 250A. Through the above steps, insulators with different thicknesses can be provided above the oxide 230 b and on the side surface of the conductor 242. That is, on the side surface of the conductor 242, an insulator thicker than the insulator above the oxide 230b can be provided.

  Next, the insulator 272A is preferably formed over the insulator 273A. By using an insulating barrier as the insulator 272A, oxidation of the conductor 260 which functions as a gate electrode, which is formed in a later step, can be suppressed. On the other hand, in the case where the conductor 260 is formed of an oxidation resistant material, or in the case where the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 272A is not necessarily provided. The insulator 272A can be formed using the same material as the insulator 244A or a device similar to the insulator 273A.

  Subsequently, the conductive film 260A and the conductive film 260B are sequentially formed (see FIG. 11). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A film of titanium nitride may be formed as the conductive film 260A, and a film of tungsten may be formed as the conductive film 260B.

  As the conductive film 260A, a metal nitride may be formed by a CVD method or a sputtering method. By using a metal nitride for the conductive film 260A, it is possible to prevent the conductivity of the conductive film 260B from being oxidized due to the oxygen contained in the insulator 250C.

  In addition, by stacking a metal film with low resistance as the conductive film 260B, a transistor with low driving voltage can be provided.

  Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed in some cases. By this heat treatment, a low resistance region (region 231) may be formed in the oxide 230b.

  Next, the conductive film 260B, the conductive film 260A, the insulator 272A, the insulator 250A, and the insulator 273A are processed and planarized, and from each of the conductor 260b, the conductor 260a, the insulator 272, and the insulator 250 and an insulator 273 (see FIG. 12). As the planarization treatment, there is a method of polishing the conductive film 260B using a CMP method, a method of using an etch back method, or the like.

  At this time, the conductor 260 is formed so that at least a part thereof overlaps with the conductor 205, the oxide 230a, and the oxide 230b. The width in the channel length direction of the conductor 260 is determined by the width of the opening 245 provided in the insulator 280, the thickness of the insulator 273, the thickness of the insulator 250, and the thickness of the insulator 272. The width and thickness described above can be adjusted depending on the performance required of the transistor 200 or the semiconductor device to form the conductor 260 having a desired width.

  In this manner, the conductor 260 is formed to be embedded in the opening of the insulator 280 and the region between the conductor 242a and the conductor 242b. Since the formation of the conductor 260 is performed in a self-aligned manner without using a lithography method, it is not necessary to provide a margin for alignment of the conductor 260. Accordingly, the area occupied by the transistor 200 can be reduced, and the semiconductor device can be miniaturized and highly integrated. In addition, since the lithography process is not required, productivity improvement can be expected by process simplification.

  In order to miniaturize the semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 260 from being lowered. Therefore, when the film thickness of the conductor 260 is increased, the conductor 260 can have a shape with a high aspect ratio. In this embodiment mode, since the conductor 260 is provided so as to be embedded in the opening of the insulator 280, even if the conductor 260 has a shape with a high aspect ratio, the conductor 260 is formed without collapsing in the process. Can.

  Here, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, damage to the oxide 230 b due to the formation of the insulator 273, the insulator 250, the insulator 272, or the conductor 260 can be recovered. In addition, a low resistance region (region 231) may be formed in the oxide 230 by the heat treatment.

  Next, the insulator 274 is formed to cover the insulator 280, the insulator 273, the insulator 250, the insulator 272, the conductor 260a, and the conductor 260b (see FIG. 13). Oxygen is preferably supplied to the insulator 280 by the formation of the insulator 274. In this embodiment, aluminum oxide is formed as the insulator 274 by a sputtering method. Oxygen can be supplied to the insulator 280 by forming the insulator 274 using a gas containing oxygen or using a target containing oxygen. In addition, oxygen contained in the insulator 274 may be supplied to the insulator 280 by performing heat treatment after the insulator 274 is formed. The heat treatment may be performed after the insulator 274 is formed or may be performed after the insulator 281 is formed.

  Next, the insulator 281 is formed over the insulator 274 (see FIG. 13). The insulator 281 can be formed using a similar device to the insulator 280 and using a similar material. For example, the insulator 281 including silicon oxynitride is formed by a CVD method.

  Next, the insulator 281, the insulator 274, the insulator 280, and the insulator 244 are processed by a lithography method to form an opening connected to the conductor 242 (see FIG. 14).

  Next, the conductor 240 (the conductor 240 a and the conductor 240 b) may be formed so as to be embedded in the opening, whereby the transistor 200 illustrated in FIG. 1 can be formed.

  Through the above steps, a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 5 to 14, the transistor 200 can be formed by using the method for manufacturing a semiconductor device described in this embodiment.

  According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

<Modification 1 of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from that shown in <Configuration Example of Semiconductor Device> described above, will be described with reference to FIG.

  FIG. 4A is a top view of a semiconductor device including the transistor 200. FIG. 4B and 4C are cross-sectional views of the semiconductor device. Here, FIG. 4B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 4A and is also a cross-sectional view in the channel length direction of the transistor 200. 4C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 4A, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of FIG. 4A, some elements are omitted for clarity of the drawing.

  In the semiconductor device shown in FIG. 4, the same reference numerals are appended to the structures having the same functions as the structures constituting the semiconductor device (see FIG. 1) shown in <Configuration Example of Semiconductor Device>.

  Hereinafter, the configuration of the transistor 200 is described with reference to FIG. Note that also in this item, as a constituent material of the transistor 200, any of the materials described in detail in <Configuration Example of Semiconductor Device> can be used.

  In the semiconductor device shown in FIG. 4, an oxide 230c having an opening is provided between the insulator 224 and the oxide 230a in the semiconductor device shown in <Structural Example of Semiconductor Device> (see FIG. 1). The difference is that The oxide 230a is in contact with the insulator 224 through an opening provided in the oxide 230c.

  The material used for the oxide 230c is preferably a material with a high ratio of Ga and Zn as compared to the oxide 230a and the oxide 230b. Specifically, in the metal oxide used for the oxide 230c, the atomic ratio of the element M in the constituent elements is smaller than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230a, It is preferable that the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230 b be larger. In the metal oxide used for the oxide 230c, the atomic ratio of the element M to In is the atomic ratio of the element M to In in the metal oxide used for the oxide 230a, and the metal oxide used for the oxide 230b. It is preferable that the atomic ratio of the element M to the In in the atomic ratio of. For example, as the oxide 230c, an oxide film formed using a target of In: Ga: Zn = 1: 3: 4 [atomic number ratio] by a sputtering method can be used.

  It is preferable to use a material which hardly transmits oxygen as the oxide 230c. On the other hand, the oxide 230 c has an opening at a position overlapping with the region 234. Therefore, oxygen contained in the insulator 224 diffuses into the oxide 230 a and the oxide 230 b through the opening. Arrows shown in FIG. 4B visualize how oxygen contained in the insulator 280 and the insulator 224 diffuses. Oxygen contained in the insulator 280 is diffused to the insulator 224 through the opening 290. In addition, oxygen contained in the insulator 224 is diffused into the oxide 230 a and the region 234 of the oxide 230 b through the opening provided in the oxide 230 c. Note that oxygen supplied to the oxide 230 a and the oxide 230 b may diffuse to the region 231. By providing the oxide 230 c in the transistor 200, oxygen can be efficiently supplied to the region 234.

  In the case of manufacturing the transistor 200 including the oxide 230c, an oxide film to be the oxide 230c (hereinafter, referred to as an oxide film 230C) is formed over the insulator 224. Next, an opening is formed in the oxide film 230C. The opening is formed to overlap with the conductor 205 and the conductor 203. In addition, the opening is preferably formed to overlap with the region 234 of the oxide 230 which is formed in a later step.

  Next, the oxide film 230A, the oxide film 230B, and the conductive film 242A are formed over the oxide film 230C in the same manner as in the above-described <Method for manufacturing semiconductor device>. Before and after formation of the film, heat treatment may be appropriately performed.

  Next, the conductive film 242A, the oxide film 230B, the oxide film 230A, and the oxide film 230C are processed into an island shape by a lithography method to form a conductor 242B, an oxide 230b, an oxide 230a, and an oxide 230c. . The processing can be performed using a dry etching method or a wet etching method. Machining by dry etching is suitable for micromachining. In addition, after the processing of the conductive film 242A, the processing may be performed on the oxide film 230B, the oxide film 230A, and the oxide film 230C by using the conductor 242B as a hard mask.

  Next, an insulator 244A is formed over the insulator 224, the oxide 230c, the oxide 230a, the oxide 230b, and the conductor 242B. The insulator 244A is provided to cover the side surfaces of the oxide 230c, the oxide 230a, and the oxide 230b.

  After that, the transistor 200 including the oxide 230c can be manufactured by performing steps similar to the above <Method for Manufacturing Semiconductor Device>.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

Second Embodiment
In this embodiment, one mode of a semiconductor device functioning as a memory device, which is different from the above embodiment, will be described with reference to FIGS.

<Storage device 1>
15A and 15B show a cell 600 which constitutes a memory device. The cell 600 includes a transistor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b. FIG. 15A is a top view of the cell 600. FIG. FIG. 15B is a cross-sectional view of a portion indicated by an alternate long and short dash line in A1-A2 in FIG. Note that in the top view of FIG. 15A, some elements are omitted for clarity of the drawing.

  The cell 600 includes a transistor 200a and a transistor 200b, has a capacitor 100a superimposed on the transistor 200a, and has a capacitor 100b superimposed on the transistor 200b. In the cell 600, the transistor 200a and the transistor 200b, and the capacitor 100a and the capacitor 100b may be arranged in line symmetry. Thus, the transistor 200a and the transistor 200b preferably have similar structures, and the capacitor 100a and the capacitor 100b preferably have similar structures.

  The insulator 130 is provided over the insulator 281 over the transistors 200 a and 200 b, and the insulator 150 is provided over the insulator 130. Here, as the insulator 150, an insulator that can be used for the insulator 281 may be used.

  Furthermore, the conductor 160 is provided over the insulator 150. A conductor 240 is provided so as to be embedded in an opening formed in the insulator 280, the insulator 281, the insulator 130, and the insulator 150. The lower surface of the conductor 240 is in contact with the conductor 242 b, and the upper surface of the conductor 240 is in contact with the conductor 160. The conductor 240 is in electrical contact with the conductor 242 b in contact with the top surface and the side surface of the insulator 273.

  The transistor 200 described in the above embodiment can be used for the transistor 200 a and the transistor 200 b. Thus, for the structures of the transistor 200a and the transistor 200b, the description of the transistor 200 can be referred to. In FIGS. 15A and 15B, reference numerals of elements of the transistors 200a and 200b are omitted. Note that the transistor 200a and the transistor 200b illustrated in FIGS. 15A and 15B are examples, and the present invention is not limited to the structures thereof, and appropriate transistors may be used depending on the circuit configuration and the driving method.

  The transistors 200a and 200b are both formed in the oxide 230, and one of the source and the drain of the transistor 200a and one of the source and the drain of the transistor 200b are in contact with the conductor 242b. Thus, one of the source and the drain of the transistor 200a and one of the source and the drain of the transistor 200b are electrically connected to the conductor 240 through the conductor 242b. Thus, the contact portions of the transistor 200a and the transistor 200b are shared, and the number of plugs and contact holes can be reduced. As described above, by sharing the wiring electrically connected to one of the source and the drain, the occupied area of the memory cell array can be further reduced.

[Capacitance Element 100a and Capacitance Element 100b]
As illustrated in FIGS. 15A and 15B, the capacitor 100a is provided in a region overlapping with the transistor 200a. Similarly, the capacitor 100 b is provided in a region overlapping with the transistor 200 b. Note that the capacitor 100 b has a structure corresponding to that of the capacitor 100 a. Although the detailed structure of the capacitive element 100a will be described below, the description of the capacitive element 100a can be referred to for the capacitive element 100b unless otherwise noted.

  The capacitive element 100 a includes the conductor 110, the insulator 130, and the conductor 120 over the insulator 130. Here, as the conductor 110 and the conductor 120, a conductor that can be used for the conductor 203, the conductor 205, the conductor 260, or the like may be used.

  The capacitor element 100 a is formed in an opening of the insulator 244, the insulator 280, the insulator 274, and the insulator 281. The conductor 110 functioning as the lower electrode and the conductor 120 functioning as the upper electrode face each other on the bottom surface and the side surface of the opening with the insulator 130 functioning as the dielectric interposed therebetween. Here, the conductor 110 of the capacitor 100a is formed in contact with the conductor 242a of the transistor 200a.

  In particular, by increasing the depth of the openings of the insulator 280 and the insulator 281, the projected area does not change, and the capacitance of the capacitor 100a can be increased. Therefore, it is preferable that the capacitive element 100 a be cylindrical (the side area is larger than the base area).

  With the above structure, the capacitance per unit area of the capacitor 100a can be increased, and miniaturization or high integration of the semiconductor device can be promoted. In addition, the value of the capacitance of the capacitor 100a can be set as appropriate depending on the thicknesses of the insulator 280 and the insulator 281. Therefore, a semiconductor device with a high degree of freedom in design can be provided.

  Further, as the insulator 130, it is preferable to use an insulator having a large dielectric constant. For example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. As an insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

  The insulator 130 may have a stacked structure, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, an oxide containing hafnium and aluminum (hafnium aluminate), etc. Therefore, two or more layers may be selected to form a laminated structure. For example, it is preferable to deposit hafnium oxide, aluminum oxide, and hafnium oxide in order by an ALD method to form a stacked structure. The film thicknesses of hafnium oxide and aluminum oxide are respectively 0.5 nm or more and 5 nm or less. With such a stacked structure, the capacitor 100a can have a large capacitance value and a small leak current.

  Note that the conductor 110 or the conductor 120 may have a stacked structure. For example, the conductor 110 or the conductor 120 is a stack of a conductive material whose main component is titanium, titanium nitride, tantalum, or tantalum nitride, and a conductive material whose main component is tungsten, copper, or aluminum. It may be a structure. The conductor 110 or the conductor 120 may have a single-layer structure or a stacked structure of three or more layers.

  In the opening for forming the capacitor 100 a, the insulator 140 is preferably formed inside the conductor 120. Here, as the insulator 140, an insulator that can be used for the insulator 281 may be used. The top surface of the insulator 140 is preferably substantially flush with the top surface of the conductor 120. However, the present invention is not limited to this. For example, the film thickness of the conductor 120 may be increased to fill the opening, or the insulator 150 may be formed in a state where the opening is formed inside the conductor 120 You may fill the opening.

[Structure of cell array]
Next, an example of a cell array in which the above cells are arranged in a matrix or matrix will be described with reference to FIGS.

  FIG. 16 is a circuit diagram showing one form in which the cells shown in FIG. 15 are arranged in a matrix. FIG. 17 is a schematic view showing a cross-sectional structure in the vicinity of the cell 600 in the circuit diagram shown in FIG. 16 and the cell 601 adjacent to the cell 600. As shown in FIG. FIG. 18 is a schematic view showing a layout of the wiring WL, the wiring BL, and the oxide 230 in the circuit diagram shown in FIG. In FIGS. 16 to 18, the extending direction of the wiring BL is the x direction, the extending direction of the wiring WL is the y direction, and the direction perpendicular to the xy plane is the z direction. Although FIG. 16 and FIG. 18 show an example in which 3 × 3 cells are arranged, the present embodiment is not limited to this, and the number and arrangement of memory cells, wirings, etc. included in the cell array. May be set as appropriate. Further, in the top view of FIG. 18, some elements shown in FIG. 16 are omitted for clarity of the figure.

  As shown in FIG. 16, one of the source and the drain of the transistor 200a and the transistor 200b which form a cell is electrically connected to a common wiring BL (BL01, BL02, BL03). The wiring BL is also electrically connected to one of the source and the drain of the transistor 200 a and the transistor 200 b included in the cell 600 arranged in the x direction. On the other hand, the first gate of the transistor 200a and the first gate of the transistor 200b which form the cell 600 are electrically connected to different wirings WL (WL01 to WL06). In addition, the wirings WL electrically connect a first gate of the transistor 200 a and a first gate of the transistor 200 b included in the cell 600 arranged in the y direction.

  Further, one electrode of the capacitor 100 a and one electrode of the capacitor 100 b included in the cell 600 are electrically connected to the wiring PL. For example, the wiring PL may be formed to extend in the y direction.

  In addition, the second gate BG may be provided in the transistor 200 a and the transistor 200 b included in each cell 600. The potential applied to BG can control the threshold of the transistor. The BG is connected to the transistor 400, and the potential applied to the BG can be controlled by the transistor 400.

  For example, as shown in FIG. 17, the conductor 160 is extended in the x direction to function as the wiring BL, and the conductor 260 is extended in the y direction to function as the wiring WL, and the conductor 120 is extended in the y direction. Thus, it can function as the wiring PL. Alternatively, the conductor 203 can be extended in the y direction to function as a wiring connected to BG.

  Further, as shown in FIG. 17, the conductor 120 functioning as one electrode of the capacitor 100b of the cell 600 preferably doubles as one of the electrodes of the capacitor 100a of the cell 601. Although not shown, the conductor 120 functioning as one electrode of the capacitor 100 a of the cell 600 doubles as one electrode of the capacitor of the cell adjacent to the left side of the cell 600. The same configuration is applied to the cell on the right side of the cell 601. Therefore, a cell array can be configured. With the configuration of the cell array, the distance between adjacent cells can be reduced, so that the projection area of the cell array can be reduced and high integration can be achieved.

  Further, as shown in FIG. 18, the oxide 230 and the wirings WL are arranged in a matrix, whereby the semiconductor device of the circuit diagram shown in FIG. 25 can be formed. Here, the wiring BL is preferably provided in a layer different from the wiring WL and the oxide 230. In particular, by providing the capacitor 100a and the capacitor 100b in a lower layer than the wiring BL, a layout in which the long side direction of the oxide 230 and the wiring BL are substantially parallel can be realized. Therefore, the layout of cells can be simplified, the degree of freedom in design can be improved, and the process cost can be reduced.

  In FIG. 18, the oxide 230 and the wiring WL are provided such that the long side of the oxide 230 is substantially orthogonal to the extending direction of the wiring WL, but the present invention is not limited to this. For example, the long side of the oxide 230 may not be orthogonal to the extending direction of the wiring WL, and the long side of the oxide 230 may be inclined with respect to the extending direction of the wiring WL. Preferably, the oxide 230 and the wiring WL may be provided such that the angle between the long side of the oxide 230 and the wiring WL is 20 ° to 70 °, preferably 30 ° to 60 °.

  In addition, the cell array may be stacked not only on a plane surface. By stacking a plurality of cell arrays, cells can be integrated and arranged without increasing the area occupied by the cell array. That is, a 3D cell array can be configured.

  As described above, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off current can be provided. Alternatively, according to one embodiment of the present invention, a transistor with large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Third Embodiment
In this embodiment, one mode of a semiconductor device functioning as a memory device, which is different from the above embodiment, will be described with reference to FIGS.

<Storage device 2>
The memory device illustrated in FIG. 19 includes a transistor 300, a transistor 200, and a capacitor 100. FIG. 19 is a cross-sectional view of the transistors 200 and 300 in the channel length direction. FIG. 20 shows a cross-sectional view in the channel width direction of the transistor 300 in the vicinity of the transistor 300. The memory device illustrated in FIG. 21 includes the transistor 500, the transistor 200, and the capacitor 100. FIG. 21 is a cross-sectional view of the transistors 200 and 500 in the channel length direction.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has low off-state current, stored data can be held for a long time by using the transistor for the memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, power consumption of the memory device can be sufficiently reduced.

  In the memory device illustrated in FIG. 19, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. There is. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .

  The memory device illustrated in FIG. 19 has such a characteristic that the potential of the gate of the transistor 300 can be held, whereby information can be written, held, and read as described below.

  The writing and holding of information will be described. First, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, whereby the transistor 200 is turned on. Thus, the potential of the wiring 1003 is applied to the node SN electrically connected to the gate of the transistor 300 and one of the electrodes of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of charges (hereinafter referred to as low level charge and high level charge) giving two different potential levels is given. After that, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off, whereby the transistor 200 is turned off, whereby charge is held at the node SN (holding).

  When the off-state current of the transistor 200 is small, the charge of the node SN is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the wiring 1005 in a state where a predetermined potential (constant potential) is supplied to the wiring 1001, the wiring 1002 takes a potential corresponding to the amount of charge held at the node SN. This is because, if the transistor 300 is an n-channel type, the apparent threshold voltage V th — _H when the high level charge is given to the gate of the transistor 300 is when the low level charge is given to the gate of the transistor 300 This is because the apparent threshold voltage V _{th_L of the} Here, the apparent threshold voltage refers to the potential of the wiring 1005 required to make the transistor 300 conductive. Therefore, by _setting the potential of the wiring 1005 to the potential V ₀ between V _{th — H} and V th — _L , the charge given to the node SN can be determined. For example, in the case where a high level charge is given to the node SN in writing, the transistor 300 is turned on when the potential of the wiring 1005 is V ₀ (> V th — _H ). On the other hand, in the case where low level charge is applied to the node SN, the transistor 300 remains off even when the potential of the wiring 1005 becomes V ₀ (<V th — _L ). Therefore, the information held in the node SN can be read by determining the potential of the wiring 1002.

Note that in the case where memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. For example, in the case where the memory cell array has a NOR configuration, only information of a desired memory cell can be read by turning off the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 is turned off regardless of the charge applied to the node SN, that is, a potential lower than _{Vth_H} may be applied to the wiring 1005 connected to the memory cell which does not read data. . Alternatively, for example, in the case where the memory cell array has a NAND configuration, only information of a desired memory cell can be read by turning on the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 is turned on regardless of the charge applied to the node SN, that is, a potential higher than V th — _L may be applied to the wiring 1005 connected to the memory cell from which data is not read.

<Structure of Storage Device 2>
The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

  The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b. Have.

  As illustrated in FIG. 20, in the transistor 300, the top surface of the semiconductor region 313 and the side surface in the channel width direction are covered with the conductor 316 with the insulator 315 interposed therebetween. As described above, by setting the transistor 300 to a Fin type, the on-characteristic of the transistor 300 can be improved by increasing the effective channel width. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

  The transistor 300 may be either p-channel or n-channel.

  A semiconductor such as a silicon-based semiconductor is preferably included in a region where the channel of the semiconductor region 313 is to be formed, a region in the vicinity thereof, a low resistance region 314a to be a source or drain region, a low resistance region 314b, and the like. Preferably, crystalline silicon is included. Alternatively, it may be formed using a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide) or the like. It is also possible to use silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.

  The low-resistance region 314a and the low-resistance region 314b impart p-type conductivity such as an element imparting n-type conductivity such as arsenic or phosphorus or p-type conductivity such as boron in addition to the semiconductor material applied to the semiconductor region 313 Containing elements.

  The conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron, a metal material, an alloy Materials or conductive materials such as metal oxide materials can be used.

  Note that the Vth of the transistor can be adjusted by defining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

  Note that the transistor 300 illustrated in FIG. 19 is an example, and is not limited to the structure. An appropriate transistor may be used depending on the circuit configuration and the driving method.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked over the transistor 300.

  For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used as the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Just do it.

  The insulator 322 may have a function as a planarization film which planarizes a step difference generated by the transistor 300 and the like provided below the insulator. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance the planarity.

  For the insulator 324, a film having a barrier property to prevent diffusion of hydrogen or an impurity from the substrate 311, the transistor 300, or the like to the region where the transistor 200 is provided is preferably used.

  As an example of a film having a barrier property to hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 200 or the like, the characteristics of the semiconductor element may be deteriorated. Therefore, it is preferable to use a film which suppresses diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of desorption of hydrogen.

The desorption amount of hydrogen can be analyzed, for example, using a thermal desorption gas analysis method (TDS) or the like. For example, in the TDS analysis, the desorption amount of hydrogen in the insulator 324 is 10 × 10 5 in the range of 50 ° C. to 500 ° C. when the desorption amount in terms of hydrogen atoms is converted per area of the insulator 324. ¹⁵ atom / cm ² or less, and may be preferably 5 × ¹⁰ 15 atom / cm ² or less.

  Note that the insulator 326 preferably has a dielectric constant lower than that of the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Further, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less of the relative permittivity of the insulator 324, and more preferably 0.6 times or less. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

  In the insulator 320, the insulator 322, the insulator 324, and the insulator 326, the conductor 328 electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 have a function as a plug or a wiring. Moreover, the conductor which has a function as a plug or wiring may put several structure together, and may provide the same code | symbol. In the present specification and the like, the wiring and the plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and a wiring (conductor 328 and conductor 330 and the like), a single layer or a stack of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material It can be used. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 19, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to the conductor 328 and the conductor 330.

  Note that, for example, for the insulator 350, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 350 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  As a conductor having a barrier property to hydrogen, for example, tantalum nitride or the like may be used. Further, by stacking tantalum nitride and tungsten with high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, the tantalum nitride layer having a barrier property to hydrogen preferably has a structure in contact with the insulator 350 having a barrier property to hydrogen.

  A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 19, the insulator 360, the insulator 362, and the insulator 364 are sequentially stacked and provided. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductor 328 and the conductor 330.

  Note that, for example, for the insulator 360, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 360 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 19, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed over the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to the conductor 328 and the conductor 330.

  Note that, for example, for the insulator 370, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening portion of the insulator 370 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 19, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to the conductor 328 and the conductor 330.

  Note that for example, for the insulator 380, as in the case of the insulator 324, it is preferable to use an insulator having a barrier property to hydrogen. The conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 380 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described above, the memory device according to this embodiment It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

  An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. For any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216, a material having a barrier property to oxygen or hydrogen is preferably used.

  For example, for the insulator 210 and the insulator 214, for example, a film having a barrier property to prevent diffusion of hydrogen and impurities from the region where the substrate 311 or the transistor 300 is provided to the region where the transistor 200 is provided Is preferred. Therefore, the same material as the insulator 324 can be used.

  As an example of a film having a barrier property to hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 200 or the like, the characteristics of the semiconductor element may be deteriorated. Therefore, it is preferable to use a film which suppresses diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of desorption of hydrogen.

  Further, as the film having a barrier property to hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

  In particular, aluminum oxide has a high blocking effect of preventing permeation of the film against both oxygen and impurities such as hydrogen and moisture which cause fluctuation of the electrical characteristics of the transistor. Thus, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed in the transistor 200 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide of the transistor 200 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 200.

  For example, for the insulator 212 and the insulator 216, the same material as the insulator 320 can be used. In addition, by using a material having a relatively low dielectric constant as the interlayer film for the insulating film, parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 212 and the insulator 216.

  In the insulator 210, the insulator 212, the insulator 214, and the insulator 216, the conductor 218, a conductor (the conductor 205) included in the transistor 200, and the like are embedded. Note that the conductor 218 has a function as a plug electrically connected to the capacitor 100 or the transistor 300, or a wiring. The conductor 218 can be provided using a material similar to the conductor 328 and the conductor 330.

  In particular, the conductor 218 in a region in contact with the insulator 210 and the insulator 214 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. According to this structure, the transistor 300 and the transistor 200 can be completely separated in a layer having a barrier property to oxygen, hydrogen, and water, and can suppress diffusion of hydrogen from the transistor 300 to the transistor 200. .

  The transistor 200 is provided above the insulator 216. Note that the structure of the transistor 200 may be a transistor included in the semiconductor device described in the above embodiment. The transistor 200 illustrated in FIG. 19 is an example, and is not limited to the structure. An appropriate transistor may be used according to the circuit configuration and the driving method.

  An insulator 281 is provided above the transistor 200.

  An insulator 282 is provided on the insulator 281. For the insulator 282, a substance having a barrier property to oxygen or hydrogen is preferably used. Therefore, the same material as the insulator 214 can be used for the insulator 282. For example, for the insulator 282, metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.

  In particular, aluminum oxide has a high blocking effect of preventing permeation of the film against both oxygen and impurities such as hydrogen and moisture which cause fluctuation of the electrical characteristics of the transistor. Thus, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed in the transistor 200 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide of the transistor 200 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 200.

  In addition, an insulator 286 is provided over the insulator 282. The insulator 286 can be made of the same material as the insulator 320. In addition, by using a material having a relatively low dielectric constant as the interlayer film for the insulating film, parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 286.

  For the insulator 220, the insulator 222, the insulator 224, the insulator 244, the insulator 280, the insulator 274, the insulator 281, the insulator 282, and the insulator 286, the conductor 246, the conductor 248, and the like Is embedded.

  The conductor 246 and the conductor 248 each function as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Subsequently, a capacitor 100 is provided above the transistor 200. The capacitive element 100 includes a conductor 110, a conductor 120, and an insulator 130.

  The conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 110 has a function as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.

  For the conductor 112 and the conductor 110, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or a metal nitride film containing the above-described element as a component (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide can also be applied.

  Although the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 19, the structure is not limited to this structure, and a stacked structure of two or more layers may be used. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor having high adhesion to a conductor having a barrier property and a conductor having high conductivity may be formed.

  The conductor 120 is provided to overlap with the conductor 110 through the insulator 130. Note that as the conductor 120, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper) or Al (aluminum) or the like which is a low resistance metal material may be used.

  An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Moreover, the insulator 150 may function as a planarizing film which covers the uneven shape below it.

  Further, the transistor 300 is not limited to a transistor provided on a semiconductor substrate. For example, as shown in FIG. 21, a transistor 500 may be used instead of the transistor 300. The transistor 500 has a structure similar to that of the transistor 200, and can be manufactured by a similar process.

  The transistor 500 is provided on an insulator 410 provided on a substrate (not shown). The insulator 412 can be provided using a similar material and using a method similar to the insulator 212. Similarly, insulator 414, insulator 416, insulator 420, insulator 422, insulator 424, insulator 444, insulator 480, and insulator 484 are insulator 214, insulator 216, insulator 220, respectively. A similar material can be provided using a method similar to the insulator 222, the insulator 224, the insulator 244, the insulator 280, and the insulator 284.

  The conductor 110 which is one of the electrodes of the capacitor 100 is electrically connected to the gate of the transistor 500 through the conductor 246, the conductor 248, the conductor 218, the conductor 428, and the like. The description of the portions of the transistor 500 in common with the transistor 200 is omitted.

  With this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, in a semiconductor device using a transistor including an oxide semiconductor, miniaturization or high integration can be achieved.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

Embodiment 4
In this embodiment, a transistor using an oxide as a semiconductor (hereinafter, referred to as an OS transistor) and a memory element to which a capacitor is applied according to one embodiment of the present invention with reference to FIGS. A NOSRAM will be described as an example of the device. NOSRAM (registered trademark) is an abbreviation of "nonvolatile oxide semiconductor RAM" and refers to a RAM having memory cells of gain cell type (2T type, 3T type). In the following, a memory device using an OS transistor such as a NOSRAM may be referred to as an OS memory.

  In the NOSRAM, a memory device (hereinafter referred to as “OS memory”) in which an OS transistor is used for a memory cell is applied. The OS memory is a memory that has at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with extremely small off current, the OS memory has excellent retention characteristics and can function as a non-volatile memory.

<< NOSRAM 1600 >>
FIG. 22 shows a configuration example of the NOSRAM. The NOSRAM 1600 shown in FIG. 22 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. The NOSRAM 1600 is a multivalued NOSRAM that stores multivalued data in one memory cell.

  The memory cell array 1610 has a plurality of memory cells 1611, a plurality of word lines WWL, a plurality of word lines RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, 3-bit (eight-valued) data is stored in one memory cell 1611.

  The controller 1640 controls the entire NOSRAM 1600 in a centralized manner, writes the data WDA [31: 0], and reads the data RDA [31: 0]. The controller 1640 processes external command signals (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660 and the output driver 1670.

  The row driver 1650 has a function of selecting a row to access. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.

  Column driver 1660 drives source line SL and bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.

  The DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into analog voltages every three bits.

  The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and an input of the write voltage generated by the DAC 1663 to the selected source line SL. Have a function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.

  The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed, and transmits the potential of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The potential of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.

  The configurations of the row driver 1650, the column driver 1660, and the output driver 1670 described in this embodiment are not limited to the above. Arrangements of these drivers and wirings connected to the drivers may be changed according to the configuration or driving method of the memory cell array 1610 or the like, or functions of the drivers and wirings connected to the drivers are changed Or you may add. For example, part of the functions of the source line SL may be provided to the bit line BL.

  Although the amount of information held in each memory cell 1611 is 3 bits in the above description, the configuration of the storage device described in this embodiment is not limited to this. The amount of information held by each memory cell 1611 may be 2 bits or less, or 4 bits or more. For example, when the amount of information held in each memory cell 1611 is 1 bit, the DAC 1663 and the ADC 1672 may not be provided.

<Memory Cell 1611 to Memory Cell 1614>
FIG. 23A is a circuit diagram showing a configuration example of the memory cell 1611. The memory cell 1611 is a 2T-type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, the word line RWL, the bit line BL, the source line SL, and the wiring BGL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitive element C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is formed of, for example, a p-channel Si transistor. The capacitive element C61 is a holding capacitance for holding the potential of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.

  Since the write transistor of the memory cell 1611 is configured by the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

  In the example of FIG. 23A, the bit line is a common bit line for writing and reading, but as shown in FIG. 23B, the bit line WBL, which functions as a writing bit line, and the reading bit line And the bit line RBL may be provided.

  FIGS. 23C to 23E show other configuration examples of the memory cell. FIGS. 23C to 23E show an example in which the write bit line WBL and the read bit line RBL are provided. However, as shown in FIG. 23A, the write and read bits are shared. Bit lines may be provided.

  A memory cell 1612 shown in FIG. 23C is a modified example of the memory cell 1611, in which the read transistor is changed to an n-channel transistor (MN 61). The transistor MN61 may be an OS transistor or a Si transistor.

  In the memory cell 1611 and the memory cell 1612, the OS transistor MO61 may be an OS transistor without a bottom gate.

  The memory cell 1613 shown in FIG. 23D is a 3T type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL, the bit lines RBL, the source lines SL, the wirings BGL, and the wirings PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.

  A memory cell 1614 shown in FIG. 23E is a modification of the memory cell 1613, in which the read transistor and the select transistor are changed to n-channel transistors (transistor MN62 and transistor MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.

  The OS transistor provided in each of the memory cells 1611 to 1614 may be a transistor without a bottom gate or a transistor with a bottom gate.

  In the above, a so-called NOR type memory device in which memory cells 1611 and the like are connected in parallel is described, but the memory device described in this embodiment is not limited to this. For example, a so-called NAND memory device in which memory cells 1615 as shown below are connected in series may be used.

  FIG. 24 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610. Referring to FIG. The memory cell array 1610 illustrated in FIG. 24 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615. The memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitive element C63. Here, the transistor MN64 is formed of, for example, an n-channel Si transistor. The transistor MN 64 may be a p-channel Si transistor or an OS transistor.

  Hereinafter, the memory cell 1615a and the memory cell 1615b illustrated in FIG. 24 will be described as an example. Here, reference numerals of a wiring or a circuit element connected to either the memory cell 1615 a or the memory cell 1615 b are denoted by a or b.

  In the memory cell 1615a, the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitive element C63a are electrically connected. Further, the bit line WBL and the other of the source and the drain of the OS transistor MO63a are electrically connected. In addition, the word line WWLa and the gate of the OS transistor MO63a are electrically connected. Further, the wiring BGLa and the bottom gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other of the electrodes of the capacitive element C 63 a are electrically connected.

  The memory cell 1615 b can be provided symmetrically with the memory cell 1615 a with the contact portion with the bit line WBL as an axis of symmetry. Accordingly, the circuit element included in the memory cell 1615 b is also connected to the wiring in the same manner as the memory cell 1615 a.

  Further, the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b in the memory cell 1615b. The drain of the transistor MN64a included in the memory cell 1615a is electrically connected to the bit line RBL. The source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory cells 1615. As described above, in the NAND-type memory cell array 1610, the plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.

  In the memory device having the memory cell array 1610 shown in FIG. 24, the write operation and the read operation are performed for each of a plurality of memory cells (hereinafter referred to as a memory cell column) connected to the same word line WWL (or word line RWL). Do. For example, the write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column to be written, and the OS transistor MO63 of the memory cell column to be written is turned on. As a result, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 of the designated memory cell column and the electrode of the capacitive element C63, and a predetermined charge is applied to the gate. Then, when the OS transistor MO63 of the memory cell column is turned off, the predetermined charge applied to the gate can be held. Thus, data can be written to the memory cell 1615 of the specified memory cell column.

  Also, for example, the read operation can be performed as follows. First, to a word line RWL not connected to a memory cell column to be read, a potential that turns on the transistor MN64 regardless of the charge applied to the gate of the transistor MN64 is applied to read a memory cell column The other transistors MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column to be read by the charge of the gate of the transistor MN64 so that the on state or the off state of the transistor MN64 is selected. Then, a constant potential is applied to the source line SL, and the reading circuit connected to the bit line RBL is brought into an operating state. Here, since the plurality of transistors MN64 between the source line SL and the bit line RBL are in the on state except for the memory cell column to be read, the conductance between the source line SL and the bit line RBL is for reading It is determined by the state (on state or off state) of the transistor MN64 of the memory cell column. The conductance of the transistor differs depending on the charge of the gate of the transistor MN64 in the memory cell column to be read, and accordingly, the potential of the bit line RBL takes a different value. Information can be read out from the memory cell 1615 of the specified memory cell column by reading out the potential of the bit line RBL by the reading circuit.

  Since data is rewritten by charging / discharging of the capacitive element C61, the capacitive element C62, or the capacitive element C63, the number of times of rewriting is in principle not limited, and data can be written and read with low energy. In addition, since it is possible to hold data for a long time, the refresh frequency can be reduced.

  When the semiconductor device described in the above embodiment is used for the memory cell 1611, the memory cell 1612, the memory cell 1613, the memory cell 1614, and the memory cell 1615, the transistor 200 is used as the OS transistor MO61, the OS transistor MO62, and the OS transistor MO63. The capacitor C100 can be used as the element C61, the capacitor C62, and the capacitor C63, and the transistor 300 can be used as the transistor MP61, the transistor MP62, the transistor MP63, the transistor MN61, the transistor MN62, the transistor MN63, and the transistor MN64. Thus, the area occupied by the pair of the transistor and the capacitor in top view can be reduced, so that the memory device according to this embodiment can be further highly integrated. Therefore, the storage capacity per unit area of the storage device according to the present embodiment can be increased.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

Fifth Embodiment
In this embodiment, a DOSRAM is described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention with reference to FIGS. 25 and 26. DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor RAM", and refers to a RAM having memory cells of 1T (transistor) 1C (capacitance) type. OS memory is applied to the DOSRAM as well as the NOSRAM.

<< DOSRAM1400 >>
FIG. 25 shows a configuration example of the DOSRAM. As shown in FIG. 25, the DOSRAM 1400 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and a sense amplifier array 1420 (hereinafter referred to as "MC-SA array 1420").

  The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 has a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. Global bit line GBLL and global bit line GBLR are stacked on memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure hierarchized by local bit lines and global bit lines is adopted as the structure of bit lines.

  The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> to local memory cell arrays 1425 <N-1>. FIG. 26A shows a configuration example of the local memory cell array 1425. The local memory cell array 1425 has a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, and a plurality of bit lines BLR. In the example of FIG. 26A, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.

  FIG. 26B shows an example of a circuit configuration of a pair of memory cells 1445a and 1445b connected to a common bit line BLL (bit line BLR). The memory cell 1445a includes a transistor MW1a, a capacitive element CS1a, a terminal B1a, and a terminal B2a, and is connected to the word line WLa and the bit line BLL (bit line BLR). The memory cell 1445 b includes a transistor MW1 b, a capacitive element CS1 b, a terminal B1 b, and a terminal B2 b, and is connected to the word line WLb and the bit line BLL (bit line BLR). Note that, in the following, when one of the memory cell 1445a and the memory cell 1445b is not particularly limited, the memory cell 1445 and the configuration attached to the memory cell 1445 may not be denoted by the symbol a or b.

  The transistor MW1a has a function of controlling charging and discharging of the capacitive element CS1a, and the transistor MW1b has a function of controlling charging and discharging of the capacitive element CS1b. The gate of transistor MW1a is electrically connected to word line WLa, the first terminal is electrically connected to bit line BLL (bit line BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1a It is done. The gate of transistor MW1b is electrically connected to word line WLb, the first terminal is electrically connected to bit line BLL (bit line BLR), and the second terminal is electrically connected to the first terminal of capacitive element CS1b. It is connected to the. Thus, the bit line BLL (bit line BLR) is commonly used for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.

  The transistor MW1 has a function of controlling charging and discharging of the capacitive element CS1. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant potential (for example, low power supply potential) is input to the terminal B2.

  In the case of using the semiconductor device described in the above embodiment for the memory cell 1445a and the memory cell 1445b, the transistor 200a as the transistor MW1a and the transistor 200b as the transistor MW1b, the capacitive element 100a as the capacitive element CS1a, and a capacitive element as the capacitive element CS1b 100b can be used. Thus, the area occupied by the pair of the transistor and the capacitor in top view can be reduced, so that the memory device according to this embodiment can be highly integrated. Therefore, the storage capacity per unit area of the storage device according to the present embodiment can be increased.

  The transistor MW1 comprises a bottom gate, which is electrically connected to the terminal B1. Therefore, the Vth of the transistor MW1 can be changed by the potential of the terminal B1. For example, the potential of the terminal B1 may be a fixed potential (for example, a negative constant potential), or the potential of the terminal B1 may be changed according to the operation of the DOSRAM 1400.

  The bottom gate of the transistor MW1 may be electrically connected to the gate, the source, or the drain of the transistor MW1. Alternatively, the transistor MW1 may not have a bottom gate.

  The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> to 1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference of the bit line pair, and a function of holding this potential difference. Switch array 1444 has a function of selecting a bit line pair and electrically connecting the selected bit line pair and the global bit line pair.

  Here, the bit line pair means two bit lines which are simultaneously compared by the sense amplifier. The global bit line pair refers to two global bit lines which are simultaneously compared by the global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form a pair of bit lines. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the term “bit line pair (BLL, BLR)” and “global bit line pair (BLL, BLR)” are also used.

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOS RAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and generates a control signal for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. And a function of holding an address signal input from the outside, and a function of generating an internal address signal.

(Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL in the access target row.

  The column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting a bit line of the access target column. The selection signal of column selector 1413 controls switch array 1444 of each local sense amplifier array 1426. The control signals of the sense amplifier driver circuit 1414 drive the plurality of local sense amplifier arrays 1426 independently.

(Column circuit 1415)
Column circuit 1415 has a function of controlling an input of data signal WDA [31: 0] and a function of controlling an output of data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

  Global sense amplifier 1447 is electrically connected to global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying the potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Writing and reading of data to the global bit line pair (GBLL, GBLR) are performed by the input / output circuit 1417.

  An outline of the write operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 designated by the address. The local sense amplifier array 1426 amplifies and holds the written data. In the designated local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held by the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.

  An outline of the read operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data of the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the potential difference of the bit line pair of each column as data. Among the data held in local sense amplifier array 1426, data in the column designated by the address is written to the global bit line pair by switch array 1444. Global sense amplifier array 1416 detects and holds data of global bit line pairs. The held data of the global sense amplifier array 1416 is output to the input / output circuit 1417. Thus, the read operation is completed.

  Since the data is rewritten by the charge and discharge of the capacitive element CS1, the number of times of rewriting is not limited in principle in the DOSRAM 1400, and data can be written and read with low energy. In addition, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.

  The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, charge leakage from the capacitive element CS1 can be suppressed. Therefore, the retention time of the DOS RAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data with high frequency, for example, a frame memory used for image processing.

  Since MC-SA array 1420 has a stacked structure, bit lines can be shortened to a length approximately equal to the length of local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacitance of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. From the above reasons, the load driven at the time of access to the DOS RAM 1400 is reduced, and power consumption can be reduced.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

Sixth Embodiment
In this embodiment, an AI system to which the semiconductor device described in the above embodiments is applied will be described with reference to FIG.

  FIG. 27 is a block diagram showing a configuration example of the AI system 4041. The AI system 4041 includes an operation unit 4010, a control unit 4020, and an input / output unit 4030.

  The operation unit 4010 includes an analog operation circuit 4011, a DOSRAM 4012, an NOSRAM 4013, and an FPGA (field programmable array gate) 4014. As the DOSRAM 4012 and the NOSRAM 4013, the DOSRAM 1400 and the NOSRAM 1600 described in the above embodiment can be used. Also, in the FPGA 4014, OS memory is applied to the configuration memory and the register. Here, such an FPGA is called "OS-FPGA".

  The control unit 4020 includes a central processing unit (CPU) 4021, a graphics processing unit (GPU) 4022, a phase locked loop (PLL) 4023, a static random access memory (SRAM) 4024, and a programmable read only memory (PROM) 4025. , A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.

  The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general purpose input / output module 4034, and a communication module 4035.

  The operation unit 4010 can execute learning or inference by a neural network.

  The analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.

  The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog operation circuit 4011 using the OS transistor has an analog memory, and can perform the product-sum operation necessary for learning or inference with low power consumption.

  The DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory for temporarily storing digital data sent from the CPU 4021. The DOSRAM 4012 has a memory cell including an OS transistor and a read out circuit unit including an Si transistor. Since the memory cell and the read out circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.

  Calculations using neural networks may have more than 1000 input data. When the input data is stored in the SRAM, the SRAM has a limited circuit area and a small storage capacity, so the input data can not but be divided and stored. The DOSRAM 4012 can arrange memory cells in a highly integrated manner even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.

  The NOSRAM 4013 is a non-volatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data as compared to other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory) and MRAM (Magnetoresistive Random Access Memory). In addition, unlike the flash memory and the ReRAM, there is no deterioration of the element when writing data, and there is no limit to the number of times data can be written.

  Further, the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data. The NOSRAM 4013 can reduce the memory cell area per bit by storing multi-value data.

  In addition to digital data, the NOSRAM 4013 can store analog data. Therefore, the analog operation circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of peripheral circuits. In the present specification, analog data refers to data having a resolution of 3 bits (eight values) or more. The above-mentioned multi-value data may be included in the analog data.

  Data and parameters used for neural network calculations can be temporarily stored in the NOSRAM 4013. The above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021. However, the NOSRAM 4013 provided internally has higher speed and lower power consumption for the above data and parameters. Can be stored. Further, since the NOSRAM 4013 can make the bit line longer than the DOS RAM 4012, the storage capacity can be increased.

  The FPGA 4014 is an FPGA using an OS transistor. The AI system 4041 uses the FPGA 4014 to perform deep neural networks (DNN), convolutional neural networks (CNN), recursive neural networks (RNN), self-coder, deep Boltzmann machine (DBM), which will be described later in hardware. It is possible to configure connections of neural networks, such as Deep Belief Networks (DBNs). The connection of the above neural network can be implemented at higher speed by configuring it with hardware.

  The FPGA 4014 is an FPGA having an OS transistor. The OS-FPGA can have a smaller memory area than an FPGA configured with an SRAM. Therefore, even if the context switching function is added, the area increase is small. Also, the OS-FPGA can transmit data and parameters at high speed by boosting.

  The AI system 4041 can provide the analog operation circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 on one die (chip). Therefore, the AI system 4041 can execute neural network calculation at high speed and low power consumption. Further, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured by the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

  Note that the arithmetic unit 4010 need not have all the DOS RAM 4012, the NOSRAM 4013, and the FPGA 4014. One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided in accordance with the problem that the AI system 4041 wants to solve.

  The AI system 4041 can perform deep neural network (DNN), convolutional neural network (CNN), recursive neural network (RNN), self-coder, deep Boltzmann machine (DBM), deep belief network ( Operations such as DBN) can be performed. The PROM 4025 can store programs for executing these operations. Also, part or all of these programs may be stored in the NOSRAM 4013.

  Many existing programs that exist as libraries are based on GPU processing. Therefore, the AI system 4041 preferably includes a GPU 4022. Among the product-sum operations used in learning and inference, the AI system 4041 can execute the product-sum operation that is rate-limiting in the operation unit 4010 and can execute the other product-sum operations in the GPU 4022. By doing so, learning and inference can be performed at high speed.

  The power supply circuit 4027 not only generates a low voltage potential for the logic circuit, but also performs potential generation for analog operation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.

  The PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.

  The CPU 4021 and the GPU 4022 preferably have OS memory as a register. By having the OS memory, the CPU 4021 and the GPU 4022 can keep data (logical value) in the OS memory even when the power supply is turned off. As a result, the AI system 4041 can save power.

  The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. The PLL 4023 having an OS memory can hold an analog potential for controlling the oscillation cycle of the clock.

  The AI system 4041 may store data in an external memory such as DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. In addition, the memory controller 4026 is preferably disposed near the CPU 4021 or the GPU 4022. By doing so, it is possible to exchange data at high speed.

  Part or all of the circuits illustrated in the control unit 4020 can be formed over the same die as the computing unit 4010. By doing so, the AI system 4041 can execute neural network calculations at high speed and low power consumption.

  Data used for neural network calculations are often stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.

  Since learning and inference using neural networks often deal with voice and video, the AI system 4041 includes a voice codec 4032 and a video codec 4033. The audio codec 4032 encodes (decodes) and decodes (decodes) audio data, and the video codec 4033 encodes and decodes video data.

  The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, Universal Serial Bus (USB), Inter-Integrated Circuit (I2C), and the like.

  The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 4035.

  The analog operation circuit 4011 may use a multi-level flash memory as an analog memory. However, the flash memory is limited in the number of rewrites. In addition, it is very difficult to form multilevel flash memory by embedding (forming the arithmetic circuit and the memory on the same die).

  In addition, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM is limited in the number of times of rewriting, and there is a problem in storage accuracy. Furthermore, since the element has two terminals, the circuit design that separates writing and reading of data becomes complicated.

  The analog operation circuit 4011 may use an MRAM as an analog memory. However, the MRAM has a low rate of change in resistance, and has problems in storage accuracy.

  In view of the above, it is preferable that the analog arithmetic circuit 4011 use the OS memory as an analog memory.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

Seventh Embodiment
<Example of application of AI system>
In this embodiment, an application example of the AI system described in the above embodiment will be described with reference to FIG.

  FIG. 28A shows an AI system 4041A in which the AI systems 4041 described with reference to FIG. 27 are arranged in parallel to enable transmission and reception of signals between the systems via a bus line.

  An AI system 4041A illustrated in FIG. 28A includes a plurality of AI systems 4041_1 to AI systems 4041 — n (n is a natural number). The AI systems 4041_1 to AI systems 4041 — n are connected to one another via a bus line 4098.

  FIG. 28B is an AI system 4041B in which the AI systems 4041 described in FIG. 27 are arranged in parallel in the same manner as FIG. 28A to enable transmission and reception of signals between systems via a network. is there.

  An AI system 4041B illustrated in FIG. 28B includes a plurality of AI systems 4041_1 to AI systems 4041 — n. The AI systems 4041_1 to AI systems 4041 — n are connected to one another via a network 4099.

  The network 4099 may be provided with a communication module for each of the AI systems 4041_1 to 4041_n to perform communication by wireless or wired communication. The communication module can communicate via the antenna. For example, the Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area), which is the foundation of the World Wide Web (WWW). Communication can be performed by connecting each electronic device to a computer network such as Network) or GAN (Global Area Network). When performing wireless communication, as a communication protocol or communication technology, LTE (Long Term Evolution), GSM (Global System for Mobile Communication (registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000) A communication standard such as W-CDMA (registered trademark) or a specification standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark) can be used.

  With the configurations shown in FIGS. 28A and 28B, analog signals obtained by an external sensor or the like can be processed by separate AI systems. For example, as in biological information, information such as brain waves, pulse, blood pressure, and body temperature may be acquired by various sensors such as brain wave sensors, pulse wave sensors, blood pressure sensors, and temperature sensors, and analog signals may be processed by separate AI systems. it can. By processing or learning signals in each of the separate AI systems, it is possible to reduce the amount of information processing per AI system. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be enhanced. From information obtained by each AI system, it can be expected that changes in complexly changing biological information can be grasped in an integrated manner in an instant.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

Eighth Embodiment
This embodiment mode shows an example of an IC in which the AI system shown in the above embodiment mode is incorporated.

  The AI system described in the above embodiment integrates a digital processing circuit consisting of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, an OS memory such as an OS-FPGA and DOSRAM, NOSRAM, etc. into one die. be able to.

  FIG. 29 shows an example of an IC incorporating an AI system. The AI system IC 7000 shown in FIG. 29 has leads 7001 and a circuit portion 7003. AI system IC 7000 is mounted on, for example, printed circuit board 7002. A plurality of such IC chips are combined and electrically connected on the printed circuit board 7002 to complete a board (mounting board 7004) on which electronic components are mounted. In the circuit portion 7003, the various circuits described in the above embodiment are provided in one die. As described in the above embodiment, the circuit portion 7003 has a stacked structure and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the AI system IC 7000 can be easily miniaturized.

  In FIG. 29, although QFP (Quad Flat Package) is applied to the package of AI system IC7000, the aspect of the package is not limited to this.

  A digital processing circuit such as a CPU, an analog operation circuit using an OS transistor, an OS-FPGA and an OS memory such as DOSRAM or NOSRAM may be formed in the Si transistor layer 7031, the wiring layer 7032 and the OS transistor layer 7033 it can. That is, the elements constituting the above AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment does not need to increase the manufacturing process even if the number of elements is increased, and the above-mentioned AI system can be incorporated at low cost.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments and examples.

(Embodiment 9)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU or a computer. 30 to 32 illustrate specific examples of an electronic device provided with a processor such as a CPU or a GPU, or a computer, according to one embodiment of the present invention.

<Electronic equipment / system>
A processor such as a CPU or a GPU or a computer according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc. In addition to electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, etc. may be mentioned. In addition, by providing the integrated circuit or the computer according to one embodiment of the present invention to an electronic device, artificial intelligence can be mounted on the electronic device.

  The electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion. In addition, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

  The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow, humidity, inclination, vibration, odor or infrared.

  The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided. FIG. 30 shows an example of the electronic device.

[mobile phone]

  FIG. 30A shows a mobile phone (smart phone) which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display portion 5511. A touch panel is provided in the display portion 5511 as an input interface, and a button is provided in the housing 5510.

  The information terminal 5500 can execute an application using artificial intelligence by applying the computer of one embodiment of the present invention. As an application using artificial intelligence, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5511, recognizes characters, figures, and the like input by the user with respect to a touch panel included in the display unit 5511; An application displayed on the display portion 5511, an application for performing biometric authentication such as fingerprint or voiceprint, and the like can be given.

[Information terminal 1]
A desktop information terminal 5300 is illustrated in FIG. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

  The desktop information terminal 5300 can execute an application using artificial intelligence by applying the computer of one embodiment of the present invention, as in the case of the information terminal 5500 described above. Examples of applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. In addition, by using the desktop information terminal 5300, new artificial intelligence can be developed.

  In the above, although the smartphone and the desktop information terminal are illustrated in FIGS. 30A and 30B as the electronic device as an example, an information terminal other than the smartphone and the desktop information terminal may be applied. it can. As an information terminal other than a smart phone and a desktop information terminal, for example, a PDA (Personal Digital Assistant), a notebook information terminal, a work station, etc. may be mentioned.

[Electronics]
FIG. 30C illustrates an electric refrigerator-freezer 5800 which is an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803 and the like.

  By applying the computer of one embodiment of the present invention to the electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 is automatically stored in the electric refrigerator-freezer 5800, which automatically generates a menu based on the food stored in the electric refrigerator-freezer 5800, the expiration date of the food, etc. It can have a function of automatically adjusting to the temperature according to the food.

  In this example, the electric refrigerator-freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Appliances, washing machines, dryers, audiovisual equipment etc. may be mentioned.

[game machine]

  FIG. 30D illustrates a portable game console 5200 which is an example of the game console. The portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.

  By applying the GPU or the computer of one embodiment of the present invention to the portable game device 5200, a low-power consumption portable game device 5200 can be realized. Further, since low power consumption can reduce heat generation from the circuit, it is possible to reduce the influence of heat generation on the circuit itself, peripheral circuits, and modules.

  Furthermore, by applying the GPU or the computer of one embodiment of the present invention to the portable game device 5200, a portable game device 5200 having artificial intelligence can be realized.

  Originally, expressions such as the progress of the game, the behavior and behavior of creatures appearing on the game, and the phenomena occurring on the game are determined by the program possessed by the game, but by applying artificial intelligence to the portable game machine 5200 The expression which is not limited to the program of the game becomes possible. For example, it is possible to express that the contents asked by the player, the progress of the game, the time, and the behavior of the person appearing on the game change.

  In addition, when playing a game that requires a plurality of players in the portable game machine 5200, since the game player can be artificially constructed by artificial intelligence, even by using an opponent as a game player by artificial intelligence, even one person can play a game. I can play the game.

  Although FIG. 30D illustrates a portable game machine as an example of the game machine, a game machine to which the GPU or the computer of one embodiment of the present invention is applied is not limited to this. As a game machine to which the GPU or computer of one aspect of the present invention is applied, for example, a home-use stationary game machine, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a sports facility Pitching machines for batting practice.

[Mobile body]
The GPU or computer of one embodiment of the present invention can be applied to an automobile that is a mobile body and around the driver's seat of the automobile.

  FIG. 30 (E1) shows a car 5700 which is an example of a moving object, and FIG. 30 (E2) shows a periphery of a windshield in a room of the car. FIG. 30E1 illustrates the display panel 5704 attached to the pillar, in addition to the display panel 5701 attached to the dashboard, the display panel 5702, and the display panel 5703.

  The display panel 5701 to the display panel 5703 can provide various other information such as a speedometer, a tachometer, a travel distance, a refueling amount, a gear state, setting of an air conditioner, and the like. In addition, display items, layouts, and the like displayed on the display panel can be appropriately changed in accordance with the user's preference, and design can be enhanced. The display panels 5701 to 5703 can also be used as lighting devices.

  By projecting an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, it is possible to complement the view (dead angle) blocked by the pillar. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated to enhance safety. In addition, by displaying an image that complements the invisible part, it is possible to check the safety more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

  Since the GPU or computer of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the computer can be used for an autonomous driving system of a car 5700. Further, the computer can be used for a system that performs road guidance, danger prediction, and the like. Information such as road guidance and danger prediction may be displayed on the display panel 5701 to the display panel 5704.

  In addition, although the motor vehicle is demonstrated as an example of a mobile body in the above-mentioned, a mobile body is not limited to a motor vehicle. For example, the moving object may also be a train, a monorail, a ship, a flying object (helicopter, unmanned aircraft (drone), airplane, rocket) or the like, and the computer of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be provided.

[Broadcasting system]
The GPU or computer of one embodiment of the present invention can be applied to a broadcast system.

  FIG. 30F schematically shows data transmission in the broadcast system. Specifically, FIG. 30F shows a path until the radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches the television receiver (TV) 5600 of each home. The TV 5600 includes a receiver (not shown), and a broadcast signal received by the antenna 5650 is transmitted to the TV 5600 through the receiver.

  In FIG. 30F, the antenna 5650 is a UHF (Ultra High Frequency) antenna. However, as the antenna 5650, a BS · 110 ° CS antenna, a CS antenna, or the like can be used.

  The radio wave 5675A and the radio wave 5675B are broadcast signals for ground wave broadcasting, and the radio wave tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. Each household can view terrestrial TV broadcast on the TV 5600 by receiving the radio wave 5675 B by the antenna 5650. The broadcast system is not limited to the terrestrial broadcast shown in FIG. 30F, and may be satellite broadcast using an artificial satellite, data broadcast by an optical line, or the like.

  The broadcast system described above may be a broadcast system using artificial intelligence by applying the computer of one embodiment of the present invention. When broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each home, compression of the broadcast data is performed by the encoder, and when the antenna 5650 receives the broadcast data, the decoder of the receiving apparatus included in the TV 5600 Restoration is performed. By utilizing artificial intelligence, for example, in motion compensation prediction which is one of compression methods of an encoder, it is possible to recognize a display pattern included in a display image. In addition, intra-frame prediction using artificial intelligence can also be performed. In addition, for example, when broadcast data with low resolution is received and the broadcast data is displayed by the TV 5600 with high resolution, image interpolation processing such as up conversion can be performed in restoration of broadcast data by the decoder.

  The above-described broadcast system using artificial intelligence is suitable for ultra high definition television (UHDTV: 4K, 8K) broadcast where the amount of broadcast data is increased.

  In addition, as an application of artificial intelligence on the TV 5600 side, for example, the TV 5600 may be provided with a recording device having artificial intelligence. With such a configuration, it is possible to automatically record a program according to the user's preference by making the recording device learn the user's preference to the artificial intelligence.

<Parallel computer>
A parallel computer can be configured by clustering a plurality of computers of one embodiment of the present invention.

  A large parallel computer 5400 is shown in FIG. 31 (A). In the parallel computer 5400, a plurality of rack mount computers 5420 are stored in the rack 5410.

  The calculator 5420 can have a configuration of a perspective view illustrated in FIG. 31B, for example. In FIG. 31B, a calculator 5420 includes a motherboard 5430, and the motherboard includes a plurality of slots 5431, a plurality of connection terminals 5432, and a plurality of connection terminals 5433. The PC card 5421 is inserted in the slot 5431. In addition, the PC card 5421 has a connection terminal 5423, a connection terminal 5424, and a connection terminal 5425, which are connected to the mother board 5430, respectively.

  The PC card 5421 is the processing board provided with the CPU, the GPU, the storage device, and the like described in the first embodiment. For example, in FIG. 31C, the PC card 5421 has a board 5422, and the board 5422 includes a connection terminal 5423, a connection terminal 5424, a connection terminal 5425, a chip 5426, a chip 5427, and a connection terminal 5428, Shows a configuration having 31C illustrates chips other than the chips 5426 and 5427, the description of the chips 5426 and 5427 described below is referred to for those chips.

  The connection terminal 5428 has a shape that can be inserted into the slot 5431 of the motherboard 5430, and the connection terminal 5428 functions as an interface for connecting the PC card 5421 and the motherboard 5430. Examples of the standard of the connection terminal 5428 include PCIe and the like.

  The connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 can be, for example, an interface for supplying power, inputting a signal, or the like to the PC card 5421. Also, for example, an interface for outputting a signal calculated by the PC card 5421 can be used. Examples of the respective standards of the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). Further, in the case of outputting a video signal from the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425, examples of the respective standards include HDMI (registered trademark).

  The chip 5426 has a terminal (not shown) for inputting and outputting signals, and the chip 5426 and the PC card 5421 can be inserted by inserting the terminal into a socket (not shown) of the PC card 5421. Can be connected electrically. The chip 5426 can be, for example, the GPU 12 described in the above embodiment.

  The chip 5427 has a plurality of terminals, and the terminals are electrically connected to the PC card 5421 by, for example, performing reflow soldering to the wiring of the PC card 5421. can do. As the chip 5427, for example, a memory device, a field programmable gate array (FPGA), a CPU, or the like can be given.

  By applying the computer of one embodiment of the present invention to the computer 5420 of the parallel computer 5400 illustrated in FIG. 31A, large-scale calculations necessary for, for example, learning and reasoning of artificial intelligence can be performed.

<Server and System Including Server>
The computer of one embodiment of the present invention can be applied to, for example, a server that functions over a network. Moreover, thereby, the system containing the said server can be comprised.

  FIG. 32A schematically shows, as an example, communication between server 5100 to which the computer of one embodiment of the present invention is applied, and information terminal 5500 and desktop information terminal 5300 described above. Is shown. In FIG. 32A, the communication 5110 is illustrated as the communication is performed.

  By configuring such a form, the user can access the server 5100 from the information terminal 5500, the desktop information terminal 5300, and the like. Then, the user can receive the service provided by the administrator of the server 5100 through the communication 5110 via the Internet. Such services include, for example, electronic mail, social networking services (SNS), online software, cloud storage, navigation systems, translation systems, internet games, online shopping, financial transactions such as stocks / forex / credits, public facilities / commercial facilities・ Reservation of accommodation facilities and hospitals, watching of videos such as Internet programs, lectures and lectures, etc.

  In particular, by applying the computer of one embodiment of the present invention to the server 5100, artificial intelligence may be able to be used in the above-described service. For example, by introducing artificial intelligence to a navigation system, the system may be able to adaptively guide to a destination according to the congestion of roads, train operation information, and the like. Also, for example, by introducing artificial intelligence into a translation system, the system may be able to appropriately translate unique expressions such as dialects and slang. In addition, for example, by using artificial intelligence for a reservation system such as a hospital, the system may be able to introduce an appropriate hospital, a doctor's office, etc. judging from the user's symptoms and degree of injury etc. is there.

  When the user wants to develop artificial intelligence, the server 5100 can be accessed via the Internet, and the development can be performed on the server 5100. This is suitable when, for example, the information terminal 5500 and the desktop information terminal 5300 at hand of the user do not have sufficient processing capability, and the development terminal can not be constructed with the information terminal 5500 and the desktop information terminal 5300.

  32A shows an example of a system including an information terminal and a server 5100 as a system including a server, but as another example, the system includes an electronic device other than the information terminal and the server 5100 System may be used. That is, the electronic device may be connected to the Internet in the form of Internet of Things (IoT).

  32B schematically shows, as an example, communication between the electronic device (electric refrigerator-freezer 5800, portable game machine 5200, car 5700, TV 5600) described in FIG. 30 and the server 5100. There is. In FIG. 32B, the communication 5110 is illustrated as the communication is performed.

  When artificial intelligence is applied to each of the electronic devices described with reference to FIG. 30, as shown in FIG. 32B, the server 5100 can execute calculations necessary to operate the artificial intelligence. For example, input data required for calculation is transmitted from one of the electronic devices to the server 5100 by the communication 5110, and artificial intelligence of the server 5100 is used to calculate output data based on the input data. The output data is transmitted from the server 5100 to one of the electronic devices by the communication 5110. Thus, one of the electronic devices can perform an operation based on the data output from the artificial intelligence.

  The electronic device illustrated in FIG. 32B is an example, and an electronic device not illustrated in FIG. 32B may be connected to the server 5100 to perform communication with each other as described above.

  The electronic device described in this embodiment, the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be combined with the description of other electronic devices as appropriate.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

100 capacitive element 100a capacitive element 100b capacitive element 110 conductor 112 conductor 130 conductor 130 insulator 140 insulator 150 insulator 160 conductor 200 transistor 200a transistor 200b transistor 203 conductor 203a conductor 203b conductor 205 conductor 205a conduction Body 205b conductor 210 insulator 212 insulator 214 insulator 216 insulator 218 conductor 220 insulator 222 insulator 224 insulator 230 oxide 230a oxide 230A oxide film 230b oxide 230B oxide film 230c oxide 230C oxide film 231 Region 231a Region 231b Region 234 Region 239 Region 240 Conductor 240a Conductor 240A Conductor Film 240b Conductor 242 Conductor 242a Conductor 242A Conductor Film 242b Conductor 242B Conductor 244 insulator 244A insulator 245 opening 246 conductor 246A conductor 248 conductor 250 insulator 250A insulator 250C insulator 260 conductor 260a conductor 260A conductor film 260b conductor 260B conductor film 272 insulator 272A insulator 273 insulator 273A insulator 274 insulator 280 insulator 281 insulator 282 insulator 284 insulator 290 opening 300 transistor 311 substrate 313 semiconductor region 314 a low resistance region 314 b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 conductor 350 insulator 352 insulator 356 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 conductor 370 insulator 372 insulator 374 insulator 376 Current collector 380 Insulator 382 Insulator 384 Insulator 386 Conductor 400 Insulator 412 Insulator 414 Insulator 416 Insulator 416 Insulator 420 Insulator 422 Insulator 422 Insulator 424 Insulator 428 Insulator 444 Insulator 480 Insulator 484 Insulator 500 Transistor 600 cell 601 cell 1001 wiring 1002 wiring 1003 wiring 1004 wiring 1005 wiring 1005 wiring 1400 DOSRAM
1405 controller 1410 row circuit 1411 decoder 1412 word line driver circuit 1413 column selector 1414 sense amplifier driver circuit 1415 column circuit 1416 global sense amplifier array 1417 input / output circuit 1420 sense amplifier array 1422 memory cell array 1423 sense amplifier array 1425 local memory cell array 1426 local sense Amplifier array 1444 Switch array 1445 Memory cell 1445a Memory cell 1445b Memory cell 1446 Sense amplifier 1447 Global sense amplifier 1600 NOSRAM
1610 memory cell array 1611 memory cell 1612 memory cell 1613 memory cell 1614 memory cell 1615 memory cell 1615 a memory cell 1615 b memory cell 1640 controller 1650 row driver 1651 row decoder 1652 word line driver 1660 column driver 1661 column decoder 1661 driver 1663 DAC
1670 output driver 1671 selector 1672 ADC
1673 Output buffer 2000 CDMA
4010 arithmetic unit 4011 analog arithmetic circuit 4012 DOSRAM
4013 NOSRAM
4014 FPGA
4020 control unit 4021 CPU
4022 GPU
4023 PLL
4025 PROM
4026 Memory controller 4027 Power supply circuit 4028 PMU
4030 I / O unit 4031 external storage control circuit 4032 audio codec 4033 video codec 4034 general-purpose input / output module 4035 communication module 4041 AI system 4041A AI system 4041B AI system 4098 bus line 4099 network 5100 server 5110 communication 5200 portable game console 5201 display 5202 display Section 5203 Button 5300 Desktop type information terminal 5301 Main unit 5302 Display 5303 Keyboard 5400 Keyboard 5410 Rack 5420 Computer 5421 PC card 5422 Connection terminal 5424 Connection terminal 5425 Connection terminal 5426 Chip 5427 Chip 5428 Connection terminal 5430 Mother board 5431 Slot 5432 Connection terminal 5433 Connection terminal 550 Information terminal 5510 housing 5511 display unit 5600 TV
5650 antenna 5670 radio wave tower 5675A radio wave 5675B radio wave 5680 broadcast station 5700 display panel 5702 display panel 5703 display panel 5704 display panel 5800 electric refrigerator-freezer 5801 housing 5802 refrigerator compartment door 5803 freezer compartment door 7000 AI system IC
7001 lead 7002 printed circuit board 7003 circuit portion 7004 mounting substrate 7031 Si transistor layer 7032 wiring layer 7033 OS transistor layer

Claims (10)

A first insulator,
An oxide on the first insulator;
A first conductor on the oxide, and a second conductor;
A third conductor on the oxide,
A second insulator disposed between the oxide and the third conductor and covering the side surface of the third conductor;
A third in contact with the side surface of the second insulator and covering the upper surface and the side surface of the first conductor, the upper surface and the side surface of the second conductor, and the side surface of the oxide With insulators,
A fourth insulator on the third insulator;
A fifth insulator in contact with the top surface of the second insulator and covering the third conductor;
Have
The third insulator has an opening exposing the first insulator,
The semiconductor device, wherein the fourth insulator is in contact with the first insulator through the opening. A first insulator,
A first oxide having a first opening on the first insulator;
A second oxide on the first oxide;
A first conductor on the second oxide, and a second conductor;
A third conductor on the oxide,
A second insulator disposed between the oxide and the third conductor and covering the side surface of the third conductor;
In contact with the side surface of the second insulator, the upper surface and side surface of the first conductor, the upper surface and side surface of the second conductor, the side surface of the first oxide, and A third insulator covering the oxide side of 2;
A fourth insulator on the third insulator;
A fifth insulator in contact with the top surface of the second insulator and covering the third conductor;
Have
The second oxide is in contact with the first insulator through the first opening,
The third insulator has a second opening that exposes the first insulator,
The semiconductor device characterized in that the fourth insulator is in contact with the first insulator via the second opening. In claim 1,
The oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
A semiconductor device characterized by In claim 2,
The first oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
The second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
A semiconductor device characterized by In any one of claims 1 to 4,
The semiconductor device characterized in that the second insulator is an oxide containing one or both of aluminum and hafnium. In any one of claims 1 to 5,
The semiconductor device characterized in that the third insulator is an oxide containing one or both of aluminum and hafnium. In any one of claims 1 to 6,
The semiconductor device characterized in that the fifth insulator is an oxide containing one or both of aluminum and hafnium. In any one of claims 1 to 7,
The semiconductor device further includes a sixth insulator,
The semiconductor device according to claim 6, wherein the sixth insulator is provided between the third conductor and the second insulator. In any one of claims 1 to 8,
The first conductor and the second conductor are each independently aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, 20. A semiconductor device comprising at least one of magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum. In any one of claims 1 to 9,
The first conductor and the second conductor are each independently tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, strontium 20. A semiconductor device comprising: at least one of an oxide containing ruthenium and an oxide containing lanthanum and nickel.

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