JP7027193B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine that plays a game.

As a gaming machine, a gaming medium such as a gaming ball is launched into the gaming area by a launching device, and when the gaming medium wins a prize in a starting winning area such as a winning opening provided in the gaming area, a variable display of a plurality of types of identification information is displayed. There is a pachinko gaming machine in which a predetermined number of bets is stored, and a slot machine in which a plurality of types of identification information (for example, a symbol) are variably displayed when a start operation is performed. In a gaming machine configured to be able to execute variable display of identification information in this way, when the display result of variable display of identification information becomes a predetermined display result in the variable display unit, a predetermined game value (for example, a jackpot) Some are configured to give the player a transition to a state, etc.).

As such a gaming machine, there is known a gaming machine that initializes a plurality of storage areas by sequentially storing clear data having a fixed value in the storage area while updating the address of the storage area (). For example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2016-154726

By the way, in the gaming machine of Patent Document 1, a plurality of storage areas are initialized by repeating the same process while updating the address, but for some reason, data different from the original data is read out as clear data. In that case, the storage area may be initialized by unintended data.

The present invention has been made by paying attention to such a problem, and an object of the present invention is to provide a gaming machine capable of preventing unintended data from being stored in a storage area and initializing the storage area. ..

In order to solve the above problems, the gaming machine of the present invention
A gaming machine (for example, gaming machine 1) that plays a predetermined game.
A storage means (for example, RAM) for storing control-related data in a plurality of storage areas,
It is provided with an initialization means (for example, RAM clear processing shown in FIG. 2) that initializes the plurality of storage areas according to the satisfied predetermined conditions so as to be common initial data when the predetermined conditions are satisfied. ,
The initialization means is
In initializing one of the plurality of storage areas, the initial data is stored in a specific register , and the initial data stored in the specific register is written to the one storage area . Initialize the storage area (for example, the part where the processing of Sa6 and Sa7 in FIG. 2 is performed).
In initializing the other storage areas of the plurality of storage areas in succession to the one storage area, the initial data is stored again in the specific register , and the initial data stored in the specific register is stored in the specific register. Initialize the other storage area by writing to the other storage area (for example, the portion where the processing of Sa6 and Sa7 in FIG. 2 is performed).
The gaming machine is
A first instruction executing means for executing a first instruction for storing data indicated by an argument in a storage area indicated by a predetermined address, and
Further provided with a second instruction executing means for executing a second instruction for storing data of a specific register in a storage area indicated by a predetermined address.
The initialization means stores the created initial data in the specific register, and initializes the storage area by the second instruction.
According to this configuration, it is possible to prevent unintended data from being stored in the storage area and initializing the storage area.

A first instruction executing means for executing a first instruction for storing data stored by using an argument in a storage area indicated by a predetermined address, and a first instruction executing means.
A second instruction executing means for executing a second instruction for storing data of a specific register in a storage area indicated by a predetermined address is provided.
The program capacity used to execute the second instruction is smaller than that used to execute the first instruction.
The initialization means stores the initial data created for initializing the storage area in the specific register by executing the second instruction, and initializes the storage area using the initial data stored in the specific register. According to this, the program capacity for initializing a plurality of storage areas can be reduced.

When the storage area is initialized by executing the second instruction, the initialization means re-stores the initial data in the specific register each time the storage area is initialized by executing the second instruction.
The storage area is initialized using the initial data stored in the specific register again (for example, the portion where the processing of Sa6 in FIG. 2 is performed).
According to this configuration, it is possible to prevent unintended data from being stored in the storage area and initializing the storage area.

Initialization means
A plurality of storage areas in which a plurality of data of the first type are stored are initialized at the first trigger in the progress of the game, and a plurality of data of the second type are stored at the second trigger in the progress of the game. Initialize the storage area and
A plurality of storage areas are initialized by performing a common process between the first trigger and the second trigger (for example, the RAM clear process shown in FIG. 2).
According to this configuration, the program capacity for initializing a plurality of storage areas can be reduced.

The initialization means includes an address specifying means for specifying the address of the storage area to be initialized while updating the address of the read location in the address storage table that stores the addresses of the plurality of storage areas (for example, the process of Sa2 in FIG. 2). The part to do).
According to this configuration, a process for initializing a plurality of storage areas can be suitably executed.

The address specifying means initially initializes the address (for example, N) by starting the update of the address (for example, Nn) from the address immediately before the address (for example, N) which is the first read location in the address storage table. Specify the address of the area (for example, Sa2 in FIG. 2)
The part that processes).
According to this configuration, the iterative treatment can be suitably diverted.

It is a figure which shows the gaming machine which concerns on this embodiment. It is a flowchart of a RAM clear process executed by a gaming machine. It is explanatory drawing of the address used for storing the clear data and the control data other than the clear data when a bonus is won. It is explanatory drawing which shows an example of the address map in RAM.

[Composition of gaming machines]
FIG. 1 is a diagram showing a gaming machine 1 according to the present embodiment. As shown in FIG. 1, the gaming machine 1 according to the present embodiment includes a liquid crystal display 51 for displaying an image and speakers 53 and 54 for outputting sounds such as music and production sounds.

The gaming machine 1 includes a microcomputer for gaming control. The game control microcomputer includes a CPU that performs control operations according to a program, a ROM that stores a game progress control program, and a RAM as a storage means that is used as a work memory.

[About RAM]
The RAM is provided with a plurality of storage areas for storing various control data such as data related to game control, and is used as a work area when executing game control. The RAM can back up data related to control indicating a game state before the power supply is stopped when the power supply is stopped.

[About RAM clear processing (initialization processing)]
The RAM clear process (initialization process) is executed when a predetermined condition is satisfied. The predetermined conditions are, for example, that the clear switch has been turned on, that the power has been turned on, that an error has occurred, that the advantageous state has started, that the advantageous state has ended, that the unit game has ended, and the like. .. The RAM clearing process is a process of initializing a plurality of storage areas in the RAM according to a predetermined condition to be returned to the initial value state. A plurality of storage areas are provided in the RAM, and an address is assigned to each of the storage areas. The address indicates the location of one storage area in the RAM. The addresses allocated to the plurality of storage areas are stored in the address storage table stored in the RAM.
In the RAM clear process, each of a plurality of addresses (storage areas) to be initialized is one.
By storing common clear data (00H) which is an initial value (fixed value), a plurality of storage areas are returned to the initial value state. In this way, the clear data (00), which is the initial value for the address.
The process of storing H) is called initialization. In this embodiment, the storage area may be referred to as an address. At the time of initialization, not the clear data (00H), but
Data other than the initial value, which is not used in normal games, may be stored in the address.

In the RAM clear process, when initializing a plurality of storage areas so that they become common clear data (00h), clear data is used when initializing the storage area (one address) of one of the plurality of addresses. In creating (00h), storing the created clear data (00h) in one address, initializing one address, and initializing another storage area (one address) in succession to one address. Clear data (00h) is created again, the created clear data (00h) is stored in an address different from that address, and another address is initialized. As a result, the clear data (00H) common to the plurality of storage areas is sequentially stored, and each storage area is sequentially initialized. In the RAM clear processing of this embodiment,
In addition to storing clear data (00H) at a plurality of addresses in the RAM, control data other than the clear data may be stored in a predetermined storage area according to a predetermined condition that is satisfied.

When initializing multiple addresses in sequence as described above, the process of creating clear data is not performed, and the same process of reading the clear data originally created and storing it in the address is passed each time. If the clear data having an initial value different from the clear data that should be originally stored is read for some reason, the address may be initialized by the unintended clear data. However, as described above, by creating clear data and storing the clear data at one address, and then re-creating and storing the same clear data when storing the clear data at another address, It is possible to prevent unintended clear data from being stored at the initialized address.

Here, the storage area of one of the plurality of storage areas and the other storage areas are in the order of the Nth address (N is an integer) and the N + nth address (n is an integer). The storage area of one of the plurality of storage areas and the other storage areas may be in a continuous order or a discontinuous order. For example, if one storage area is the first address, the other storage area may be the second address, or if one storage area is the first address, the other storage area is 5. It may be related to the second address. Further, as for one storage area and the other storage area of a plurality of storage areas, an area in which a plurality of addresses are grouped is regarded as one storage area, and another area in which a plurality of addresses are grouped is referred to as another storage area. It may be a relationship. Specifically, when one storage area is the first to third address, the other storage area may be the fourth to sixth address. Further, when one storage area is the first to third addresses, the other storage areas may be the seventh to ninth addresses.
It should be noted that one storage area includes a plurality of areas and the other storage area is one area, or one storage area is one area and the other storage area includes a plurality of areas. You may.

[About RAM clear processing]
Next, the RAM clearing process of the present embodiment will be described with reference to FIG. The CPU executes the RAM clear process when a predetermined condition is satisfied.

As shown in FIG. 2, in the RAM clearing process, the CPU first sets the number of initializations for initializing the address according to a predetermined condition that is satisfied, and registers the number of times the data is set, which is the number of times the control data is stored. Set to (Sa1). The number of data settings is the total number of times the clear data is stored in the address (that is, the number of initializations) and the number of times control data other than the clear data is stored in the predetermined address according to the established predetermined conditions. be.

Next, the read address is specified by updating the address to be read (“read address” in the figure) in the address storage table (Sa2). Specifically, N + n is set in N. When the address is initialized for the first time, the address Nn immediately before the first address is set in N, so the update is started from the address Nn one before and N + n in N. When is set, the first address N is specified at first. Thereby, the repetitive treatment can be suitably diverted.

Next, the read address specified from the address storage table is set in the register as the write address of the control data (Sa3). Next, it is determined whether or not the number of initializations of the address set in the process of Sa1 has reached "0" (Sa4).

If the number of address initializations is not "0", the number of address initializations is subtracted "1" (Sa5). Then, the fixed value clear data (00H) is stored in the specific register (A register) (Sa6). Next, the control data stored in the specific register (A register) is stored in the write address (Sa7). Specifically, the clear data (00H) stored in the specific register (A register) is stored in the write address set in Sa3.

On the other hand, when the number of times the address is initialized becomes "0", the read address is specified by updating the read address in the address storage table (Sa10). Then, the control data is read from the specified read address, and the read control data is stored in the specific register (A register) (Sa11). Next, the control data stored in the specific register (A register) is stored in the write address (Sa7). Specifically, the control data stored in the specific register (A register) in Sa11 is stored in the write address set in Sa3. That is, after the number of times the address is initialized becomes "0", the control data stored in the address different from the write address is read, and the process for storing this in the write address is performed. For example, the process of reading the control data stored in the fifth write address from the sixth read address and storing it in the fifth write address is performed.

When the processing of Sa7 is completed, the number of data settings set in Sa1 is subtracted "1" times (
Sa8). Next, it is determined whether or not the number of times of data setting has reached "0" (Sa9). If the number of data settings is not "0", the process returns to the Sa2 step. When the number of data settings reaches "0", the process ends.

Here, the gaming machine 1 has an argument (1 byte numerical value, 0h) to the address indicated by the predetermined address.
The first instruction for storing the data stored by) and the second instruction for storing the data of the specific register (A register) at the address indicated by the predetermined address can be executed. Since no argument is required, the program capacity of the program used for executing the second instruction is smaller than that of the program used for executing the first instruction. Therefore, in the RAM clear processing of the present embodiment, the plurality of addresses are initialized by storing the clear data (00h) in the plurality of addresses by executing the second instruction. As a result, the program capacity for initializing a plurality of addresses can be reduced.

Further, in the RAM clear processing of the present embodiment, by performing the processing of Sa6 in FIG. 2, the data of the specific register (A register) is cleared every time the address is initialized by the execution of the second instruction (00h). Restore in and initialize multiple storage areas. This will result in
It is possible to prevent unintended data from being stored in the address and initializing the address.

Further, in the RAM clear processing of the present embodiment, a plurality of addresses in which a plurality of data of the first type are stored are initialized at the first trigger in the progress of the game, and the second type is initialized at the second trigger in the progress of the game. The plurality of addresses in which the plurality of data are stored are initialized, and the plurality of addresses are initialized by performing the common RAM clear processing shown in FIG. 2 at the first trigger and the second trigger. As a result, the program capacity for initializing a plurality of storage areas can be reduced. The first and second triggers are, for example, when the advantageous state starts, when the advantageous state ends, and when the unit game ends.

[Specific examples when performing RAM clear processing]
Next, a specific example of performing the RAM clearing process will be described with reference to FIGS. 3 and 4. 3 and 4 show an example in which the gaming machine 1 is assumed to be a slot machine and the RAM clear processing is executed when a bonus is won.

FIG. 3 shows an address used to store clear data (00h) and control data other than clear data when a bonus is won. In addition, "1" to "7" indicate the order specified as a reading place. FIG. 4 shows an example of an address map of addresses used when a bonus is won in RAM.

When the bonus is won, the storage address of the number of inter-bonus games (upper) and the storage address of the number of inter-bonus games (lower) where control data that can specify the number of games between bonuses is stored, ART (assist replay time) The storage address of the ART entry flag that stores the control data that can be specified to be controlled, the storage address of the next main state that stores the control data that can specify the game state of the next game, and the game state of the next game are bonuses. Address, RB (
RB that stores control data that can specify the number of times a prize has occurred during (regular bonus)
The storage address of the middle prize count counter and the address where the initial value of the RB middle prize count, which is control data capable of specifying the initial value of the number of times a prize has occurred in the RB, are used are used. note that,
Less than,

Then, as shown in FIG. 4, for example, a storage address for the number of inter-bonus games (upper) is assigned to the area of the address F010H. A storage address for the number of inter-bonus games (lower) is assigned to the area of the address F020H. The storage address of the ART entry flag is assigned to the area of the address F035H. The storage address of the next main state is assigned to the area of the address F045H. An address in which the specified value during the bonus is stored is assigned to the area of the address F046H. Address F060
The storage address of the winning number counter in RB is assigned to the area of H. Address F
An address in which the initial value of the number of winnings during RB is stored is assigned to the area of 061H.

When the RAM clear process of FIG. 2 is executed at the time of winning a bonus in the configurations of FIGS. 3 and 4, first, the number of initializations is set to 3 and the number of data settings is set to 5 (see Sa1 in FIG. 2).
.. Specifically, the addresses shown in "1" to "3" in FIG. 3 are initialized, the control data shown in "5" is stored in the address shown in "4", and "6" is stored in the address shown in "6". The control data shown in "7" is stored. Then, when the addresses shown in "1" to "3" are sequentially initialized, the number of initializations becomes three, so that the number of initializations is set to three. Further, when the control data to the addresses shown in "4" and "6" are sequentially stored in this, the number of times of data setting becomes 2 times, and the number of times of initialization is 3 times in total, and the number of times of data setting is 5 times. Is set to.

Next, the read address is updated in the address storage table, and the address F010H at the read location is specified (see Sa2 in FIG. 2). Further, the specified address is set as a write address (see Sa3 in FIG. 2). Then, the number of initializations is subtracted once (see Sa5 in FIG. 2), and fixed value clear data (00H) is created and stored in a specific register (A register) (see Sa6 in FIG. 2). The clear data (00H) stored in the specific register (A register) is stored in the storage address of the number of bonus games (upper) of the address F010H (see Sa7 in FIG. 2). Then, the number of times the data is set is subtracted once (see Sa9 in FIG. 2). When the initialization of the storage address of the number of games between bonuses (upper) of the address F010H is completed, the remaining number of initializations is 2 and the remaining number of data settings is 4.
It will be times.

Next, the read address is updated in the address storage table, and the address F020H of the read location is specified (see Sa2 in FIG. 2). Further, the specified address is set as a write address (see Sa3 in FIG. 2). Then, the number of initializations is subtracted once (see Sa5 in FIG. 2), and the fixed value clear data (00H) is recreated and stored in the specific register (A register) (see Sa6 in FIG. 2). The clear data (00H) stored in the specific register (A register) is the number of games between bonuses at address F020H (lower).
It is stored in the storage address of (see Sa7 in FIG. 2). Then, the number of times the data is set is subtracted once (see Sa9 in FIG. 2). When the initialization of the storage address of the number of games (lower) between bonuses of the address F020H is completed, the remaining number of initializations is 1 and the remaining number of data settings is 3.

Next, the read address is updated in the address storage table, and the address F035H at the read location is specified (see Sa2 in FIG. 2). Further, the specified address is set as a write address (see Sa3 in FIG. 2). Then, the number of initializations is subtracted once (see Sa5 in FIG. 2), and the fixed value clear data (00H) is recreated and stored in the specific register (A register) (see Sa6 in FIG. 2). The clear data (00H) stored in the specific register (A register) is stored in the storage address of the ART entry flag of the address F035H (see Sa7 in FIG. 2). Then, the number of times the data is set is subtracted once (see Sa9 in FIG. 2). When the initialization of the storage address of the ART entry flag of the address F035H is completed, the remaining number of initializations is 0, and the remaining number of data settings is 2.

By the above processing, the storage address of the number of bonus games (upper) of the address F010H, the storage address of the number of bonus games (lower) of the address F020H, and the address F035.
In the area of H, the initialization of the storage address of the ART entry flag is completed.

Next, the read address is updated in the address storage table, and the address F045H at the read location is specified (see Sa2 in FIG. 2). Further, the specified address is set as a write address (see Sa3 in FIG. 2). Then, the read address is further updated in the address storage table, and the address F046H of the read location is specified (see Sa10 in FIG. 2). After that, the specified value in the bonus stored in the address F046H is stored in the specific register (A register) (see Sa11 in FIG. 2). The specified value in the bonus stored in the specific register (A register) is stored in the storage address of the next main state of the address F045H set as the write address (see Sa7 in FIG. 2). Then, the number of times the data is set is subtracted once (see Sa9 in FIG. 2). Address F045
When the process for storing the specified value in the bonus of the address F046H is completed at the storage address in the next main state of H, the remaining number of data setting times becomes one.

Next, the read address is updated in the address storage table, and the address F060H of the read location is specified (see Sa2 in FIG. 2). Further, the specified address is set as a write address (see Sa3 in FIG. 2). Then, the read address is further updated in the address storage table, and the address F061H of the read location is specified (see Sa10 in FIG. 2). After that, the initial value of the number of winnings in the RB of the address F061H is stored in the specific register (A register) (see Sa11 in FIG. 2). The initial value of the number of winnings in RB stored in the specific register (A register) is stored in the storage address of the number of winnings in RB counter set as the write address (see Sa7 in FIG. 2). Then, the number of times the data is set is subtracted once (see Sa9 in FIG. 2). Address F06
When the process for storing the initial value of the RB winning count of the address F061H is completed in the storage address of the RB winning count counter of 0H, the remaining number of data setting times becomes 0.

As a result, the address initialization process and the control data storage process at the time of bonus winning are completed.

[Effect of this embodiment]
In the present embodiment, a plurality of addresses are initialized to be common clear data (00h), and when initializing one of the plurality of addresses, clear data (00h) is created and the clear data is created. In initializing the one address using the data (00h) and initializing the other addresses in succession to the one address, the clear data (00h) is recreated and the clear data (00h) is used. Initialize the address (in this example, Figure 2)
The part that processes Sa6 and Sa7).
Therefore, it is possible to prevent unintended data from being stored in the address and initializing the address.

In the present embodiment, it is possible to execute a first instruction for storing data stored in an address indicated by a predetermined address using an argument and a second instruction for storing data in a specific register at the address indicated by the predetermined address. The program used to execute the second instruction has a smaller program capacity than the program used to execute the first instruction, and the clear data (00h) created when initializing the address is stored in the specific register by executing the second instruction. The address is initialized using the clear data (00h) stored in the specific register.
Therefore, the program capacity for initializing a plurality of addresses can be reduced.

In the present embodiment, when the address is initialized by the execution of the second instruction, the clear data (00h) is re-stored in the specific register each time the address is initialized by the execution of the second instruction, and is stored in the specific register. The address is initialized using the cleared clear data (00h) (in this example, the part where the processing of Sa6 in FIG. 2 is performed).
Therefore, it is possible to prevent unintended data from being stored in the address and initializing the address.

In the present embodiment, a plurality of addresses in which a plurality of data of the first type are stored are initialized at the first trigger in the progress of the game (in this example, at the time of winning a bonus), and the second trigger in the progress of the game is performed. (In this example, at the end of the unit game), the plurality of addresses in which the second type of data are stored are initialized, and the processing common to the first and second triggers (in this example, RA in FIG. 2).
Initialize a plurality of addresses by performing M clear processing).
Therefore, the program capacity for initializing a plurality of addresses can be reduced.

In the present embodiment, in the address storage table that stores a plurality of addresses, the address to be initialized while updating the address of the read location is specified (in this example, S in FIG. 2).
The part where the processing of a2 is performed).
Therefore, it is possible to preferably execute the process for initializing a plurality of addresses.

In the present embodiment, the address to be initialized first is specified by starting the update of the address from the address immediately before the address to be the first read location in the address storage table (in this example, FIG. 2). The part where the processing of Sa2 is performed).
According to this configuration, the iterative treatment can be suitably diverted.

[Modification example]
Although the main embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications and applications are possible. Hereinafter, a modified example of the above embodiment applicable to the present invention will be described.

[About pachinko machines]
The above-mentioned gaming machine 1 is provided with a plurality of variable display units capable of variablely displaying a plurality of types of identification information that can be identified by each, and after variable display of the variable display unit, display is performed by stopping the variable display of the variable display unit. It may be a slot machine capable of deriving a result and generating a prize according to a display result combination which is a combination of display results of a plurality of variable display units. The above-mentioned gaming machine 1 may be a pachinko gaming machine that can be controlled to a jackpot gaming state that is advantageous to the player according to the result of variable display of a plurality of types of identification information that can be identified by each.

[About RAM clear processing]
In the above embodiment, an example in which the RAM clear processing is performed by the game control microcomputer has been described, but the same processing may be executed by the effect control microcomputer provided separately from the game control microcomputer.

1 Pachinko machine, 51 liquid crystal display, 53, 54 speakers

Claims (1)

A gaming machine that plays a predetermined game,
A storage means for storing control-related data in multiple storage areas,
It is provided with an initialization means for initializing the plurality of storage areas according to the predetermined conditions so as to be common initial data when the predetermined conditions are satisfied.
The initialization means is
In initializing one of the plurality of storage areas, the initial data is stored in a specific register , and the initial data stored in the specific register is written to the one storage area. Initialize the storage area of
In initializing the other storage areas of the plurality of storage areas in succession to the one storage area, the initial data is stored again in the specific register , and the initial data stored in the specific register is stored in the specific register. Initialize the other storage area by writing to the other storage area and
The gaming machine is
A first instruction executing means for executing a first instruction for storing data indicated by an argument in a storage area indicated by a predetermined address, and
Further provided with a second instruction executing means for executing a second instruction for storing data of a specific register in a storage area indicated by a predetermined address.
The initialization means is a gaming machine characterized in that the created initial data is stored in the specific register and the storage area is initialized by the second instruction.

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