JP7005111B2 - Electronic component mounting product - Google Patents

Electronic component mounting product Download PDF

Info

Publication number
JP7005111B2
JP7005111B2 JP2018021647A JP2018021647A JP7005111B2 JP 7005111 B2 JP7005111 B2 JP 7005111B2 JP 2018021647 A JP2018021647 A JP 2018021647A JP 2018021647 A JP2018021647 A JP 2018021647A JP 7005111 B2 JP7005111 B2 JP 7005111B2
Authority
JP
Japan
Prior art keywords
electronic component
pattern
along
circuit
mounting recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018021647A
Other languages
Japanese (ja)
Other versions
JP2019140221A (en
Inventor
聡 田中
孝充 相葉
敏訓 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yazaki Corp
Original Assignee
Yazaki Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yazaki Corp filed Critical Yazaki Corp
Priority to JP2018021647A priority Critical patent/JP7005111B2/en
Publication of JP2019140221A publication Critical patent/JP2019140221A/en
Application granted granted Critical
Publication of JP7005111B2 publication Critical patent/JP7005111B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は、電子部品実装品に関する。 The present invention relates to an electronic component mounted product.

従来の電子部品実装品として、例えば、特許文献1には、発光素子と、チップ部品と、パッケージと、チップ部品実装用部材とを備える発光モジュールが開示されている。チップ部品は、発光素子と電気的に接続される。パッケージは、発光素子及びチップ部品を内蔵し、内面に沿った接地配線を有する。チップ部品実装用部材は、パッケージの内面上に載置される。このチップ部品実装用部材は、チップ部品の第1及び第2の電極が第1及び第2のパッド上にそれぞれ導電接合され、第1及び第2のパッドにはボンディングワイヤがそれぞれ導電接合されている。 As a conventional electronic component mounting product, for example, Patent Document 1 discloses a light emitting module including a light emitting element, a chip component, a package, and a chip component mounting member. The chip component is electrically connected to the light emitting element. The package contains a light emitting element and a chip component, and has a ground wiring along the inner surface. The chip component mounting member is placed on the inner surface of the package. In this chip component mounting member, the first and second electrodes of the chip component are conductively bonded on the first and second pads, respectively, and the bonding wire is conductively bonded to the first and second pads, respectively. There is.

特開2012-028515号公報Japanese Unexamined Patent Publication No. 2012-0285115

ところで、上述の特許文献1に記載の発光モジュールは、例えば、SHF帯(Super High Frequency)等のGHzクラス以上(例えば、3GHzから30GHz)の信号伝送用回路に実装された場合であっても、適正に信号伝送を行うことができることが望まれている。 By the way, even when the light emitting module described in Patent Document 1 described above is mounted in a signal transmission circuit of GHz class or higher (for example, 3 GHz to 30 GHz) such as the SHF band (Super High Frequency). It is desired that signal transmission can be performed properly.

本発明は、上記の事情に鑑みてなされたものであって、適正な信号伝送を実現することができる電子部品実装品を提供することを目的とする。 The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electronic component mounted product capable of realizing appropriate signal transmission.

上記目的を達成するために、本発明に係る電子部品実装品は、絶縁性を有する絶縁体、導電性を有し前記絶縁体に設けられパターン最小幅が200[μm]である伝送路パターン、及び、導電性を有し前記絶縁体に内蔵され当該絶縁体を介在させて前記伝送路パターンと第1方向に沿って対向し当該伝送路パターンを設計インピーダンス値が50[Ω]である伝送路として構成させる内層パターンを含む回路部品と、前記回路部品に実装される電子部品と、前記伝送路パターンと前記電子部品とを電気的に接続する配線材とを備え、前記回路部品は、前記伝送路パターンと隣接して凹部状に設けられ底面に前記電子部品が実装される実装凹部を有し、前記内層パターンは、前記実装凹部の前記伝送路パターン側の内壁面に露出する露出部、及び、前記第1方向と交差する第2方向に沿って前記電子部品と対向する位置に前記露出部と隣接して設けられ前記実装凹部の前記内壁面から前記第2方向に沿って0より大きく150[μm]以下の範囲で退避した退避部を有することを特徴とする。 In order to achieve the above object, the electronic component mounted product according to the present invention includes an insulator having an insulating property, a transmission path pattern provided in the insulating body having electrical conductivity and having a pattern minimum width of 200 [μm]. A transmission line having conductivity and built in the insulator and facing the transmission line pattern along the first direction with the insulator interposed therebetween, and designing the transmission line pattern with an impedance value of 50 [Ω]. The circuit component includes a circuit component including an inner layer pattern, an electronic component mounted on the circuit component, and a wiring material for electrically connecting the transmission path pattern and the electronic component, and the circuit component is the transmission. The inner layer pattern has a mounting recess provided in a concave shape adjacent to the path pattern and on the bottom surface on which the electronic component is mounted, and the inner layer pattern includes an exposed portion exposed on the inner wall surface of the mounting recess on the transmission path pattern side and an exposed portion. , Which is provided adjacent to the exposed portion at a position facing the electronic component along the second direction intersecting the first direction, and is larger than 0 along the second direction from the inner wall surface of the mounting recess 150. [Μm] It is characterized by having a retracted portion retracted within the following range.

また、上記電子部品実装品では、導電性を有し前記実装凹部の前記底面と前記電子部品との間に介在し当該底面と当該電子部品とを接着する導電性接着剤と、前記第2方向に沿って前記退避部と対向する位置に、前記第2方向に対して前記実装凹部の前記内壁面と前記電子部品との間に形成される空隙部として設けられ、前記導電性接着剤の一部を貯留可能である溜まり部とを備えるものとすることができる。 Further, in the electronic component mounting product, a conductive adhesive which has conductivity and is interposed between the bottom surface of the mounting recess and the electronic component to bond the bottom surface and the electronic component, and the second direction. One of the conductive adhesives, which is provided as a gap formed between the inner wall surface of the mounting recess and the electronic component in the second direction at a position facing the retracted portion along the above. It may be provided with a pool portion capable of storing the portion.

また、上記電子部品実装品では、前記回路部品は、導電性を有し前記第1方向に対して前記電子部品の前記底面側に設けられ、前記第2方向に沿った前記退避部との間隔が200[μm]以上確保された底面側パターンを含むものとすることができる。 Further, in the electronic component mounted product, the circuit component has conductivity and is provided on the bottom surface side of the electronic component with respect to the first direction, and is spaced from the retracted portion along the second direction. It is possible to include a bottom side pattern in which 200 [μm] or more is secured.

また、上記電子部品実装品では、前記回路部品は、前記実装凹部の前記底面に実装された前記電子部品の周りに設けられ前記第1方向に沿って当該回路部品を貫通した貫通孔部を有するものとすることができる。 Further, in the electronic component mounted product, the circuit component has a through hole portion provided around the electronic component mounted on the bottom surface of the mounting recess and penetrating the circuit component along the first direction. Can be.

本発明に係る電子部品実装品は、上記構成を備えることで、配線材の寄生インダクタンスを適正に抑制することができる。この結果、電子部品実装品は、適正な信号伝送を実現することができる、という効果を奏する。 By providing the above-mentioned configuration, the electronic component mounted product according to the present invention can appropriately suppress the parasitic inductance of the wiring material. As a result, the electronic component mounted product has the effect that proper signal transmission can be realized.

図1は、実施形態1に係る電子部品実装品の概略構成を表す模式的な部分斜視図である。FIG. 1 is a schematic partial perspective view showing a schematic configuration of an electronic component mounted product according to the first embodiment. 図2は、実施形態1に係る電子部品実装品の概略構成を表す模式的な部分断面図である。FIG. 2 is a schematic partial cross-sectional view showing a schematic configuration of an electronic component mounted product according to the first embodiment. 図3は、実施形態2に係る電子部品実装品の概略構成を表す模式的な部分斜視図である。FIG. 3 is a schematic partial perspective view showing a schematic configuration of an electronic component mounted product according to the second embodiment. 図4は、実施形態2に係る電子部品実装品の概略構成を表す模式的な部分断面図である。FIG. 4 is a schematic partial cross-sectional view showing a schematic configuration of an electronic component mounted product according to the second embodiment. 図5は、実施形態3に係る電子部品実装品の概略構成を表す模式的な部分斜視図である。FIG. 5 is a schematic partial perspective view showing a schematic configuration of an electronic component mounted product according to the third embodiment. 図6は、変形例に係る電子部品実装品の概略構成を表す模式的な部分斜視図である。FIG. 6 is a schematic partial perspective view showing a schematic configuration of an electronic component mounted product according to a modified example.

以下に、本発明に係る実施形態を図面に基づいて詳細に説明する。なお、この実施形態によりこの発明が限定されるものではない。また、下記実施形態における構成要素には、当業者が置換可能かつ容易なもの、あるいは実質的に同一のものが含まれる。 Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to this embodiment. In addition, the components in the following embodiments include those that can be easily replaced by those skilled in the art, or those that are substantially the same.

[実施形態1]
図1、図2に示す電子部品実装品1は、回路部品3に電子部品2が実装され、電子回路を構成するものである。本実施形態の電子部品実装品1は、例えば、SHF帯の信号伝送用回路の一部を構成するものである。そして、本実施形態の電子部品実装品1は、回路部品3に所定の構造を付加することで、より適正な信号伝送を実現したものである。以下、各図を参照して電子部品実装品1の各構成について詳細に説明する。
[Embodiment 1]
In the electronic component mounted product 1 shown in FIGS. 1 and 2, the electronic component 2 is mounted on the circuit component 3 to form an electronic circuit. The electronic component mounting product 1 of the present embodiment constitutes, for example, a part of a signal transmission circuit in the SHF band. The electronic component mounted product 1 of the present embodiment realizes more appropriate signal transmission by adding a predetermined structure to the circuit component 3. Hereinafter, each configuration of the electronic component mounted product 1 will be described in detail with reference to each figure.

なお、以下の説明では、互いに交差する第1方向、第2方向、及び、第3方向のうち、第1方向を「厚み方向X」といい、第2方向を「第1幅方向Y」といい、第3方向を「第2幅方向Z」という。ここでは、厚み方向Xと第1幅方向Yと第2幅方向Zとは、相互に直交する。厚み方向Xは、典型的には、回路部品3の各層が積層される方向に相当し、回路部品3において電子部品2が実装される実装面の法線方向に相当する。本実施形態の厚み方向Xは、回路部品3において伝送路パターン32Aと内層パターン32Bとが対向する方向に相当する。第1幅方向Y、及び、第2幅方向Zは、典型的には、回路部品3において電子部品2が実装される実装面の延在方向に相当する。本実施形態の第1幅方向Yは、電子部品2と内層パターン32Bの退避部32Bbとが対向する方向に相当する。以下の説明で用いる各方向は、特に断りのない限り、各部が相互に組み付けられた状態での方向を表すものとする。 In the following description, of the first direction, the second direction, and the third direction that intersect each other, the first direction is referred to as "thickness direction X", and the second direction is referred to as "first width direction Y". The third direction is called "second width direction Z". Here, the thickness direction X, the first width direction Y, and the second width direction Z are orthogonal to each other. The thickness direction X typically corresponds to the direction in which the layers of the circuit component 3 are laminated, and corresponds to the normal direction of the mounting surface on which the electronic component 2 is mounted in the circuit component 3. The thickness direction X of the present embodiment corresponds to the direction in which the transmission line pattern 32A and the inner layer pattern 32B face each other in the circuit component 3. The first width direction Y and the second width direction Z typically correspond to the extending direction of the mounting surface on which the electronic component 2 is mounted in the circuit component 3. The first width direction Y of the present embodiment corresponds to the direction in which the electronic component 2 and the retracted portion 32Bb of the inner layer pattern 32B face each other. Unless otherwise specified, each direction used in the following description shall represent a direction in which each part is assembled to each other.

具体的には、電子部品実装品1は、電子部品2と、回路部品3と、導電性接着剤4と、溜まり部5と、配線材6とを備える。 Specifically, the electronic component mounting product 1 includes an electronic component 2, a circuit component 3, a conductive adhesive 4, a pool portion 5, and a wiring material 6.

電子部品2は、回路部品3に実装され種々の機能を発揮する素子である。本実施形態の電子部品2は、典型的には、SHF帯の高周波数の光信号を伝送するための半導体素子である。ここでは、電子部品2は、例えば、光信号を出力する発光素子や当該発光素子や高周波信号で駆動するIC(Integrated Circuit)チップ等である。 The electronic component 2 is an element mounted on the circuit component 3 and exerting various functions. The electronic component 2 of the present embodiment is typically a semiconductor device for transmitting a high frequency optical signal in the SHF band. Here, the electronic component 2 is, for example, a light emitting element that outputs an optical signal, an IC (Integrated Circuit) chip that is driven by the light emitting element, a high frequency signal, or the like.

回路部品3は、電子部品2が実装され当該電子部品2を電気的に接続する電子回路を構成するものである。回路部品3は、板厚方向が厚み方向Xに沿う略矩形板状に形成され、第1幅方向Y、及び、第2幅方向Zに沿って延在して形成される。回路部品3は、絶縁性を有する絶縁体31、及び、導電性を有し絶縁体31に設けられる導電パターン32を含んで構成される。本実施形態の回路部品3は、いわゆるプリント回路基板(Printed Circuit Board)である。すなわち、回路部品3は、層状に構成される絶縁体31に導電パターン32(プリントパターン)が印刷されることで当該導電パターン32によって回路が構成される。絶縁体31は、導電性よりも誘電性が優位な誘電体である。絶縁体31は、エポキシ樹脂、ガラスエポキシ樹脂、紙エポキシ樹脂やセラミック等の絶縁性を有する樹脂材料によって形成される。導電パターン32は、銅等の導電性を有する金属材料によって形成される。導電パターン32は、要求される機能に応じた回路系統を構成する。 The circuit component 3 constitutes an electronic circuit in which the electronic component 2 is mounted and the electronic component 2 is electrically connected. The circuit component 3 is formed in a substantially rectangular plate shape in which the plate thickness direction is along the thickness direction X, and is formed so as to extend along the first width direction Y and the second width direction Z. The circuit component 3 includes an insulator 31 having an insulating property and a conductive pattern 32 provided on the insulating body 31 having a conductive property. The circuit component 3 of the present embodiment is a so-called printed circuit board (Printed Circuit Board). That is, in the circuit component 3, the conductive pattern 32 (print pattern) is printed on the insulator 31 formed in layers, and the circuit is formed by the conductive pattern 32. The insulator 31 is a dielectric whose dielectric property is superior to that of conductivity. The insulator 31 is formed of an insulating resin material such as an epoxy resin, a glass epoxy resin, a paper epoxy resin, or a ceramic. The conductive pattern 32 is formed of a conductive metal material such as copper. The conductive pattern 32 constitutes a circuit system according to the required function.

本実施形態の回路部品3は、複数の導電パターン32が絶縁体(絶縁層)31を介して厚み方向Xに沿って積層されて設けられる。すなわち、回路部品3は、導電パターン32が印刷された絶縁体31を厚み方向Xに沿って複数積層させて構成される。この構成により、回路部品3は、複数の絶縁体31と複数の導電パターン32とが交互に積層されて多層化されたいわゆる多層基板を構成する。そして、本実施形態の複数の導電パターン32は、伝送路パターン32A、及び、内層パターン32Bを含んで構成される。 The circuit component 3 of the present embodiment is provided with a plurality of conductive patterns 32 laminated along the thickness direction X via an insulator (insulating layer) 31. That is, the circuit component 3 is configured by laminating a plurality of insulators 31 on which the conductive pattern 32 is printed along the thickness direction X. With this configuration, the circuit component 3 constitutes a so-called multilayer substrate in which a plurality of insulators 31 and a plurality of conductive patterns 32 are alternately laminated to form a multilayer. The plurality of conductive patterns 32 of the present embodiment are configured to include the transmission line pattern 32A and the inner layer pattern 32B.

伝送路パターン32Aは、内層パターン32Bと協働して設計インピーダンス値が50[Ω]である伝送路を構成するものである。ここで、設計インピーダンス値とは、予め設計的に設定される伝送路のインピーダンス値である。伝送路を構成する伝送路パターン32Aは、高密度で設けられることで電子部品実装品1全体の大型化を抑制した上でより細かい部品実装に対応可能となる。本実施形態の伝送路パターン32Aは、複数設けられ、パターン最小幅W1、及び、パターン最小間隔P1がそれぞれ200[μm]程度となるように設けられる。ここで、パターン最小幅W1とは、伝送路として延在する方向と直交する方向の最小の幅である。また、パターン最小間隔P1とは、第1幅方向Y、又は、第2幅方向Zに沿って隣り合う2つの伝送路パターン32Aの間の最小の間隔である。パターン最小幅W1、及び、パターン最小間隔P1は、典型的には、導電パターン32の印刷精度上、必要な寸法精度を確保した上で印刷可能な値に応じて決まる。ここでは、各伝送路パターン32Aは、複数積層される絶縁体31の最外層に設けられる表層パターンとして形成される。 The transmission line pattern 32A constitutes a transmission line having a design impedance value of 50 [Ω] in cooperation with the inner layer pattern 32B. Here, the design impedance value is an impedance value of a transmission line that is set in advance by design. Since the transmission line pattern 32A constituting the transmission line is provided at a high density, it is possible to suppress the increase in size of the entire electronic component mounting product 1 and to support finer component mounting. A plurality of transmission line patterns 32A of the present embodiment are provided so that the pattern minimum width W1 and the pattern minimum interval P1 are each about 200 [μm]. Here, the pattern minimum width W1 is the minimum width in the direction orthogonal to the direction extending as the transmission line. Further, the pattern minimum spacing P1 is the minimum spacing between two transmission line patterns 32A adjacent to each other along the first width direction Y or the second width direction Z. The pattern minimum width W1 and the pattern minimum interval P1 are typically determined according to a value that can be printed while ensuring the necessary dimensional accuracy in terms of the printing accuracy of the conductive pattern 32. Here, each transmission line pattern 32A is formed as a surface layer pattern provided on the outermost layer of a plurality of laminated insulators 31.

内層パターン32Bは、伝送路パターン32Aのグランド面を構成するものである。内層パターン32Bは、積層された絶縁体31の間に内蔵され当該絶縁体31を介在させて伝送路パターン32Aと厚み方向Xに沿って対向する位置に形成される。この構成により、内層パターン32Bは、伝送路パターン32Aのグランド面を構成し、伝送路パターン32Aを設計インピーダンス値が50[Ω]である伝送路として構成させる。ここでは、回路部品3は、一例として、伝送路パターン32Aと内層パターン32Bとの間に介在する誘電体である絶縁体31の比誘電率が3程度、当該絶縁体31の厚み方向Xに沿った厚みT1が120[μm]程度とされる。この構成により、内層パターン32Bは、伝送路パターン32Aを設計インピーダンス値が50[Ω]である伝送路として機能させるためのグランド面として構成される。伝送路パターン32A、及び、内層パターン32Bによって構成される伝送路は、典型的には、いわゆるマイクロストリップラインを構成する。 The inner layer pattern 32B constitutes the ground surface of the transmission line pattern 32A. The inner layer pattern 32B is built in between the laminated insulators 31 and is formed at a position facing the transmission path pattern 32A along the thickness direction X with the insulator 31 interposed therebetween. With this configuration, the inner layer pattern 32B constitutes the ground surface of the transmission line pattern 32A, and the transmission line pattern 32A is configured as a transmission line having a design impedance value of 50 [Ω]. Here, as an example, the circuit component 3 has a relative permittivity of about 3 of the insulator 31, which is a dielectric interposed between the transmission path pattern 32A and the inner layer pattern 32B, along the thickness direction X of the insulator 31. The thickness T1 is about 120 [μm]. With this configuration, the inner layer pattern 32B is configured as a ground surface for allowing the transmission line pattern 32A to function as a transmission line having a design impedance value of 50 [Ω]. The transmission line composed of the transmission line pattern 32A and the inner layer pattern 32B typically constitutes a so-called microstrip line.

本実施形態の回路部品3は、上記のような構成において、電子部品2が実装される実装凹部33を有する。実装凹部33は、回路部品3において、伝送路パターン32Aと隣接して凹部状に設けられる。実装凹部33は、回路部品3において、伝送路パターン32Aが設けられた最外層から厚み方向Xに沿って窪むようにして形成される。ここでは、実装凹部33は、伝送路パターン32Aと第1幅方向Yに沿って隣接する位置に形成される。またここでは、実装凹部33は、厚み方向Xと直交する断面形状が略矩形状である凹部状に形成される。実装凹部33は、後述する配線材6の伝送路パターン32A側の接続位置と電子部品2側の接続位置とが厚み方向Xに対して可能な限り近くなるように、厚み方向Xに沿った深さD1が電子部品2の厚み方向Xに沿った高さH1を見込んだ深さとなるように形成される。ここでは、電子部品2の厚み方向Xに沿った高さH1としては、例えば、最大150[μm]程度が見込まれる。そして、実装凹部33は、厚み方向Xの底面33aに電子部品2が実装される。つまり、実装凹部33の底面33aは、電子部品2が実装される実装面を構成する。この底面33aは、厚み方向Xと略直交し第1幅方向Y、及び、第2幅方向Zに沿って延在する面として形成される。本実施形態の電子部品2は、この実装凹部33の底面33aに導電性接着剤4を介して実装される。図2の例では、実装凹部33は、底面33aに導電性接着剤4を介して実装された電子部品2の厚み方向Xの表面(底面33a側とは反対側の面)と伝送路パターン32Aの厚み方向Xの表面(絶縁体31側とは反対側の面)とが厚み方向Xに対して略揃う深さに形成される。 The circuit component 3 of the present embodiment has a mounting recess 33 on which the electronic component 2 is mounted in the above configuration. The mounting recess 33 is provided in the circuit component 3 in a recess shape adjacent to the transmission path pattern 32A. The mounting recess 33 is formed in the circuit component 3 so as to be recessed along the thickness direction X from the outermost layer provided with the transmission path pattern 32A. Here, the mounting recess 33 is formed at a position adjacent to the transmission path pattern 32A along the first width direction Y. Further, here, the mounting recess 33 is formed in a concave shape having a substantially rectangular cross-sectional shape orthogonal to the thickness direction X. The mounting recess 33 has a depth along the thickness direction X so that the connection position on the transmission path pattern 32A side and the connection position on the electronic component 2 side of the wiring material 6 described later are as close as possible to the thickness direction X. The D1 is formed so as to have a depth expected to be a height H1 along the thickness direction X of the electronic component 2. Here, the height H1 along the thickness direction X of the electronic component 2 is expected to be, for example, about 150 [μm] at the maximum. Then, in the mounting recess 33, the electronic component 2 is mounted on the bottom surface 33a in the thickness direction X. That is, the bottom surface 33a of the mounting recess 33 constitutes a mounting surface on which the electronic component 2 is mounted. The bottom surface 33a is formed as a surface substantially orthogonal to the thickness direction X and extending along the first width direction Y and the second width direction Z. The electronic component 2 of the present embodiment is mounted on the bottom surface 33a of the mounting recess 33 via the conductive adhesive 4. In the example of FIG. 2, the mounting recess 33 is the surface of the electronic component 2 mounted on the bottom surface 33a via the conductive adhesive 4 in the thickness direction X (the surface opposite to the bottom surface 33a side) and the transmission path pattern 32A. The surface of the thickness direction X (the surface opposite to the insulator 31 side) is formed at a depth substantially aligned with the thickness direction X.

導電性接着剤4は、導電性を有し実装凹部33の底面33aと電子部品2との間に介在し当該底面33aと当該電子部品2とを接着固定するものである。導電性接着剤4は、例えば、エポキシ樹脂等の有機バインダに、銀や金等の導電性材料を均一分散させたものを用いることができる。 The conductive adhesive 4 has conductivity and is interposed between the bottom surface 33a of the mounting recess 33 and the electronic component 2 to bond and fix the bottom surface 33a and the electronic component 2. As the conductive adhesive 4, for example, an organic binder such as an epoxy resin in which a conductive material such as silver or gold is uniformly dispersed can be used.

そして、本実施形態の回路部品3は、伝送路パターン32Aと隣接して上記のように実装凹部33が設けられることで、実装凹部33の内壁面33bに内層パターン32Bの一部の端部が露出する。ここで、内壁面33bは、実装凹部33を形成する内壁面であって伝送路パターン32A側に位置する内壁面である。ここでは、内壁面33bは、厚み方向X、及び、第2幅方向Zに沿って延在する面として形成される。つまり、本実施形態の内層パターン32Bは、実装凹部33の伝送路パターン32A側の内壁面33bに露出する露出部32Baを有する。内層パターン32Bは、実装凹部33側の端面が内壁面33bに露出することで露出部32Baを構成し、当該露出部32Baを構成する端面が第2幅方向Zに沿って延在する。なおここでは、内層パターン32Bは、実装凹部33の内壁面33b以外の内壁面にも一部の端部が露出している。 In the circuit component 3 of the present embodiment, the mounting recess 33 is provided adjacent to the transmission path pattern 32A as described above, so that a part of the end portion of the inner layer pattern 32B is formed on the inner wall surface 33b of the mounting recess 33. Be exposed. Here, the inner wall surface 33b is an inner wall surface forming the mounting recess 33 and is located on the transmission path pattern 32A side. Here, the inner wall surface 33b is formed as a surface extending along the thickness direction X and the second width direction Z. That is, the inner layer pattern 32B of the present embodiment has an exposed portion 32Ba exposed on the inner wall surface 33b on the transmission path pattern 32A side of the mounting recess 33. In the inner layer pattern 32B, the end surface on the mounting recess 33 side is exposed to the inner wall surface 33b to form the exposed portion 32Ba, and the end surface constituting the exposed portion 32Ba extends along the second width direction Z. Here, a part of the inner layer pattern 32B is exposed on the inner wall surface other than the inner wall surface 33b of the mounting recess 33.

そしてさらに、本実施形態の回路部品3は、露出部32Baと隣接して退避部32Bbを有する。この退避部32Bbは、内層パターン32Bにおいて、内壁面33bから第1幅方向Yに沿って退避した部分である。言い換えれば、退避部32Bbは、内層パターン32Bにおいて、内壁面33bから第1幅方向Yに沿ってセットバックされたセットバック部である。退避部32Bbは、内層パターン32Bにおいて、略矩形状に形成された切り欠き部として構成される。退避部32Bbは、第1幅方向Yに沿って電子部品2と対向する位置に露出部32Baと隣接して設けられる。言い換えれば、電子部品2は、底面33aにおいて、第1幅方向Yに沿って退避部32Bbと対向する位置に実装される。ここでは、退避部32Bbは、内壁面33bにおいて、第2幅方向Zに対して、一対の露出部32Baの間に挟まれるようにして設けられる。退避部32Bbは、第2幅方向Zに沿った幅W2が電子部品2の第2幅方向Zに沿った幅W3よりも広くなるように形成される。より詳細には、退避部32Bbは、第2幅方向Zに沿った幅W2が導電性接着剤4の第2幅方向Zに沿った幅W4よりも広くなるように形成される。そして、本実施形態の退避部32Bbは、内壁面33bから第1幅方向Yに沿って0より大きく150[μm]以下の範囲で退避した部分として形成される。つまり、退避部32Bbは、第1幅方向Yに沿った内壁面33bからの退避量(セットバック量)L1が0より大きく150[μm]以下の範囲となるように形成される。第1幅方向Yに沿った退避部32Bbの内壁面33bからの退避量L1は、言い換えれば、第1幅方向Yに沿った内層パターン32Bの切り欠き量に相当する。そして、本実施形態の電子部品実装品1は、第1幅方向Yに沿って当該退避部32Bbと対向する位置に溜まり部5が設けられている。 Further, the circuit component 3 of the present embodiment has a retracted portion 32Bb adjacent to the exposed portion 32Ba. The retracted portion 32Bb is a portion of the inner layer pattern 32B retracted from the inner wall surface 33b along the first width direction Y. In other words, the retracted portion 32Bb is a setback portion set back from the inner wall surface 33b along the first width direction Y in the inner layer pattern 32B. The retracted portion 32Bb is configured as a notch portion formed in a substantially rectangular shape in the inner layer pattern 32B. The retracting portion 32Bb is provided adjacent to the exposed portion 32Ba at a position facing the electronic component 2 along the first width direction Y. In other words, the electronic component 2 is mounted on the bottom surface 33a at a position facing the retracted portion 32Bb along the first width direction Y. Here, the retracted portion 32Bb is provided on the inner wall surface 33b so as to be sandwiched between the pair of exposed portions 32Ba in the second width direction Z. The retracting portion 32Bb is formed so that the width W2 along the second width direction Z is wider than the width W3 along the second width direction Z of the electronic component 2. More specifically, the retracting portion 32Bb is formed so that the width W2 along the second width direction Z is wider than the width W4 along the second width direction Z of the conductive adhesive 4. The retracted portion 32Bb of the present embodiment is formed as a portion retracted from the inner wall surface 33b along the first width direction Y in a range larger than 0 and 150 [μm] or less. That is, the retracted portion 32Bb is formed so that the retracted amount (setback amount) L1 from the inner wall surface 33b along the first width direction Y is larger than 0 and is in the range of 150 [μm] or less. The amount of evacuation L1 from the inner wall surface 33b of the evacuation portion 32Bb along the first width direction Y corresponds to, in other words, the amount of notch of the inner layer pattern 32B along the first width direction Y. The electronic component mounted product 1 of the present embodiment is provided with a pool portion 5 at a position facing the retracted portion 32Bb along the first width direction Y.

溜まり部5は、実装凹部33の底面33aに電子部品2を接着固定するための導電性接着剤4の一部を貯留可能な部分である。上述した導電性接着剤4は、電子部品2を底面33aに接着固定する過程でその一部が電子部品2の外形からはみ出て底面33a上で電子部品2の周りに拡がる傾向にある。導電性接着剤4の電子部品2からの拡がり幅W5は、典型的には、少なくとも電子部品2の高さH1の半分程度を見込むことが好ましい。例えば、電子部品2の高さH1が150[μm]程度である場合には、拡がり幅W5は、75[μm]程度が見込まれることが好ましい。そしてここでは、溜まり部5は、第1幅方向Yに対して内壁面33bと電子部品2との間に形成される空隙部として設けられる。この構成により、溜まり部5は、電子部品2の外形からはみ出て内壁面33b側に拡がった導電性接着剤4の一部を貯留可能に構成される。この溜まり部5は、第1幅方向Yに対して内壁面33bと電子部品2との間に設けられることで、言い換えれば、上述したように第1幅方向Yに沿って退避部32Bbと対向する位置に設けられることとなる。ここでは、溜まり部5は、例えば、第1幅方向Yに沿った幅W6が50[μm]程度となるように形成される。 The pool portion 5 is a portion capable of storing a part of the conductive adhesive 4 for adhesively fixing the electronic component 2 to the bottom surface 33a of the mounting recess 33. A part of the above-mentioned conductive adhesive 4 tends to protrude from the outer shape of the electronic component 2 and spread around the electronic component 2 on the bottom surface 33a in the process of adhering and fixing the electronic component 2 to the bottom surface 33a. It is preferable that the width W5 of the conductive adhesive 4 spread from the electronic component 2 is typically at least about half the height H1 of the electronic component 2. For example, when the height H1 of the electronic component 2 is about 150 [μm], it is preferable that the spread width W5 is expected to be about 75 [μm]. Here, the pool portion 5 is provided as a gap portion formed between the inner wall surface 33b and the electronic component 2 in the first width direction Y. With this configuration, the pool portion 5 is configured to be able to store a part of the conductive adhesive 4 that protrudes from the outer shape of the electronic component 2 and spreads toward the inner wall surface 33b. The pool portion 5 is provided between the inner wall surface 33b and the electronic component 2 with respect to the first width direction Y, in other words, as described above, faces the retracted portion 32Bb along the first width direction Y. It will be provided at the position where it is evacuated. Here, the pool portion 5 is formed so that the width W6 along the first width direction Y is, for example, about 50 [μm].

配線材6は、伝送路パターン32Aと電子部品2とを電気的に接続するものである。配線材6は、典型的には、金、アルミニウム、銅等の導電性を有する金属材料によって形成されたボンディングワイヤである。配線材6は、伝送路パターン32Aの厚み方向Xの表面(絶縁体31側とは反対側の面)と電子部品2の厚み方向Xの表面(底面33a側とは反対側の面)側の電極とを電気的に接続する。配線材6は、例えば、ボールボンディングやウェッジボンディング等の種々の手法によって設けられる。 The wiring material 6 electrically connects the transmission line pattern 32A and the electronic component 2. The wiring material 6 is typically a bonding wire formed of a conductive metal material such as gold, aluminum, or copper. The wiring material 6 is on the surface of the transmission path pattern 32A in the thickness direction X (the surface opposite to the insulator 31 side) and the surface of the electronic component 2 in the thickness direction X (the surface opposite to the bottom surface 33a side). Electrically connect to the electrodes. The wiring material 6 is provided by various methods such as ball bonding and wedge bonding.

以上で説明した電子部品実装品1は、上記構成を備えることで、配線材6の寄生インダクタンスを適正に抑制することができるので、適正な信号伝送を実現することができる。 Since the electronic component mounted product 1 described above is provided with the above configuration, the parasitic inductance of the wiring material 6 can be appropriately suppressed, so that appropriate signal transmission can be realized.

すなわち、電子部品実装品1は、回路部品3が絶縁体31、伝送路パターン32A、及び、内層パターン32Bを含んで構成される。この構成により、電子部品実装品1は、伝送路パターン32Aを、パターン最小幅W1が200[μm]でかつ設計インピーダンス値が50[Ω]である伝送路として構成させることができる。そして、電子部品実装品1は、回路部品3に実装された電子部品2とこの伝送路パターン32Aとが配線材6を介して電気的に接続される。 That is, the electronic component mounting product 1 includes the circuit component 3 including the insulator 31, the transmission path pattern 32A, and the inner layer pattern 32B. With this configuration, the electronic component mounting product 1 can configure the transmission line pattern 32A as a transmission line having a pattern minimum width W1 of 200 [μm] and a design impedance value of 50 [Ω]. Then, in the electronic component mounted product 1, the electronic component 2 mounted on the circuit component 3 and the transmission path pattern 32A are electrically connected via the wiring material 6.

この構成において、電子部品実装品1は、回路部品3に当該伝送路パターン32Aと隣接して設けられる実装凹部33の底面33aに当該電子部品2が実装される。この構成により、電子部品実装品1は、別途部品を設けることなく、厚み方向Xに対して、配線材6と伝送路パターン32Aとの接続位置と、配線材6と電子部品2との接続位置とを相対的に近接させることができる。この結果、電子部品実装品1は、配線材6の長さを相対的に短く抑制することができるので、伝送路の伝送特性に悪影響を及ぼす可能性がある配線材6の寄生インダクタンスを抑制することができる。 In this configuration, in the electronic component mounting product 1, the electronic component 2 is mounted on the bottom surface 33a of the mounting recess 33 provided adjacent to the transmission path pattern 32A in the circuit component 3. With this configuration, the electronic component mounted product 1 has a connection position between the wiring material 6 and the transmission path pattern 32A and a connection position between the wiring material 6 and the electronic component 2 in the thickness direction X without providing a separate component. Can be relatively close to each other. As a result, the electronic component mounting product 1 can suppress the length of the wiring material 6 to be relatively short, so that the parasitic inductance of the wiring material 6 which may adversely affect the transmission characteristics of the transmission line is suppressed. be able to.

電子部品実装品1は、上記のように、内層パターン32Bによって伝送路パターン32Aの上記伝送路としての性能を確保し、その上で、実装凹部33が伝送路パターン32Aと隣接して設けられる構成とされている。この構成により、電子部品実装品1は、内層パターン32Bの一部の端部が露出部32Baとして実装凹部33の伝送路パターン32A側の内壁面33bに露出する構成となる。この構成において、電子部品実装品1は、露出部32Baが露出する内壁面33bに、当該内層パターン32Bの退避部32Bbが設けられている。この退避部32Bbは、第1幅方向Yに沿って電子部品2と対向する位置に露出部32Baと隣接して設けられ、内壁面33bから第1幅方向Yに沿って退避するようにして形成される。この構成により、電子部品実装品1は、電子部品2を内壁面33bに可能な限り近づけて設けた上で、電子部品2と内層パターン32Bとの間で短絡が発生することを防止することができる。この構成により、電子部品実装品1は、別途部品を設けることなく、第1幅方向Yに対して、配線材6と伝送路パターン32Aとの接続位置と、配線材6と電子部品2との接続位置とを相対的に近接させることができる。したがってこの点でも、電子部品実装品1は、配線材6の長さを相対的に短く抑制することができるので、配線材6の寄生インダクタンスを抑制することができる。 As described above, the electronic component mounting product 1 has a configuration in which the performance of the transmission line pattern 32A as the transmission line is ensured by the inner layer pattern 32B, and the mounting recess 33 is provided adjacent to the transmission line pattern 32A. It is said that. With this configuration, the electronic component mounting product 1 has a configuration in which a part of the end portion of the inner layer pattern 32B is exposed as an exposed portion 32Ba on the inner wall surface 33b on the transmission path pattern 32A side of the mounting recess 33. In this configuration, the electronic component mounting product 1 is provided with a retracted portion 32Bb of the inner layer pattern 32B on the inner wall surface 33b where the exposed portion 32Ba is exposed. The retracted portion 32Bb is provided adjacent to the exposed portion 32Ba at a position facing the electronic component 2 along the first width direction Y, and is formed so as to retract from the inner wall surface 33b along the first width direction Y. Will be done. With this configuration, the electronic component mounting product 1 is provided with the electronic component 2 as close as possible to the inner wall surface 33b, and can prevent a short circuit from occurring between the electronic component 2 and the inner layer pattern 32B. can. With this configuration, the electronic component mounted product 1 has the connection position between the wiring material 6 and the transmission path pattern 32A and the wiring material 6 and the electronic component 2 in the first width direction Y without providing a separate component. It can be relatively close to the connection position. Therefore, also in this respect, the electronic component mounting product 1 can suppress the length of the wiring material 6 to be relatively short, so that the parasitic inductance of the wiring material 6 can be suppressed.

このように、電子部品実装品1は、配線材6の長さを相対的に短く抑制し、配線材6の寄生インダクタンスを抑制することができることで、例えば、伝送信号のカットオフ周波数が低下することを抑制することができ、伝送信号の高周波化に対応することができる。 In this way, the electronic component mounted product 1 can suppress the length of the wiring material 6 to be relatively short and suppress the parasitic inductance of the wiring material 6, so that, for example, the cutoff frequency of the transmission signal is lowered. This can be suppressed, and it is possible to cope with the increase in the frequency of the transmission signal.

そして、電子部品実装品1は、内層パターン32Bの退避部32Bbが実装凹部33の内壁面33bから第1幅方向Yに沿って0より大きく150[μm]以下の範囲で退避するように設けられている。この構成により、電子部品実装品1は、伝送路パターン32Aを上記伝送路として機能させるための内層パターン32Bに設けられた退避部32Bbに起因した当該伝送路の伝送特性の劣化を影響のない範囲に抑制することができる。例えば、内層パターン32Bに退避部32Bbが設けられていない比較例に係る電子部品実装品は、SHF帯の一部である28GHzの信号伝送において、伝送路パターン32A、配線材6を含む透過特性(いわゆるS21パラメータ)が-0.73dB程度となる。これに対して、電子部品実装品1は、例えば、退避部32Bbの退避量L1が150[μm]程度である場合、SHF帯の一部である28GHzの信号伝送において、伝送路パターン32A、配線材6を含む透過特性が-0.54dB程度となり、伝送路の伝送特性の劣化を影響のない範囲に抑制することができる。 The electronic component mounting product 1 is provided so that the retracting portion 32Bb of the inner layer pattern 32B retracts from the inner wall surface 33b of the mounting recess 33 along the first width direction Y in a range larger than 0 and 150 [μm] or less. ing. With this configuration, the electronic component mounted product 1 has a range in which the deterioration of the transmission characteristics of the transmission line due to the retracted portion 32Bb provided in the inner layer pattern 32B for making the transmission line pattern 32A function as the transmission line is not affected. Can be suppressed. For example, the electronic component mounted product according to the comparative example in which the retractable portion 32Bb is not provided in the inner layer pattern 32B has transmission characteristics (transmission path pattern 32A and wiring material 6) including the transmission path pattern 32A and the wiring material 6 in the signal transmission of 28 GHz which is a part of the SHF band. The so-called S21 parameter) is about −0.73 dB. On the other hand, in the electronic component mounted product 1, for example, when the retracted amount L1 of the retracted portion 32Bb is about 150 [μm], the transmission path pattern 32A and the wiring are used in the signal transmission of 28 GHz, which is a part of the SHF band. The transmission characteristic including the material 6 is about −0.54 dB, and the deterioration of the transmission characteristic of the transmission line can be suppressed within a range that does not affect it.

以上のように、電子部品実装品1は、上記構成を備えることで、適正な信号伝送を実現することができる。例えば、電子部品実装品1は、SHF帯の信号伝送用回路の一部を構成する場合であっても、追加部品を不要とし、かつ、低コスト化が望める汎用的な回路基板をベースとした上で、高周波化に伴い伝送特性に対する悪影響がより顕在化する可能性の寄生インダクタンスを効果的に抑制することができる。この結果、電子部品実装品1は、良好な信号伝送が可能になる。また、電子部品実装品1は、例えば、一般的な導電パターン32の配線幅と間隔(L/S(大きい場合で0.2mm/0.2mm程度、実力値の例で0.15mm/0.15mm程度))を維持した状態のまま実施が可能であり、これにより、例えば、コスト増加を抑制できる。また、電子部品実装品1は、例えば、 イコライザ等の波形整形回路の使用を低減でき、低消費電力化等を図ることもできる。 As described above, the electronic component mounting product 1 can realize proper signal transmission by providing the above configuration. For example, the electronic component mounted product 1 is based on a general-purpose circuit board that does not require additional components and can be expected to reduce costs even when a part of a signal transmission circuit in the SHF band is configured. In addition, it is possible to effectively suppress the parasitic inductance that may cause the adverse effect on the transmission characteristics to become more apparent as the frequency increases. As a result, the electronic component mounted product 1 enables good signal transmission. Further, in the electronic component mounted product 1, for example, the wiring width and spacing of a general conductive pattern 32 (L / S (about 0.2 mm / 0.2 mm in the case of a large size, 0.15 mm / 0 in the example of the actual value). It can be carried out while maintaining (about 15 mm))), and thereby, for example, an increase in cost can be suppressed. Further, the electronic component mounted product 1 can reduce the use of a waveform shaping circuit such as an equalizer, and can reduce power consumption and the like.

さらに、以上で説明した電子部品実装品1は、導電性接着剤4と、溜まり部5とを備える。この構成により、電子部品実装品1は、導電性接着剤4によって電子部品2を実装凹部33の底面33aに接着固定する構造において、内壁面33b側に拡がった導電性接着剤4の一部を溜まり部5に貯留することができる。このとき、電子部品実装品1は、溜まり部5が退避部32Bbと対向する位置に設けられていることから、導電性接着剤4が内壁面33bと接触する状態で溜まり部5に貯留されても、導電性接着剤4と内層パターン32Bとの間で短絡が発生することを防止することができる。つまりこの構成により、電子部品実装品1は、導電性接着剤4と内壁面33bとの間に絶縁のためのマージンを見込むことなく、導電性接着剤4によって電子部品2を底面33aに接着固定することができる。この結果、電子部品実装品1は、導電性接着剤4、及び、電子部品2を内壁面33bに可能な限り近づけて設けることができる。この点でも、電子部品実装品1は、第1幅方向Yに対して、配線材6と伝送路パターン32Aとの接続位置と、配線材6と電子部品2との接続位置とを相対的に近接させることができる。この結果、電子部品実装品1は、導電性接着剤4によって電子部品2を底面33aに接着固定した上で配線材6の長さを相対的に短く抑制し、配線材6の寄生インダクタンスを抑制することができ、適正な信号伝送を実現することができる。 Further, the electronic component mounting product 1 described above includes the conductive adhesive 4 and the pool portion 5. With this configuration, the electronic component mounting product 1 has a structure in which the electronic component 2 is adhered and fixed to the bottom surface 33a of the mounting recess 33 by the conductive adhesive 4, and a part of the conductive adhesive 4 spread toward the inner wall surface 33b is removed. It can be stored in the reservoir 5. At this time, since the pooled portion 5 is provided at a position facing the retracted portion 32Bb, the electronic component mounted product 1 is stored in the pooled portion 5 in a state where the conductive adhesive 4 is in contact with the inner wall surface 33b. Also, it is possible to prevent a short circuit from occurring between the conductive adhesive 4 and the inner layer pattern 32B. That is, with this configuration, the electronic component mounting product 1 adheres and fixes the electronic component 2 to the bottom surface 33a with the conductive adhesive 4 without expecting a margin for insulation between the conductive adhesive 4 and the inner wall surface 33b. can do. As a result, the electronic component mounting product 1 can be provided with the conductive adhesive 4 and the electronic component 2 as close as possible to the inner wall surface 33b. Also in this respect, in the electronic component mounting product 1, the connection position between the wiring material 6 and the transmission path pattern 32A and the connection position between the wiring material 6 and the electronic component 2 are relatively relative to the first width direction Y. Can be brought close. As a result, in the electronic component mounted product 1, the electronic component 2 is adhered and fixed to the bottom surface 33a with the conductive adhesive 4, and then the length of the wiring material 6 is suppressed to be relatively short, and the parasitic inductance of the wiring material 6 is suppressed. It is possible to realize proper signal transmission.

[実施形態2]
実施形態2に係る電子部品実装品は、導電パターンとして底面側パターンを含む点で実施形態1とは異なる。以下では、上述した実施形態と同様の構成要素には共通の符号が付されるとともに、共通する構成、作用、効果については、重複した説明はできるだけ省略する(以下同様)。
[Embodiment 2]
The electronic component mounted product according to the second embodiment is different from the first embodiment in that the bottom side pattern is included as the conductive pattern. In the following, the same components as those in the above-described embodiment are designated by a common reference numeral, and the common configurations, actions, and effects will be omitted as much as possible (the same applies hereinafter).

図3、図4に示す本実施形態に係る電子部品実装品201は、回路部品3にかえて回路部品203を備える点で上述の電子部品実装品1と異なる。電子部品実装品201のその他の構成は、当該電子部品実装品1と略同様の構成である。回路部品203は、導電パターン32にかえて導電パターン232を含んで構成される点で上述の回路部品3と異なる。回路部品203のその他の構成は、当該回路部品3と略同様の構成である。導電パターン232は、伝送路パターン32A、内層パターン32Bに加えて、さらに底面側パターン232Cを備える点で導電パターン32と異なる。導電パターン232のその他の構成は、当該導電パターン32と略同様の構成である。 The electronic component mounted product 201 according to the present embodiment shown in FIGS. 3 and 4 is different from the above-mentioned electronic component mounted product 1 in that the circuit component 203 is provided instead of the circuit component 3. The other configurations of the electronic component mounted product 201 are substantially the same as those of the electronic component mounted product 1. The circuit component 203 is different from the circuit component 3 described above in that the circuit component 203 is configured to include the conductive pattern 232 instead of the conductive pattern 32. The other configurations of the circuit component 203 are substantially the same as those of the circuit component 3. The conductive pattern 232 is different from the conductive pattern 32 in that it further includes a bottom surface side pattern 232C in addition to the transmission line pattern 32A and the inner layer pattern 32B. The other configurations of the conductive pattern 232 are substantially the same as those of the conductive pattern 32.

本実施形態の底面側パターン232Cは、導電性を有し厚み方向Xに対して電子部品2の底面33a側に設けられる。底面側パターン232Cは、底面33aに略矩形状の島状に設けられる。電子部品2は、導電性接着剤4、及び、当該底面側パターン232Cを介して実装凹部33の底面33aに実装される。底面側パターン232Cは、例えば、電子部品2のグランド面や当該電子部品2で発生した熱を伝熱し放熱させる放熱面として機能する。そして、この底面側パターン232Cは、第1幅方向Yに対して退避部32Bbとの間に間隔L2を確保した位置に設けられる。ここでは、間隔L2は、退避部32Bbの退避量L1と溜まり部5の幅W6とを加算した値に相当する(L2=L1+W6)。間隔L2は、導電パターン32の印刷精度上、必要な寸法精度を確保した上で印刷可能な間隔の範囲で可能な限り狭いことが好ましい。ここでは、底面側パターン232Cは、第1幅方向Yに沿った退避部32Bbとの間隔L2が200[μm]以上確保されている。 The bottom surface side pattern 232C of the present embodiment has conductivity and is provided on the bottom surface 33a side of the electronic component 2 with respect to the thickness direction X. The bottom surface side pattern 232C is provided on the bottom surface 33a in a substantially rectangular island shape. The electronic component 2 is mounted on the bottom surface 33a of the mounting recess 33 via the conductive adhesive 4 and the bottom surface side pattern 232C. The bottom surface side pattern 232C functions as, for example, a ground surface of the electronic component 2 or a heat radiating surface that transfers and dissipates heat generated by the electronic component 2. The bottom surface side pattern 232C is provided at a position where a space L2 is secured between the bottom surface side pattern 232C and the retracting portion 32Bb in the first width direction Y. Here, the interval L2 corresponds to a value obtained by adding the evacuation amount L1 of the evacuation portion 32Bb and the width W6 of the accumulator portion 5 (L2 = L1 + W6). It is preferable that the interval L2 is as narrow as possible within the range of the printable interval while ensuring the necessary dimensional accuracy in terms of the printing accuracy of the conductive pattern 32. Here, in the bottom surface side pattern 232C, a distance L2 from the retracted portion 32Bb along the first width direction Y is secured to be 200 [μm] or more.

以上で説明した電子部品実装品201は、上記構成を備えることで、配線材6の寄生インダクタンスを適正に抑制することができるので、適正な信号伝送を実現することができる。 Since the electronic component mounted product 201 described above is provided with the above configuration, the parasitic inductance of the wiring material 6 can be appropriately suppressed, so that appropriate signal transmission can be realized.

その上で、以上で説明した電子部品実装品201は、底面側パターン232Cが設けられることで、導電性接着剤4による電子部品2の接着固定の確実性の向上、平坦性の確保、電子部品2の放熱性の向上等を実現することができる。そして、電子部品実装品201は、この構成を一般的な導電パターン32の配線幅と間隔(L/S)を維持した状態のまま実施が可能であり、これにより、例えば、コスト増加を抑制できる。 In addition, the electronic component mounted product 201 described above is provided with the bottom surface side pattern 232C to improve the certainty of adhesive fixing of the electronic component 2 by the conductive adhesive 4, secure the flatness, and provide the electronic component. It is possible to improve the heat dissipation of 2 and the like. Then, the electronic component mounting product 201 can carry out this configuration while maintaining the wiring width and spacing (L / S) of the general conductive pattern 32, whereby, for example, cost increase can be suppressed. ..

[実施形態3]
実施形態3に係る電子部品実装品は、回路部品が貫通孔部を有する点で実施形態1とは異なる。
[Embodiment 3]
The electronic component mounted product according to the third embodiment is different from the first embodiment in that the circuit component has a through hole portion.

図5に示す本実施形態に係る電子部品実装品301は、回路部品3にかえて回路部品303を備える点で上述の電子部品実装品1と異なる。電子部品実装品301のその他の構成は、当該電子部品実装品1と略同様の構成である。回路部品303は、貫通孔部334を有する点で上述の回路部品3と異なる。回路部品303のその他の構成は、当該回路部品3と略同様の構成である。 The electronic component mounted product 301 according to the present embodiment shown in FIG. 5 is different from the electronic component mounted product 1 described above in that the circuit component 303 is provided instead of the circuit component 3. The other configurations of the electronic component mounted product 301 are substantially the same as those of the electronic component mounted product 1. The circuit component 303 is different from the circuit component 3 described above in that it has a through hole portion 334. The other configurations of the circuit component 303 are substantially the same as those of the circuit component 3.

本実施形態の貫通孔部334は、実装凹部33の底面33aに実装された電子部品2の周りに設けられ厚み方向Xに沿って回路部品303を貫通して形成される。ここでは、貫通孔部334は、第2幅方向Zに対して電子部品2を挟んで一対で形成される。各貫通孔部334は、厚み方向Xと直交する断面形状が略矩形状である。各貫通孔部334は、各伝送路パターン32Aと第1幅方向Yに沿って隣接する位置に形成される。各貫通孔部334は、伝送路パターン32A側の内壁面が実装凹部33の内壁面33bと連続するようにして形成される。各貫通孔部334は、内部に、比誘電率が回路部品303よりも小さく相対的に寄生容量が生じ難い空気が充填され、空気層を構成する。 The through hole portion 334 of the present embodiment is provided around the electronic component 2 mounted on the bottom surface 33a of the mounting recess 33, and is formed so as to penetrate the circuit component 303 along the thickness direction X. Here, the through-hole portions 334 are formed in pairs with the electronic component 2 interposed therebetween in the second width direction Z. Each through hole portion 334 has a substantially rectangular cross-sectional shape orthogonal to the thickness direction X. Each through hole portion 334 is formed at a position adjacent to each transmission path pattern 32A along the first width direction Y. Each through hole portion 334 is formed so that the inner wall surface on the transmission path pattern 32A side is continuous with the inner wall surface 33b of the mounting recess 33. Each through-hole portion 334 is filled with air having a relative permittivity smaller than that of the circuit component 303 and relatively less likely to generate a parasitic capacitance, thereby forming an air layer.

以上で説明した電子部品実装品301は、上記構成を備えることで、配線材6の寄生インダクタンスを適正に抑制することができるので、適正な信号伝送を実現することができる。 By providing the above configuration, the electronic component mounted product 301 described above can appropriately suppress the parasitic inductance of the wiring material 6, so that appropriate signal transmission can be realized.

その上で、以上で説明した電子部品実装品301は、回路部品303の電子部品2の周りに貫通孔部334が設けられることで、回路部品303と電子部品2との間に空気層を介在させることができるので、いわゆる寄生キャパシタンスを低減することができる。この結果、電子部品実装品301は、より適正な信号伝送を実現することができる。例えば、電子部品実装品301は、SHF帯の一部である28GHzの信号伝送において、伝送路パターン32A、配線材6を含む透過特性が-0.51dB程度となる。 Further, in the electronic component mounted product 301 described above, the through hole portion 334 is provided around the electronic component 2 of the circuit component 303, so that an air layer is interposed between the circuit component 303 and the electronic component 2. Therefore, the so-called parasitic capacitance can be reduced. As a result, the electronic component mounted product 301 can realize more appropriate signal transmission. For example, the electronic component mounted product 301 has a transmission characteristic of about −0.51 dB including the transmission path pattern 32A and the wiring material 6 in the signal transmission of 28 GHz, which is a part of the SHF band.

なお、貫通孔部334は、以上で説明した形状に限られない。図6に示す変形例に係る電子部品実装品301Aは、貫通孔部334にかえて貫通孔部334Aを備える。貫通孔部334Aは、上述した一対の貫通孔部334の位置に加えて、さらに実装凹部33の内壁面33bと電子部品2との間にも設けられている。このため、貫通孔部334Aは、内壁面33bと電子部品2との間に位置する部分を含め、電子部品2の3方を囲うように連なって形成されている。この場合であっても、電子部品実装品301Aは、回路部品303の電子部品2の周りに貫通孔部334Aが設けられるので寄生キャパシタンスを低減することができ、より適正な信号伝送を実現することができる。 The through hole portion 334 is not limited to the shape described above. The electronic component mounted product 301A according to the modified example shown in FIG. 6 includes a through hole portion 334A instead of the through hole portion 334. The through-hole portion 334A is provided between the inner wall surface 33b of the mounting recess 33 and the electronic component 2 in addition to the positions of the pair of through-hole portions 334 described above. Therefore, the through hole portion 334A is formed in a row so as to surround three sides of the electronic component 2, including a portion located between the inner wall surface 33b and the electronic component 2. Even in this case, since the electronic component mounted product 301A is provided with the through hole portion 334A around the electronic component 2 of the circuit component 303, the parasitic capacitance can be reduced and more appropriate signal transmission can be realized. Can be done.

なお、上述した本発明の実施形態に係る電子部品実装品は、上述した実施形態に限定されず、特許請求の範囲に記載された範囲で種々の変更が可能である。本実施形態に係る電子部品実装品は、以上で説明した各実施形態、変形例の構成要素を適宜組み合わせることで構成してもよい。 The electronic component mounted product according to the above-described embodiment of the present invention is not limited to the above-mentioned embodiment, and various modifications can be made within the scope described in the claims. The electronic component mounted product according to the present embodiment may be configured by appropriately combining the components of each of the embodiments and modifications described above.

以上の説明では、電子部品実装品1、201、301、301Aは、SHF帯の信号伝送用回路の一部を構成するものとして説明したがこれに限らない。また、電子部品2は、発光素子やICチップ等の半導体素子であるものとして説明したがこれに限らない。また、電子部品実装品1、201、301、301Aは、回路部品3、203、303の表層への部品実装に限らず、加工が可能であれば、例えば、部品内蔵基板の内層に実装凹部33、及び、電子部品2を設けてもよい。 In the above description, the electronic component mounted products 1, 201, 301, and 301A have been described as constituting a part of the signal transmission circuit in the SHF band, but the present invention is not limited to this. Further, the electronic component 2 has been described as being a semiconductor element such as a light emitting element or an IC chip, but the present invention is not limited to this. Further, the electronic component mounting products 1, 201, 301 and 301A are not limited to the component mounting on the surface layer of the circuit components 3, 203 and 303, and if processing is possible, for example, the mounting recess 33 in the inner layer of the component built-in board. , And the electronic component 2 may be provided.

以上の説明では、回路部品3、203、303は、プリント回路基板であるものとして説明したがこれに限らない。回路部品は、絶縁体、伝送路パターン、内層パターン等を含んで構成され、実装凹部等を有するものであれば、成形樹脂回路部品(MID:Molded Interconnect Device)等であってもよい。 In the above description, the circuit components 3, 203, and 303 are described as being printed circuit boards, but the present invention is not limited to this. The circuit component may be a molded resin circuit component (MID: Molded Interconnect Device) or the like as long as it is configured to include an insulator, a transmission path pattern, an inner layer pattern, or the like and has a mounting recess or the like.

以上の説明では、電子部品実装品1、201、301、301Aは、導電性接着剤4、溜まり部5を備えるものとして説明したがこれに限らない。電子部品実装品1、201、301、301Aは、電子部品2を他の固定方法で底面33aに固定できる構成であれば、導電性接着剤4、溜まり部5を備えなくてもよい。 In the above description, the electronic component mounting products 1, 201, 301, and 301A have been described as having the conductive adhesive 4 and the pool portion 5, but the present invention is not limited to this. The electronic component mounting products 1, 201, 301, and 301A may not be provided with the conductive adhesive 4 and the pool portion 5 as long as the electronic component 2 can be fixed to the bottom surface 33a by another fixing method.

1、201、301、301A 電子部品実装品
2 電子部品
3、203、303 回路部品
4 導電性接着剤
5 溜まり部
6 配線材
31 絶縁体
32、232 導電パターン
32A 伝送路パターン
32B 内層パターン
32Ba 露出部
32Bb 退避部
33 実装凹部
33a 底面
33b 内壁面
232C 底面側パターン
334、334A 貫通孔部
X 厚み方向(第1方向)
Y 第1幅方向(第2方向)
Z 第2幅方向
1, 201, 301, 301A Electronic component mounting product 2 Electronic component 3, 203, 303 Circuit component 4 Conductive adhesive 5 Reservoir 6 Wiring material 31 Insulator 32, 232 Conductive pattern 32A Transmission path pattern 32B Inner layer pattern 32Ba Exposed section 32Bb Retracting part 33 Mounting recess 33a Bottom surface 33b Inner wall surface 232C Bottom side pattern 334 334A Through hole part X Thickness direction (first direction)
Y 1st width direction (2nd direction)
Z 2nd width direction

Claims (4)

絶縁性を有する絶縁体、導電性を有し前記絶縁体に設けられパターン最小幅が200[μm]である伝送路パターン、及び、導電性を有し前記絶縁体に内蔵され当該絶縁体を介在させて前記伝送路パターンと第1方向に沿って対向し当該伝送路パターンを設計インピーダンス値が50[Ω]である伝送路として構成させる内層パターンを含む回路部品と、
前記回路部品に実装される電子部品と、
前記伝送路パターンと前記電子部品とを電気的に接続する配線材とを備え、
前記回路部品は、前記伝送路パターンと隣接して凹部状に設けられ底面に前記電子部品が実装される実装凹部を有し、
前記内層パターンは、前記実装凹部の前記伝送路パターン側の内壁面に露出する露出部、及び、前記第1方向と交差する第2方向に沿って前記電子部品と対向する位置に前記露出部と隣接して設けられ前記実装凹部の前記内壁面から前記第2方向に沿って0より大きく150[μm]以下の範囲で退避した退避部を有することを特徴とする、
電子部品実装品。
An insulator having insulation, a transmission line pattern having conductivity and having a pattern minimum width of 200 [μm], and being built in the insulator having conductivity and interposing the insulator. A circuit component including an inner layer pattern that faces the transmission line pattern along the first direction and constitutes the transmission line pattern as a transmission line having a design impedance value of 50 [Ω].
Electronic components mounted on the circuit components and
A wiring material for electrically connecting the transmission line pattern and the electronic component is provided.
The circuit component has a mounting recess provided in a concave shape adjacent to the transmission path pattern and on the bottom surface on which the electronic component is mounted.
The inner layer pattern has an exposed portion exposed on the inner wall surface of the mounting recess on the transmission path pattern side, and the exposed portion at a position facing the electronic component along a second direction intersecting the first direction. It is characterized by having a retracting portion provided adjacently and retracted from the inner wall surface of the mounting recess in a range of more than 0 and 150 [μm] or less along the second direction.
Electronic component mounting product.
導電性を有し前記実装凹部の前記底面と前記電子部品との間に介在し当該底面と当該電子部品とを接着する導電性接着剤と、
前記第2方向に沿って前記退避部と対向する位置に、前記第2方向に対して前記実装凹部の前記内壁面と前記電子部品との間に形成される空隙部として設けられ、前記導電性接着剤の一部を貯留可能である溜まり部とを備える、
請求項1に記載の電子部品実装品。
A conductive adhesive that has conductivity and is interposed between the bottom surface of the mounting recess and the electronic component to adhere the bottom surface and the electronic component.
The conductive portion is provided at a position facing the retracted portion along the second direction as a gap portion formed between the inner wall surface of the mounting recess and the electronic component in the second direction. It is provided with a pool that can store a part of the adhesive.
The electronic component mounted product according to claim 1.
前記回路部品は、導電性を有し前記第1方向に対して前記電子部品の前記底面側に設けられ、前記第2方向に沿った前記退避部との間隔が200[μm]以上確保された底面側パターンを含む、
請求項1又は請求項2に記載の電子部品実装品。
The circuit component has conductivity and is provided on the bottom surface side of the electronic component with respect to the first direction, and a distance of 200 [μm] or more from the retracted portion along the second direction is secured. Including bottom side pattern,
The electronic component mounted product according to claim 1 or 2.
前記回路部品は、前記実装凹部の前記底面に実装された前記電子部品の周りに設けられ前記第1方向に沿って当該回路部品を貫通した貫通孔部を有する、
請求項1乃至請求項3のいずれか1項に記載の電子部品実装品。
The circuit component has a through hole portion provided around the electronic component mounted on the bottom surface of the mounting recess and penetrating the circuit component along the first direction.
The electronic component mounting product according to any one of claims 1 to 3.
JP2018021647A 2018-02-09 2018-02-09 Electronic component mounting product Active JP7005111B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2018021647A JP7005111B2 (en) 2018-02-09 2018-02-09 Electronic component mounting product

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018021647A JP7005111B2 (en) 2018-02-09 2018-02-09 Electronic component mounting product

Publications (2)

Publication Number Publication Date
JP2019140221A JP2019140221A (en) 2019-08-22
JP7005111B2 true JP7005111B2 (en) 2022-01-21

Family

ID=67694389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018021647A Active JP7005111B2 (en) 2018-02-09 2018-02-09 Electronic component mounting product

Country Status (1)

Country Link
JP (1) JP7005111B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003023843A1 (en) 2001-09-05 2003-03-20 Renesas Thechnology Corp. Semiconductor device, its manufacturing method, and radio communication device
WO2007091329A1 (en) 2006-02-10 2007-08-16 Fujitsu Limited Electronic component package
WO2010013819A1 (en) 2008-07-31 2010-02-04 京セラ株式会社 Matching circuit, wiring board, transmitter having matching circuit, receiver, transceiver and radar apparatus
JP2011134956A (en) 2009-12-25 2011-07-07 Shinko Electric Ind Co Ltd Semiconductor device
JP2015076836A (en) 2013-10-11 2015-04-20 株式会社フジクラ Waveguide substrate

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766949B2 (en) * 1990-09-28 1995-07-19 富士通株式会社 IC package
JPH04260201A (en) * 1991-02-14 1992-09-16 Shinko Electric Ind Co Ltd Semiconductor package and semiconductor device
JPH05199019A (en) * 1992-01-18 1993-08-06 Fujitsu Ltd High frequency circuit package
JP2716005B2 (en) * 1995-07-04 1998-02-18 日本電気株式会社 Wire bond type semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003023843A1 (en) 2001-09-05 2003-03-20 Renesas Thechnology Corp. Semiconductor device, its manufacturing method, and radio communication device
WO2007091329A1 (en) 2006-02-10 2007-08-16 Fujitsu Limited Electronic component package
WO2010013819A1 (en) 2008-07-31 2010-02-04 京セラ株式会社 Matching circuit, wiring board, transmitter having matching circuit, receiver, transceiver and radar apparatus
JP2011134956A (en) 2009-12-25 2011-07-07 Shinko Electric Ind Co Ltd Semiconductor device
JP2015076836A (en) 2013-10-11 2015-04-20 株式会社フジクラ Waveguide substrate

Also Published As

Publication number Publication date
JP2019140221A (en) 2019-08-22

Similar Documents

Publication Publication Date Title
US10535581B2 (en) Module for heat generating electronic component
US7889509B2 (en) Ceramic capacitor
US20060043562A1 (en) Circuit device and manufacture method for circuit device
JP6559743B2 (en) Semiconductor module
JP2004235629A (en) High-speed performance printed circuit board and manufacturing method therefor
US20080003846A1 (en) Circuit board unit
JP2008513998A (en) Concentric spacers for reducing capacitive coupling in multilayer substrate assemblies
US20110174526A1 (en) Circuit module
US20050012192A1 (en) Hybrid integrated circuit
KR101555403B1 (en) Wiring board
JP5354394B2 (en) Component built-in substrate and manufacturing method thereof
JP2007287767A (en) Optical subassembly
JP2006100699A (en) Printed wiring board, method for manufacturing the same and information processor
JP7005111B2 (en) Electronic component mounting product
JP3438715B2 (en) Microwave circuit board
JP2004111938A (en) Semiconductor device
JP2003086755A (en) Hybrid module
JP4639600B2 (en) Semiconductor package
JPH08148601A (en) Multilayer interconnection board
JPH0851171A (en) Semiconductor ceramic package
JP2005340713A (en) Multichip module
JP5739363B2 (en) Wiring board
WO2023026848A1 (en) Antenna module
JP4099072B2 (en) Built-in module
JP2009231480A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210119

TRDD Decision of grant or rejection written
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20211222

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220104

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220104

R150 Certificate of patent or registration of utility model

Ref document number: 7005111

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350