JP7002126B2 - Semiconductor devices, semiconductor device manufacturing methods, infrared photoelectric conversion elements, infrared detection elements, and infrared light emitting elements - Google Patents

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, an infrared photoelectric conversion element, an infrared detection element, and an infrared light emitting element.

The GaAs semiconductor (gallium arsenide semiconductor) has a feature that the electron mobility is faster than that of Si (silicon), the resistivity of the undoped substrate is high, and the leakage current to the substrate and the parasitic capacitance are easily reduced. Therefore, the GaAs semiconductor device is widely used as a high-speed low power consumption semiconductor device.

Further, since the GaAs semiconductor is a direct transition type semiconductor and its band gap is 1.43 eV, which is a band gap in the infrared region, a photoelectric conversion element in the infrared region, that is, an infrared light emitting element such as an infrared laser or an infrared diode. It is widely used as an infrared detector and an infrared light receiving / receiving element.

Here, in the photoelectric conversion element based on GaAs, it is necessary to inject a current into the GaAs semiconductor or take out the current from the semiconductor. As an efficient structure for doing this, there is a double-sided electrode structure in which electrodes are arranged on both the first and second main surfaces of the GaAs semiconductor layer. For example, as a double-sided electrode structure GaAs light receiving element, both sides are described in Patent Document 1. It is disclosed in Patent Document 2 as an electrode structure GaAs light emitting device.
When the electrodes formed on both the first and second main surfaces contain a metal, the light reflection effect and the plasmon effect of the metal can be utilized, so that the element is a high-performance element having excellent light-receiving and light-emitting characteristics.
Further, when the semiconductor device is a laser, if both electrodes contain metal, both electrodes have the effect of reflecting light, so that a semiconductor waveguide having high light confinement efficiency can be formed, and thus high performance with excellent characteristics. It becomes an element.

Japanese Unexamined Patent Publication No. 2010-114247 Japanese Unexamined Patent Publication No. 2009-10191

"III-V Group Compound Semiconductor" by Isamu Akasaki Baifukan Chapter 8 p. 117 Apple. Phys. Let. , Vol. 39, p. 800 (1981) Apple. Phys. Let. , Vol. 66, p. 1412 (1995) Apple. Phys. Let. , Vol. 83, p. 2124 (2003) Apple. Phys. Let. , Vol. 49, p. 292 (1986) Semiconductor Sci. Technol. , Vol. 26, p. 105021 (2011) Apple. Phys. Let. , Vol. 104, p. 031113 (2014) Semiconductor Sci. Technol. , Vol. 20, p. 105021 (2011)

The problem to be solved by the present invention is that in a photoelectric conversion element based on an N-type GaAs semiconductor having a double-sided electrode structure, an element with improved performance, that is, a light receiving element, has a detection sensitivity and a noise (dark current) ratio. It is an object of the present invention to provide an element having a high light emitting output in a high element and a light emitting element.
Further, a photoelectric conversion element based on an N-type GaAs semiconductor having a double-sided electrode structure having stable electrical characteristics and little variation between elements, specifically, stable electrical characteristics and variation between elements. It is to provide a small number of infrared detection elements and infrared light emitting elements.

The configuration of the present invention is shown below.
(Structure 1)
A first electrode containing a metal is formed on the first main surface of a single crystal semiconductor layer containing Ga and As via a first interface layer, and a second main surface containing a metal is contained in the second main surface of the semiconductor layer. Is a semiconductor device in which the electrodes of the above are formed via the second interface layer.
The first interface layer and the second interface layer are N-type semiconductor layers, which are single crystals containing Ga and As.
At least one boundary portion of the first interface layer or the semiconductor layer in contact with the second interface layer has the same crystal lattice as a GaAs single crystal.
The first interface layer and the first electrode, and the second interface layer and the second electrode make ohmic contact.
The thickness of the metal diffusion layer forming the first electrode formed at the interface between the first interface layer and the first electrode, and the thickness of the second interface layer and the second electrode. A semiconductor device in which the thickness of the metal diffusion layer forming the second electrode formed at the interface is 3 nm or less.
(Structure 2)
A first electrode containing a metal is formed on the first main surface of a single crystal semiconductor layer containing Ga and As via a first interface layer, and a second main surface containing a metal is contained in the second main surface of the semiconductor layer. Is a semiconductor device in which the electrodes of the above are formed via the second interface layer.
The first interface layer and the second interface layer are N-type semiconductor layers, which are single crystals containing Ga and As.
At least one boundary portion of the first interface layer or the semiconductor layer in contact with the second interface layer has the same crystal lattice as a GaAs single crystal.
The first interface layer or at least one of the second interface layers has a volume density of Si of 6 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less.
The thickness of the metal diffusion layer forming the first electrode formed at the interface between the first interface layer and the first electrode, and the thickness of the second interface layer and the second electrode. A semiconductor device in which the thickness of the metal diffusion layer forming the second electrode formed at the interface is 3 nm or less.
(Structure 3)
The semiconductor device according to the configuration 1 or 2, wherein the thickness of the first interface layer and the second interface layer is 5 nm or more and 1000 nm or less.
(Structure 4)
The first electrode and the second electrode are Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc. , Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al, one or more metals selected from the group, Ti, Cr, Ni, Au, Pt, Ag. , Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir , In, Al, an alloy containing one or more metals selected from the group consisting of Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Compounds containing one or more metals selected from the group consisting of Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al, and ITO. The semiconductor device according to any one of configurations 1 to 3, comprising any of AZO, GZO, IZO, IGZO, ATO, FTO, FZO, and TiN.
(Structure 5)
A sacrificial layer forming step of forming a sacrificial layer having an etching rate higher than that of GaAs on a rigid substrate.
Formation of a first interface layer that forms the first interface layer of an N-type semiconductor with a single crystal containing Ga and As having a Si volume content of 6 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less. Process and
A semiconductor layer forming step of a semiconductor layer containing Ga and As, wherein the boundary portion of the semiconductor layer in contact with the first interface layer is a single crystal semiconductor having the same crystal lattice as a GaAs single crystal.
A second interface layer forming step of forming a second interface layer of an N-type semiconductor with a single crystal containing Ga and As, and a second interface layer forming step.
A second electrode forming step of forming a second electrode made of a material containing metal, and
The support substrate pasting step of pasting the support substrate on the second electrode and the process of pasting the support substrate,
An etching process for removing the substrate and the sacrificial layer by etching,
A method for manufacturing a semiconductor device, comprising a first electrode forming step of forming a first electrode made of a material containing a metal on the first interface layer.
(Structure 6)
The method for manufacturing a semiconductor device according to the configuration 5, wherein the second interface layer contains Si having a volume content of 6 × 10 ¹⁸ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less.
(Structure 7)
The method for manufacturing a semiconductor device according to the configuration 5 or 6, wherein the second interface layer is made of GaAs epitaxially formed at a temperature of 150 ° C. or higher and 300 ° C. or lower.
(Structure 8)
The method for manufacturing a semiconductor device according to any one of configurations 5 to 7, wherein the sacrificial layer is made of AlGaAs having an Al composition ratio of 50% or more and 100% or less.
(Structure 9)
The method for manufacturing a semiconductor device according to any one of configurations 5 to 8, wherein the semiconductor layer is epitaxially formed at a temperature of 300 ° C. or higher and 580 ° C. or lower.
(Structure 10)
The method for manufacturing a semiconductor device according to any one of configurations 5 to 8, wherein the semiconductor layer is epitaxially formed at a temperature of 300 ° C. or higher and 550 ° C. or lower.
(Structure 11)
The method for manufacturing a semiconductor device according to the configuration 9 or 10, wherein the time for epitaxial formation of the semiconductor layer is 2 minutes or more and 48 hours or less.
(Structure 12)
An infrared photoelectric conversion element using the semiconductor device according to any one of configurations 1 to 4 or the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of configurations 5 to 11.
(Structure 13)
An infrared detection element using the semiconductor device according to any one of configurations 1 to 4 or the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of configurations 5 to 11.
(Structure 14)
An infrared light emitting device using the semiconductor device according to any one of configurations 1 to 4 or the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of configurations 5 to 11.

According to the present invention, it is possible to provide a GaAs semiconductor-based double-sided electrode type semiconductor device having an excellent S / N ratio and stable electrical characteristics without forming an alloy layer. Further, it becomes possible to provide a method for manufacturing a double-sided electrode type semiconductor device based on a GaAs semiconductor, which has an excellent S / N ratio and stable electrical characteristics. In particular, the S / N ratio is excellent in double-sided electrode type infrared detection elements, infrared light emitting elements, and infrared photoelectric conversion elements based on GaAs semiconductors that utilize the surface plasmon effect and the light reflection effect at the interface between the electrode and the semiconductor device. , It becomes possible to provide an element having stable photoelectric conversion characteristics.

The schematic diagram which shows the structure of the main part of the semiconductor device of this invention in the cross section. The cross-sectional view which shows the outline of the structure of the semiconductor device of this invention. The cross-sectional view which shows the outline of the structure of the semiconductor device of this invention. The cross-sectional view which shows the outline of the structure of the semiconductor device of this invention. FIG. 3 is a manufacturing process diagram showing a manufacturing process of the semiconductor device of the present invention in a cross-sectional view. FIG. 3 is a manufacturing process diagram showing a manufacturing process of the semiconductor device of the present invention in a cross-sectional view. FIG. 3 is a manufacturing process diagram showing a manufacturing process of the semiconductor device of the present invention in a cross-sectional view. A structural schematic diagram showing a bird's-eye view of the semiconductor device of the present invention during the manufacturing process. FIG. 3 is a manufacturing process diagram showing a manufacturing process of the semiconductor device of the present invention in a cross-sectional view. FIG. 3 is a manufacturing process diagram showing a manufacturing process of the semiconductor device of the present invention in a cross-sectional view. The cross-sectional view which shows the detailed structure of the sample preparation stage of Example 1. FIG. The characteristic diagram which shows the electric contact characteristic of Example 1. FIG. The cross-sectional view which shows the detailed structure of the sample preparation stage of the comparative example 1. FIG. The characteristic diagram which shows the electric contact characteristic of the comparative example 1. FIG. The cross-sectional view which shows the detailed structure of the sample preparation stage of Example 2. FIG. The characteristic diagram which shows the electric contact characteristic of Example 2. FIG. The characteristic diagram which shows the electric contact characteristic of Example 2. FIG. The cross-sectional view which shows the outline structure of the infrared detection element of Example 3. FIG. The cross-sectional view which shows the detailed structure of the sample preparation stage of Example 3. FIG. The characteristic diagram which shows the electric contact characteristic of Example 3. FIG. The characteristic diagram which shows the electric contact characteristic of Example 3. FIG. The SIMS analysis figure of the 2nd interface layer 23 and the 2nd metal-containing layer 24. The characteristic diagram which shows the photoelectric response characteristic of the infrared detection element of Example 3. FIG. The characteristic figure which shows the current density characteristic with respect to the voltage of the infrared detection element of Example 3. FIG. The characteristic diagram which shows the photoelectric response characteristic of the infrared detection element of the comparative example 2. FIG. The characteristic figure which shows the current density characteristic with respect to the voltage of the infrared detection element of the comparative example 2. The cross-sectional view which shows the detailed structure of the sample preparation stage of Example 4. FIG. A characteristic diagram showing the relationship between the Si doping density and the carrier density. The cross-sectional view which shows the detailed structure of the sample preparation stage of Example 4. FIG. A characteristic diagram showing the relationship between the Si doping density and the specific contact resistance. FIG. 5 is a cross-sectional view showing a detailed structure of the sample preparation stage of Example 5. The characteristic diagram which shows the electric contact characteristic of Example 5.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<Structure and features>
First, the outline configuration of the double-sided electrode type semiconductor light emitting device and the semiconductor photodetection element will be described.

FIG. 2 shows the configuration of the double-sided electrode type semiconductor light emitting device 102. The semiconductor light emitting device 102 includes a semiconductor layer 1, a first electrode 2 formed on the first main surface of the semiconductor layer 1, and a second electrode 3 formed on the second main surface, and is composed of the electrode 2 and an electrode. When a voltage is applied from the power source 4 between the three, the light 6 is generated from the semiconductor layer 1.
Here, in order to increase the luminous efficiency, it is preferable to form a dielectric film on the wall surface 7 where the semiconductor layer 1 is exposed. The dielectric film can also function as a passivation film.

FIG. 3 shows the configuration of the double-sided electrode type semiconductor photodetector 103.
The semiconductor photodetection element 103 includes a semiconductor layer 1, a first electrode 2 formed on the first main surface of the semiconductor layer 1, and a second electrode 3a formed on the second main surface, and is the first main electrode. A voltage is applied by the power supply 4 between the first electrode 2 formed on the surface and the second electrode 3a formed on the second main surface. In the state where the light is not irradiated, almost no current flows, but when the semiconductor layer 1 is irradiated with the light 6, the current between the first electrode 2 and the second electrode 3a increases, and the current is monitored. It is configured to be detected by 5.
Here, an opening is formed in the electrode on the side that irradiates the light 6 (the second electrode 3a in the case of FIG. 3) so that the light 6 can sufficiently reach the semiconductor layer 1. Alternatively, as shown in FIG. 4, the second electrode 3b of the semiconductor photodetection element 104 is an electrode made of a transparent conductive material. In addition, a metal electrode having an opening formed on the transparent conductive material may be formed.

The inventor has conducted research on improving the S / N ratio of this type of semiconductor light emitting device and semiconductor photodetector when a semiconductor based on GaAs is used as the semiconductor layer 1. At the same time, we worked on improving the variation in characteristics between elements.
As a result, if a metal-containing electrode layer is formed without forming an alloy layer at the interface between the electrode layer and the semiconductor layer on both sides, and ohmic contact can be made with the electrodes on both sides, the S / N ratio is improved and the device It was found that the variation in characteristics between them is reduced.
When an alloy layer is formed at the interface between the electrode layer and the semiconductor layer, the light reflection effect of the metal-containing electrode becomes small, and a sufficient plasmon effect cannot be obtained, making it difficult to increase the signal (S).
Further, if it becomes a Schottky contact instead of an ohmic contact, it becomes a factor that limits the signal (S), and the noise (N), specifically, the dark current becomes large.
The S / N ratio can be improved only by forming a metal-containing electrode layer without an alloy layer, and the S / N ratio can be improved only by using the electrodes on both sides as ohmic contacts. The S / N ratio and characteristic variation were further improved by the synergistic effect instead of the simple sum.

However, in a double-sided electrode type semiconductor device, a photodetection element, and a light emitting element using a semiconductor based on GaAs, it has been difficult to form an alloy layer on both electrode surfaces and to make an ohmic contact.

In a semiconductor device based on an N-type GaAs semiconductor having a double-sided electrode structure, it is necessary to form an alloy layer by heat treatment (sintering) in order to realize ohmic contact on both sides of the semiconductor device and the double-sided electrode. The formation of the alloy layer causes deterioration of the optical properties as described above.
On the other hand, in the method in which this alloy layer does not form an alloy layer by heat treatment, a Schottky contact is formed between the semiconductor device and the electrode.

Hereinafter, the difficulty of forming an alloy layer on both electrode surfaces and making ohmic contact will be described in detail.

Si used as an N-type dopant for GaAs is an amphoteric dopant. Therefore, even if the doping amount of Si is increased, the number of carriers (number of donors) does not monotonically increase, and is saturated at a volume density of 5'10 ¹⁸ / cm ³ to 10'10 ¹⁸ / cm ³ (Non-Patent Documents). (Refer to 1 and 2), even if Si is added more, the number of carriers does not increase, but rather decreases.
Therefore, in order to form ohmic contacts on the Si-doped N-type GaAs layer, a metal material such as gold (Au) containing an element that becomes an N-type dopant when it enters GaAs such as germanium (Ge) and tin (Sn). Is adsorbed on a Si-doped N-type GaAs layer by vapor deposition or the like, and then alloyed (alloyed) with GaAs by heat treatment (sintering) (see Non-Patent Document 1). However, with this method, an alloy layer with insufficient crystallinity is formed at the interface between the metal and GaAs, so the characteristics of the device that utilizes the surface plasmon effect and the light reflection effect at the interface between the electrode and the semiconductor device are not particularly good. It will be enough.

As a method that does not require alloying by heat treatment, a method of forming a low-temperature GaAs layer on the outermost surface of the crystal growth layer has been reported (see Non-Patent Documents 3 and 4).
By using this method, ohmic contact can be realized without using heat treatment (sintering).
However, since the low-temperature GaAs layer is a layer containing excess arsenic and having insufficient crystallinity, it can be used for the outermost surface, which is the final stage of crystal growth, but this layer is on the opposite side of the surface. Cannot be used on the surface of. This is because when used on the opposite surface, highly complete crystals cannot be epitaxially formed on it. That is, the crystallinity and quality of the semiconductor layer 1 cannot be made sufficient.
Therefore, this method of forming the low temperature GaAs layer is not suitable as a method of making ohmic contact with the electrodes on both sides with respect to the semiconductor layer 1 based on GaAs.

As another method that does not require alloying by heat treatment, a method of doping ultra-high concentration Si (equivalent to 2 × 10 ²⁰ / cm ³ ) has been reported (see Non-Patent Document 5).
This method does not cause the problem of crystallinity as in the case of the low temperature GaAs layer. However, the inventor has found that ohmic contact cannot be formed on the side where the semiconductor layer is epitaxially grown thereafter because the excessively added Si significantly reduces the number of carriers (number of donors).
Therefore, this method using ultra-high concentration Si is not suitable as a method of making ohmic contact with the semiconductor layer 1 based on GaAs on both electrodes.

In the quantum cascade laser, a method using a low-temperature growth GaAs on the side after forming the semiconductor layer is used, and a layer doped with Si (equivalent to 5 × 10 ¹⁸ / cm ³ ) is placed on the side where the semiconductor layer is epitaxially formed. The method used has been reported. However, with this method, it is difficult to realize ohmic contact with excellent characteristics on the side where the semiconductor layer is epitaxially formed, and in fact, it is reported in the literature that it is not an ohmic contact but a Schottky characteristic ( See Non-Patent Document 6).

However, as a result of detailed studies by the inventor, even in a semiconductor device based on an N-type GaAs semiconductor having a double-sided electrode structure, an alloy layer is not formed on both electrode surfaces and ohmic contact can be compatible, and the S / N ratio and the element can be achieved. It was confirmed that there is an effect of reducing interim variation.
The details will be described below.

When a semiconductor based on GaAs is used as the semiconductor layer 1, the light 6 generated from the semiconductor layer is infrared light due to the semiconductor band gap. Further, the light having the light receiving sensitivity of the semiconductor layer 1 is also infrared light.
In the present application, light having a wavelength of 0.7 μm or more and 1 mm or less is referred to as infrared light.

In the present embodiment, both the first main surface and the second main surface of the semiconductor layer have the structure shown in FIG. 1 so that ohmic contact can be made with the electrodes.

The core portion 101 of the semiconductor device of the present embodiment is a semiconductor layer 20 containing gallium (Ga) and arsenic (As), and a first interface formed in contact with an interface 11 which is the first main surface of the semiconductor layer 20. The second main surface of the first metal-containing layer 22 and the semiconductor layer 20 which are the first electrodes formed in contact with the interface 12 on the opposite side of the layer 21 and the semiconductor layer 20 of the first interface layer 21. The second interface layer 23 formed in contact with the interface 13 and the second metal-containing second electrode formed in contact with the interface 14 on the opposite side of the semiconductor layer 20 of the second interface layer 23. It consists of layers 24.

The semiconductor layer 20 is made of a material containing a single crystal semiconductor containing gallium (Ga) and arsenide (As) as a host, and at least one boundary portion of the semiconductor layer 20, that is, at least the boundary 11 or the boundary 13 of the semiconductor layer 20. At one boundary, it has the same crystal lattice as a GaAs single crystal. Further, in the case of a photoelectric conversion element, the semiconductor layer 20 has a pn junction and / or a heterojunction.
Specific examples of the semiconductor layer 20 include a laminated film of silicon (Si) -doped GaAs and AlGaAs (aluminum gallium arsenide) such as Al _0.3 Ga _0.7 As.
Here, the same crystal lattice as the GaAs single crystal means that the crystal type is the same as that of the GaAs single crystal, and the difference in the length of the lattice from the GaAs single crystal is within ± 1%.
It should be noted that GaAs is suitable for materials with a narrow bandgap such as antimony (Sb) at a level that does not impair crystallinity at at least one of the above-mentioned boundaries, specifically, at a level where the same crystal lattice as a GaAs single crystal can be obtained. It is also possible to replace the part. Examples of the substitution material include Sb and at least one substance selected from the group of Al, In, bismuth (Bi), nitrogen (N), and phosphorus (P).
The thickness of the semiconductor layer 20 can be 50 nm or more and 10 μm or less, but is not necessarily limited to this film thickness range.

The first interface layer 21 and the second interface layer 23 are N-type semiconductor layers, which are single crystals containing Ga and As, and are at least one of the first interface layer 21 and the second interface layer 23. The interface layer is made of a material having a volume density of Si of 6 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less. If the volume density of Si in at least one of the first interface layer 21 or the second interface layer 23 is less than 6 × 10 ¹⁸ / cm ³ , the number of carriers will be insufficient and ohmic contact will not be possible. A problem arises, and if it exceeds 3 × 10 ¹⁹ / cm ³ , the resistance becomes high and the ohmic contact cannot be obtained.
The thickness of the first interface layer 21 and the second interface layer 23 is preferably 5 nm or more and 1000 nm or less, when the thickness of the interface layer is defined as the thickness of the region having the highest concentration of Si. If the thickness of the interface is less than 5 nm, there is a problem that the number of carriers required for optical bonding is insufficient, and if it exceeds 1000 nm, free electron absorption by a large number of electrons in the interface layer and the semiconductor layer 20 and the first alloy are contained. There arises a problem that the optical characteristics are deteriorated due to a decrease in the photoelectric field caused by a large distance from the layer 22 and the second alloy-containing layer 24.

The first metal-containing layer 22 and the second metal-containing layer 24 are made of a metal-containing material, and the materials thereof are, for example, titanium (Ti), chromium (Cr), nickel (Ni), gold (Au), and the like. Platinum (Pt), Silver (Ag), Palladium (Pd), Tungsten (W), Copper (Cu), Itterbium (Yb), Samarium (Sm), Ittrium (Y), Terbium (Tb), Holmium (Ho), Terbium (Tm), gadolinium (Gd), erbium (Er), neodymium (Nd), scandium (Sc), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), vanadium (V), Selected from the group consisting of iron (Fe), molybdenum (Mo), terbium (Ru), cobalt (Co), rhodium (Rh), renium (Re), iridium (Ir), indium (In), and aluminum (Al). One or more metals, Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb , V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al, an alloy containing one or more metals selected from the group, Ti, Cr, Ni, Au, Pt, Ag, Pd, W, From Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al Compounds containing one or more metals selected from the group consisting of ITO (Indium Tin Oxide), AZO (Alluminium-topped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), IZO (Indium Zinc Oxide), IG Which of Zinc Oxide), ATO (Antimony Dopped Tin Oxide), FTO (Fluorine Dopped Tin Oxide), FZO (Fluorine Dopped Zinc Oxide), and TiN (Terbium Metal) can be mentioned.
Of these, Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Ru, Rh, and Al can be preferably used from the viewpoint of conductivity.
When the semiconductor device to be manufactured is an infrared detection element, transparent electrodes ITO, AZO, GZO, IZO, IGZO, ATO, FTO, and FZO can be preferably used as the electrode on the side irradiated with infrared rays. ..
By using the first metal-containing layer 22 and the second metal-containing layer 24 as a material containing a metal, the plasmon effect of the metal can be obtained, so that excellent optical properties can be obtained.

In the case of an infrared photodetector, when a metal material such as Au or Al is used for the metal-containing layer on the side to be irradiated with light, an opening is provided in the metal-containing layer so that the light reaches the semiconductor layer 20. Need to be.

The thickness of the first metal-containing layer 22 and the second metal-containing layer 24 is preferably 5 nm or more and 10 μm or less. When the thickness of the metal-containing layer is less than 5 nm, the resistance becomes high, and since it becomes thinner than the skin depth with respect to light, it loses its function as a good reflector and plasmon medium. If it exceeds 10 μm, the thickness of the semiconductor device becomes thick. Further, in the case of an infrared photodetector, when the metal-containing layer on the side irradiated with light becomes thick, the light received is taken into the semiconductor layer 20 due to the influence of the shadow and diffraction of the high metal-containing wall at the electrode opening. There is also the problem that the amount is small.

It is required that no alloy layer is formed at the interface 12 between the first interface layer 21 and the first metal-containing layer 22 and the interface 14 between the second interface layer 23 and the second metal-containing layer 24. As described in the manufacturing method, no special heat treatment is required after the first metal-containing layer 22 and the second metal-containing layer 24. Therefore, in this structure, the alloy layer is not formed at the interface 12 and the interface 14. Can be done.
The smaller the diffusion of the metal contained in the first metal-containing layer 22 into the first interface layer 21 and the diffusion of the metal contained in the second metal-containing layer 23 into the second interface layer 23, the more preferable. The thickness of the diffusion layer of the metal is defined by the region width in which the diffusion amount of the metal is 1 / e, and is preferably 0 nm or more and 3 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and 0.5 nm or less. More preferred. If the thickness of the diffusion layer of the metal exceeds 3 nm, problems such as a decrease in the plasmon effect of the metal occur.

According to this structure, the semiconductor layer 20 has ohmic contact with both the first electrode 22 and the second electrode 24, and the first electrode 22 and the second electrode 24 do not form an alloy layer on the semiconductor surface side. Become. Therefore, the S / N ratio is excellent, and the variation between manufactured elements is small. Since a steep metal interface is formed, the optical characteristics are also improved.
On top of that, the semiconductor layer 20 is of high quality with few defects because epitaxial growth with high single crystallinity can be performed while suppressing metal diffusion.
Further, since metal diffusion is not used at the contact portions between the semiconductor layer 20 and the first and second electrodes 22 and 24, there is an effect that it can be applied to an extremely thin device.
Further, since the resistance between the first interface layer 21 and the first metal-containing layer 22 and the resistance between the second interface layer 23 and the second metal-containing layer 24 are both lowered, the element characteristics such as power consumption are improved. ..

<Manufacturing method>
Next, the first manufacturing method of the semiconductor device 105 of the present embodiment will be described with reference to FIGS. 5 to 7.

The upper limit of the number of N-type carriers in a commercially available GaAs single crystal substrate is approximately 3 × 10 ¹⁸ / cm ³ , and it is difficult to form ohmic contacts without heat treatment for a GaAs substrate having this number of carriers. be. Therefore, the structure of the semiconductor device core portion 101 shown in FIG. 1 is manufactured by crystal growth on the GaAs single crystal substrate with the sacrificial layer interposed therebetween, and then the GaAs single crystal substrate and the sacrificial layer are removed by etching. (See FIG. 5 (a)).

First, a substrate 31 having sufficient rigidity is prepared, and a buffer layer 32 and a sacrificial layer 33 responsible for surface flattening are sequentially formed on the substrate 31.

The substrate 31 can be used as long as it has sufficient rigidity and a semiconductor layer based on GaAs can be epitaxially formed on the substrate 31. However, in order to improve the quality of the GaAs-based semiconductor layer formed thereafter, it is preferable to use a GaAs substrate.

The material of the buffer layer 32 is not specified as long as its surface can be sufficiently flattened and smoothed, but a GaAs film is used in order to improve the quality of the GaAs-based semiconductor layer to be formed thereafter. Is preferable.
Examples of the method for producing the buffer layer 32 include MBE (Molecular Beam Epitaxy), MOCVD (MetalOrganic Vapor Deposition), MOPVE (MetalOrganic Vapor Phase Epitaxy), HDPE (HVPE), and HVPE (HVPE). It can be mentioned, but it is not limited to these.
The thickness of the buffer layer 32 is not particularly limited, but may be, for example, 50 nm or more and 1000 nm or less.

The sacrificial layer 33 is a film having an etching rate higher than that of GaAs, and AlGaAs, in particular, AlGaAs having an Al composition ratio of 50% or more and 100% or less can be preferably used. This is because AlGaAs having an Al composition ratio can be easily removed by wet etching with an aqueous solution of hydrofluoric acid.
Examples of the method for producing the sacrificial layer 33 include MBE (Molecular Beam Epitaxy), MOCVD (MetalOrganic Vapor Deposition), MOPVE (MetalOrganic Vapor Phase Epitaxy), HDPE (HVPE), and HVPE (HVPE). It can be mentioned, but it is not limited to these.
The thickness of the sacrificial layer 33 is not particularly limited, but may be, for example, 500 nm or more and 2000 nm or less.

Next, the first interface layer 21 is formed on the sacrificial layer 33 (see FIG. 5B).
The first interface layer 21 is a single crystal containing Si-doped Ga and As and is an N-type material, and the Si-doped amount is 6 × 10 ¹⁸ / cm ³ or more in terms of volume content 3 ×. 10 ¹⁹ / cm ³ or less.
Examples of the film forming method for the first interface layer 21 include, but are not limited to, MBE, MOCVD, MOPVE, HVPE, and LPE. However, it is necessary to epitaxially form the first interface layer 21 so that the upper surface of the first interface layer 21 has the same crystal lattice as the GaAs single crystal.

The first interface layer 21 is formed as a laminated film containing Si, and Si is further δ-doped at each stage of stacking the laminated film, which is 6 × 10 ¹⁸ / cm ³ or more 3 × 10 ¹⁹ /. It is preferable for doping Si having a high concentration of cm ³ or less. For example, a GaAs film containing 5 × 10 ¹⁸ / cm ³ in volume of Si is formed at 4 nm, and then Si is δ-doped at a concentration of 3 × 10 ¹² / cm ² to form the first Si-containing GaAs film. The Si-containing GaAs laminated film formed by repeating the formation a plurality of times, for example, 7 times is referred to as a second interface layer 23.
Here, the temperature at which the first interface layer 21 is formed is preferably 300 ° C to 550 ° C.
The thickness of the first interface layer 21 is preferably 5 nm or more and 1000 nm or less.

After that, the semiconductor layer 20 is formed on the first interface layer 21 (see FIG. 5C).
The semiconductor layer 20 is a semiconductor layer containing Ga and As, and the boundary portion of the semiconductor layer 20 in contact with the first interface layer 21 is made of a single crystal semiconductor having the same crystal lattice as a GaAs single crystal.
The semiconductor layer 20 is preferably epitaxially formed by a method such as MBE, MOCVD, MOPVE, HVPE, or LPE.
As the semiconductor layer 20, a laminated film can be preferably used, but a single-layer film can also be used. When a photoelectric conversion element is manufactured using a single-layer film, a distribution of impurities is created to form a pn junction in the semiconductor layer 20.
When the semiconductor layer 20 is used as a laminated film, for example, a plurality of combinations of a Si-doped GaAs layer, an undoped GaAs layer, and an AlGaAs layer are laminated by the MBE method.

The temperature at which the semiconductor layer 20 is formed is preferably 300 ° C. or higher and 580 ° C. or lower, and more preferably 300 ° C. or higher and 550 ° C. or lower. When the temperature is in this range, the specific contact resistance between the first metal-containing layer and the semiconductor layer 20 to be formed after that can be reduced.
Further, the time for epitaxially forming the semiconductor layer 20 is preferably 2 minutes or more and 48 hours or less. If the epitaxial formation time is less than 2 minutes, the growth rate becomes excessive and it becomes difficult to epitaxially form a sufficiently crystalline semiconductor layer, and if it exceeds 48 hours, it is simply a waste of time and the manufacturing throughput is reduced. Decrease.

After that, the second interface layer 23 is formed on the semiconductor layer 20 (see FIG. 5D).
The second interface layer 23 is a single crystal containing Ga and As and is made of an N-type material.
Examples of the film forming method for the second interface layer 23 include, but are not limited to, MBE, MOCVD, MOPVE, HVPE, and LPE.

The second interface layer 23 is preferably doped with Si of 6 × 10 ¹⁸ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less in terms of volume content.
Further, the second interface layer 23 is preferably epitaxially formed at a temperature of 150 ° C. or higher and 300 ° C. or lower.
When the temperature of Si dope and epitaxial formation is within this range, the electrical contact characteristics between the second metal-containing layer 24 and the semiconductor layer 20 that are subsequently formed become more ohmic and specific contact. The resistance will be small.
The second interface layer 23 may be formed as a laminated film containing Si, and Si may be further δ-doped at each stage of stacking the laminated film. For example, a GaAs film containing 5 × 10 ¹⁸ / cm ³ in volume of Si is formed at 4 nm, and then Si is δ-doped at a concentration of 3 × 10 ¹² / cm ² to form the first Si-containing GaAs film. The Si-containing GaAs laminated film formed by repeating the formation a plurality of times, for example, 7 times is referred to as a second interface layer 23.
The thickness of the second interface layer 23 is preferably 5 nm or more and 1000 nm or less.

Then, the second metal-containing layer 24 is formed on the second interface layer 23 (see FIG. 6A).
The second metal-containing layer 24 is made of a material containing a metal, and specifically, Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm. , Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al, one or more metals selected from the group, Ti, Cr. , Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru , Co, Rh, Re, Ir, In, Al alloys containing one or more metals selected from the group consisting of Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, One or more selected from the group consisting of Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al. A compound containing a metal and any one of ITO, AZO, GZO, IZO, IGZO, ATO, FTO, FZO, and TiN can be mentioned.
The second metal-containing layer 24 may be a single-layer film or a laminated film.
Examples of the method for forming the second metal-containing layer 24 include a DC and RF sputtering method, a heat vapor deposition method, an electron beam vapor deposition method, a MOCVD method, and the like, but the method is not limited to these methods and is electrically conductive. Any forming method having excellent adhesion and surface flatness can be used.
Here, it is preferable not to use a special heat treatment in forming the second metal-containing layer 24 from the viewpoint of preventing the formation of the alloy layer.

Then, the sample is turned upside down, and the sample is bonded onto the substrate 40 so that the second metal-containing layer 24 is in contact with the substrate (see FIG. 6 (b)).
Examples of the bonding method include the Au-Au diffusion bonding method.
In this method, for example, Ti having a thickness of 10 nm and Au having a thickness of 500 nm are laminated and formed on the substrate 40. At least the surface side of the second metal-containing layer 24 is set to Au, and both are brought into pressure contact with each other under heating. As the conditions, for example, a pressurization of 5 to 10 MPa and a temperature of 250 to 330 ° C. for 1 hour can be mentioned.
Here, in order to reduce the stress generated at this time, it is also preferable to continuously apply the heat treatment under the same conditions under no pressurization. Further, the substrate 40 is preferably a GaAs substrate in consideration of the thermal expansion rate. In the heat treatment at 330 ° C., Ti may become a barrier, and an alloy layer is not formed between the second metal-containing layer 24 and the second interface layer 23.
As a second bonding method, an epoxy bonding method or the like can be mentioned.
In the epoxy bonding method, an epoxy adhesive is dropped onto the substrate 40, and the second metal-containing layer 24 and the substrate 40 are pressure-bonded under heating. Examples of this condition include pressurization of 1 to 5 MPa and a temperature of 150 ° C. for 1 hour. Here, in order to reduce the stress generated at this time, it is also preferable to continuously apply the heat treatment under the same conditions under no pressurization. Further, the substrate 40 is preferably a GaAs substrate in consideration of the thermal expansion rate. In the heat treatment at 150 ° C., Ti may become a barrier, and an alloy layer is not formed between the second metal-containing layer 24 and the second interface layer 23.
In addition, as other bonding methods, eutectic bonding (soldering, silver wax bonding), anode bonding, surface activation bonding (clean the surface with Ar ⁺ ions under ultra-high vacuum and bond at room temperature) , Diffusion bonding using Au fine particles and the like can also be mentioned.

The substrate 40 can be used as long as it has sufficient rigidity and its surface has flatness and smoothness suitable for bonding. For example, as the substrate 40, a GaAs substrate, a Si substrate, an InP substrate, a sapphire substrate, a synthetic quartz glass, a glass substrate such as borosilicate glass and soda lime glass, a ceramics substrate such as alumina and silicon nitride, acrylic and polystyrene (PS), Examples thereof include organic material substrates such as polypropylene (PP), polyethylene terephthalate (PET), and polycarbonate (PC), and metal substrates such as aluminum, iron, stainless steel, and copper. Among these, the GaAs substrate can be preferably used from the viewpoint of making the thermal expansion rate uniform.

After that, the substrate 31 is removed by etching, and subsequently, the buffer layer 32 is also removed by etching (see FIG. 6 (c)). These etchings may be mechanical polishing, wet etching, or dry etching. For example, the substrate 31 in the case of a GaAs substrate can be easily wet-etched and removed with a citric acid solution.

After that, the sacrificial layer 33 is removed by etching (see FIG. 7A). This etching may be wet etching or dry etching. For example, when the sacrificial layer 33 is made of AlGaAs, it can be easily removed by wet etching with an aqueous solution of hydrofluoric acid.

After that, the first metal-containing layer 22 is formed on the exposed first interface layer 21, and the semiconductor device 105 is manufactured (see FIG. 7 (b)).
The first metal-containing layer 22 is made of a material containing a metal, and specifically, Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm. , Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al, one or more metals selected from the group, Ti, Cr. , Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru , Co, Rh, Re, Ir, In, Al alloys containing one or more metals selected from the group consisting of Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, One or more selected from the group consisting of Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al. A compound containing a metal and any one of ITO, AZO, GZO, IZO, IGZO, ATO, FTO, FZO, and TiN can be mentioned.
The first metal-containing layer 22 may be a single-layer film or a laminated film. For example, it may be an Au / Ti two-layer film.
Examples of the method for forming the first metal-containing layer 22 include a DC and RF sputtering method, a heat vapor deposition method, an electron beam vapor deposition method, a MOCVD method, and the like, but the same as the method for forming the second metal-containing layer 24. However, it is not limited to these methods.
Here, it is preferable not to use a special heat treatment in forming the first metal-containing layer 22 from the viewpoint of preventing the formation of the alloy layer.

In the above method, the method of directly bonding the second metal-containing layer 24 on the substrate 40 has been described. However, the temporary bonding layer is formed on the substrate 40, and the substrate 40 and the second metal layer 24 are formed via the temporary bonding layer. A so-called temporary bonding method in which the metal-containing layers 24 are bonded together can also be used.
In this temporary bonding method, after preparing a sample by the above procedure up to the stage of FIG. 7B, the sample is turned upside down and the sample with the first metal-containing layer 22 facing down is pasted on a new substrate. match. After that, the substrate 40 and the temporary bonding layer are removed. Here, examples of the temporary bonding layer include organic materials such as an epoxy adhesive that peels off with warm water, an adhesive that peels off with a shearing force or an impact force, and an adhesive that peels off with laser light irradiation.
According to this temporary bonding method, the first metal-containing layer 22 can be formed on the substrate side, that is, on the lower side.

Further, in the above method, a method of bonding the substrate 40 to the second metal-containing layer 24 and then removing the substrate 31 to manufacture the semiconductor device 105 is shown, but the second interface layer 23 is formed. Later, there is also a method of wet-etching the sacrificial layer 33 to manufacture a semiconductor device.

This method will be described with reference to FIGS. 8 to 10.
After forming the second interface layer 23 by the above method, as shown in FIG. 8A, the sacrificial layer 33 is wet-etched to prepare a structure 106, and the structure 106 to the first interface layer are formed. The core unit 60 shown in FIG. 8B, which is composed of 21, the semiconductor layer 20 and the second interface layer 23, is cut out (diced).

Then, the core unit 60 is turned upside down and attached on the substrate on which the second metal-containing layer 51 is formed on the substrate 41 (FIG. 9A), and then the first surface layer 21 is attached. The metal-containing layer 52 of the above is formed to manufacture a semiconductor device 107 (FIG. 9 (b)).
Alternatively, the core unit 60 is attached to the substrate on which the first metal-containing layer 53 is formed on the substrate 42 with the first interface layer 21 as the lower surface (FIG. 10A), and then the second interface layer 23 is attached. A second metal-containing layer 54 is formed on the semiconductor device 108 (FIG. 10 (b)).
Therefore, in the semiconductor device of the present invention, the first interface layer 21 may be on the upper surface side or the lower surface side with respect to the semiconductor layer 20.

Here, the substrates 41 and 42 can be used as long as they have sufficient rigidity like the substrate 40 and the surface thereof has flatness and smoothness suitable for bonding. For example, as the substrates 41 and 42, GaAs substrate, Si substrate, InP substrate, sapphire substrate, synthetic quartz glass, borosilicate glass, glass substrate such as soda lime glass, ceramics substrate such as alumina and silicon nitride, acrylic and polystyrene (PS). ), Organic material substrates such as polypropylene (PP), polyethylene terephthalate (PET), polycarbonate (PC), and metal substrates such as aluminum, iron, stainless steel, and copper.
Further, the first metal-containing layers 52 and 53 may be formed in the same manner as the first metal-containing layer 22, and the second metal-containing layers 51 and 54 may also be formed of the second metal-containing layer 24. The same thing as the above may be formed by the same method.

The semiconductor device having the above structure is a double-sided electrode type semiconductor device based on a GaAs semiconductor with stable electrical characteristics. Further, the manufacturing method of the present embodiment makes it possible to provide a GaAs semiconductor-based double-sided electrode type semiconductor device having a small dark current, a high S / N ratio, and stable electrical characteristics.

Further, since the semiconductor devices 105, 107 and 108 have good photoelectric conversion characteristics with respect to infrared rays, in particular, a double-sided electrode type infrared detection element, an infrared light emitting element, and an infrared photoelectric conversion based on a GaAs semiconductor are used. It is possible to provide an element having a high S / N ratio and stable photoelectric conversion characteristics.

To reiterate, the double-sided electrode type semiconductor device based on the GaAs semiconductor of the present invention does not form an alloy layer at the interface between the double-sided electrode layer and the interface layer, and the electrodes on both sides are in ohmic contact. For this reason, it becomes possible to achieve both the reflection effect, plasmon effect, and ohmic contact, and with the addition of the synergistic effect, a double-sided electrode type based on a GaAs semiconductor with excellent performance, which is not the conventional Schottky contact. It becomes possible to provide the semiconductor device of.

Hereinafter, the present invention will be described in more detail by way of examples, but these examples are given here only for the purpose of assisting the understanding of the present invention, and the present invention is not limited thereto.

(Example 1)
Example 1 is an example relating to a method for forming the first interface layer 21.
In Example 1, a simulated layer 71 in which the semiconductor layer 20 and the second interface layer 23 are simplified into one layer of Si-doped GaAs, two layers of undoped GaAs, and one layer of Al _0.3 Ga _0.7 As. The sample used was prepared, and the contact resistance characteristics between the first metal-containing layer 22 and the simulated layer 71 via the first interface layer 21 were evaluated. Here, FIG. 11 shows the structure of the sample at the stage corresponding to FIG. 5 (d) and the heat treatment conditions up to that point.

First, the GaAs (100) substrate 31 was prepared, and then the oxide film on the surface of the GaAs substrate 31 was removed by heating at 580 ° C. Then, a GaAs buffer layer 32 for surface flattening was grown to a thickness of 300 nm using a molecular beam epitaxial forming apparatus (COMPACT21T, manufactured by RIBER). Here, the subsequent films containing Ga and As were formed using the same molecular beam epitaxial device.
After that, an AlGaAs sacrificial layer 33 having an Al composition of 55% was formed to a thickness of about 1 μm. The formation temperature at this time is 580 ° C.
Subsequently, as shown in FIG. 11, a total of 7 layers including Ga and As were formed as the first interface layer 21.

The first interface layer 21 is a total of 28 nm-thick Si-doped GaAs in which a total of 7 layers of 4 nm-thick Si-doped GaAs (Si: 5 × 10 ¹⁸ / cm ³ ) are laminated, and each time each layer is formed, Si is formed. Was δ-doped 7 times in total at 3 × 10 ¹² / cm ² . As a result, the volume density of Si in the first interface layer 21 is 1.25 × 10 ¹⁹ / cm ³ . The temperature at which this layer is formed is 530 ° C.
The first interface layer 21 is a single crystal N-type GaAs doped with Si at the above volume density. Further, the portion of the simulated layer 71 in contact with the first interface layer 21 is a Si-doped GaAs single crystal.

Then, GaAs with a thickness of 15 nm and a volume content of Si of 3 × 10 ¹⁸ / ^cm3 , undoped GaAs with a thickness of 10 nm, Al _0.3 Ga _0.7 As with a thickness of 300 nm and a thickness of 300 nm. Undoped GaAs of 700 nm was sequentially laminated to form a simulated layer 71 composed of these four layers on the first interface layer 21.
The temperature of film formation at this time was 530 ° C. up to the Si-doped GaAs film and the undoped GaAs film having a thickness of 10 nm. An Al _0.3 Ga _0.7 As film having a thickness of 300 nm and an undoped GaAs film having a thickness of 700 nm were formed at a temperature of 580 ° C. for about 1 hour.

Then, the substrate was turned upside down, the upper surface of the simulated layer 71 was attached to the substrate made of GaAs, and the GaAs substrate 31 and the buffer layer 32 were selectively removed by mechanical polishing and a citric acid solution.
Subsequently, the AlGaAs sacrificial layer 33 is selectively removed with an aqueous hydrofluoric acid solution, and a two-layer film composed of Au having a thickness of 100 nm and a Ti film having a thickness of 3 nm is formed on the first interface layer 21 exposed on the surface. A sample was prepared by forming the metal-containing layer 22 by a vacuum vapor deposition method.

Next, when the bonding characteristics of the interface layer 21 and the first metal-containing layer 22 were examined by the transmission line method, it was found that the specific contact resistance was 1.7 × 10 ^-1 Ωcm ² at room temperature.
The current-voltage characteristic between the two electrodes became a nearly linear characteristic as shown in FIG. From this, it was found that ohmic contact can be obtained by the first interface layer 21 without any special heat treatment.

(Comparative Example 1)
Comparative Example 1 is an example in which the amount of Si doping at the time of forming the first interface layer 21 is made very high according to Non-Patent Document 5.

FIG. 13 is a schematic cross-sectional view showing the structure of the sample main part at the production stage corresponding to FIG. 11 of Example 1. Here, the structure around the interface layer 21 does not change even when the sample preparation is completed. The sample of Comparative Example 1 was prepared in the same manner as in Example 1 except that the first interface layer 21 was changed as follows.
The first interface layer 21 is a total of 30 nm-thick Si-doped GaAs in which a total of 15 layers of 2 nm-thick Si-doped GaAs (Si: 5 × 10 ¹⁸ / cm ³ ) are laminated, and each time each layer is formed, Si is formed. Was δ-doped 15 times in total at 1 × 10 ¹³ / cm ² . As a result, the volume density of Si in the first interface layer 21 is 5.5 × 10 ¹⁹ / cm ³ . The temperature at which this layer is formed is 530 ° C.

Next, when the bonding characteristics of the first metal-containing layer and the simulated layer via the interface layer 21 were examined by the transmission line method, it became clear that they were Schottky contacts as shown in FIG. 14, and the specific contact resistance. Was unmeasurable.
From this, if the volume content of Si doped in the first interface layer 21 is as large as 5.5 × 10 ¹⁹ / cm ³ , on the interface layer (first interface layer 21) side, ohmic contact is formed. It was confirmed that it should not be.

(Example 2)
Example 2 relates to the effect of the formation temperature of the crystal layer after the growth of the first interface layer 21.
There, the formation of the crystal layer after the growth of the first interface layer 21, that is, the case where the formation temperature of a part of the simulated layer 71 is set to 580 ° C and the case where all the formation temperatures are unified at 530 ° C are compared, and the ratio is the same. The effect on contact resistance was evaluated. The formation time of the simulated layer 71 is 1 hour and 20 minutes when a part of the simulated layer 71 is formed at 580 ° C., and 1 hour and 16 minutes when all of the simulated layer 71 is formed at 530 ° C. For reference, FIG. 15 shows the structure and process conditions of the sample main part at the same manufacturing stage as in FIGS. 11 and 13.

When the bonding characteristics of the first metal-containing layer and the simulated layer via the interface layer 21 were investigated by the transmission line method, the specific contact resistance at room temperature was shown in the figure in which the formation temperature of a part of the simulated layer 71 was 580 ° C. In the case of 16, it was 1.7 × 10 ^-1 Ωcm ² , and in the case of FIG. 17, where all the formation temperatures of the simulated layer 71 were 530 ° C, it was 2 × 10 ^-2 Ωcm ² . By setting the temperature to 530 ° C, it was possible to improve by an order of magnitude. The current-voltage characteristics between the two electrodes (between the first metal-containing layer electrodes) were completely linear as shown in FIGS. 16 and 17. From the above, it was confirmed that it is preferable to keep the substrate temperature low after the first interface layer 21 is formed.

(Example 3)
Example 3 is an example of manufacturing an infrared detection element.
FIG. 18 shows a schematic diagram of the structure of the infrared detection element 109 in a cross-sectional view, and FIG. 19 shows the structure of the sample main part at the same manufacturing stage as in FIGS. 11, 13, and 15.
In Example 3, the semiconductor layer 20 and the second interface layer 23 were used instead of the simulated layers 71 of Examples 1 and 2. The first interface layer 21 has the same structure as the interface layer shown in Example 2, the second interface layer 23 has a structure symmetrical to that of the first interface layer 21, and the process is also the same. As shown in FIG. 18, the semiconductor layer 20 is a laminated film of a single crystal film containing Ga and As consisting of 10 layers. The semiconductor layer 20 at the boundary portion in contact with the first interface layer 21 and the second interface layer 23 is GaAs doped with Si at both boundaries.
The first metal-containing layer 22 forming the first wiring is composed of Au having a thickness of 150 nm and Ti having a thickness of 3 nm.
The second metal-containing layer 24 forming the second wiring is made of a metal-containing layer 24a composed of Au having a thickness of 500 nm and Ti having a thickness of 10 nm, Ti having a thickness of 3 nm, and Au having a thickness of 150 nm. It is composed of a metal-containing layer 24b. Here, Ti is formed for the purpose of improving the adhesion and suppressing the diffusion of the metal containing Au into the first and second interface layers.
The substrate 40 was a GaAs substrate.

The manufacturing process of the infrared detection element 109 conforms to the manufacturing method of the first embodiment, and is manufactured by the process from FIG. 5 to FIG. 7.

In Example 3, the specific contact resistance at the stage where the metal-containing layer (Au / Ti) was first formed on the second interface layer 23 ((a) in FIG. 6) was evaluated. As a result, at a liquid nitrogen temperature (77K) where the specific contact resistance was higher than room temperature, a specific contact resistance of 5.8 × 10 ^-4 Ωcm ² was observed, and ohmic contact was realized.
Subsequently, a metal-containing layer (Au / Ti) was formed by exposing the first interface layer 21 by a process, and the state of electrical contact thereof was investigated. As a result, the specific contact resistance at the liquid nitrogen temperature (77K) was found. It was 5.8 × 10 ^-3 Ωcm ² , which was a significant improvement from Example 2.
In this sample, the growth time of the upper layer after growing the first interface layer 21 is shortened from 1 hour in Example 2 to 30 minutes or less. Therefore, it was found that a short time for the first interface layer 21 to be substantially heat-treated is useful for improving the specific contact resistance characteristics.
The current-voltage characteristics of the first interface layer 21 and the second interface layer 23 at the liquid nitrogen temperature are shown in FIGS. 20 and 21, respectively. Ohmic contact is realized on both sides.

Next, the above-mentioned second metal layer 24 composed of Ti and Au is formed on the second interface 23, Au-Au bonding is performed at a temperature of 330 ° C., and a sample at the stage of being bonded to the substrate 40 is prepared. Then, the interface between the second metal layer 24 and the second interface layer 23 was evaluated by a secondary ion mass spectrometer (SIMS). The evaluated location is the region above 50 nm-Al _0.3 Ga _0.7 As, which is the second from the top of the semiconductor layer 20 shown in FIG.
The result is shown in FIG. The diffusion of Ti into the second interface 23 was about 0.5 nm, and it was confirmed that almost no alloy layer was formed between the second interface layer 23 and the second metal layer 24.
When the first metal layer 22 is formed on the first interface layer 21, heat treatment (sintering) is not performed, so that the diffusion of Ti to the first interface 21 is further suppressed and the first interface is formed. No further alloy layer is formed between the layer 21 and the first metal layer 22.

Next, the infrared light receiving characteristics of the infrared detection element 109 at a temperature of 77K were investigated. The measurement was performed by a Fourier transform infrared spectrophotometer (FTIR). FIG. 23 shows the photoelectric conversion response characteristics with respect to the wavelength of infrared rays. The applied voltage is +0.60V. Good photoelectric conversion characteristics with high detection sensitivity were obtained with a peak wavelength of about 7 μm. The dark current was 0.51 μA, which was a good value. Therefore, the infrared detection element 109 manufactured in Example 3 has an extremely good S / N ratio.

In Example 3, five samples were prepared under the same conditions, and variations in their electrical characteristics were measured and evaluated.
FIG. 24 shows the results of measuring the voltage current density characteristics between the first electrode (first metal-containing layer 22) and the second electrode (second metal-containing layer 24) at a temperature of 77 K. It is plotted in two figures. It can be seen that the plotted characteristic curves overlap, and the current-voltage characteristics of the five samples are almost the same, and the infrared detection element 109 with extremely little characteristic variation is obtained.
In a double-sided electrode type infrared detection element using a GaAs-based semiconductor layer 20, by making both electrode surfaces ohmic contacts, it is possible to stably provide an element with extremely little variation in electrical characteristics, in other words, a highly accurate element. confirmed.

(Comparative Example 2)
Comparative Example 2 is an example of manufacturing an infrared detection element, in which the first interface layer 21 and the second interface layer 23 are formed by the same structure and manufacturing method as in Comparative Example 1. Other structures and processes were the same as in Example 3.
Therefore, the first interface layer 21 and the second interface layer 23 have a volume content of doped Si of 5.5 × 10 ¹⁹ / cm ³ . Therefore, Example 3 except that the electrical contact between the semiconductor layer 20 and the first electrode and the second electrode via the first interface layer 21 and the second interface layer 23 is a Schottky contact. It is an infrared detection element having the same structure as.

FIG. 25 shows the photoelectric conversion response characteristics to the wavelength of infrared rays at the temperature of 77K of the manufactured infrared detection element. The applied voltage is + 0.73V. Photoelectric conversion characteristics with a peak wavelength of about 7 μm were obtained, but the responsiveness, for example, the responsiveness at a wavelength of around 7 μm was about 20% lower than that of the device manufactured in Example 3, and the dark current was 2.92 μA, which was a leaky characteristic. there were. Therefore, the element of Comparative Example 2 has a significantly smaller S / N ratio than the element of Example 3 in which the electrodes on both sides form ohmic contacts and the alloy layer is not formed on both sides at the interface with the interface layer. It was confirmed that.

Further, similarly to Example 3, the current-voltage characteristics between the first electrode (first metal-containing layer 22) and the second electrode (second metal-containing layer 24) at a temperature of 77 K were measured. The result is shown in FIG. Five samples were plotted together, but the plotted characteristic curves were different, and it was found that the characteristics varied.
It was confirmed that in the double-sided electrode type infrared detection element using the GaAs-based semiconductor layer 20, if both electrode surfaces are not ohmic contacts, the electrical characteristics vary and the dark current also increases.

(Example 4)
In Example 4, the relationship between the amount of Si doping and the contact resistance characteristics was investigated.

The specific contact resistance strongly depends on the number of carriers in the boundary layer, and as disclosed in Non-Patent Document 8, generally, the higher the value, the better the value.
Therefore, first, the dependence of the number of effective carriers on the Si doping concentration was investigated.
As shown in FIG. 27, which shows the structure of the main part of the sample at the same production stage as in FIG. 11, a sample in which the doping concentration of Si was changed in the first interface layer 21 was prepared, and the number of carriers actually activated. Was measured by Hall effect measurement.

A plot of the concentration of doped Si and the actually measured carrier density is shown in FIG. Here, in calculating this carrier density, the number of carriers estimated to be contained in N-GaAs having a Si volume density of 2 × 10 ¹⁸ / cm ³ and a thickness of 15 nm is 4.5 × 10 ¹² / cm ² . There is.
As can be seen from the figure, when the Si doping concentration is increased, the carrier density increases at first, but reaches a maximum near 1.5 × 10 ¹⁹ / cm ³ and then decreases.
In order to realize ohmic contact, it is necessary to improve at least an order of magnitude from the specific contact resistance of the carrier density of 5 × 10 ¹⁸ / ^cm3 , which has been reported in the past, and for that purpose, the carrier density is 5.6 × 10 ¹⁸ / Cm ³ or more must be achieved. From this, the density of Si to be doped needs to be 6 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less.

Next, the relationship between the Si doping density and the ohmic contact and specific contact resistance was investigated by direct experiments.
There, as shown in FIG. 29 showing the structure of the sample main part at the same production stage as in FIG. 11, a sample in which the doping concentration of Si was changed in the first interface layer 21 was prepared and examined.
The results of the investigation at room temperature (23 ° C.) are shown in FIG.
As can be seen from FIG. 30, the range of the Si doping density at which ohmic contact can be obtained in the first interface layer 21 was 6 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less. However, it was found that the preferred range of Si doping density for lowering the specific contact resistance was 6 × 10 ¹⁸ / cm ³ or more and 2 × 10 ¹⁹ / cm ³ or less.

(Example 5)
In Example 5, the effect of having a uniform distribution of Si doping amount was investigated.
There, as shown in FIG. 31, which shows the structure of the sample main part at the same manufacturing stage as in FIG. 11, the doping concentration (volume density) of Si in the first interface layer 21 is set in the first interface layer 21. A uniform 1.25 × 10 ¹⁹ / cm ³ was used.
Next, when the electrical contact characteristics between the first metal-containing layer and the simulated layer via the first interface layer 21 were examined by the transmission line method, the specific contact resistance was 8 × 10 ^-3 Ωcm ² . I understood. This value is superior to the case where the volume density of Si in the first interface layer is 1.25 × 10 ¹⁹ / cm ³ using δ dope.
The current-voltage characteristic between the two electrodes became a nearly linear characteristic as shown in FIG. 32. From this, it was found that the doping of Si to the first and / and the second interface layer is not limited to the one having a spatial distribution using the δ doping, and may be a uniform distribution.

INDUSTRIAL APPLICABILITY According to the present invention, it becomes possible to provide a semiconductor device having electrical characteristics with little variation, particularly an infrared detection element, an infrared light emitting element, and an infrared photoelectric conversion element having photoelectric conversion characteristics with little variation.
Demand for highly accurate infrared detection elements and infrared light emitting elements is very high. For example, one of the key technologies for autonomous driving and drive safety is highly accurate infrared photodetection and infrared emission, and the present invention can be widely used in industry including such fields. Be expected.

1: Semiconductor layer 2: First electrode 3: Second electrode 3a: Second electrode 3b: Second electrode (transparent electrode)
4: Power supply 5: Monitor 6: Light 7: Wall surface 11, 12, 13, 14: Interface 20: Semiconductor layer 21: First interface layer 22: First metal-containing layer (first electrode)
23: Second interface layer 24: Second metal-containing layer (second electrode)
24a: Metal-containing layer 24b: Metal-containing layer 31: Base 32: Buffer layer 33: Sacrificial layer 40, 41, 42: Base 51: Second metal-containing layer 52: First metal-containing layer 53: First metal Containing layer 54: Second metal-containing layer 60: Core unit 71: Simulated layer 101: Semiconductor device core part 102: Semiconductor light emitting device 103, 104: Semiconductor photodetection device 105: Semiconductor device 106: Structure 107, 108: Semiconductor Device 109: Infrared detection element

Claims (14)

A first electrode containing a metal is formed on the first main surface of a single crystal semiconductor layer containing Ga and As via a first interface layer, and a second main surface containing a metal is contained in the second main surface of the semiconductor layer. Is a semiconductor device in which the electrodes of the above are formed via the second interface layer.
The first interface layer and the second interface layer are N-type semiconductor layers, which are single crystals containing Ga and As.
At least one boundary portion of the first interface layer or the semiconductor layer in contact with the second interface layer has the same crystal lattice as a GaAs single crystal.
The first interface layer and the first electrode, and the second interface layer and the second electrode make ohmic contact.
The thickness of the metal diffusion layer forming the first electrode formed at the interface between the first interface layer and the first electrode, and the thickness of the second interface layer and the second electrode. A semiconductor device in which the thickness of the metal diffusion layer forming the second electrode formed at the interface is 3 nm or less. A first electrode containing a metal is formed on the first main surface of a single crystal semiconductor layer containing Ga and As via a first interface layer, and a second main surface containing a metal is contained in the second main surface of the semiconductor layer. Is a semiconductor device in which the electrodes of the above are formed via the second interface layer.
The first interface layer and the second interface layer are N-type semiconductor layers, which are single crystals containing Ga and As.
At least one boundary portion of the first interface layer or the semiconductor layer in contact with the second interface layer has the same crystal lattice as a GaAs single crystal.
The first interface layer or at least one of the second interface layers has a volume density of Si of 6 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less.
The thickness of the metal diffusion layer forming the first electrode formed at the interface between the first interface layer and the first electrode, and the thickness of the second interface layer and the second electrode. A semiconductor device in which the thickness of the metal diffusion layer forming the second electrode formed at the interface is 3 nm or less. The semiconductor device according to claim 1 or 2, wherein the thickness of the first interface layer and the second interface layer is 5 nm or more and 1000 nm or less. The first electrode and the second electrode are Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc. , Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al, one or more metals selected from the group, Ti, Cr, Ni, Au, Pt, Ag. , Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir , In, Al, an alloy containing one or more metals selected from the group consisting of Ti, Cr, Ni, Au, Pt, Ag, Pd, W, Cu, Yb, Sm, Y, Tb, Ho, Tm, Gd, Compounds containing one or more metals selected from the group consisting of Er, Nd, Sc, Zr, Hf, Ta, Nb, V, Fe, Mo, Ru, Co, Rh, Re, Ir, In, Al, and ITO. The semiconductor device according to any one of claims 1 to 3, comprising any one of AZO, GZO, IZO, IGZO, ATO, FTO, FZO, and TiN. A sacrificial layer forming step of forming a sacrificial layer having an etching rate higher than that of GaAs on a rigid substrate.
Formation of a first interface layer that forms the first interface layer of an N-type semiconductor with a single crystal containing Ga and As having a Si volume content of 6 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less. Process and
A semiconductor layer forming step of a semiconductor layer containing Ga and As, wherein the boundary portion of the semiconductor layer in contact with the first interface layer is a single crystal semiconductor having the same crystal lattice as a GaAs single crystal.
A second interface layer forming step of forming a second interface layer of an N-type semiconductor with a single crystal containing Ga and As, and a second interface layer forming step.
A second electrode forming step of forming a second electrode made of a material containing metal, and
The support substrate pasting step of pasting the support substrate on the second electrode and the process of pasting the support substrate,
An etching process for removing the substrate and the sacrificial layer by etching,
A method for manufacturing a semiconductor device, comprising a first electrode forming step of forming a first electrode made of a material containing a metal on the first interface layer. The method for manufacturing a semiconductor device according to claim 5, wherein the second interface layer contains Si having a volume content of 6 × 10 ¹⁸ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less. The method for manufacturing a semiconductor device according to claim 5 or 6, wherein the second interface layer is made of GaAs epitaxially formed at a temperature of 150 ° C. or higher and 300 ° C. or lower. The method for manufacturing a semiconductor device according to any one of claims 5 to 7, wherein the sacrificial layer is made of AlGaAs having an Al composition ratio of 50% or more and 100% or less. The method for manufacturing a semiconductor device according to any one of claims 5 to 8, wherein the semiconductor layer is epitaxially formed at a temperature of 300 ° C. or higher and 580 ° C. or lower. The method for manufacturing a semiconductor device according to any one of claims 5 to 8, wherein the semiconductor layer is epitaxially formed at a temperature of 300 ° C. or higher and 550 ° C. or lower. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the time for epitaxial formation of the semiconductor layer is 2 minutes or more and 48 hours or less. An infrared photoelectric conversion element using the semiconductor device according to any one of claims 1 to 4 or the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 5 to 11. An infrared detection element using the semiconductor device according to any one of claims 1 to 4 or the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 5 to 11. An infrared light emitting device using the semiconductor device according to any one of claims 1 to 4 or the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 5 to 11.

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